Ad conversion circuit

Abstract

To provide an A / D conversion circuit for executing offset compensation without sacrificing conversion speed.SOLUTION: An AD conversion circuit according to an embodiment of the present invention includes a plurality of capacitors having capacitance values weighted by a binary ratio and having one ends connected in parallel to a common terminal, a plurality of switches that connect the other ends of the plurality of capacitors to any of an input terminal of an analog signal, a reference voltage terminal, and a ground terminal, first and second comparison circuits that output a comparison result between a voltage of the common terminal and a reference voltage, and a control circuit that controls switching of the plurality of switches, comparison timing in the first and second comparison circuits, and offset. The control circuit controls the comparison timing so that the first and second comparison circuits alternately output the comparison results, feeds back the comparison result of the first or second comparison circuit when the plurality of switches are in the OFF state during the sampling of the analog signal, and the first and second comparison circuits adjust the offset according to the fed-back comparison result.SELECTED DRAWING: FIG. 2A

Description

[Technical Field]

[0001] The present invention relates to an AD conversion circuit, and more particularly to a successive approximation type AD conversion circuit. [Background technology]

[0002] As shown in Figure 8, a method has been proposed to speed up AD conversion circuits by performing time-interleaved operation on AD converters arranged in multiple channels. This method has the problem that offset errors in each AD converter affect the conversion accuracy of the AD conversion.

[0003] Various configurations for offset compensation in AD converters have been reported, and recently, AD converters using comparators that achieve infinite gain through a positive feedback loop, which is advantageous in terms of power consumption, have become mainstream.

[0004] In a comparator that obtains infinite gain through a positive feedback loop, a judgment is made under the condition that there is no potential difference between the two input signals being compared (corresponding to the boundary between "1" and "0"), and by setting the probability of this judgment result being "1" and "0" at 50%, respectively, it is possible to set the offset to zero.

[0005] For example, in the AD converter of Non-Patent Document 1, after a series of successive approximation operations are completed, a state is created in which there is no potential difference between the two input signals being compared in the comparator, a decision operation is performed in this state, and the decision result is fed back to the comparator to perform offset compensation. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] L. Kull et al., “A 3.1mW 8b 1.2GS / s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS”, ISSCC2013.https: / / ieeexplore.ieee.org / document / 6487818 Summary of the Invention [Problem to be solved by the invention]

[0007] In Non-Patent Document 1, the time required for feedback of the decision result is added to the actual conversion operation period, and therefore offset compensation affects the conversion speed of the AD conversion. To speed up the AD conversion circuit, a configuration has been proposed in which multiple comparators are placed within a single AD conversion circuit and operated alternately or sequentially, but in this case too, differences in the offsets of the comparators affect the conversion accuracy of the AD conversion, making offset compensation necessary.

[0008] The present invention has been made to solve the above-mentioned problems, and has an object to provide an AD conversion circuit that performs offset compensation without sacrificing conversion speed. [Means for solving the problem]

[0009] In order to achieve the above object, an AD conversion circuit of the present invention includes an input terminal to which an analog signal is input, a plurality of capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to a common terminal, a plurality of switches connecting the other ends of the plurality of capacitors to either the input terminal, a reference voltage terminal, or a ground terminal, respectively, a first comparison circuit and a second comparison circuit that compare a voltage of the common terminal with a reference voltage and output a comparison result, and a control circuit that controls switching of the plurality of switches and comparison timing and offsets in the first comparison circuit and the second comparison circuit, wherein the control circuit controls switching of the plurality of switches to perform a binary search after sampling the analog signal to the common terminal, and controls the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the A / D conversion results, and is configured to turn off the plurality of switches during sampling of the analog signal and feed back the comparison result of the first comparison circuit or the second comparison circuit to the respective comparators, and the first comparison circuit and the second comparison circuit adjust their respective offsets in accordance with the fed back comparison result.

[0010] In order to achieve the above object, an AD conversion circuit of the present invention includes an input terminal to which an analog signal is input, a plurality of capacitors having capacitance values ​​weighted by a non-binary ratio and one end connected in parallel to a common terminal, a plurality of switches connecting the other ends of the plurality of capacitors to either the input terminal, a reference voltage terminal, or a ground terminal, respectively, a first comparison circuit and a second comparison circuit that output a comparison result obtained by comparing a voltage of the common terminal with a reference voltage, and a control circuit that controls switching of the plurality of switches and comparison timing and offsets in the first comparison circuit and the second comparison circuit, wherein the control circuit controls switching of the plurality of switches to perform a binary search after sampling the analog signal to the common terminal, and controls the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the A / D conversion results, and is configured to turn off the plurality of switches during sampling of the analog signal and feed back the comparison result of the first comparison circuit or the second comparison circuit to the respective comparators, and the first comparison circuit and the second comparison circuit adjust their respective offsets in accordance with the fed-back comparison result.

[0011] In order to solve the above problem, an AD conversion circuit of the present invention includes an input terminal to which an analog signal is input, a plurality of capacitors having capacitance values ​​weighted by a binary ratio and one end of which is connected in parallel to a common terminal, a plurality of switches that connect the other ends of the plurality of capacitors to either the input terminal, a reference voltage terminal or a ground terminal, respectively, a first comparison circuit and a second comparison circuit that output a comparison result obtained by comparing the voltage of the common terminal with a reference voltage, a control circuit that controls the switching of the plurality of switches and the comparison timing in the first comparison circuit and the second comparison circuit, and a control circuit that controls the first comparison circuit and the second comparison circuit based on the output frequency of a predetermined output code in the first comparison circuit and the second comparison circuit. and a detection circuit that detects an offset difference of the second comparison circuit, wherein the control circuit is configured to control switching of the plurality of switches to perform a binary search after sampling the analog signal at the common terminal, and to control the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the A / D conversion results, and the detection circuit is configured to feed back the detection result of the offset difference to the first comparison circuit or the second comparison circuit during sampling of the analog signal, and the first comparison circuit and the second comparison circuit adjust their respective offsets according to the fed-back detection result.

[0012] In order to solve the above-mentioned problems, an AD conversion circuit of the present invention includes an input terminal to which an analog signal is input, a plurality of capacitors having capacitance values ​​weighted by a non-binary ratio and one end of which is connected in parallel to a common terminal, a plurality of switches connecting the other ends of the plurality of capacitors to either the input terminal, a reference voltage terminal or a ground terminal, respectively, a first comparison circuit and a second comparison circuit that output a comparison result obtained by comparing the voltage of the common terminal with a reference voltage, a control circuit that controls the switching of the plurality of switches and the comparison timing in the first comparison circuit and the second comparison circuit, and a control circuit that controls the first comparison circuit and the second comparison circuit based on the output frequency of predetermined output codes in the first comparison circuit and the second comparison circuit. and a detection circuit that detects an offset difference of the second comparison circuit, wherein the control circuit is configured to control switching of the plurality of switches to perform a binary search after sampling the analog signal at the common terminal, and to control the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the A / D conversion results, and the detection circuit is configured to feed back the detection result of the offset difference to the first comparison circuit or the second comparison circuit during sampling of the analog signal, and the first comparison circuit and the second comparison circuit adjust their respective offsets in accordance with the fed-back detection result.

[0013] In order to solve the above-mentioned problems, an AD conversion circuit of the present invention includes an input terminal to which an analog signal is input, a plurality of capacitors having capacitance values ​​weighted by a binary ratio and one end of which is connected in parallel to a common terminal, a plurality of switches connecting the other ends of the plurality of capacitors to either the input terminal, a reference voltage terminal or a ground terminal, respectively, a first comparison circuit and a second comparison circuit that output a comparison result obtained by comparing a voltage of the common terminal with a reference voltage, a control circuit that controls the switching of the plurality of switches and the comparison timing in the first comparison circuit and the second comparison circuit, and a control circuit that controls the output frequency of logic "1" and logic "0" in the most significant bit of an output code of the first comparison circuit and / or the second comparison circuit to output a comparison result obtained by comparing the voltage of the common terminal with a reference voltage, and a detection circuit that detects an offset of the first comparison circuit and / or the second comparison circuit, wherein the control circuit is configured to control switching of the plurality of switches to perform a binary search after sampling the analog signal at the common terminal, and to control the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the comparison results, and the detection circuit is configured to feed back the offset detection result to the first comparison circuit and / or the second comparison circuit during sampling of the analog signal, and the first comparison circuit and / or the second comparison circuit adjust their respective offsets in accordance with the fed-back detection result. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide an AD conversion circuit that performs offset compensation without sacrificing the conversion speed of AD conversion. [Brief explanation of the drawings]

[0015] [Figure 1A] FIG. 1A is a diagram illustrating a configuration example of a successive approximation type AD conversion circuit. [Figure 1B] FIG. 1B is a diagram for explaining the operation (foreground) of the successive approximation type AD conversion circuit. [Figure 1C]FIG. 1C is a diagram for explaining the operation (background) of the successive approximation type AD conversion circuit. [Figure 1D] FIG. 1D is a diagram illustrating a configuration example of a comparison circuit of a successive approximation type AD conversion circuit. [Figure 2A] FIG. 2A is a diagram showing an example of the configuration of an AD conversion circuit according to the first embodiment of the present invention. [Figure 2B] FIG. 2B is a diagram for explaining the operation of the AD conversion circuit according to the first embodiment of the present invention. [Figure 2C] FIG. 2C is a diagram for explaining the operation of the AD conversion circuit according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a diagram showing an example of the configuration of an AD conversion circuit according to a second embodiment of the present invention. [Figure 3B] FIG. 3B is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 3C] FIG. 3C is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 4] FIG. 4 is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 5] FIG. 5 is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 6] FIG. 6 is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 7] FIG. 7 is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 8] FIG. 8 is a diagram showing an example of the configuration of a conventional AD conversion circuit. DETAILED DESCRIPTION OF THE INVENTION

[0016] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings, in which: FIG.

[0017] <Successive approximation type AD conversion circuit> Before describing the embodiments of the present invention, the configuration and operation of a successive approximation type AD conversion circuit on which the present invention is based will be described.

[0018] 1A is a diagram showing an example of the configuration of a successive approximation type AD conversion circuit. The AD conversion circuit 1 in Fig. 1A is a 6-bit resolution AD conversion circuit. It includes a capacitive DA converter (CDAC) 2, a comparison circuit 3, and a control circuit 5.

[0019] The CDAC2 includes a plurality of capacitors (10-16) and a plurality of switches (20-26) whose capacitances are weighted by a predetermined ratio, for example, a binary ratio. Capacitor 10 is an MSB capacitor, and capacitor 15 is an LSB capacitor. Capacitor 16 is a dummy capacitor, and the capacitance of the dummy capacitor is equal to the capacitance of the LSB capacitor. The capacitances of the plurality of capacitors (10-16) may be weighted by a non-binary ratio, for example, a ratio of Radix<2.

[0020] One end of each capacitor (10-16) is connected in parallel to a common terminal 8, and the other end of each capacitor (10-16) is connected via each switch (20-26) to a reference voltage terminal 30, an input terminal 31, and a ground terminal 32. A reference voltage Vref is supplied to the reference voltage terminal 30, and an input voltage Vin of an analog signal is supplied to the input terminal 31. The ground terminal 32 is grounded.

[0021] The common terminal 8 is connected to ground 7 via the switch 6. When the input voltage Vin is charged to each capacitance, that is, when the analog signal is sampled, the switch 6 is turned on by a control signal Φs, and the common terminal 8 is connected to ground 7.

[0022] A control signal DCDAC is supplied to each switch (20-26) of the CDAC2 from the control circuit 5. In response to the control signal DCDAC, each switch (20-26) switches the connection between the other end of each capacitor (10-16) and the reference voltage terminal 30, the input terminal 31, or the ground terminal 32.

[0023] When sampling the input voltage Vin of the analog signal, each switch (20-26) connects the other end of each capacitor (10-16) to the input terminal 31. After sampling the input voltage Vin, the control signal Φs turns off the switch 6, and the control signal DCDAC controls each switch (20-26) to be off.

[0024] The conversion operation of the CDAC 2 is performed by a binary search. First, the other end of the MSB capacitor 10 is disconnected from the input terminal 31 and connected to the reference voltage terminal 30, and the reference voltage Vref is applied.

[0025] At this time, the potential VCDAC of the common terminal 8 becomes -Vin+Vref / 2. The potential VCDAC of the common terminal 8 is compared with the ground potential, which is the reference voltage, by the comparator circuit 3. As a result, the comparator circuit 3 compares whether Vin is greater than Vref / 2 or not.

[0026] When Vin is greater than Vref / 2, the comparator circuit 3 outputs a logic "1." On the other hand, when Vin is less than Vref / 2, the comparator circuit 3 outputs a logic "0."

[0027] When the output of the comparison circuit 3 is "1", the other end of the MSB capacitance 10 remains connected to the reference voltage terminal 30, and when the output of the comparison circuit 3 is "0", the other end of the MSB capacitance 10 is connected to the ground terminal 32 and is grounded.

[0028] Next, the other end of the capacitor 11 having the second largest capacitance after the MSB capacitor 10 is connected to the reference voltage terminal 30 to apply the reference voltage Vref, and the potential VCDAC of the common terminal 8 and the ground potential are compared by the comparator circuit 3 .

[0029] Similarly, when the potential VCDAC of the common terminal 8 is higher than the ground potential, that is, when the output of the comparison circuit 3 is logic "1", the lower end of the capacitor 11 remains connected to the reference voltage Vref, and in the case of logic "0", the other end of the MSB capacitor 10 is connected to the ground terminal 32 and grounded. This comparison operation is performed until all bits are determined.

[0030] According to whether the output signal of the comparison circuit 3 is logic "1" or "0" by this sequential conversion operation, the connection states of the respective switches (20 - 26) are controlled. The control circuit 5 outputs the logic signals from the MSB to the LSB output by the comparison circuit 3 as the digital signal Dout.

[0031] <Offset adjustment of the AD conversion circuit> Next, the offset adjustment in the successive approximation type AD conversion circuit will be described. FIG. 1B is a diagram for explaining the operation (foreground) of the successive approximation type AD conversion circuit.

[0032] In FIG. 1B, before the start of a series of successive comparison operations (immediately after analog signal sampling), the comparison operation is performed by providing a state where there is no potential difference between the two input signals compared in the comparison circuit 3, and offset compensation is performed by feeding back the comparison result to the comparator.

[0033] In FIG. 1B, Φs is a control signal for controlling the sampling of the analog signal, Φc is a control signal for controlling the comparison timing of the comparison operation of the comparison circuit 3, DCDAC is a control signal for switching the switches (20 - 26), VCDAC is the potential of the common terminal 8 compared in the comparison circuit 3, and Dcal is a control signal for controlling the offset of the comparison circuit 3.

[0034] In FIG. 1B, when sampling the input voltage Vin of the analog signal, Φs becomes the ON state, and DCDAC controls each switch (20 - 26) so that the other end of each capacitor (10 - 16) is connected to the input terminal 31.

[0035] The polarity of the offset is determined between the end of analog signal sampling and the determination of the MSB capacitance. The polarity of the offset can be measured by operating the comparator circuit 3 with the switches (20-26) in the OFF state, which corresponds to an input signal of 0.

[0036] The control circuit 5 feeds back the result of determining the polarity of the offset as Dcal to the comparison circuit 3. The comparison circuit 3 performs offset adjustment according to the polarity of the offset that has been fed back.

[0037] In this foreground operation of offset adjustment, the polarity of the offset is determined between the end of sampling of the analog signal and the determination of the MSB capacitance, and therefore the conversion speed of the binary determination is reduced due to the time taken to perform the offset determination.

[0038] Figure 1C is a diagram for explaining the operation (background) of a successive approximation type AD conversion circuit. In Figure 1C, the polarity of the offset is determined during sampling of the analog signal. This allows offset determination to be performed without affecting the conversion speed of binary determination.

[0039] <Offset adjustment in comparison circuit> 1D is a diagram showing an example of the configuration of a comparison circuit of a successive approximation type AD conversion circuit. As described above, the signal is fed back to the comparison circuit 3 as Dcal. The comparison circuit 3 performs offset adjustment in response to the control signal Dcal based on the offset determination result fed back from the control circuit 5.

[0040] The comparator circuit 3 in FIG. 1D uses a differential amplifier circuit to compare DCDAC and GND. A variable capacitor for offset adjustment is connected in series to the transistor in the input stage of the comparator circuit 3, and the offset of the comparator circuit 3 can be adjusted by controlling the capacitance value of this variable capacitor according to Dcal. The offset adjustment range in the comparator circuit 3 can be set appropriately according to the required conversion accuracy. For example, a voltage equivalent to the least significant bit (LSB) may be adjusted as the adjustment range.

[0041] The AD conversion circuit of this embodiment is configured to increase the speed of the AD conversion circuit by arranging multiple comparison circuits within the AD conversion circuit and operating them alternately, and further, when performing offset compensation for each comparison circuit, a background operation is performed to determine the polarity of the offset while sampling the analog signal, so that offset compensation can be performed without affecting the conversion speed of the AD conversion.

[0042] First Embodiment 2A is a diagram showing an example of the configuration of an AD conversion circuit according to a first embodiment of the present invention. The difference from the configuration in FIG. 1A is that a comparison circuit 3 (first comparison circuit) and a comparison circuit 4 (second comparison circuit) are arranged in the AD conversion circuit 1, and control signals Dcal (A, B) based on the offset determination results are fed back to the two comparison circuits (3, 4).

[0043] FIG. 2B is a diagram for explaining the operation of the AD conversion circuit according to the first embodiment of the present invention.

[0044] In FIG. 2B, Φs is a control signal for controlling the sampling of the analog signal, Φc(A) is a control signal for controlling the comparison timing of the comparison operation of the comparison circuit 3 (Ach), Φc(B) is a control signal for controlling the comparison timing of the comparison operation of the comparison circuit 4 (Bch), DCDAC is a control signal for switching the switches (20-26), VCDAC is the potential of the common terminal 8 compared in the comparison circuit 3, and Dcal is a control signal for controlling the offset of the comparison circuit 3.

[0045] The settling time shown in Figure 2B is the time it takes for the input voltages of each comparator to be compared. Each comparator must start its comparison operation after the settling time for each decision bit has elapsed.

[0046] In this embodiment, as shown in Fig. 2B, control signals Φc(A) and Φc(B) for controlling the comparison timing of the comparison operation are used to alternately operate the comparison circuits 3 and 4. In the example of Fig. 2B, as shown in Fig. 2C, of ​​the 6-bit (D5-D0) determination operation, the comparison circuit 3 determines D5 (MSB), D3, and D1, and the comparison circuit 4 determines D4, D2, and D0 (LSB).

[0047] With this configuration, when one comparison circuit is performing a comparison operation, the reset time of the other comparison circuit can be masked, thereby ensuring time to reset the comparison circuit and eliminating the effect that the reset time of the comparison circuit has on the conversion speed of AD conversion.

[0048] In this embodiment, the offset polarity is also determined alternately in the comparison circuit 3 and the comparison circuit 4. In the example of Fig. 2B, the offset polarity in the comparison circuit 3 (Ach) is determined while the comparison circuit 4 (Bch) is determining D5, and the determination result is immediately fed back to the comparison circuit 3, and the offset is adjusted in the comparison circuit 3 before the comparison circuit 3 starts determining D4.

[0049] With this configuration, when one comparison circuit is performing a comparison operation, the offset of the other comparison circuit can be adjusted, so that it is possible to perform offset adjustment for each comparison circuit without affecting the conversion speed of the AD conversion.

[0050] <Second embodiment> <Relative offset compensation> In the first embodiment, a configuration was described in which two comparison circuits are arranged in the AD conversion circuit 1 and offset adjustment is performed in each of the two comparison circuits. In this case, the offset difference between the two comparison circuits may affect the conversion accuracy of the AD conversion. In the second embodiment, an AD conversion circuit that can compensate for the relative offset difference between the two comparison circuits will be described.

[0051] 3A is a diagram showing an example of the configuration of an AD conversion circuit according to a second embodiment of the present invention. The difference from the configuration of FIG. 2A is that a detection circuit 9 is provided that detects differential non-linearity (DNL) errors of output codes of a plurality of comparison circuits in the output signal of the AD conversion circuit 1. In this embodiment, a control signal Dcal for controlling the offsets of the comparison circuits 3 and 4 is generated based on the detection result of the detection circuit 9.

[0052] 3B is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. The AD conversion circuit according to the second embodiment is configured to compensate for the offset difference between the two comparison circuits based on the nonlinearity error (DNL) detected by the detection circuit 9.

[0053] 3B, Φs is a control signal for controlling the sampling of the analog signal, Φc(A) is a control signal for controlling the timing of the comparison operation of the comparison circuit 3 (Ach), and Φc(B) is a control signal for controlling the timing of the comparison operation of the comparison circuit 4 (Bch). As in the first embodiment, the comparison circuits 3 and 4 are alternately operated using the control signals Φc(A) and Φc(B) for controlling the timing of the comparison operation.

[0054] DCDAC is a control signal for switching the switches (20-26), and VCDAC is the potential of the common terminal 8 compared in the comparison circuit 3. Dcal(A, B) is a control signal for controlling the offsets of the comparison circuits 3 and 4, and is output from the detection circuit 9.

[0055] 3C is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention. As in the first embodiment, among the 6-bit (D5-D0) determination operations, comparison circuit 3 determines D5 (MSB), D3, and D1, and comparison circuit 4 determines D4, D2, and D0 (LSB).

[0056] In the second embodiment, the detection circuit 9 detects a nonlinear error using the output codes of the two comparison circuits, and compensates for the offset difference using the detected nonlinear error. Therefore, the comparison circuit does not operate to detect the offset during the sampling period of the analog signal. Also, during the sampling period, the offset control signal Dcal(A, B) generated based on the detection result in the detection circuit 9 is used to adjust the offsets of the comparison circuits 3 and 4.

[0057] According to the present embodiment, as in the first embodiment, when one comparison circuit is performing a comparison operation, the reset time of the other comparison circuit can be masked, so that time for resetting the comparison circuit can be secured and the effect of the reset time of the comparison circuit on the conversion speed of AD conversion can be eliminated.

[0058] Furthermore, in this embodiment, the detection circuit 9 detects nonlinear errors using the output codes of the two comparison circuits and compensates for the offset difference using the detected nonlinear errors, so the comparison circuits do not operate during the sampling period of the analog signal. This allows the offset adjustment of the comparison circuits to be performed during the sampling period, making it possible to compensate for the offset difference between the comparison circuits without affecting the conversion speed of the AD conversion.

[0059] 4 and 5, detection of a nonlinearity error (DNL) in the output code of the comparator circuit and offset adjustment using the detection will be described in the second embodiment.

[0060] 4 is a diagram illustrating the operation of an AD conversion circuit according to a second embodiment of the present invention. FIG. 4 shows an example of conversion in an AD conversion circuit with 4-bit resolution. FIG. 4(a) shows a conversion example when there is no offset, FIG. 4(b) shows a conversion example of even samples when there is an offset, and FIG. 4(c) shows a conversion example of odd samples when there is an offset. In FIG. 4, it is assumed that the difference in offset between comparison circuit A and comparison circuit B is half the voltage corresponding to the least significant bit [0.5 LSB].

[0061] In Figures 4(b) and 4(c), there is a 0.5LSB offset difference between the two comparison circuits (A and B), which causes a deviation from the correct decision point. As a result, in Figure 4(b), the nonlinearity error (DNL) at the two least significant bits "10" is less than 1LSB, and the nonlinearity error (DNL) at the two least significant bits "01" is greater than 1LSB. On the other hand, in Figure 4(c), the nonlinearity error (DNL) at "10" is greater than 1LSB, and the nonlinearity error (DNL) at "01" is less than 1LSB.

[0062] Figure 5 shows an example of conversion in a 4-bit resolution AD conversion circuit. Figure 5(a) shows a conversion example without offset, Figure 5(b) shows a conversion example of even samples with offset, and Figure 5(c) shows a conversion example of odd samples with offset. In Figure 5, it is assumed that the difference in offset between comparison circuit A and comparison circuit B is 1.5 times the voltage equivalent to the least significant bit [1.5 LSB].

[0063] In Figures 5(b) and 5(c), there is a 1.5 LSB offset difference between the two comparison circuits (A and B), which causes a deviation from the correct decision point. As a result, in Figure 5(b), the nonlinearity error (DNL) at the two least significant bits "10" is less than 0 LSB, and the nonlinearity error (DNL) at the two least significant bits "01" is greater than 2 LSB. On the other hand, in Figure 5(c), the nonlinearity error (DNL) at "10" is greater than 2 LSB, and the nonlinearity error (DNL) at "01" is less than 0 LSB.

[0064] If we assume that the input voltage Vin of the sampled analog signal is uniformly distributed, the nonlinearity error (DNL) is proportional to the output frequency of each code. Therefore, by counting the output frequency of a specific bit, we can detect the difference in DNL.

[0065] As described above, the difference in DNL varies depending on the relative offset difference between comparison circuit A and comparison circuit B. Therefore, by adjusting the offset difference so that the difference in the detected output frequency becomes smaller, it is possible to compensate for the relative offset difference between comparison circuit A and comparison circuit B.

[0066] The operation of offset compensation in the second embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram for explaining the operation of the AD conversion circuit according to the second embodiment of the present invention.

[0067] When the control circuit 5 outputs a digital signal after AD conversion, the detection circuit 9 specifies the target output code and the number of samples of the output code to be acquired (S1-1, S1-2).

[0068] In this embodiment, it is assumed that in an AD conversion circuit with 4-bit resolution, the lower 2 bits are designated as the output code to be acquired, and output codes of several tens of samples or more are acquired.

[0069] The detection circuit 9 starts acquiring the output codes to be acquired and determines whether the number of acquired output codes exceeds the specified number of samples (S1-3 to S1-5).

[0070] As described in FIGS. 4 and 5, since the acquisition process of the output codes is different between the even samples and the odd samples of the samples to be acquired, the acquisition process of the output codes is performed by distinguishing between the even samples and the odd samples.

[0071] As a result of the determination, if the number of acquired output codes exceeds the specified number of samples (S1-5: YES), the output frequencies of the target output codes are compared, and the offset of the comparison circuits is controlled so that the output frequencies are about the same (S1-7 to S1-9).

[0072] For example, when the detection circuit 9 sets the output frequency of the output code “10” as C_10 and the output frequency of the output code “01” as C_01, when C_01 < C_10, the offset control signal Dcal(A,B) is fed back to the comparison circuits 3 and 4 so that C_01 > C_10.

[0073] On the other hand, when C_01 > C_10, the detection circuit 9 feeds back the offset control signal Dcal(A,B) to the comparison circuits 3 and 4 so that C_01 < C_10.

[0074] The comparison circuits 3 and 4 adjust the offset according to the offset control signal Dcal(A,B) transmitted from the detection circuit 9. As a result, it becomes possible to compensate for the offset difference between the comparison circuits 3 and 4. The method of adjusting the offset in the comparison circuits 3 and 4 is the same as the method described in FIG. 1D.

[0075] <The Third Embodiment> <Compensation of Absolute Offset> In the second embodiment, an AD conversion circuit capable of adjusting the relative offset difference between two comparison circuits has been described. In the third embodiment, an AD conversion circuit capable of adjusting the absolute offset of a comparison circuit will be described.

[0076] The configuration of the AD conversion circuit of the third embodiment is the same as that of the second embodiment. In the third embodiment, the operation of detecting nonlinearity error in the detection circuit 9 is different from that of the second embodiment.

[0077] The operation of offset compensation in the third embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram for explaining the operation of the AD conversion circuit according to the third embodiment of the present invention.

[0078] When the control circuit 5 outputs the digital signal after AD conversion, the detection circuit 9 specifies the comparison circuit A to be subjected to offset compensation and the number of samples of the output code to be acquired (S2-1, S2-2).

[0079] In this embodiment, it is assumed that an AD conversion circuit with a 4-bit resolution will acquire output codes of several thousand samples or more.

[0080] The detection circuit 9 acquires the output codes of the target comparison circuit A, and determines whether the number of acquired output codes exceeds a designated number of samples (S2-3 to S2-5).

[0081] As in the second embodiment, the process of obtaining the output code differs between even-numbered samples and odd-numbered samples, so the process of obtaining the output code is performed by distinguishing between even-numbered samples and odd-numbered samples.

[0082] If the result of the determination is that the number of acquired output codes exceeds the specified number of samples (S2-5: YES), the output frequency of logic "1" and logic "0" in the most significant bit (MSB) of the acquired output code is compared, and the offset is controlled so that the output frequency of MSB="1" and the output frequency of MSB="0" are approximately the same (S2-7 to S2-9).

[0083] For example, when the output frequency of MSB = “1” > the output frequency of MSB = “0”, the detection circuit 9 feeds back the offset control signal Dcal to the comparison circuit to be targeted so that the output frequency of MSB = “1” < the output frequency of MSB = “0”.

[0084] On the other hand, when the output frequency of MSB = “1” < the output frequency of MSB = “0”, the detection circuit 9 feeds back the offset control signal Dcal to the comparison circuit A to be controlled so that the output frequency of MSB = “1” > the output frequency of MSB = “0”.

[0085] The comparison circuit A to be controlled adjusts the offset according to the offset control signal Dcal transmitted from the detection circuit 9. As a result, it becomes possible to compensate for the absolute offset of the comparison circuit A to be controlled. The method for adjusting the offset in the comparison circuit is the same as the method described in FIG. 1D.

[0086] In the above, the case of compensating for the absolute offset in the comparison circuit A has been described. However, it is also possible to compensate for the absolute offset in the comparison circuit B and to compensate for the absolute offset in both the comparison circuit A and the comparison circuit B. Further, in either one of the comparison circuits A and B, absolute offset compensation may be performed, and in the other comparison circuit, relative offset compensation may be performed.

Industrial Applicability

[0087] [[ID=********]] [[ID=********]] The present invention can be applied to an AD conversion circuit.

Explanation of Signs

[0088] 1... AD conversion circuit, 2... capacitive DA converter (CDAC), 3... comparison circuit, 4... comparison circuit, 5... control circuit, 6... switch, 7... ground, 8... common terminal, 9... detection circuit, 10 to 16... capacitors, 20 to 26... switches, 30... reference voltage terminal, 31... input terminal, 32... ground terminal.

Claims

1. an input terminal to which an analog signal is input; a plurality of capacitors having capacitance values ​​weighted by a binary ratio and one end of which is connected in parallel to a common terminal; a plurality of switches that connect the other ends of the plurality of capacitors to any one of the input terminal, the reference voltage terminal, and the ground terminal; a first comparison circuit and a second comparison circuit that compare the voltage of the common terminal with a reference voltage and output a comparison result; a control circuit for controlling the switching of the plurality of switches and the comparison timing and offset in the first comparison circuit and the second comparison circuit; Equipped with The control circuit Controlling the switching of the plurality of switches to sample the analog signal at the common terminal and then performing a binary search; controlling the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the comparison results; During sampling of the analog signal, the plurality of switches are turned off, and the comparison result of the first comparison circuit or the second comparison circuit is fed back to each comparator. It is configured as follows: The first comparison circuit and the second comparison circuit adjust their respective offsets in response to the comparison results fed back. It is configured as follows: AD conversion circuit.

2. an input terminal to which an analog signal is input; a plurality of capacitors having capacitance values ​​weighted by a non-binary ratio and one end of which is connected in parallel to a common terminal; a plurality of switches that connect the other ends of the plurality of capacitors to any one of the input terminal, the reference voltage terminal, and the ground terminal; a first comparison circuit and a second comparison circuit that compare the voltage of the common terminal with a reference voltage and output a comparison result; a control circuit for controlling the switching of the plurality of switches and the comparison timing and offset in the first comparison circuit and the second comparison circuit; Equipped with The control circuit Controlling the switching of the plurality of switches to sample the analog signal at the common terminal and then performing a binary search; controlling the comparison timing so that the first comparison circuit and the second comparison circuit alternately output the comparison results; During sampling of the analog signal, the plurality of switches are turned off, and the comparison result of the first comparison circuit or the second comparison circuit is fed back to each comparator. It is configured as follows: The first comparison circuit and the second comparison circuit adjust their respective offsets in response to the comparison results fed back. It is configured as follows: AD conversion circuit.

3. an input terminal to which an analog signal is input; a plurality of capacitors having capacitance values ​​weighted by a binary ratio and one end of which is connected in parallel to a common terminal; a plurality of switches that connect the other ends of the plurality of capacitors to any one of the input terminal, the reference voltage terminal, and the ground terminal; a first comparison circuit and a second comparison circuit that compare the voltage of the common terminal with a reference voltage and output a comparison result; a control circuit for controlling the switching of the plurality of switches and the comparison timings of the first comparison circuit and the second comparison circuit; a detection circuit that detects an offset difference between the first comparison circuit and the second comparison circuit based on the output frequency of a predetermined output code in the first comparison circuit and the second comparison circuit; Equipped with The control circuit Controlling the switching of the plurality of switches to sample the analog signal at the common terminal and then performing a binary search; The comparison timing is controlled so that the first comparison circuit and the second comparison circuit alternately output the comparison results. It is configured as follows: The detection circuit feeding back the detection result of the offset difference to the first comparison circuit or the second comparison circuit during sampling of the analog signal; The first comparison circuit and the second comparison circuit The respective offsets are adjusted according to the feedback detection results. It is configured as follows: AD conversion circuit.

4. an input terminal to which an analog signal is input; a plurality of capacitors having capacitance values ​​weighted by a non-binary ratio and one end of which is connected in parallel to a common terminal; a plurality of switches that connect the other ends of the plurality of capacitors to any one of the input terminal, the reference voltage terminal, and the ground terminal; a first comparison circuit and a second comparison circuit that compare the voltage of the common terminal with a reference voltage and output a comparison result; a control circuit for controlling the switching of the plurality of switches and the comparison timings of the first comparison circuit and the second comparison circuit; a detection circuit that detects an offset difference between the first comparison circuit and the second comparison circuit based on the output frequency of a predetermined output code in the first comparison circuit and the second comparison circuit; Equipped with The control circuit Controlling the switching of the plurality of switches to sample the analog signal at the common terminal and then performing a binary search; The comparison timing is controlled so that the first comparison circuit and the second comparison circuit alternately output the comparison results. It is configured as follows: The detection circuit feeding back the detection result of the offset difference to the first comparison circuit or the second comparison circuit during sampling of the analog signal; The first comparison circuit and the second comparison circuit The respective offsets are adjusted according to the feedback detection results. It is configured as follows: AD conversion circuit.

5. an input terminal to which an analog signal is input; a plurality of capacitors having capacitance values ​​weighted by a binary ratio and one end of which is connected in parallel to a common terminal; a plurality of switches that connect the other ends of the plurality of capacitors to any one of the input terminal, the reference voltage terminal, and the ground terminal; a first comparison circuit and a second comparison circuit that compare the voltage of the common terminal with a reference voltage and output a comparison result; a control circuit for controlling the switching of the plurality of switches and the comparison timings of the first comparison circuit and the second comparison circuit; a detection circuit that detects an offset of the first comparison circuit and / or the second comparison circuit based on the frequency of output of logic "1" and logic "0" in the most significant bit of the output code of the first comparison circuit and / or the second comparison circuit; Equipped with The control circuit Controlling the switching of the plurality of switches to sample the analog signal at the common terminal and then performing a binary search; The comparison timing is controlled so that the first comparison circuit and the second comparison circuit alternately output the comparison results. It is configured as follows: The detection circuit feeding back the offset detection result to the first comparison circuit and / or the second comparison circuit during sampling of the analog signal; The first comparison circuit and / or the second comparison circuit The respective offsets are adjusted according to the feedback detection results. It is configured as follows: AD conversion circuit.

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