Gate drive circuit

Abstract

A gate drive circuit capable of reducing the power consumption of a power conversion circuit is provided. [Solution] A gate drive circuit (10A) includes a signal line (SL1), a first switching element (132), a second switching element (133), a first diode, a second diode, a capacitor, a third switching element, a control unit, and a delay circuit (42). The signal line (SL1) is connected to the gate terminal of a voltage-controlled switching element. The first switching element (132) is connected between the positive electrode of a DC power supply and the signal line (SL1). The second switching element (133) is connected between the negative electrode of the DC power supply and the signal line (SL1). The delay circuit (42) delays the rising edge of a signal input to the gate terminal of the second switching element (133).

Description

[Technical Field]

[0001] The present invention relates to a gate drive circuit. [Background technology]

[0002] In recent years, HVIC (High Voltage Integrated Circuit) technology has been developed to achieve high efficiency, energy saving, miniaturization, and high reliability in IDC (Internet Data Center) power supply systems such as servers and UPS (Uninterruptible Power Supplies). HVIC is a high-voltage gate drive circuit that drives the gates of power devices that make up a power conversion circuit (see, for example, Patent Documents 1 and 2). IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as power devices. The power conversion circuit also includes a series circuit of high-side and low-side power devices.

[0003] The HVIC is composed of a level shift circuit that converts the level of a control signal from GND potential to VS potential, which is connected to the reference potential (emitter or source) of the high-side power device, and a driver circuit that drives the power device. The control signal is a control signal based on the GND (ground) potential for driving the high-side power device. The high-side potential of the driver circuit is connected to the positive pole of the drive power supply. The low-side potential of the driver circuit is connected to the negative pole of the drive power supply.

[0004] In the above HVIC, when the control signal switches from low to high, the switching element on the low potential side of the driver circuit is turned off and the switching element on the high potential side is turned on, and charge is accumulated in the gate of the power device from the drive power supply, thereby turning it on.On the other hand, in the above HVIC, when the control signal switches from high to low, the switching element on the high potential side of the driver circuit is turned off and the switching element on the low potential side is turned on, and the charge accumulated in the gate of the power device is extracted, turning it off.

[0005] When a power device is turned off, the charge accumulated in the gate of the power device flows to the low-potential side of the driver circuit, increasing the power consumption of the power conversion circuit. Particularly in high-frequency operation, the power conversion circuit contributes more to the power consumption, so measures to reduce power consumption during standby have been taken, such as reducing the number of switching operations or suspending switching for a certain period of time. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-107045 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-44914 Summary of the Invention [Problem to be solved by the invention]

[0007] However, power conversion circuits using the above-mentioned power devices are required to perform stable operation for a long period of time without interruption, so there has long been a demand for measures other than reducing the number of switching operations or suspending switching for a certain period of time.

[0008] The technology described in Patent Document 1 is a technology that prevents a large inrush current that occurs when the power is turned on, while achieving miniaturization by using the precharge resistor of the smoothing capacitor as a discharge resistor, but is not a technology that suppresses an increase in power consumption of the power conversion circuit. Similarly, the technology described in Patent Document 2, like the technology described in Patent Document 1, is a technology that suppresses an inrush current that occurs when the power is turned on, but is not a technology that suppresses an increase in power consumption of the power conversion circuit.

[0009] An object of the present invention is to provide a gate drive circuit that can reduce the power consumption of a power conversion circuit. [Means for solving the problem]

[0010] In order to achieve the above object, a gate drive circuit according to one aspect of the present invention is a gate drive circuit that generates a drive signal for driving a voltage-controlled switching element based on a control signal for controlling on / off of the voltage-controlled switching element supplied with power from a DC power supply, the gate drive circuit including a signal line connected to a gate terminal of the voltage-controlled switching element, a first switching element connected between a positive electrode of the DC power supply and the signal line, a second switching element connected between a negative electrode of the DC power supply and the signal line, a first diode having an anode connected to the signal line, a second diode having an anode connected to a cathode of the first diode and a cathode connected to the positive electrode of the DC power supply, and a capacitor having a high potential side connected to the cathode of the first diode and the anode of the second diode. a third switching element connected between the low potential side of the capacitor and a reference potential of a drive signal to the voltage-controlled switching element; a control unit that, when a control signal to turn on the first switching element is input, controls the first switching element to an on state and the second switching element and the third switching element to an off state, thereby outputting the drive signal from the first switching element to a gate terminal of the voltage-controlled switching element, and, when a control signal to turn off the first switching element is input, controls the first switching element to an off state and the second switching element and the third switching element to an on state, thereby stopping the output of the drive signal; and a delay circuit that delays the rising edge of the signal input to the gate terminal of the second switching element. [Effects of the Invention]

[0011] According to one aspect of the present invention, it is possible to reduce the power consumption of a power conversion circuit. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing an example of the configuration of a semiconductor device on which a gate drive circuit according to a first embodiment of the present invention is mounted. [Figure 2]FIG. 10 is a block diagram showing a configuration example of a semiconductor device equipped with a gate drive circuit as a comparative example. [Figure 3] FIG. 10 is a circuit diagram showing a configuration of a driver circuit as a comparative example. [Figure 4] FIG. 10 is a signal timing diagram illustrating the operation of a high-side driver circuit as a comparative example. [Figure 5] FIG. 2 is a circuit diagram showing a configuration of a driver circuit according to the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of the regenerative circuit shown in FIG. 5. [Figure 7] FIG. 3 is a signal timing diagram illustrating the operation of the high-side driver circuit according to the first embodiment. [Figure 8] FIG. 10 is a circuit diagram showing a configuration of a driver circuit of a semiconductor device according to a second embodiment of the present invention. [Figure 9] FIG. 10 is a signal timing diagram illustrating the operation of the high-side driver circuit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] The embodiments of the present invention are merely examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0014] First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device equipped with a gate drive circuit according to a first embodiment of the present invention.

[0015] The semiconductor device 1A includes a high-side driver circuit 10A (an example of a gate drive circuit) and a power conversion circuit 20. The power conversion circuit 20 includes, for example, a bridge-connected high-side power device 21 (an example of a voltage-controlled switching element) and a low-side power device (not shown). The high-side power device 21 is supplied with power from a DC power supply Vdc, and has a gate terminal (G) connected to the high-side driver circuit 10A. For example, an IGBT (insulated gate bipolar transistor) or a MOSFET (metal oxide semiconductor field effect transistor) is used for the high-side power device 21.

[0016] The collector terminal (C) of the high-side power device 21 is connected to the positive electrode of the DC power supply Vdc. The emitter terminal (E) of the high-side power device 21 is connected to a diode 22 and an inductor 23. That is, the emitter terminal (E) of the high-side power device 21 is connected to a cathode terminal (K) of the diode 22 and one end of the inductor 23. The anode terminal (A) of the diode 22 is connected to the ground potential GND. The other end of the inductor 23 is connected to the ground potential GND.

[0017] The high-side driver circuit 10A generates a gate drive signal for driving the high-side power device 21. A control device 30, which controls the high-side power device 21 by switching between an ON state and an OFF state, is connected to the high-side driver circuit 10A via an input signal terminal 15. The high-side driver circuit 10A is also connected to a ground potential GND via a GND terminal 16. A drive power supply Vb for driving the high-side power device 21 is also connected to the high-side driver circuit 10A via a positive terminal 17 and a negative terminal 18. The high-side driver circuit 10A is configured to generate the gate drive signal using a control signal input from the control device 30.

[0018] The high-side driver circuit 10A includes a control circuit 11, a level shift circuit 12, and a driver circuit 13A. The control circuit 11 receives power from a main power supply Vcc via a power supply terminal 14, and has a function of generating a set pulse (Set) for turning on the high-side power device 21 in response to the rising edge of a control signal output from the control device 30 via an input signal terminal 15, and generating reset pulses (Reset and Reset2) for turning off the high-side power device 21 in response to the falling edge of the control signal.

[0019] The level shift circuit 12 has a function of level-shifting the control signal from the ground potential GND to a signal Q having a high-side reference potential VS, using a set pulse and a reset pulse output from the control circuit 11. The driver circuit 13A has a function of generating a gate drive signal in response to the signal Q output from the level shift circuit 12, and outputting the gate drive signal to the gate terminal (G) of the high-side power device 21 via an output signal terminal 19 and a signal line SL1. The reset pulse (Reset2) output from the control circuit 11 is also directly input to the driver circuit 13.

[0020] <Comparative Example of the First Embodiment> 2 is a block diagram showing an example of the configuration of a semiconductor device incorporating a gate drive circuit as a comparative example, in which the same components as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

[0021] The semiconductor device B1 serving as a comparative example includes a high-side driver circuit B10 and a power conversion circuit 20. The high-side driver circuit B10 includes a control circuit B11, a level shift circuit B12, and a driver circuit B13.

[0022] (Configuration of driver circuit B13) 3 is a circuit diagram showing the configuration of a driver circuit B13 as a comparative example. The driver circuit B13 includes a NOT circuit 131, a P-channel MOSFET 132 (an example of a first switching element), and an N-channel MOSFET 133 (an example of a second switching element). An input terminal of the NOT circuit 131 is connected to the level shift circuit B12 via an input signal terminal 13a. An output terminal of the NOT circuit 131 is connected to a gate terminal (G) of the P-channel MOSFET 132 and a gate terminal (G) of the N-channel MOSFET 133.

[0023] A source terminal (S) of the P-channel MOSFET 132 is connected to the positive electrode of the DC power supply Vdc and the positive electrode of the drive power supply Vb via the positive terminal 13b. A drain terminal (D) of the P-channel MOSFET 132 is connected to the gate terminal (G) of the high-side power device 21 via the signal line SL1 and the output signal terminal 13c. In addition, the drain terminal (D) of the P-channel MOSFET 132 is connected to the drain terminal (D) of the N-channel MOSFET 133. A source terminal (S) of the N-channel MOSFET 133 is connected to the negative electrode of the drive power supply Vb via the negative terminal 13d.

[0024] The P-channel MOSFET 132 is in a conductive state (ON state) when the voltage of a signal obtained by inverting the signal Q of the high-side reference potential VS by the NOT circuit 131 is equal to or lower than the threshold voltage between the gate and source. When the P-channel MOSFET 132 is in an ON state, it outputs the output current output from the drive power supply Vb to the gate terminal (G) of the high-side power device 21 as a gate drive signal to the gate terminal (G) of the high-side power device 21. On the other hand, when the voltage of the signal obtained by inverting the signal Q of the high-side reference potential VS is higher than the threshold voltage between the gate and source, the P-channel MOSFET 132 is in a non-conductive state (OFF state).

[0025] N-channel MOSFET 133 is in a conductive state (ON state) when the voltage of a signal obtained by inverting signal Q of high-side reference potential VS by NOT circuit 131 is equal to or higher than the threshold voltage between the gate and source. When N-channel MOSFET 133 is in an ON state, a current flows from the gate terminal (G) of high-side power device 21 to the negative side of drive power supply Vb, thereby drawing out the charge accumulated in the gate terminal (G) of high-side power device 21 and turning off high-side power device 21. On the other hand, when the voltage of the signal obtained by inverting signal Q of high-side reference potential VS is lower than the threshold voltage between the gate and source, N-channel MOSFET 133 is in a non-conductive state (OFF state).

[0026] (Operation of high-side driver circuit B10) Next, the operation of the high-side driver circuit B10 as a comparative example will be described using FIG. 4 with reference to FIGS.

[0027] FIG. 4 is a signal timing diagram illustrating the operation of a comparative high-side driver circuit B10. In FIG. 4, the vertical axis represents potential, and the horizontal axis represents time. FIG. 4(1) shows the waveform of a control signal (IN) input to the input signal terminal 15 of the high-side driver circuit B10. FIG. 4(2) shows the waveform of a set pulse (Set) output from the control circuit B11. FIG. 4(3) shows the waveform of a reset pulse (Reset) output from the control circuit B11. FIG. 4(4) shows the waveform of a signal Q of a high-side reference potential VS output from the level shift circuit B12. FIG. 4(5) shows the waveforms of a signal Pg input to the gate terminal (G) of the P-channel MOSFET 132 and a signal Ng input to the gate terminal (G) of the N-channel MOSFET 133. FIG. 4(6) shows the waveform of a voltage HO at the gate terminal (G) of the high-side power device 21. FIG. 4(7) shows the waveform of the high-side reference potential VS of the high-side power device 21.

[0028] In the high-side driver circuit B10, when the control signal (IN) input to the input signal terminal 15 switches from low level to high level (time t11), as shown in FIG. 4(1), the control circuit B11 outputs a set pulse (Set) shown in FIG. 4(2) to the level shift circuit B12 (time t12).

[0029] When the set pulse (Set) is input, the level shift circuit B12 switches the signal Q of the high-side reference potential VS output to the driver circuit B13 from low level to high level (time t13), as shown in Fig. 4(4). In the driver circuit B13, the NOT circuit 131 inverts the signal Q of the high-side reference potential VS, and outputs a signal (Pg) shown in Fig. 4(5) to the gate terminal (G) of the P-channel MOSFET 132 and a signal (Ng) to the gate terminal (G) of the N-channel MOSFET 133.

[0030] At time t13, the P-channel MOSFET 132 is turned on and the N-channel MOSFET 133 is turned off, causing the current output from the drive power supply Vb to flow through the positive terminal 13b and the source terminal (S) and drain terminal (D) of the P-channel MOSFET 132 to a gate-emitter capacitance (not shown) formed between the gate terminal (G) and emitter terminal (E) of the high-side power device 21. This charges the gate-emitter capacitance of the high-side power device 21, causing the voltage (gate voltage HO) of the gate terminal (G) of the high-side power device 21 to rise.

[0031] 4(6), at time t14, a predetermined time after time t13, the gate voltage HO of the high-side power device 21 becomes higher than the high-side reference potential VS of the high-side power device 21. After a mirror period (from time t14 to time t15) after a predetermined time has elapsed since time t14, the gate voltage HO of the high-side power device 21 rises to a voltage value that can maintain the high-side power device 21 in an on-state (time t15). In other words, the high-side power device 21 is turned on.

[0032] When the high-side power device 21 is turned on, the high-side reference potential VS of the high-side power device 21 shown in FIG. 4(7) gradually rises from the potential COM of the diode 22 and inductor 23 to the potential of the DC power supply Vdc (from time t14 to time t15).

[0033] On the other hand, as shown in FIG. 4(1), when the control signal (IN) input to the input signal terminal 15 switches from high level to low level (time t16), the control circuit B11 outputs a reset pulse (Reset) shown in FIG. 4(3) to the level shift circuit B12 (time t17).

[0034] When the reset pulse (Reset) is input, the level shift circuit B12 switches the signal Q of the high-side reference potential VS output to the driver circuit B13 from high level to low level (time t18), as shown in FIG. 4(4).

[0035] At time t18, the P-channel MOSFET 132 is turned off and the N-channel MOSFET 133 is turned on, causing the voltage level of the gate drive signal output from the output signal terminal 13c to be low. As a result, the charge accumulated in the gate-emitter capacitance of the high-side power device 21 flows to the N-channel MOSFET 133 via the output signal terminal 13c and the signal line SL1, discharging the gate-emitter capacitance of the high-side power device 21. As a result, as shown in FIG. 4(6), the gate voltage HO of the high-side power device 21 drops. In other words, the high-side power device 21 is turned off.

[0036] When the high-side power device 21 is turned off, the high-side reference potential VS of the high-side power device 21 shown in FIG. 4(7) gradually falls from the potential of the DC power supply Vdc to the potential COM of the diode 22 and inductor 23.

[0037] In the comparative example, when the high-side power device 21 is turned off, the charge accumulated in the gate terminal (G) of the high-side power device 21 is consumed as Joule heat in the N-channel MOSFET 133 of the driver circuit B13, which increases the power consumption of the power conversion circuit 20.

[0038] <Implementation means according to the first embodiment> Fig. 5 is a circuit diagram showing the configuration of a driver circuit 13A according to the first embodiment. In Fig. 5, the same parts as those in Fig. 3 are given the same reference numerals and detailed description thereof will be omitted.

[0039] The driver circuit 13A includes a NOT circuit 131, a P-channel MOSFET 132 (an example of a first switching element), an N-channel MOSFET 133 (an example of a second switching element), a regenerative circuit 41, and a delay circuit 42. The regenerative circuit 41 is connected to the positive electrode of the drive power supply Vb, i.e., to a positive electrode terminal 13b, and to a signal line SL1. The regenerative circuit 41 also includes an input signal terminal 13e to which a reset pulse (Reset2) output from the control circuit 11 is input, and a GND terminal 13f.

[0040] The delay circuit 42 is provided between the NOT circuit 131 and the gate terminal (G) of the N-channel MOSFET 133. The delay circuit 42 delays the rising edge of the signal Ng input to the gate terminal (G) of the N-channel MOSFET 133 by a certain period of time.

[0041] (Configuration of regeneration circuit 41) 6 is a circuit diagram showing the configuration of the regeneration circuit 41. The regeneration circuit 41 includes a diode 411 (an example of a first diode), a diode 412 (an example of a second diode), a capacitor 413, and an N-channel MOSFET 414 (an example of a third switching element).

[0042] The diode 411 has an anode terminal (A) connected to the signal line SL1 via the signal terminal 41a, and a cathode terminal (K) connected to the anode terminal (A) of the diode 412. The diode 412 has an anode terminal (A) connected to the cathode terminal (K) of the diode 411, and a cathode terminal (K) connected to the positive electrode of the driving power supply Vb via the electrode terminal 41b.

[0043] The high potential side of the capacitor 413 is connected to the cathode terminal (K) of the diode 411 and the anode terminal (A) of the diode 412, and the low potential side is connected to the drain terminal (D) of the N-channel MOSFET 414. The source terminal (S) of the N-channel MOSFET 414 is connected to the ground potential GND via the GND terminal 13f. The gate terminal (G) of the N-channel MOSFET 414 is connected to the control circuit 11 via the input signal terminal 13e.

[0044] The N-channel MOSFET 414 is turned on when the voltage of the reset pulse (Reset2) is equal to or higher than the gate-source threshold voltage. When the N-channel MOSFET 414 is turned on, it can increase the potential of the capacitor 413, thereby storing the charge stored in the gate terminal (G) of the high-side power device 21 in the capacitor 413.

[0045] (Operation of high-side driver circuit 10A) Next, the operation of the high-side driver circuit 10A according to the first embodiment will be described using FIG. 7 with reference to FIGS. 1, 5, and 6.

[0046] 7 is a signal timing diagram showing the operation of the high-side driver circuit 10A according to the first embodiment. In FIG. 7, the vertical axis represents potential and the horizontal axis represents time. FIG. 7(1) shows the waveform of the control signal (IN) input to the input signal terminal 15 of the high-side driver circuit 10A.

[0047] FIG. 7(2) shows the waveform of the set pulse (Set) output from the control circuit 11. FIG. 7(3) shows the waveform of the reset pulse (Reset) output from the control circuit 11. FIG. 7(4) shows the waveform of the reset pulse (Reset2) output from the control circuit 11. FIG. 7(5) shows the waveform of the signal Q of the high-side reference potential VS output from the level shift circuit 12. FIG. 7(6) shows the waveform of the signal Pg input to the gate terminal (G) of the P-channel MOSFET 132. FIG. 7(7) shows the waveform of the signal Ng input to the gate terminal (G) of the N-channel MOSFET 133. FIG. 7(8) shows the waveform of the voltage HO at the gate terminal (G) of the high-side power device 21. FIG. 7(9) shows the waveform of the high-side reference potential VS of the high-side power device 21.

[0048] 7(10) shows the waveform of the voltage Vcp on the high potential side of the capacitor 413 of the regenerative circuit 41 and the waveform of the voltage VB at the positive electrode of the driving power supply Vb. D1 7(12) shows the waveform of the current I flowing through the diode 412 of the regenerative circuit 41. D2 The waveform of

[0049] In the high-side driver circuit 10A, when the control signal (IN) input to the input signal terminal 15 switches from low level to high level (time t21), as shown in FIG. 7(1), the control circuit 11 outputs a set pulse (Set) shown in FIG. 7(2) to the level shift circuit B12 (time t22).

[0050] When the set pulse (Set) is input, the level shift circuit 12 switches the signal Q of the high-side reference potential VS output to the driver circuit 13A from low level to high level (time t23), as shown in Fig. 7(5). In the driver circuit 13A, the NOT circuit 131 inverts the signal Q of the high-side reference potential VS, and outputs a signal (Pg) shown in Fig. 7(6) to the gate terminal (G) of the P-channel MOSFET 132 and a signal (Ng) shown in Fig. 7(7) to the gate terminal (G) of the N-channel MOSFET 133.

[0051] At time t23, the P-channel MOSFET 132 is turned on and the N-channel MOSFET 133 is turned off, causing the current output from the drive power supply Vb to flow through the positive terminal 13b and the source terminal (S) and drain terminal (D) of the P-channel MOSFET 132 to a gate-emitter capacitance (not shown) formed between the gate terminal (G) and emitter terminal (E) of the high-side power device 21. As a result, the gate-emitter capacitance of the high-side power device 21 is charged, and the gate voltage HO of the gate terminal (G) of the high-side power device 21 rises.

[0052] As a result, as shown in FIG. 7(8), at time t24, a predetermined time after time t23, the gate voltage HO of the high-side power device 21 becomes higher than the high-side reference potential VS of the high-side power device 21. After a mirror period (from time t24 to time t25) has elapsed since time t24, the gate voltage HO of the high-side power device 21 rises to a voltage value that can maintain the high-side power device 21 in an on-state (time t25). In other words, the high-side power device 21 is turned on. During the mirror period, the current output from the drive power supply Vb also flows through the diode 411 of the regenerative circuit 41, as shown in FIG. 7(11).

[0053] When the high-side power device 21 is turned on, the high-side reference potential VS of the high-side power device 21 shown in FIG. 7(9) gradually rises from the ground potential GND to the potential of the DC power supply Vdc (from time t24 to time t25). Also, the voltage VB (shown by a solid line in FIG. 7) applied to the positive terminal 41b shown in FIG. 7(10) gradually rises from the potential of the drive power supply Vb to the sum potential of the potentials of the DC power supply Vdc and the drive power supply Vb (shown as Vdc+Vb in FIG. 7) (from time t24 to time t25). Furthermore, the voltage Vcp (shown by a dashed line in FIG. 7) on the high potential side of the capacitor 413 of the regenerative circuit 41 gradually rises from the potential of the drive power supply Vb to the sum potential of the potentials of the DC power supply Vdc and the drive power supply Vb (from time t24 to time t25). D1flows into the capacitor 413, and therefore gradually rises (from time t24 to time t25).

[0054] On the other hand, as shown in FIG. 7(1), when the control signal (IN) input to the input signal terminal 15 switches from high level to low level (time t26), the control circuit 11 outputs a reset pulse (Reset) shown in FIG. 7(3) to the level shift circuit 12 (time t27), and then outputs a reset pulse (Reset2) shown in FIG. 7(4) to the regeneration circuit 41 of the driver circuit 13A (time t28).

[0055] When the reset pulse (Reset) is input, the level shift circuit 12 switches the signal Q of the high-side reference potential VS output to the driver circuit 13A from high level to low level (time t28), as shown in FIG. 7(5).

[0056] At time t28, the P-channel MOSFET 132 is turned off, causing the voltage level of the gate drive signal output from the output signal terminal 13c to be low. Therefore, the charge accumulated in the gate-emitter capacitance of the high-side power device 21 flows to the diode 411 of the regenerative circuit 41 via the output signal terminal 13c and the signal line SL1 and is stored in the capacitor 413, thereby discharging the gate-emitter capacitance of the high-side power device 21. Note that, because the N-channel MOSFET 133 is turned off, the charge accumulated in the gate-emitter capacitance of the high-side power device 21 does not flow to the N-channel MOSFET 133 via the output signal terminal 13c and the signal line SL1. As a result, the gate voltage HO of the high-side power device 21 drops, as shown in FIG. 7(8). In other words, the high-side power device 21 is turned off.

[0057] When the high-side power device 21 is turned off, the N-channel MOSFET 414 is turned on for a certain period after the P-channel MOSFET 132 is turned off, and the current I D1The charge (gate charge) accumulated in the gate-emitter capacitance of the high-side power device 21 is transferred to the capacitor 413, and the gate charge is extracted.

[0058] When the high-side power device 21 is turned off, the high-side reference potential VS of the high-side power device 21 shown in FIG. 7(9) gradually falls from the potential of the DC power supply Vdc to the ground potential GND (from time t28 to time t29). At the same time, the voltage VB shown in FIG. 7(10) gradually falls from the sum of the potential of the DC power supply Vdc and the potential of the drive power supply Vb to the potential of the drive power supply Vb (from time t28 to time t29). When the voltage VB shown in FIG. 7(10) falls, the voltage Vcp on the high-potential side of the capacitor 413 becomes relatively higher than the voltage VB (time t30). As a result, the diode 412 flows the current I shown in FIG. 7(12). D2 The charge stored in the capacitor 413 is regenerated to the driving power supply Vb via the diode 412 and the positive terminal 17.

[0059] A certain delay time is provided from when the P-channel MOSFET 132 is turned off until after the N-channel MOSFET 414 is turned off, and after the delay time has elapsed since the signal (Ng) was input, the delay circuit 42 outputs the signal (Ng) shown in FIG. 7(7) to the gate terminal (G) of the N-channel MOSFET 133 (time t30), turning on the N-channel MOSFET 133 and thereby fixing the high-side power device 21 to the off state.

[0060] When a signal (Ng) that rises from a low level to a high level is input, the delay circuit 42 outputs the signal (Ng) to the gate terminal (G) of the N-channel MOSFET 133 after a delay time has elapsed.

[0061] <Effects of the First Embodiment> As described above, according to the first embodiment, the following are added to the conventional driver circuit B13: a capacitor 413 that accumulates gate charge of the high-side power device 21; a diode 411 that provides forward conduction only from the gate terminal (G) of the high-side power device 21 to the capacitor 413; a diode 412 that provides forward conduction only from the capacitor 413 to the drive power supply Vb; and an N-channel MOSFET 414 that is turned on only during the period in which the gate charge is accumulated in the capacitor 413.

[0062] This reduces the power consumption of the power conversion circuit 20. Furthermore, since the gate drive charge, which has conventionally been consumed as Joule heat, is regenerated to the drive power supply Vb, this contributes to improving power consumption efficiency during standby operation and other long-term operation with a high carrier frequency and a small power conversion capacity of the main circuit.

[0063] <Second embodiment> In the second embodiment of the present invention, the timing for turning on N-channel MOSFET 133 is preferably the timing when regeneration to drive power supply Vb ends, and a signal corresponding to this timing is detected using voltage Vcp on the high potential side of capacitor 413 and threshold voltage Vref, and N-channel MOSFET 133 is turned on after a certain delay time is provided, and high-side power device 21 is fixed to be off. Fig. 8 is a circuit diagram showing the configuration of a driver circuit 13B of a semiconductor device 1B according to the second embodiment. In Fig. 8, the same parts as those in Fig. 5 are given the same reference numerals and detailed description thereof will be omitted.

[0064] The driver circuit 13B includes a NOT circuit 131, a P-channel MOSFET 132 (an example of a first switching element), an N-channel MOSFET 133 (an example of a second switching element), a regeneration circuit 41, a delay circuit 42, a comparator 43 (an example of a delay control unit), and a NOT circuit 441 and NOR circuits 442, 443, and 444 that constitute a signal holding unit 44.

[0065] The comparator 43 compares the voltage Vcp of the cathode terminal (K) of the diode 411 output from the regeneration circuit 41, i.e., the voltage Vcp on the high potential side of the capacitor 413, with a threshold voltage Vref based on the high side reference potential VS, and controls the start timing of the delay circuit 42 based on the comparison result.

[0066] An input terminal of the NOT circuit 441 is connected to an output terminal of the NOT circuit 131. An output terminal of the NOT circuit 441 is connected to one input terminal of a NOR circuit 442. An output terminal of a NOR circuit 443 is connected to the other input terminal of the NOR circuit 442. An output terminal of the NOR circuit 442 is connected to one input terminal of the NOR circuit 443 and one input terminal of a NOR circuit 444.

[0067] The other input terminal of the NOR circuit 443 is connected to the output terminal of the delay circuit 42. The other input terminal of the NOR circuit 444 is connected to the output terminal of the delay circuit 42. The output terminal of the NOR circuit 444 is connected to the gate terminal (G) of the N-channel MOSFET 133.

[0068] When the high-side power device 21 is in the on state, the signal holding unit 44 turns off the N-channel MOSFET 133 based on the low-level signal output from the NOT circuit 131. When the high-side power device 21 is turned off, the signal holding unit 44 receives the high-level signal output from the NOT circuit 131, but maintains the N-channel MOSFET 133 in the off state until a delayed signal is input from the delay circuit 42. When a delayed signal is input from the delay circuit 42, the signal holding unit 44 turns on the N-channel MOSFET 133.

[0069] (Operation of the high-side driver circuit 10B) Next, the operation of the high-side driver circuit 10B according to the second embodiment will be described with reference to FIG. 8 and FIG.

[0070] 9 is a signal timing diagram showing the operation of the high-side driver circuit 10B according to the second embodiment. In FIG. 9, the vertical axis represents potential, and the horizontal axis represents time. Since FIGS. 9(1) to 9(12) are the same as FIGS. 7(1) to 7(12), detailed explanations will be omitted. FIG. 9(13) shows the voltage Vcp on the high potential side of the capacitor 413 compared by the comparator 43, and the threshold voltage Vref based on the high-side reference potential VS.

[0071] In the high-side driver circuit 10A, when the control signal (IN) input to the input signal terminal 15 switches from low level to high level (time t31), as shown in FIG. 9(1), the control circuit 11 outputs a set pulse (Set) shown in FIG. 9(2) to the level shift circuit B12 (time t32).

[0072] When the set pulse (Set) is input, the level shift circuit 12 switches the signal Q of the high-side reference potential VS output to the driver circuit 13B from low level to high level (time t33), as shown in Fig. 9(5). In the driver circuit 13B, the NOT circuit 131 inverts the signal Q of the high-side reference potential VS, outputs a signal (Pg) shown in Fig. 9(6) to the gate terminal (G) of the P-channel MOSFET 132, and outputs a signal (Ng) shown in Fig. 9(7) to the gate terminal (G) of the N-channel MOSFET 133 via the signal holding unit 44.

[0073] At time t33, the P-channel MOSFET 132 is turned on and the N-channel MOSFET 133 is turned off, causing the current output from the drive power supply Vb to flow through the positive terminal 13b and the source terminal (S) and drain terminal (D) of the P-channel MOSFET 132 to a gate-emitter capacitance (not shown) formed between the gate terminal (G) and emitter terminal (E) of the high-side power device 21. As a result, the gate-emitter capacitance of the high-side power device 21 is charged, and the gate voltage HO of the gate terminal (G) of the high-side power device 21 rises.

[0074] As a result, as shown in FIG. 9(8), at time t34, a predetermined time after time t33, the gate voltage HO of the high-side power device 21 becomes higher than the high-side reference potential VS of the high-side power device 21. After a mirror period (from time t34 to time t36) has elapsed since time t34, the gate voltage HO of the high-side power device 21 rises to a voltage value that can maintain the high-side power device 21 in an on-state (time t36). In other words, the high-side power device 21 is turned on. During the mirror period, the voltage Vcp on the high-potential side of the capacitor 413 shown in FIG. 9(13) drops to near the threshold voltage Vref (time t35). As a result, the current output from the drive power supply Vb also flows through the diode 411 of the regenerative circuit 41, as shown in FIG. 9(11).

[0075] When the high-side power device 21 is turned on, the high-side reference potential VS of the high-side power device 21 shown in FIG. 9(9) gradually rises from the ground potential GND to the potential of the DC power supply Vdc (from time t34 to time t36). Also, the voltage VB (shown by a solid line in FIG. 9) applied to the positive terminal 41b shown in FIG. 9(10) gradually rises from the potential of the drive power supply Vb to the sum potential of the potentials of the DC power supply Vdc and the drive power supply Vb (shown as Vdc+Vb in FIG. 9) (from time t34 to time t36). Furthermore, the voltage Vcp (shown by a dashed line in FIG. 9) on the high-potential side of the capacitor 413 of the regenerative circuit 41 gradually rises from the potential of the drive power supply Vb to the sum potential of the potentials of the DC power supply Vdc and the drive power supply Vb (from time t34 to time t36). D1 flows into the capacitor 413, and therefore gradually rises (from time t34 to time t36).

[0076] On the other hand, as shown in FIG. 9(1), when the control signal (IN) input to the input signal terminal 15 switches from high level to low level (time t37), the control circuit 11 outputs a reset pulse (Reset) shown in FIG. 9(3) to the level shift circuit 12 (time t38), and then outputs a reset pulse (Reset2) shown in FIG. 9(4) to the regeneration circuit 41 of the driver circuit 13A (time t39).

[0077] When the reset pulse (Reset) is input, the level shift circuit 12 switches the signal Q of the high-side reference potential VS output to the driver circuit 13B from high level to low level (time t39), as shown in FIG. 9(5).

[0078] At time t39, the P-channel MOSFET 132 is turned off, and the voltage level of the gate drive signal output from the output signal terminal 13c is low. As a result, the charge accumulated in the gate-emitter capacitance of the high-side power device 21 flows to the diode 411 of the regenerative circuit 41 via the output signal terminal 13c and the signal line SL1 and is stored in the capacitor 413, thereby discharging the gate-emitter capacitance of the high-side power device 21. Note that, because the N-channel MOSFET 133 is turned off, the charge accumulated in the gate-emitter capacitance of the high-side power device 21 does not flow to the N-channel MOSFET 133 via the output signal terminal 13c and the signal line SL1. As a result, the gate voltage HO of the high-side power device 21 drops, as shown in FIG. 9(8).

[0079] When the high-side power device 21 is turned off, the N-channel MOSFET 414 is turned on for a certain period after the P-channel MOSFET 132 is turned off, and the current I D1 At this time, the charge (gate charge) accumulated in the gate-emitter capacitance of the high-side power device 21 is transferred to the capacitor 413, and the gate charge is extracted. At this time, as shown in FIG. 9(13), the voltage Vcp on the high potential side of the capacitor 413 falls below the high-side reference potential VS (time t39).

[0080] When the high-side power device 21 is turned off, the high-side reference potential VS of the high-side power device 21 shown in FIG. 9(9) gradually falls from the potential of the DC power supply Vdc to the ground potential GND (time t39 to time t41). At the same time, the voltage VB shown in FIG. 9(10) gradually falls from the sum of the potential of the DC power supply Vdc and the potential of the drive power supply Vb to the potential of the drive power supply Vb (time t39 to time t41). When the voltage VB shown in FIG. 9(10) falls, the voltage Vcp on the high-potential side of the capacitor 413 becomes relatively higher than the voltage VB (time t41). As a result, the diode 412 flows the current I shown in FIG. 9(12). D2 The charge stored in the capacitor 413 is regenerated to the driving power supply Vb via the diode 412 and the positive terminal 17.

[0081] 9(13), the voltage Vcp on the high potential side of the capacitor 413 exceeds the threshold voltage Vref (time t41). When the voltage Vcp on the high potential side of the capacitor 413 exceeds the threshold voltage Vref, the comparator 43 outputs a high-level signal to the delay circuit 42.

[0082] The delay circuit 42 outputs a delay signal to the signal holding unit 44 after a delay time has elapsed at the timing when the high-level signal output from the comparator 43 is input. When the delay signal is input from the delay circuit 42, the signal holding unit 44 outputs the high-level signal output from the NOT circuit 131, which has been held as an output, to the gate terminal (G) of the N-channel MOSFET 133, thereby turning on the N-channel MOSFET 133.

[0083] <Effects of the Second Embodiment> As described above, according to the second embodiment, by using the comparator 43 to compare the potential of the cathode of the diode 411, i.e., the voltage Vcp on the high potential side of the capacitor 413, with the threshold voltage Vref, it is possible to detect the timing at which regeneration to the drive power supply Vb ends, and to synchronize the timing at which the N-channel MOSFET 133 is turned on with the timing at which regeneration to the drive power supply Vb ends.

[0084] <Other embodiments> The technical scope of the present invention is not limited to the exemplary embodiments shown and described, but also includes all embodiments that achieve equivalent effects to the object of the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of inventive features defined by the claims, but can be defined by any desired combination of specific features from among all the respective disclosed features. [Explanation of symbols]

[0085] 1A, 1B Semiconductor device 10A, 10B, B10 High-side driver circuit 11, B11 control circuit 12,B12 Level shift circuit 13a, 15 Input signal terminals 13A, 13B, B13 driver circuit 13b,17 Positive terminal 13c, 19 Output signal terminals 13d,18 Negative terminal 13e Input signal terminal 13f,16 GND terminal 14 Power terminal 20 Power Conversion Circuit 21 High-side power devices 22 Diode 23 Inductor 30 Control device 41 Regeneration circuit 41a signal terminal 41b Electrode terminal 41b indicates the positive terminal 42 Delay Circuit 43 Comparator 44 Signal holding section 131 NOT circuit 132 P-channel MOSFETs 133 N-channel MOSFET 411,412 Diodes 413 Capacitor 441 NOT circuit 442, 443, 444 NOR circuit Vb Drive power supply Vcc main power Vdc DC power supply SL1 signal line

Claims

1. A gate drive circuit that generates a drive signal for driving a voltage-controlled switching element based on a control signal for controlling on / off of the voltage-controlled switching element supplied with power from a DC power supply, a signal line connected to a gate terminal of the voltage-controlled switching element; a first switching element connected between the positive electrode of the DC power supply and the signal line; a second switching element connected between the negative electrode of the DC power supply and the signal line; a regeneration circuit that stores the charge accumulated in the gate terminal when the voltage controlled switching element is turned on, and regenerates the charge to the DC power supply when the voltage controlled switching element is turned off; A gate drive circuit comprising:

2. The regenerative circuit includes: a first diode having an anode connected to the signal line; a second diode having an anode connected to the cathode of the first diode and a cathode connected to the positive electrode of the DC power supply; a capacitor having a high potential side connected to the cathode of the first diode and the anode of the second diode; a third switching element connected between the low potential side of the capacitor and a reference potential of a drive signal to the voltage controlled switching element; Equipped with a control unit that, when a control signal for turning on the first switching element is input, controls the first switching element to an on state and the second switching element and the third switching element to an off state, thereby outputting the drive signal from the first switching element to a gate terminal of the voltage-controlled switching element, and, when a control signal for turning off the first switching element is input, controls the first switching element to an off state and the second switching element and the third switching element to an on state, thereby stopping the output of the drive signal; a delay circuit that delays the rising edge of a signal input to a gate terminal of the second switching element; The gate drive circuit of claim 1 further comprising:

3. The control unit 3. The gate drive circuit according to claim 2, wherein after an on-period of the voltage-controlled switching element ends, the third switching element is controlled to be in an on-state for a predetermined set time, thereby transferring the charge accumulated in the gate terminal of the voltage-controlled switching element to the capacitor.

4. 3. The gate drive circuit according to claim 2, further comprising a delay control section that controls a start timing of the delay circuit so that the start timing coincides with the timing at which the potential of the cathode of the first diode exceeds a threshold voltage.

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