Semiconductor drive device

Abstract

An object of the present disclosure is to achieve high speed, robustness, and miniaturization in a semiconductor driving device equipped with a half-bridge driving circuit. [Solution] A semiconductor driver 101 includes half-bridge driver circuits 14p, 14n mounted on a first Si substrate K2 for driving a totem-pole-connected P-side semiconductor element 2p and an N-side semiconductor element 2n, and signal transmission circuits 11p, 11n mounted on a second Si substrate K1 for transmitting drive signals to the half-bridge driver circuits 14p, 14n. The P-side half-bridge driver circuit 14p and the N-side half-bridge driver circuit 14n are electrically isolated from each other by a high-voltage holding structure R1 on the first Si substrate K2.

Description

[Technical Field]

[0001] The present disclosure relates to a technique for driving a totem-pole connected power semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a configuration in which physical isolation between the transmitting circuit and the receiving circuit in a half-bridge drive circuit is achieved by a pulse transformer, and signal transmission to the P side is achieved by a high-voltage level shift with high voltage isolation. A signal from a microcomputer is transmitted to the P-side drive circuit via the physical isolation and high-voltage level shift. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-219294 Summary of the Invention [Problem to be solved by the invention]

[0004] In the case of a half-bridge drive circuit using physical isolation, it is necessary to provide separate drive units for the P side and N side, or to use a structure with separate lead frames even within the same device, which hinders miniaturization and cost reduction.

[0005] Therefore, it is necessary to reduce the size by electrically separating the physically isolated signals between the N side and P side. However, if electrical isolation is provided between the N side and P side, a high-voltage level shift must be used to transmit the signal to the P side, which raises concerns about the responsiveness of the high-voltage level shift section or robustness due to parasitic operation.

[0006] Therefore, in a half-bridge drive circuit, the high speed and robustness that are the effects of physical isolation using a pulse transformer or the like are transmitted directly to the P-side drive circuit, while the N-side and P-side circuits are integrated and made smaller, thereby realizing a half-bridge drive circuit using physical isolation.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to achieve high speed, robustness, and miniaturization in a semiconductor driving device equipped with a half-bridge driving circuit. [Means for solving the problem]

[0008] The semiconductor driving device of the present disclosure is a semiconductor driving device including a half-bridge driving circuit mounted on a first Si substrate for driving a P-side semiconductor element and an N-side semiconductor element connected in a totem pole configuration, and a signal transmission circuit mounted on a second Si substrate for transmitting a P-side driving signal for driving the P-side semiconductor element and an N-side driving signal for driving the N-side semiconductor element to the half-bridge driving circuit, wherein the half-bridge driving circuit includes a P-side half-bridge driving circuit for driving the P-side semiconductor element and an N-side half-bridge driving circuit for driving the N-side semiconductor element, and the signal transmission circuit includes a transmission circuit for transmitting the P-side driving signal and the N-side driving signal, a P-side pulse transformer for transmitting the P-side driving signal transmitted from the transmission circuit to the P-side half-bridge driving circuit, and a P-side pulse transformer for transmitting the P-side driving signal transmitted from the transmission circuit to the P-side half-bridge driving circuit. and an N-side pulse transformer that transmits the N-side drive signal received from the transmitter circuit to an N-side half-bridge drive circuit, the P-side half-bridge drive circuit being connected to the P-side pulse transformer by a wire and comprising: a P-side receiving circuit that receives the P-side drive signal from the transmitter circuit via the P-side pulse transformer; and a P-side drive circuit that drives the P-side semiconductor elements by the P-side drive signal received by the P-side receiving circuit, the N-side half-bridge drive circuit being connected to the N-side pulse transformer by a wire and comprising: an N-side receiving circuit that receives the N-side drive signal from the transmitter circuit via the N-side pulse transformer; and an N-side drive circuit that drives the N-side semiconductor elements by the N-side drive signal received by the N-side receiving circuit, and the P-side half-bridge drive circuit and the N-side half-bridge drive circuit are electrically isolated by a high-voltage holding structure on the first Si substrate. [Effects of the Invention]

[0009] The semiconductor driver of the present disclosure achieves high speed, robustness, and compactness.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram showing the configuration of a semiconductor drive device according to the first prior art. [Figure 2] It is a diagram showing the package configuration of a semiconductor drive device according to the first prior art. [Figure 3] It is a diagram showing the package configuration of a semiconductor drive device according to the second prior art. [Figure 4] It is a diagram showing the configuration of a semiconductor drive device according to Embodiment 1. [Figure 5] It is a diagram showing the package configuration of a semiconductor drive device according to Embodiment 1. [Figure 6] [[ID=二十ー]]It is a diagram showing the configuration on the lead frame in the semiconductor drive device according to Embodiment 1.

Modes for Carrying Out the Invention

[0011] <A. Prior Art> FIG. 1 shows the configuration of a semiconductor drive device 101 according to the first prior art. The semiconductor drive device 101 receives a signal from an MCU (Micro Controller Unit) 1 and drives power semiconductor elements 2p and 2n.

[0012] The power semiconductor element 2p is a P-side power semiconductor element, and the power semiconductor element 2n is an N-side power semiconductor element. The power semiconductor elements 2p and 2n are each composed of an IGBT (Insulated Gate Bipolar Transisto) and a diode connected in parallel to the IGBT.

[0013] A power supply V is arranged between the collector terminal of the IGBT constituting the power semiconductor element 2p and the reference potential V1.

[0014] The emitter terminal of the IGBT constituting power semiconductor element 2n is connected to reference potential V1. The emitter terminal of the IGBT constituting power semiconductor element 2p is connected to the collector terminal of the IGBT constituting power semiconductor element 2n, and the output terminal OUT is drawn from this connection point. In this way, power semiconductor elements 2p and 2n are totem-pole connected.

[0015] The semiconductor driving device 101 includes a P-side driver 21p and an N-side driver 21n. The P-side driver 21p includes a P-side signal transmission circuit 11p and a P-side half-bridge driving circuit 14p.

[0016] The P-side signal transmission circuit 11p includes a P-side transmission circuit 12p and a P-side pulse transformer 13p.

[0017] The P-side transmission circuit 12p receives a signal from the MCU1 with V3 as the reference potential, and transmits a P-side drive signal for driving the power semiconductor device 2p to the P-side half-bridge drive circuit 14p.

[0018] The P-side half-bridge drive circuit 14p is configured to include a P-side receiving circuit 15p and a P-side drive circuit 16p.

[0019] The P-side transmitter circuit 12p and the P-side half-bridge driver circuit 14p are physically insulated from each other by a P-side pulse transformer 13p. A P-side drive signal transmitted from the P-side transmitter circuit 12p, with V3 as its reference potential, is received by a P-side receiver circuit 15p as a P-side drive signal with V2 as its reference potential via the P-side pulse transformer 13p, and is then transmitted from the P-side receiver circuit 15p to a P-side driver circuit 16p. The P-side driver circuit 16p drives the power semiconductor element 2p with the P-side drive signal with V2 as its reference potential. V2 is higher than V1.

[0020] The N-side driver 21n includes an N-side signal transmission circuit 11n and an N-side half-bridge drive circuit 14n.

[0021] The N-side signal transfer circuit 11n includes an N-side transmission circuit 12n and an N-side pulse transformer 13n.

[0022] The N-side transmission circuit 12n receives a signal from the MCU1 with V3 as the reference potential, and transmits an N-side drive signal for driving the power semiconductor device 2n to the N-side half-bridge drive circuit 14n.

[0023] The N-side half-bridge drive circuit 14n includes an N-side receiver circuit 15n and an N-side drive circuit 16n.

[0024] The N-side transmitter circuit 12n and the N-side half-bridge driver circuit 14n are physically insulated from each other by an N-side pulse transformer 13n. An N-side drive signal having V3 as a reference potential transmitted from the N-side transmitter circuit 12n is received by an N-side receiver circuit 15n as an N-side drive signal having V1 as a reference potential via the N-side pulse transformer 13n, and is then transmitted from the N-side receiver circuit 15n to an N-side driver circuit 16n. The N-side driver circuit 16n drives the power semiconductor device 2n by the N-side drive signal having V1 as a reference potential.

[0025] 2 is a diagram showing a package configuration of the semiconductor driving device 101. In the semiconductor driving device 101, the N-side driver 21n is configured as an N-side driver module 21nm that is separate from the P-side driver module 21pm that configures the P-side driver 21p.

[0026] Terminals T11n, T12n, T13n, T14n, T15n, and T16n are exposed from the side of the package of the N-side driver module 21nm. A signal from the MCU 1 is input to the terminal T11n. An N-side drive signal from the N-side drive circuit 16n is input to the gate terminal of the IGBT that constitutes the power semiconductor element 2n via the terminal T15n.

[0027] As described above, the semiconductor driving device 101 according to the first prerequisite technology requires separate driving devices, the P-side driver 21p and the N-side driver 21n, to be provided on the P-side and N-side, respectively, which poses challenges in miniaturization and cost reduction.

[0028] 3 is a diagram showing the package configuration of a semiconductor driving device 102 according to the second prerequisite technology. The configuration of the semiconductor driving device 102 will be described below. The semiconductor driving device 102 has a configuration similar to that of the semiconductor driving device 101, realized in a single module 21m. While the semiconductor driving device 101 has two signal transmission circuits, a P-side signal transmission circuit 11p and an N-side signal transmission circuit 11n, the semiconductor driving device 102 has only one signal transmission circuit 11.

[0029] The signal transmission circuit 11 includes a transmission circuit 12, a P-side pulse transformer 13p, and an N-side pulse transformer 13n.

[0030] The transmission circuit 12 receives signals from the MCU 1 with V3 as the reference potential, and transmits an N-side drive signal for driving the power semiconductor device 2n and a P-side drive signal for driving the power semiconductor device 2p.

[0031] The transmitter circuit 12 and the P-side half-bridge driver circuit 14p are physically insulated from each other by a P-side pulse transformer 13p. A P-side drive signal transmitted from the transmitter circuit 12, with V3 as its reference potential, is received by a P-side receiver circuit 15p via the P-side pulse transformer 13p as a P-side drive signal with V2 as its reference potential, and is then transmitted from the P-side receiver circuit 15p to a P-side driver circuit 16p. The P-side driver circuit 16p drives the power semiconductor element 2p with the P-side drive signal with V2 as its reference potential. V2 is higher than V1.

[0032] The transmitter circuit 12 and the N-side half-bridge driver circuit 14n are physically insulated from each other by an N-side pulse transformer 13n. An N-side drive signal transmitted from the transmitter circuit 12 with V3 as its reference potential is received by an N-side receiver circuit 15n via the N-side pulse transformer 13n as an N-side drive signal with V1 as its reference potential, and is then transmitted from the N-side receiver circuit 15n to an N-side driver circuit 16n. The N-side driver circuit 16n drives the power semiconductor device 2n with the N-side drive signal with V1 as its reference potential.

[0033] The signal transmission circuit 11 is mounted on the lead frame L1. The P-side half-bridge drive circuit 14p is mounted on the lead frame L2p. The N-side half-bridge drive circuit 14n is mounted on the lead frame L2n.

[0034] From the side of the module 21m, the terminals T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and T12 are exposed. A signal from the MCU1 is input to the terminal T2. The P-side drive signal from the P-side drive circuit 16p is input to the gate terminal of the IGBT constituting the power semiconductor element 2p through the terminal T8. The N-side drive signal from the N-side drive circuit 16n is input to the gate terminal of the IGBT constituting the power semiconductor element 2n through the terminal T11.

[0035] In the semiconductor drive device 102 according to the second prior art, the signal transmission circuit 11, the P-side half-bridge drive circuit 14p, and the N-side half-bridge drive circuit 14n can be realized by one module 21m. However, in the module 21m, since the P-side half-bridge drive circuit 14p and the N-side half-bridge drive circuit 14n need to be mounted on different lead frames, there are problems in miniaturization and cost reduction.

[0036] <B. Embodiment 1> Therefore, in the semiconductor drive device according to the following Embodiment 1, by integrating the P-side half-bridge drive circuit and the N-side half-bridge drive circuit on one lead frame, while ensuring the high speed and robustness which are the effects of physical insulation using a pulse transformer, miniaturization of the semiconductor drive device is realized.

[0037] FIG. 4 shows the configuration of the semiconductor drive device 111 according to Embodiment 1. The semiconductor drive device 111 is different from the semiconductor drive device 102 according to the second prior art in that in the half-bridge drive circuit 14, the P-side half-bridge drive circuit 14p and the N-side half-bridge drive circuit 14n are electrically insulated by the high-voltage holding structure R1. The high-voltage holding structure R1 may be a high-voltage RESURF structure using a pn junction, or may be a structure using dielectric isolation.

[0038] FIG. 5 is a diagram showing a package configuration of the semiconductor driving device 111 according to the first embodiment.

[0039] The signal transmission circuit 11 is mounted on a lead frame L1, and the half-bridge drive circuit 14 is mounted on a lead frame L2. The lead frames L1 and L2 are physically insulated from each other. When the signal transmission circuit 11 and the half-bridge drive circuit 14 of the semiconductor drive device 111 are configured in the same package 111m, the lead frames L1 and L2 are physically insulated from each other by a highly insulating resin.

[0040] FIG. 6 shows the configuration on the lead frame L1 and the lead frame L2 in the semiconductor driving device 111 according to the first embodiment.

[0041] A silicon (Si) substrate K1 is provided on the lead frame L1. The transmitting circuit 12, a P-side pulse transformer 13p, and an N-side pulse transformer 13n are mounted on the Si substrate K1. Note that the N-side pulse transformer 13n is not shown in FIG. 6.

[0042] A silicon (Si) substrate K2, which is a substrate separate from the Si substrate K1, is provided on the lead frame L2. The Si substrate K2 is also referred to as a first Si substrate, and the Si substrate K1 is also referred to as a second Si substrate. An N-side half-bridge drive circuit 14n and a P-side half-bridge drive circuit 14p are mounted on the Si substrate K2. However, the N-side half-bridge drive circuit 14n and the P-side half-bridge drive circuit 14p are electrically insulated from each other by a high-voltage holding structure R1.

[0043] The P-side pulse transformer 13p and the P-side receiving circuit 15p are directly connected by a wire W2, and the P-side drive signal is transmitted through this path. In this way, a high-voltage level shifter is not used to transmit the P-side drive signal. The wire W2 is made of gold, aluminum, or copper.

[0044] The N-side pulse transformer 13n and the P-side pulse transformer 13p may be capacitors that perform capacitive coupling, or may be photocouplers that perform optical coupling.

[0045] In the semiconductor driving device 111 according to the first embodiment, the P-side half-bridge driving circuit 14p and the N-side half-bridge driving circuit 14n are integrated on one lead frame L2, thereby realizing miniaturization of the semiconductor driving device 111 while ensuring high speed and robustness, which are the effects of physical isolation using the N-side pulse transformer 13n and the P-side pulse transformer 13p.

[0046] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims.

[0047] Various aspects of the present disclosure are summarized below as appendices.

[0048] (Appendix 1) a half-bridge drive circuit mounted on the first Si substrate for driving the totem-pole-connected P-side semiconductor element and N-side semiconductor element; a signal transmission circuit mounted on a second Si substrate, which transmits a P-side drive signal for driving the P-side semiconductor element and an N-side drive signal for driving the N-side semiconductor element to the half-bridge drive circuit, The half-bridge drive circuit a P-side half-bridge drive circuit that drives the P-side semiconductor element; an N-side half-bridge drive circuit that drives the N-side semiconductor element; The signal transmission circuit includes: a transmission circuit for transmitting the P-side drive signal and the N-side drive signal; a P-side pulse transformer that transmits the P-side drive signal transmitted from the transmission circuit to the P-side half-bridge drive circuit; an N-side pulse transformer that transmits the N-side drive signal transmitted from the transmission circuit to the N-side half-bridge drive circuit, The P-side half-bridge drive circuit comprises: a P-side receiving circuit connected to the P-side pulse transformer by a wire and receiving the P-side drive signal from the transmitting circuit via the P-side pulse transformer; a P-side drive circuit that drives the P-side semiconductor element by the P-side drive signal received by the P-side receiver circuit, The N-side half-bridge drive circuit an N-side receiving circuit connected to the N-side pulse transformer by a wire and receiving the N-side drive signal from the transmitting circuit via the N-side pulse transformer; an N-side drive circuit that drives the N-side semiconductor element by the N-side drive signal received by the N-side receiver circuit, the P-side half-bridge drive circuit and the N-side half-bridge drive circuit are electrically separated by a high-voltage holding structure on the first Si substrate; Semiconductor drive device.

[0049] (Appendix 2) The high voltage holding structure is a high voltage RESURF structure using a pn junction. 2. The semiconductor driving device according to claim 1.

[0050] (Appendix 3) the high voltage holding structure is a structure using dielectric isolation; 2. The semiconductor driving device according to claim 1.

[0051] (Appendix 4) The P-side pulse transformer and the N-side pulse transformer are capacitively coupled using capacitors. 4. The semiconductor driving device according to claim 1, wherein the semiconductor driving device is a semiconductor device having a first insulating film.

[0052] (Appendix 5) The P-side pulse transformer and the N-side pulse transformer are optically coupled using a photocoupler. 4. The semiconductor driving device according to claim 1, wherein the semiconductor driving device is a semiconductor device having a first insulating film. [Explanation of symbols]

[0053] 2n,2p power semiconductor element, 11 signal transmission circuit, 11n N-side signal transmission circuit, 11p P-side signal transmission circuit, 12 transmitting circuit, 12n N-side transmitting circuit, 12p P-side transmitting circuit, 13n N-side pulse transformer, 13p P-side pulse transformer, 14 half-bridge drive circuit, 14n N-side half-bridge drive circuit, 14p P-side half-bridge drive circuit, 15n N-side receiving circuit, 15p P-side receiving circuit, 16n N-side drive circuit, 16p P-side drive circuit, 21m module, 21n N-side driver, 21nm N-side driver module, 21p P-side driver, 21pm P-side driver module, 101,102 semiconductor drive device, 111 semiconductor drive device, 111m package, K1,K2 Si substrate, L1,L2,L2n,L2p lead frame, R1 high voltage holding structure.

Claims

1. a half-bridge drive circuit mounted on the first Si substrate for driving the totem-pole-connected P-side semiconductor element and N-side semiconductor element; a signal transmission circuit mounted on a second Si substrate, which transmits a P-side drive signal for driving the P-side semiconductor element and an N-side drive signal for driving the N-side semiconductor element to the half-bridge drive circuit, The half-bridge drive circuit a P-side half-bridge drive circuit that drives the P-side semiconductor element; an N-side half-bridge drive circuit that drives the N-side semiconductor element, The signal transmission circuit includes: a transmission circuit for transmitting the positive drive signal and the negative drive signal; a P-side pulse transformer that transmits the P-side drive signal transmitted from the transmission circuit to the P-side half-bridge drive circuit; an N-side pulse transformer that transmits the N-side drive signal transmitted from the transmission circuit to the N-side half-bridge drive circuit, The P-side half-bridge drive circuit comprises: a positive-side receiving circuit connected to the positive-side pulse transformer by a wire and receiving the positive-side drive signal from the transmitting circuit via the positive-side pulse transformer; a P-side drive circuit that drives the P-side semiconductor element by the P-side drive signal received by the P-side receiver circuit, The N-side half-bridge drive circuit comprises: an N-side receiving circuit connected to the N-side pulse transformer by a wire and receiving the N-side drive signal from the transmitting circuit via the N-side pulse transformer; an N-side drive circuit that drives the N-side semiconductor element by the N-side drive signal received by the N-side receiver circuit, the P-side half-bridge drive circuit and the N-side half-bridge drive circuit are electrically separated by a high-voltage holding structure on the first Si substrate; Semiconductor drive device.

2. the high-voltage holding structure is a high-voltage RESURF structure using a pn junction; 2. The semiconductor driving device according to claim 1.

3. the high voltage holding structure is a structure using dielectric isolation; 2. The semiconductor driving device according to claim 1.

4. The P-side pulse transformer and the N-side pulse transformer are capacitively coupled using capacitors.

2. The semiconductor driving device according to claim 1.

5. The P-side pulse transformer and the N-side pulse transformer are optically coupled using a photocoupler.

2. The semiconductor driving device according to claim 1.

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