Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device 1 capable of suppressing wafer warpage and thinning a silicon substrate 11, and a manufacturing method thereof are provided. [Solution] The semiconductor device 1 has a silicon substrate 11, a compressive stress layer 12 disposed on a first main surface 11A of the silicon substrate 11 and having compressive stress generated as residual stress in the outer edge direction along the first main surface, a first metal layer 13 disposed on the main surface 12A of the compressive stress layer 12, a first resin layer 14 disposed on the main surface 13A of the first metal layer 13, and second metal layers 15a, 15b disposed on the main surface 14A of the first resin layer 14. Distributed constant circuits are formed in at least the second metal layers 15a, 15b.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Circuit elements for mobile communications using frequencies in the millimeter wave band (30-300 GHz) and quasi-millimeter wave band (less than 30 GHz) are designed based on distributed constant circuits due to their reduced loss and ease of fabrication. For example, Patent Document 1 proposes a quasi-millimeter wave band bandpass filter in which multiple resonators that are electromagnetically coupled to each other are formed using multiple dielectric layers. Non-Patent Document 2 also proposes a bandpass filter having a transmission line structure formed on a semiconductor substrate. Non-Patent Document 1 realizes a bandpass filter by fabricating a layered structure of a ground electrode / resin layer / transmission line on a silicon substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-57920 [Non-patent literature]

[0004] [Non-Patent Document 1] G. Prigent et al., IEEE Trans. Microw. Theory Techn. 52, 1045 (2004).

[0005] [overview] When using a laminated structure of dielectric layers, the circuit elements become thicker. Furthermore, if the thickness is reduced, mechanical reliability cannot be guaranteed. Therefore, in applications where thinness is required, such as user terminals, mounting can be difficult.

[0006] When using a silicon substrate, circuit elements can be made thinner by grinding the silicon substrate. However, thinning the silicon wafer makes it more susceptible to warping due to the tensile stress of the resin. Warping of the silicon wafer can cause problems when the silicon wafer is being picked up or transported. Warping can also cause cracks in the resin layer.

[0007] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress wafer warpage and thin a silicon substrate.

[0008] The semiconductor device of the present disclosure includes a silicon substrate, a compressive stress layer disposed on a first main surface of the silicon substrate and having compressive stress generated as residual stress in an outer peripheral direction along the first main surface, a first metal layer disposed on the main surface of the compressive stress layer, a first resin layer disposed on the main surface of the first metal layer, and a second metal layer disposed on the main surface of the first resin layer, wherein a distributed constant circuit is formed in at least the second metal layer.

[0009] A method for manufacturing a semiconductor device according to the present disclosure includes: preparing a silicon substrate; forming a compressive stress layer on a first main surface of the silicon substrate, the compressive stress layer causing compressive stress in an outer peripheral direction along the first main surface as residual stress; forming a first metal layer on the main surface of the compressive stress layer; forming a first resin layer on the main surface of the first metal layer; and forming a second metal layer on the main surface of the first resin layer. A distributed constant circuit is formed in at least the second metal layer. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device 1 according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing an example of a band-pass filter, which is an example of a distributed constant circuit included in the semiconductor device 1 of FIG. [Figure 3A] FIG. 3A is a cross-sectional view showing an image of residual stress (tensile stress) occurring in a resin layer formed on a silicon substrate. [Figure 3B]FIG. 3B is a cross-sectional view showing an image of residual stress (compressive stress) occurring in a compressive stress layer formed on a silicon substrate. [Figure 4A] FIG. 4A is a cross-sectional view (part 1) showing one manufacturing step in an example of a method for manufacturing the semiconductor device 1 of FIG. [Figure 4B] FIG. 4B is a cross-sectional view (part 2) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 4C] FIG. 4C is a cross-sectional view (part 3) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 4D] FIG. 4D is a cross-sectional view (part 4) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 4E] FIG. 4E is a cross-sectional view (part 5) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 4F] FIG. 4F is a cross-sectional view (No. 6) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 4G] FIG. 4G is a cross-sectional view (part 7) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 4H] FIG. 4H is a cross-sectional view (part 8) showing another manufacturing step in the example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 5A] FIG. 5A is a cross-sectional view for explaining a first reference example in which a support substrate is bonded to a semiconductor device. [Figure 5B] FIG. 5B is a cross-sectional view for explaining a second reference example (half dicing) in which the silicon substrate is cut partway. [Figure 6] FIG. 6 is a graph showing the relationship between the film thickness of the compressive stress layer and the total film thickness of the resin layers when a balance is achieved between the tensile stress of the resin layer and the compressive stress of the compressive stress layer. [Figure 7] FIG. 7 is a cross-sectional view showing another example of a band-pass filter, which is an example of a distributed constant circuit included in the semiconductor device 1 of FIG. [Figure 8A]FIG. 8A is a cross-sectional view (part 1) showing one manufacturing step in another example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 8B] FIG. 8B is a cross-sectional view (part 2) showing another manufacturing step in another example of the manufacturing method for the semiconductor device 1 of FIG. [Figure 8C] FIG. 8C is a cross-sectional view (part 3) showing another manufacturing step in another example of the manufacturing method for the semiconductor device 1 of FIG. [Figure 8D] FIG. 8D is a cross-sectional view (part 4) showing another manufacturing step in another example of the manufacturing method for the semiconductor device 1 of FIG. [Figure 8E] FIG. 8E is a cross-sectional view (part 5) showing another manufacturing step in another example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 8F] FIG. 8F is a cross-sectional view (No. 6) showing another manufacturing step in another example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 8G] FIG. 8G is a cross-sectional view (part 7) showing another manufacturing step in another example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 8H] FIG. 8H is a cross-sectional view (part 8) showing another manufacturing step in another example of the manufacturing method of the semiconductor device 1 of FIG. [Figure 9] FIG. 9 is a graph showing the relationship between the residual stress of a silicon oxynitride film (Si2N2O film), which is an example of a compressive stress layer, and the heat treatment temperature. [Figure 10] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 2 according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device 3 according to the third embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing the configuration of a semiconductor device 4 according to the fourth embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device 5 according to the fifth embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing the configuration of a semiconductor device 6 according to the sixth embodiment.

[0011] [Detailed explanation] Hereinafter, embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present disclosure will be described in detail with reference to the drawings. The embodiments are comprehensive or specific examples. The numerical values, shapes, materials, components, and the installation positions and connection forms of the components shown in the embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts will be described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and similar components will be assigned common reference numerals and redundant explanations will be omitted.

[0012] (First embodiment) The configuration of a semiconductor device 1 according to a first embodiment will be described with reference to FIG. 1. The semiconductor device 1 includes a silicon substrate (Si substrate) 11, a compressive stress layer 12 disposed on a first main surface 11A of the Si substrate 11, and having compressive stress acting as residual stress in the outer peripheral direction along the first main surface 11A, a first metal layer 13 disposed on the main surface 12A of the compressive stress layer 12, a first resin layer 14 disposed on the main surface 13A of the first metal layer 13, and second metal layers 15a and 15b disposed on the main surface 14A of the first resin layer 14. Although not shown in FIG. 1, distributed constant circuits are formed on at least the second metal layers 15a and 15b in the semiconductor device 1. The distributed constant circuits formed on the second metal layers 15a and 15b will be described later with reference to FIG. 2.

[0013] The semiconductor device 1 further includes a second resin layer 16 disposed on the main surfaces of the second metal layers 15a and 15b, and third metal layers 17a and 17b disposed on the main surfaces of the second resin layer 16. The second resin layer 16 is also disposed on the first resin layer 14 on which the second metal layers 15a and 15b are not disposed.

[0014] The semiconductor device 1 further includes a through via 20 (second through via) that penetrates the first resin layer 14 and the second resin layer 16 in the stacking direction and electrically connects the first metal layer 13 and the third metal layer 17a. The through via 20 includes a first through portion 30 that penetrates the first resin layer 14 and a second through portion 19a that penetrates the second resin layer 16. A first end of the first through portion 30 and a first end of the second through portion 19a are electrically connected. A second end of the first through portion 30 and the first metal layer 13 are electrically connected. A second end of the second through portion 19a and the third metal layer 17a are electrically connected.

[0015] The semiconductor device 1 further includes a through via 19b that penetrates the second resin layer 16 in the stacking direction and electrically connects the second metal layer 15b and the third metal layer 17b.

[0016] The compressive stress layer 12 includes, for example, a layer in which at least one of oxygen (O) and nitrogen (N) is bonded to silicon (Si). For example, the layer in which at least one of O and N is bonded to Si includes a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), and a silicon oxynitride film (Si2N2O film). Hereinafter, the silicon oxide film, the silicon nitride film, and the silicon oxynitride film will be referred to as an SiO film, an SiN film, and an SiNO film, respectively. Note that, in the first embodiment, the compressive stress layer 12 will be described as having a single-layer structure of any of an SiO film, an SiN film, and an SiNO film, but may have a stacked structure in which two or more layers selected from an SiO film, an SiN film, and an SiNO film are stacked.

[0017] In the first embodiment, a case will be described in which the compressive stress layer 12 includes a layer in which at least one of oxygen (O) and nitrogen (N) is bonded to silicon (Si). However, the compressive stress layer 12 is not limited to this, and other insulators or conductors that generate compressive stress as residual stress may be used.

[0018] Each of the first resin layer 14 and the second resin layer 16 contains at least one material selected from the group consisting of benzocyclobutene (BCB), polyphenylene ether, epoxy resin, polyimide, fluororesin, and liquid crystal polymer. In the first embodiment, the first resin layer 14 and the second resin layer 16 each have a single-layer structure containing one material selected from the group. Alternatively, each of the first resin layer 14 and the second resin layer 16 may have a multi-layer structure including two or more layers made of two or more materials selected from the group. For example, the first resin layer 14 and the second resin layer 16 may have a multi-layer structure including a first layer containing BCB and a second layer containing epoxy resin. Alternatively, the first resin layer 14 and the second resin layer 16 may contain different materials.

[0019] The first metal layer 13, the second metal layers 15a and 15b, and the third metal layers 17a and 17b each include a layer containing at least one element selected from the group consisting of copper (Cu), gold (Au), and silver (Ag). The through vias 19b and 20 each include a layer containing at least one element selected from the group consisting of Cu, Au, and Ag. The first metal layer 13, the second metal layers 15a and 15b, the third metal layers 17a and 17b, the through vias 19b, and the through vias 20 may be layers containing different elements or layers containing the same element.

[0020] The first metal layer 13 is a ground electrode layer having a thickness equal to or greater than the thickness at which the skin effect is achieved. By having a thickness equal to or greater than the thickness at which the skin effect is achieved, leakage of the electromagnetic field to the Si substrate 11 side can be suppressed, so that the frequency characteristics of the distributed constant circuit are not impaired. The first metal layer 13 is connected to the third metal layer 17a, which serves as an electrode pad, by a through via 20. A ground potential can be applied to the first metal layer 13 from the outside through the third metal layer 17a.

[0021] The first metal layer 13 includes a diffusion prevention film 13a for preventing diffusion of metal or Si between the first metal layer 13 and the compressive stress layer 12, and a main layer 13b containing at least one element selected from the group consisting of Cu, Au, and Ag. The diffusion prevention film 13a is disposed on the main surface 12A of the compressive stress layer 12, and the main layer 13b is disposed on the diffusion prevention film 13a. The diffusion prevention film 13a prevents the diffusion of metal contained in the main layer 13b into the compressive stress layer 12 and the diffusion of Si and other elements contained in the compressive stress layer 12 into the main layer 13b. The diffusion prevention film 13a can be made of, for example, tantalum (Ta), titanium (Ti), tungsten (W), or nitrides of these metals. Instead of the diffusion prevention film 13a, the first metal layer 13 may have an adhesion layer to improve adhesion to the compressive stress layer 12.

[0022] Referring to Fig. 2, an example of a bandpass filter, which is an example of a distributed constant circuit included in the semiconductor device 1 of Fig. 1, will be described. The bandpass filter 15 shown in Fig. 2 is formed on at least the second metal layers 15a and 15b of Fig. 1. In the first embodiment, the bandpass filter 15 is formed on the second metal layers 15a and 15b, the first metal layer 13 acts as a ground electrode layer, and the third metal layers 17a and 17b have electrode pads formed thereon that are connected to the input wiring and output wiring of the bandpass filter 15. It should be noted that the planar structure of Fig. 2 does not exactly correspond to the cross-sectional structure of Fig. 1.

[0023] The frequency (f0) targeted by the bandpass filter 15 is, for example, the millimeter wave band (30-300 GHz) and the quasi-millimeter wave band (less than 30 GHz).

[0024] As shown in FIG. 2, the bandpass filter 15 includes a plurality of transmission line pairs 152-157, an input wiring 151 that supplies signals to the plurality of transmission line pairs 152-157, and an output wiring 158 that outputs signals passing through the plurality of transmission line pairs 152-157. The input wiring 151 and the output wiring 158 are transmission lines whose impedance is adjusted to, for example, 50Ω to suppress reflection by impedance matching. Each of the plurality of transmission line pairs 152-157 is a pair of transmission lines having a length of ¼ of the wavelength (λ) at the frequency (f0). Each of the plurality of transmission line pairs 152-157 is electromagnetically coupled. One transmission line of each of the transmission line pairs 152-157 is electrically connected to one transmission line of the adjacent transmission line pairs 152-157. The two electrically connected transmission lines form a transmission line having a length of λ / 2. A transmission line with a length of λ / 2 acts as a resonator at frequency (f0).

[0025] By adjusting the length and width of each transmission line and the spacing between the two transmission lines that make up a transmission line pair, filter characteristics such as Chebyshev characteristics and Butterworth characteristics can be obtained. The number of transmission line pairs 152 to 157 used is determined by the order of the bandpass filter 15 that is to be realized.

[0026] A through via 191 is formed at the end of the input wiring 151. A through via 192 is formed at the end of the output wiring 158. The through vias 191 and 192 are vias that penetrate the second resin layer 16 in FIG. 1 and are connected to electrode pads (not shown) that are arranged on the third metal layer.

[0027] The linear expansion coefficients of the first resin layer 14 and the second resin layer 16 are larger than the linear expansion coefficient of the Si substrate 11. As a result, as shown in FIG. 3A, a tensile stress TF is generated in the first resin layer 14 and the second resin layer 16 as a residual stress in the outer edge direction along the first main surface 11A.

[0028] The linear expansion coefficient of the compressive stress layer 12 in the direction along the first main surface 11A (hereinafter simply referred to as "linear expansion coefficient") is smaller than the linear expansion coefficient of the Si substrate 11. As a result, as shown in FIG. 3B, a compressive stress CF is generated in the compressive stress layer 12 as residual stress in the outer peripheral direction along the first main surface 11A.

[0029] By disposing the compressive stress layer 12 between the Si substrate 11 and the first metal layer 13, it is possible to achieve a balance between the tensile stress TF due to the first resin layer 14 and the second resin layer 16 and the compressive stress CF due to the compressive stress layer 12. This prevents the Si substrate 11 from warping, allowing the Si substrate 11 to be made thinner. This makes the semiconductor device 1 suitable for thin elements (low-pass filters, band-pass filters, filtering antennas, matching circuits) for the millimeter wave band or quasi-millimeter wave band, more specifically, for 28 GHz band band-pass filters that can be mounted on user terminals (smartphones).

[0030] Next, an example of a method for manufacturing the semiconductor device 1 of FIG. 1 will be described with reference to FIGS. 4A to 4H.

[0031] First, a wafer-like Si substrate 11 is prepared before being divided into individual pieces. The crystallinity of the Si substrate 11 is not particularly important, and it may be single-crystal Si, polycrystalline Si, or amorphous Si. The thickness of the Si substrate 11 is set to a value that provides sufficient mechanical strength for handling the wafer during manufacturing.

[0032] As shown in Fig. 4A, a compressive stress layer 12 is formed on the first main surface 11A of the Si substrate 11. Specifically, a thermally oxidized Si film is formed on the first main surface 11A of the Si substrate 11. In more detail, the Si substrate 11 is subjected to a heat treatment (annealing) in an oxygen atmosphere to form a thermally oxidized Si film (SiO film) on the entire exposed surface including the first main surface 11A and the second main surface 11Ba of the Si substrate 11. The process temperature is 800°C to 1200°C, and the reactive gas is high-purity oxygen gas or water vapor.

[0033] Next, a first metal layer 13 is formed on the main surface 12A of the compressive stress layer 12. Specifically, as shown in FIG. 4B, a diffusion prevention film 13a is formed on the compressive stress layer 12. A main layer 13b containing at least one element selected from the group consisting of Cu, Au, and Ag is formed on the diffusion prevention film 13a. The first metal layer 13 can be formed by sputtering, CVD (Chemical Vapor Deposition), or the like.

[0034] 4C, a first resin layer 14 is formed on the main surface 13A of the first metal layer 13. The first resin layer 14 can be formed by a spin coating method in which a resin solution is dropped onto the wafer and the wafer is rotated, a CVD method, or the like.

[0035] As shown in FIG. 4D, second metal layers 15a and 15b are formed on the main surface 14A of the first resin layer 14. For example, a seed layer for the second metal layers 15a and 15b is formed on the entire surface, a resist film is patterned by photolithography, and a metal film is selectively formed in the openings of the resist film by electroplating. Then, the resist film and the exposed seed layer are peeled off in order to form the second metal layers 15a and 15b, each consisting of the seed layer and the metal film.

[0036] As shown in FIG. 4D , the first through portion 30 is formed inside the first resin layer 14. For example, if a photosensitive first resin layer 14 is used, the first resin layer 14 can be directly patterned by photolithography to form the hole. If the first resin layer 14 is not photosensitive, the hole can be formed in the first resin layer 14 by laser processing or the like. The first through portion 30 can be formed by embedding a metal film in the hole formed in the first resin layer 14. The order in which the second metal layers 15a, 15b and the first through portion 30 are formed does not matter.

[0037] As shown in Fig. 4E, a second resin layer 16 is formed on the second metal layers 15a and 15b, the first penetrating portion 30, and the main surface 14A of the first resin layer 14. The second resin layer 16 can be formed by a method similar to that for the first resin layer 14. For example, the bandpass filter 15 having the layout shown in Fig. 2 can be formed as the second metal layers 15a and 15b in Fig. 4E.

[0038] 4F, third metal layers 17a and 17b are formed on the main surface 16A of the second resin layer 16. Second penetrating portions 19a and through vias 19b are formed inside the second resin layer 16. The third metal layers 17a and 17b can be formed using a method similar to that for the second metal layers 15a and 15b. The second penetrating portions 19a and through vias 19b can be formed using a method similar to that for the first penetrating portion 30.

[0039] The Si substrate 11 and a portion of the compressive stress layer 12 are ground from the second main surface 11Ba side of the Si substrate 11 shown in Fig. 4F to thin the Si substrate 11 as shown in Fig. 4G. For example, the Si substrate 11 is thinned to a thickness of several tens of micrometers.

[0040] As shown in FIG. 4H, the wafer-like Si substrate 11 is diced into individual pieces, thereby manufacturing the semiconductor device 1 shown in FIG.

[0041] By disposing the compressive stress layer 12 between the Si substrate 11 and the first metal layer 13, the tensile stress TF due to the first resin layer 14 and the second resin layer 16 is offset by the compressive stress CF due to the compressive stress layer 12. This suppresses warping of the Si substrate 11. Therefore, as shown in FIG. 4G, it is possible to suppress warping of the Si substrate 11 when the Si substrate 11 is thinned.

[0042] Therefore, as shown in FIG. 5A, there is no need to bond a support substrate 51 to the third metal layers 17a, 17b to suppress wafer warpage before thinning the Si substrate 53. The steps of bonding and peeling the support substrate 51 are no longer necessary. This reduces manufacturing costs. Furthermore, as shown in FIG. 5B, there is no need for the half-dicing step of cutting the Si substrate 53 halfway to relieve residual stress in the resin layer before thinning the Si substrate 53. Setting the groove depth is no longer necessary, which reduces the development costs of the manufacturing process. If the groove is too deep, problems such as cracking of the Si substrate 53 may occur when laminating the laminate film.

[0043] The thickness of the compressive stress layer 12 is set according to the total thickness of the first resin layer 14 and the second resin layer 16 so that the compressive stress CF and the tensile stress TF cancel each other out. FIG. 6 is a graph showing the relationship between the thickness of the compressive stress layer 12 and the total thickness of the resin layers 14 and 16 when the residual stresses between the resin layers 14 and 16 and the compressive stress layer 12 cancel each other out. In FIG. 6, it is assumed that the compressive stress layer 12 generates a residual stress (compressive stress CF) of 0.8 GPa. The residual stress (tensile stress TF) of the epoxy resin (Epoxy) is set to 16-19 MPa, and the residual stress (tensile stress TF) of the BCB is set to 28 MPa. The thickness of the compressive stress layer 12 can be set so that the value obtained by multiplying the residual stress of the resin layers 14 and 16 by the total thickness of the resin layers 14 and 16 is equal to the value obtained by multiplying the residual stress of the compressive stress layer 12 by the thickness of the compressive stress layer 12.

[0044] (First Modification) 7 is a cross-sectional view showing another example of a bandpass filter, which is an example of a distributed constant circuit included in the semiconductor device 1 of FIG. 1. The bandpass filter shown in FIG. 7 may be disposed on the second metal layers 15a and 15b instead of the bandpass filter 15 of FIG. 2. The bandpass filter of FIG. 7 includes a plurality of λ / 2 transmission lines 162U to 166U bent at central portions 162Uc to 166Uc, an input wiring 151 that supplies signals to the plurality of λ / 2 transmission lines 162U to 166U, and an output wiring 158 that outputs signals passing through the plurality of λ / 2 transmission lines 162U to 166U. The λ / 2 transmission line 162U is electrically connected to the input wiring 151, and the λ / 2 transmission line 166U is electrically connected to the output wiring 158. Each of the plurality of λ / 2 transmission lines 162U to 166U forms a transmission line with a length of λ / 2, and therefore functions as a resonator with a frequency (f0). The multiple λ / 2 transmission lines 162U to 166U are connected in series by electromagnetic coupling. By adjusting the lengths of the λ / 2 transmission lines 162U to 166U and the spacing between the λ / 2 transmission lines 162U to 166U, a bandpass filter with Chebyshev or Butterworth characteristics can be obtained. The number of multiple λ / 2 transmission lines 162U to 166U is determined by the order of the filter to be realized.

[0045] The other configurations are the same as those of the bandpass filter 15 in Fig. 2, and therefore a repeated description will be omitted. Note that the distributed constant circuit in the embodiment is not limited to the bandpass filter 15 in Fig. 2 and the bandpass filter in Fig. 7, but other distributed constant circuits such as a lowpass filter, a filtering antenna, a matching circuit, etc. may also be arranged.

[0046] (Second Modification) The SiO film, which is an example of the compressive stress layer 12, is not limited to a thermal oxide film, and may also be a deposited film formed by a CVD method. Another example of a manufacturing method for the semiconductor device 1 of FIG. 1 will be described with reference to FIGS. 8A to 8H. As shown in FIG. 8A, an SiO film, which is an example of the compressive stress layer 12, is formed on the first main surface 11A of an undivided wafer-like Si substrate 11 by using a CVD method. When the CVD method is used, the SiO film is not formed on the second main surface 11Ba of the Si substrate 11 and on the side surface connecting the first main surface 11A and the second main surface 11Ba.

[0047] Specifically, SiH4 (silane) or TEOS (tetraethoxysilane) is introduced into a chamber containing a wafer as a silicon precursor gas, and an oxidizing gas (O2 or N2O) is introduced as an oxygen precursor gas. A SiO film is formed by chemically reacting these precursor gases on the first main surface 11A of the Si substrate 11. After film formation, annealing (heat treatment) is performed to reduce defects in the SiO film.

[0048] After the annealing, as shown in FIGS. 8B to 8F, steps similar to those shown in FIGS. 4B to 4F are carried out.

[0049] Then, a portion of the Si substrate 11 is ground from the second main surface 11Ba side of the Si substrate 11 shown in Fig. 8F to thin the Si substrate 11 to several tens of micrometers as shown in Fig. 8G. Thereafter, the wafer-like Si substrate 11 is divided into individual pieces as shown in Fig. 8H, thereby manufacturing the semiconductor device 1 shown in Fig. 1.

[0050] The SiO film may be formed using a plasma CVD method (PECVD: Plasma Enhanced Chemical Vapor Deposition), which is an example of a CVD method. When forming an SiO film using the PECVD method, high-frequency power is applied to the chamber to generate plasma, which activates the chemical reaction of the precursor gas. By adjusting the magnitude of the high-frequency power and the annealing temperature after film formation, compressive stress can be generated as residual stress in the SiO film.

[0051] Another example of the compressive stress layer 12, a silicon oxynitride (SiON) film, can also be deposited using the CVD method. By adjusting the magnitude of the high-frequency power and the annealing temperature after deposition, compressive stress can be generated as residual stress in the SiON film. FIG. 9 shows data acquired by the inventors of the present application. As shown in FIG. 9, compressive stress can be generated as residual stress in the SiON film by setting the high-frequency output in the CVD method to 300 W or more and 350 W or less. Furthermore, compressive stress can be generated as residual stress in the SiON film by setting the high-frequency output in the CVD method to 250 W or more and 350 W or less and setting the annealing temperature after deposition of the SiON film to 300 °C or more and 500 °C or less. In the data shown in FIG. 9, nitrous oxide (NO) at a flow rate of 50 sccm, ammonia (NH) at a flow rate of 10 sccm, and SiH at a flow rate of 10 sccm were introduced into the chamber, and the pressure in the chamber was set to 100 Pa.

[0052] In the case of a SiN film (silicon nitride film), which is another example of the compressive stress layer 12, compressive stress can be generated as residual stress in the SiN film by adjusting the temperature of annealing performed after the SiN film is formed by CVD.

[0053] (Third Modification) As described above, the first metal layer 13 is a ground electrode layer. The first metal layer 13 may be a film formed over the entire main surface 11A of the substrate 11, or may have a predetermined planar pattern. In this case, for example, the planar pattern of the first metal layer 13 may be formed so that a capacitive component is formed between the first metal layer 13 and the first resin layer 14. For example, a parallel plate (metal / dielectric / metal) capacitive component can be formed between the first metal layer 13 and the first resin layer 14. This allows the capacitive component to be used for impedance matching of a distributed constant circuit.

[0054] (Fourth Modification) An integrated circuit for processing signals that have passed through the distributed constant circuit may be formed on the first main surface 11A of the Si substrate 11. In this case, the region of the Si substrate 11 including the first main surface 11A is formed of single-crystal Si. A plurality of semiconductor elements formed on the first main surface 11A are electrically connected to a wiring layer disposed between the first main surface 11A of the Si substrate 11 and the compressive stress layer 12. This forms the integrated circuit. As shown in FIGS. 3A and 8A , a step of forming an integrated circuit for processing signals that have passed through the distributed constant circuit may be performed before the compressive stress layer 12 is formed on the first main surface 11A of the Si substrate 11. Forming the distributed constant circuit on the integrated circuit reduces losses due to shorter wiring lengths and enables the semiconductor device to be made thinner.

[0055] (Second embodiment) The configuration of a semiconductor device 2 according to the second embodiment will be described with reference to Fig. 10. The semiconductor device 2 includes a Si substrate 11, a compressive stress layer 12, a first metal layer 13, a first resin layer 14, second metal layers 15a and 15b, a second resin layer 16, third metal layers 17a, 17b, and 17c, a third resin layer 18, a fourth metal layer 21, a fourth resin layer 22, fifth metal layers 23a and 23b, through vias 25a, 24a, 19, and 30, a through via 24b, and a through via 25b.

[0056] The compressive stress layer 12 is disposed on the first main surface 11A of the Si substrate 11, and compressive stress is generated as residual stress along the first main surface 11A in the outer peripheral direction. The first metal layer 13 is disposed on the main surface 12A of the compressive stress layer 12. The first resin layer 14 is disposed on the main surface 13A of the first metal layer 13. The second metal layers 15a and 15b are disposed on the main surface 14A of the first resin layer 14. The second resin layer 16 is disposed on the main surfaces of the second metal layers 15a and 15b. The third metal layers 17a, 17b, and 17c are disposed on the main surface 16A of the second resin layer 16. The third resin layer 18 is disposed on the main surfaces of the third metal layers 17a, 17b, and 17c.

[0057] The fourth metal layer 21 is disposed on the main surface of the third resin layer 18. The fourth resin layer 22 is disposed on the main surface of the fourth metal layer 21. The fifth metal layers 23a, 23b are disposed on the main surface of the fourth resin layer 22. The through vias 25a, 24a, 19, and 30 penetrate the first to fourth resin layers 14 to 22 in the stacking direction, electrically connecting the first metal layer 13 and the fifth metal layer 23a. The through via 24b penetrates the third resin layer 18 in the stacking direction, electrically connecting the third metal layer 17c and the fourth metal layer 21. The through via 25b penetrates the fourth resin layer 22 in the stacking direction, electrically connecting the fourth metal layer 21 and the fifth metal layer 23b.

[0058] Although not shown in FIG. 10 , in the semiconductor device 2, distributed constant circuits are formed in the second metal layers 15a and 15b and the third metal layers 17a, 17b, and 17c. For example, a structure similar to the bandpass filter described in Patent Document 1, in which multiple dielectric layers are stacked, can be realized. Specifically, by overlapping a portion of the third metal layer 17a with a portion of the second metal layer 15a in the stacking direction, the third metal layer 17a and the second metal layer 15a can be capacitively coupled. Similarly, by overlapping the second metal layers 15a and 15b with the third metal layers 17a, 17b, and 17c in the stacking direction, capacitive coupling can be achieved. This allows for the formation of a bandpass filter with multiple resonators.

[0059] By disposing the compressive stress layer 12 between the Si substrate 11 and the first metal layer 13, the tensile stress TF caused by the first to fourth resin layers 14 to 22 is offset by the compressive stress CF caused by the compressive stress layer 12. Therefore, warping of the Si substrate 11 is suppressed, and the Si substrate 11 can be made thinner.

[0060] (Third embodiment) The configuration of a semiconductor device 3 according to the third embodiment will be described with reference to Fig. 11. The semiconductor device 3 includes a Si substrate 11, a compressive stress layer 12 disposed on a first main surface 11A of the Si substrate 11 and having compressive stress acting as residual stress in the outer peripheral direction along the first main surface 11A, a first metal layer 13 disposed on the main surface 12A of the compressive stress layer 12, a first resin layer 14 disposed on the main surface 13A of the first metal layer 13, and second metal layers 15a, 15b, and 15c disposed on the main surface 14A of the first resin layer 14.

[0061] The semiconductor device 3 further includes a through via 30 (first through via) that penetrates the first resin layer 14 and electrically connects the first metal layer 13 and the second metal layer 15a.

[0062] 11, distributed constant circuits are formed on second metal layers 15a, 15b, and 15c in semiconductor device 3. For example, a structure similar to the laminated structure of ground electrode / resin layer / transmission line on a silicon substrate described in Non-Patent Document 1 can be realized.

[0063] (Fourth embodiment) The configuration of a semiconductor device 4 according to the fourth embodiment will be described with reference to FIG. 12. In the semiconductor device 4, the first metal layer 13 and the second metal layer 15a are electrically connected by a connection wiring 26 arranged on the side surface of the first resin layer 14. The side surface of the first resin layer 14 is arranged more inward than the side surfaces of the substrate 11, the compressive stress layer 12, and the first metal layer 13. This allows the first metal layer 13 and the second metal layer 15a to be electrically connected without forming a through via 30 (FIG. 11). Furthermore, the outer shape of the chip remains unchanged, and the chip size is not increased. The other configurations are the same as those of the semiconductor device 3 in FIG. 11, and therefore description thereof will be omitted.

[0064] (Fifth embodiment) The configuration of a semiconductor device 5 according to the fifth embodiment will be described with reference to Fig. 13. By forming a hole penetrating the Si substrate 11 and the compressive stress layer 12, it is also possible to form a patch antenna 27 on the back surface (second principal surface 11B) of the Si substrate 11. The patch antenna 27 has a back surface electrode 27a disposed on the second principal surface 11B and a through via 27b embedded in the hole and electrically connected to the back surface electrode 27a. A first end of the through via 27b is electrically connected to the back surface electrode 27a, and a second end of the through via 27b is capacitively coupled to the first metal layer 13.

[0065] In this way, the semiconductor device 5 can have an AiP (Antenna in Package) structure that integrates the patch antenna 27 that receives signals in the millimeter wave band (30-300 GHz) and the quasi-millimeter wave band (less than 30 GHz) with a passive element (bandpass filter) that processes the received signals. In the semiconductor device 5, the patch antenna 27 is formed on the second main surface 11B side of the Si substrate, and input / output terminals (third metal layers 17a, 17b) are formed on the first main surface 11A side.

[0066] (Sixth embodiment) The configuration of a semiconductor device 6 according to the sixth embodiment will be described with reference to Fig. 14. The semiconductor device 6 differs from the semiconductor device 5 of Fig. 13 in that a patch antenna 27 is formed on the first main surface 11A side of the Si substrate and an input / output terminal (back surface electrode 29) is formed on the second main surface 11B side.

[0067] A fourth metal layer 28a, which is a part of the patch antenna 28, is disposed on the main surface of the third resin layer 18. A through via 28b, which is another part of the patch antenna 28, is disposed in the third resin layer 18. A first end of the through via 28b is capacitively coupled to the fourth metal layer 28a. A second end of the through via 28b is capacitively coupled to an end of the third metal layer 17a.

[0068] A back surface electrode 29a is disposed on the second main surface 11B of the Si substrate 11. The through via 29b is embedded in a hole formed in the Si substrate 11 and the compressive stress layer 12. A first end of the through via 29b is electrically connected to the back surface electrode 29a, and a second end of the through via 29b is electrically connected to an end of the through via 30b.

[0069] The semiconductor devices 2 to 6 of the second to sixth embodiments can be manufactured by applying the manufacturing method of the semiconductor device 1 of the first embodiment.

[0070] Any of the first to fourth modified examples may be applied to the second to sixth embodiments. For example, by combining the fourth modified example with the semiconductor devices 5 and 6 having the patch antennas 27 and 28, it is possible to further integrate an integrated circuit into the AiP structure.

[0071] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0072] (Appendix 1) Each of the semiconductor devices 1 to 6 includes a silicon substrate 11, a compressive stress layer 12 disposed on a first main surface 11A of the silicon substrate 11 and having a compressive stress CF generated as a residual stress in the outer peripheral direction along the first main surface 11A, a first metal layer 13 disposed on the main surface 12A of the compressive stress layer 12, a first resin layer 14 disposed on the main surface 13A of the first metal layer 13, and second metal layers 15a and 15b disposed on the main surface 14A of the first resin layer 14. A distributed constant circuit 15 is formed on at least the second metal layers 15a and 15b. Semiconductor device.

[0073] According to Supplementary Note 1, by disposing the compressive stress layer 12 between the silicon substrate 11 and the first metal layer 13, warping of the Si substrate 11 due to the tensile stress TF caused by the first metal layer 13, the first resin layer 14, and the second metal layers 15a and 15b is alleviated. This suppresses warping and cracking of the wafer, allowing the silicon substrate 11 to be made thinner. This reduces damage during processing and transportation. A support substrate is not required, which reduces manufacturing costs. The DBG (Dicing Before Grinding) process is also not required.

[0074] (Appendix 2) In the semiconductor devices 1 to 6 described in Appendix 1, the compressive stress layer 12 includes a layer in which at least one of oxygen and nitrogen is bonded to silicon. This layer applies a compressive stress CF in the outer peripheral direction along the first main surface 11A of the silicon substrate 11, thereby mitigating warpage of the Si substrate 11 due to the tensile stress TF caused by the first metal layer 13, the first resin layer 14, and the second metal layers 15a and 15b.

[0075] (Appendix 3) In the semiconductor devices 1 to 6 described in Supplementary Note 1 or 2, the first metal layer 13 is a ground electrode layer having a thickness equal to or greater than the thickness at which the skin effect is obtained. When a ground potential is applied to the first metal layer 13, the first metal layer 13 having a thickness equal to or greater than the thickness at which the skin effect is obtained can suppress leakage of the electromagnetic field to the silicon substrate 11 side, and therefore the frequency characteristics of the distributed constant circuit are not impaired.

[0076] (Appendix 4) In the semiconductor devices 1 to 6 described in any one of Supplementary Notes 1 to 3, a capacitive component is formed between the first metal layer 13 and the first resin layer 14. This can be used for impedance matching of a distributed constant circuit.

[0077] (Appendix 5) In the semiconductor devices 1 to 6 described in any one of Supplementary Notes 1 to 4, the first resin layer 14 contains at least one material selected from the group consisting of benzocyclobutene, polyphenylene ether, epoxy resin, polyimide, fluororesin, and liquid crystal polymer.

[0078] (Appendix 6) In the semiconductor devices 1 to 6 described in any one of Supplementary Notes 1 to 5, the first metal layer 13 and the second metal layers 15a and 15b each include a main layer 13b containing at least one element selected from the group consisting of copper, gold, and silver.

[0079] (Appendix 7) In the semiconductor devices 1 to 6 described in any one of Supplementary Notes 1 to 6, the first metal layer 13 includes a diffusion prevention film 13a that prevents diffusion of metal into the silicon substrate 11.

[0080] (Appendix 8) The semiconductor device 3 described in any one of Supplementary Notes 1 to 7 further includes a first through via 30 that penetrates the first resin layer 14 and electrically connects the first metal layer 13 and the second metal layer 15a.

[0081] (Appendix 9) The semiconductor devices 1, 2, 5, and 6 described in any one of Supplementary Notes 1 to 8 further include a second resin layer 16 arranged on the main surfaces of the second metal layers 15a and 15b, and third metal layers 17a, 17b, and 17c arranged on the main surfaces of the second resin layer 16.

[0082] (Appendix 10) In the semiconductor devices 1, 2, 5, and 6 described in Appendix 9, the second resin layer 16 contains at least one material selected from the group consisting of benzocyclobutene, polyphenylene ether, epoxy resin, polyimide, fluororesin, and liquid crystal polymer.

[0083] (Appendix 11) The semiconductor devices 1, 5, and 6 described in Appendix 9 or 10 further have a second through via 20 that penetrates the first resin layer 14 and the second resin layer 16 and electrically connects the first metal layer 13 and the third metal layer 17a.

[0084] (Appendix 12) In the semiconductor device 1 to 6 described in any one of Supplementary Notes 1 to 11, an integrated circuit for processing a signal that has passed through the distributed constant circuit is formed on the first main surface 11A of the silicon substrate 11. Loss due to the shorter wiring is reduced, and the semiconductor device can be made thinner.

[0085] (Appendix 13) The semiconductor device 4 according to any one of claims 1 to 12 further comprises a connection wiring 26 arranged on a side surface of the first resin layer 14, electrically connecting between the first metal layer 13 and the second metal layer 15a.

[0086] (Appendix 14) A method for manufacturing semiconductor devices 1 to 6 includes preparing a silicon substrate 11, forming a compressive stress layer 12 on a first main surface 11A of the silicon substrate 11, the compressive stress layer 12 generating a compressive stress CF in the outer edge direction along the first main surface 11A as a residual stress, forming a first metal layer 13 on the main surface 12A of the compressive stress layer 12, forming a first resin layer 14 on the main surface 13A of the first metal layer 13, and forming second metal layers 15a, 15b, and 15c on the main surface 14A of the first resin layer 14, and a distributed constant circuit is formed in at least the second metal layers 15a, 15b, and 15c.

[0087] According to Supplementary Note 14, by disposing the compressive stress layer 12 between the silicon substrate 11 and the first metal layer 13, warping of the Si substrate 11 due to the tensile stress TF caused by the first metal layer 13, the first resin layer 14, and the second metal layers 15a and 15b is alleviated. This suppresses warping and cracking of the wafer, allowing the silicon substrate 11 to be made thinner. This reduces damage during processing and transportation. A support substrate is not required, which reduces manufacturing costs. The DBG (Dicing Before Grinding) process is also not required.

[0088] (Appendix 15) In the method for manufacturing a semiconductor device described in Appendix 14, after forming second metal layers 15a and 15b, second main surface 11B of silicon substrate 11, which faces in the opposite direction to first main surface 11A, is ground to thin silicon substrate 11. Since warping of Si substrate 11 is alleviated, Si substrate 11 can be thinned.

[0089] (Appendix 16) The method for manufacturing a semiconductor device described in Supplementary Note 14 or 15 uses a CVD method to form the compressive stress layer 12. Compressive stress can be imparted to the compressive stress layer 12 by adjusting the temperature and high frequency power.

[0090] (Appendix 17) In the method for manufacturing a semiconductor device according to Appendix 16, the compressive stress layer 12 includes a silicon oxynitride film in which oxygen and nitrogen are combined with silicon, and the high-frequency output in the CVD method is 300 W or more and 350 W or less. A compressive stress can be applied to the compressive stress layer 12.

[0091] (Appendix 18) In the method for manufacturing a semiconductor device according to Appendix 16, the compressive stress layer includes a silicon oxynitride film in which oxygen and nitrogen are combined with silicon, the high frequency output in the CVD method is 250 W or more and 350 W or less, and the annealing temperature after forming the compressive stress layer is 300° C. or more and 500° C. or less. A compressive stress can be imparted to the compressive stress layer 12.

[0092] (Appendix 19) In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 16 to 18, forming the first metal layer 13 includes forming a diffusion prevention film 13a that prevents diffusion of metal into the silicon substrate 11.

[0093] (Appendix 20) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 16 to 19 forms a first through via 30 that penetrates the first resin layer 14 and electrically connects the first metal layer 13 and the second metal layer 15a.

[0094] (Appendix 21) The method for manufacturing a semiconductor device described in any one of Appendices 16 to 20 forms a second resin layer 16 on the main surfaces of the second metal layers 15a and 15b, and forms third metal layers 17a, 17b, and 17c on the main surface of the second resin layer 16.

[0095] (Appendix 22) In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 16 to 21, after forming third metal layers 17a, 17b, and 17c, second main surface 11B of silicon substrate 11, which faces in the opposite direction to first main surface 11A, is ground to thin silicon substrate 11. Since warping of Si substrate 11 is alleviated, Si substrate 11 can be thinned.

[0096] (Appendix 23) The method for manufacturing a semiconductor device described in any one of Appendices 16 to 22 forms a second through via 20 that penetrates the first resin layer 14 and the second resin layer 16 and electrically connects the first metal layer 13 and the third metal layer 17a.

[0097] (Appendix 24) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 16 to 23 forms an integrated circuit for processing a signal that has passed through a distributed constant circuit on first main surface 11A of silicon substrate 11. Loss due to shorter wiring is reduced, and the semiconductor device can be made thinner. [Explanation of symbols]

[0098] 1-6 Semiconductor devices 11 Si substrate (silicon substrate) 11A 1st main surface 11B, 11Ba 2nd main surface 12 Compressive stress layer 12A, 13A, 14A, 16A main surface 13 1st metal layer 13a Diffusion prevention film 13b Main layer 14 1st resin layer 15 Distributed constant circuit 15a~15c 2nd metal layer 16 Second resin layer 17a~17c 3rd metal layer 18 Third resin layer 19, 24a, 24b, 25a, 25b Through vias 20 Through via (second through via) 21 4th metal layer 22 4th resin layer 23a, 23b 5th metal layer 27, 28 Patch antenna CF compressive stress

Claims

1. A silicon substrate; a compressive stress layer disposed on the first main surface of the silicon substrate, in which compressive stress is generated as residual stress in an outer peripheral direction along the first main surface; a first metal layer disposed on a major surface of the compressive stress layer; a first resin layer disposed on a main surface of the first metal layer; a second metal layer disposed on a main surface of the first resin layer, A distributed constant circuit is formed at least on the second metal layer. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said compressive stress layer includes a layer in which at least one of oxygen and nitrogen is bonded to silicon.

3. 2. The semiconductor device according to claim 1, wherein said first metal layer is a ground electrode layer having a thickness equal to or greater than a thickness at which a skin effect is obtained.

4. The semiconductor device according to claim 1 , wherein a capacitance component is formed between said first metal layer and said first resin layer.

5. 2. The semiconductor device according to claim 1, wherein the first resin layer includes at least one material selected from the group consisting of benzocyclobutene, polyphenylene ether, epoxy resin, polyimide, fluororesin, and liquid crystal polymer.

6. 2. The semiconductor device according to claim 1, wherein the first metal layer and the second metal layer each include a layer containing at least one element selected from the group consisting of copper, gold, and silver.

7. 2. The semiconductor device according to claim 1, wherein said first metal layer includes a diffusion prevention film that prevents diffusion of metal into said silicon substrate.

8. 8. The semiconductor device according to claim 1, further comprising a first through via that penetrates the first resin layer and electrically connects the first metal layer and the second metal layer.

9. a second resin layer disposed on a main surface of the second metal layer; a third metal layer disposed on the main surface of the second resin layer; The semiconductor device according to claim 1 .

10. 10. The semiconductor device according to claim 9, wherein the second resin layer includes at least one material selected from the group consisting of benzocyclobutene, polyphenylene ether, epoxy resin, polyimide, fluororesin, and liquid crystal polymer.

11. 11. The semiconductor device according to claim 9, further comprising a second through via that penetrates the first resin layer and the second resin layer to electrically connect the first metal layer and the third metal layer.

12. Prepare a silicon substrate. forming a compressive stress layer on a first main surface of the silicon substrate, the compressive stress being generated as a residual stress along the first main surface in an outer edge direction; forming a first metal layer on a major surface of the compressive stress layer; forming a first resin layer on a main surface of the first metal layer; forming a second metal layer on a main surface of the first resin layer, a distributed constant circuit is formed at least on the second metal layer; A method for manufacturing a semiconductor device.

13. 13. The method for manufacturing a semiconductor device according to claim 12, further comprising the steps of: after forming the second metal layer, grinding a second main surface of the silicon substrate facing in a direction opposite to the first main surface to thin the silicon substrate.

14. 14. The method for manufacturing a semiconductor device according to claim 12, wherein the compressive stress layer is formed by a CVD method.

15. the compressive stress layer includes a silicon oxynitride film in which oxygen and nitrogen are combined with silicon, The high frequency output in the CVD method is 300 W or more and 350 W or less. The method for manufacturing a semiconductor device according to claim 14.

16. the compressive stress layer includes a silicon oxynitride film in which oxygen and nitrogen are combined with silicon, The high frequency output in the CVD method is 250 W or more and 350 W or less, the annealing temperature after the compressive stress layer is formed is 300° C. or higher and 500° C. or lower; The method for manufacturing a semiconductor device according to claim 14.

Images