Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor device is provided in which a metal film is formed while leaving a damaged layer on the surface of a semiconductor substrate in order to suppress the occurrence of silicon pits. [Solution] A method for manufacturing a semiconductor device is provided, which includes forming an insulating film on a semiconductor substrate, selectively removing the insulating film, forming a metal film on the semiconductor substrate while leaving a damaged layer on the surface of the semiconductor substrate that was generated when the insulating film was selectively removed, selectively removing the metal film to form an electrode, and forming polyimide on the electrode. The damaged layer on the surface of the semiconductor substrate that was generated when the insulating film was selectively removed may also be selectively removed.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 describes a method for manufacturing a semiconductor device in which wet etching is performed in a contact process for connecting a semiconductor substrate to metal wiring in order to reduce damage to the surface of the semiconductor substrate that would otherwise be caused by dry etching. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-54039 Summary of the Invention [Problem to be solved by the invention]

[0004] However, etching to reduce damage to the semiconductor substrate surface has the problem of generating silicon pits in subsequent processes. Therefore, an object of the present disclosure is to provide a method for manufacturing a semiconductor device in which a metal film is formed while leaving a damaged layer on the semiconductor substrate surface in order to suppress the generation of silicon pits.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes forming a metal film on a semiconductor substrate while leaving a damaged layer on the surface of the semiconductor substrate that is generated when an interlayer insulating film is selectively removed. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a method for manufacturing a semiconductor device in which a metal film is formed while leaving a damaged layer on the surface of a semiconductor substrate. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a top view of a first semiconductor device according to the present disclosure. [Figure 2] 7 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line VIB-VIB. [Figure 3] FIG. 1 is a first cross-sectional view of a semiconductor device illustrating a related method for manufacturing a semiconductor device. [Figure 4] FIG. 10 is a second cross-sectional view of the semiconductor device illustrating a related method for manufacturing the semiconductor device. [Figure 5] FIG. 10 is a third cross-sectional view of a semiconductor device illustrating a related method for manufacturing a semiconductor device. [Figure 6] FIG. 10 is a fourth cross-sectional view of the semiconductor device illustrating a related method for manufacturing a semiconductor device. [Figure 7] FIG. 10 is a fifth cross-sectional view of a semiconductor device illustrating a related method for manufacturing a semiconductor device. [Figure 8] VI characteristics when silicon pits occur in a semiconductor device and when no silicon pits occur are shown. [Figure 9] 1 is a schematic diagram of a silicon pit formed in a semiconductor device. [Figure 10] 10 is a flowchart of a related method for manufacturing a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing process of a related semiconductor device. [Figure 12] FIG. 10 is a diagram showing the relationship between light etching time and VF characteristics. [Figure 13] 1 is a flowchart of a method for manufacturing a semiconductor device according to the present disclosure. [Figure 14] 3A to 3C are cross-sectional views of a first manufacturing step of the semiconductor device of the present disclosure. [Figure 15] 10A to 10C are cross-sectional views of a second manufacturing step of the semiconductor device of the present disclosure. [Figure 16] FIG. 1 is a cross-sectional view illustrating the principle of silicon pit generation. [Figure 17] FIG. 1 is a diagram showing the relationship between the width and depth of a silicon pit. [Figure 18] FIG. 10 is a diagram showing a path of current flow when a probe is applied to a position where a silicon pit has occurred. [Figure 19] FIG. 10 is a diagram showing a path of current flow when a bonding wire is applied to a position where a silicon pit has occurred. [Figure 20] FIG. 1 illustrates a consideration regarding the spacing of silicon pits. [Figure 21] FIG. 10 is a diagram showing the results of a simulation of the relationship between the spacing of silicon pits and VR characteristics. [Figure 22] FIG. 2 is a top view of a second semiconductor device according to the present disclosure. [Figure 23] 23 is a cross-sectional view taken along the line XXI-XXI of the semiconductor device of FIG. 22. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiment Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the invention according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential means for solving the problems. For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] (Description of Semiconductor Device of the Present Disclosure) Fig. 1 is a top view of a first semiconductor device of the present disclosure. Fig. 2 is a cross-sectional view taken along line VIB-VIB of the semiconductor device of Fig. 1. The first semiconductor device of the present disclosure will be described with reference to Figs. 1 and 2.

[0011] As shown in Figure 1, the semiconductor device of the present disclosure is formed in a rectangular shape when viewed from the top of the semiconductor substrate. In this example, the shape is rectangular, but it may be a rounded rectangle, a circle, an oval, or the like so as to occupy a certain area of ​​the semiconductor substrate. When viewed from the top, the semiconductor device 100 includes a central anode pad 101 and polyimide 102 surrounding it.

[0012] As shown in FIG. 2, the semiconductor device of the present disclosure includes, from the bottom up, a cathode electrode 24, an N+ type semiconductor region 201, an N- type drift region 11, a P type body region 14, an interlayer insulating film 21, a metal layer 23, an anode electrode AE, an anode pad 101, and a polyimide 102.

[0013] The semiconductor device of the present disclosure is a diode in which a PN junction is formed between a P+ type semiconductor region and an N- type drift region. The N+ type semiconductor region 201 may be omitted.

[0014] (Description of Related Semiconductor Device Manufacturing Method) FIG. 3 is a first cross-sectional view of a semiconductor device illustrating a method for manufacturing a semiconductor device according to the present disclosure. FIG. 4 is a second cross-sectional view of a semiconductor device illustrating a method for manufacturing a semiconductor device according to the present disclosure. FIG. 5 is a third cross-sectional view of a semiconductor device illustrating a method for manufacturing a semiconductor device according to the present disclosure. FIG. 6 is a fourth cross-sectional view of a semiconductor device illustrating a method for manufacturing a semiconductor device according to the present disclosure. FIG. 7 is a fifth cross-sectional view of a semiconductor device illustrating a method for manufacturing a semiconductor device according to the present disclosure. The method for manufacturing a semiconductor layer device according to the present disclosure will be described with reference to FIGS. 3 to 7. FIGS. 3 to 7 are cross-sectional views showing manufacturing steps of the semiconductor device shown in FIG. 2.

[0015] First, a semiconductor wafer is prepared, which is made of a silicon single crystal semiconductor substrate 1s doped with an N-type impurity such as phosphorus, as shown in Fig. 3. The semiconductor wafer has a front surface 1a and a back surface 1b opposite to the front surface 1a.

[0016] The impurity concentration of the N-type impurity in the semiconductor wafer is, for example, 2 × 10 14 cm -3The thickness of the semiconductor wafer can be, for example, about 450 μm to 1,000 μm.

[0017] Next, a silicon nitride film (Si3N4) is formed on the surface of the semiconductor wafer, and the Si3N4 film is patterned to form a Si3N4 film mask. The surface of the semiconductor wafer in areas other than the Si3N4 film mask area is oxidized in an oxidizing atmosphere to form element isolation regions 12.

[0018] Next, by ion implantation using a resist pattern as a mask, a P-type impurity is introduced into the semiconductor substrate 1s on the surface 1a side of the semiconductor wafer, thereby forming a P-type field region 13. The ion implantation conditions at this time are, for example, boron (B) as the ion species and a dose of 3.5×10 13 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 75 keV.

[0019] Next, after removing the resist, annealing is performed, for example, at about 1200° C. for about 30 minutes in an atmosphere of nitrogen (N 2 ) gas as an inert gas, to repair crystal defects in the P-type field region 13 and perform extension diffusion.

[0020] Next, as shown in FIG. 4, P-type body regions 14 are formed by introducing P-type impurities into necessary portions of the cell region 2a and the scribe region 3 by ion implantation using a resist pattern as a mask.

[0021] Specifically, the P-type body region 14 is formed on the P-type field region 13 and the N-type drift region 11(1s) formed in the cell region 2a. The P-type body region 14 is also formed on the N-type drift region 11(1s) in the scribe region 3.

[0022] The ion implantation conditions at this time are, for example, B ion species and a dose of 1×10 13 cm -2A suitable example of ion implantation conditions is a temperature of about 1000° C. and an implantation energy of about 75 keV. After removing the resist, annealing is performed in an N 2 gas atmosphere at about 1000° C. for about 100 minutes.

[0023] Next, as shown in FIG. 5, an ion implantation method using a resist pattern as a mask is used to introduce N-type impurities onto the N-type drift region 11(1s) in the peripheral region 2b and onto the P-type body region 14 in the scribe region 3, thereby forming an N+ type semiconductor region 15.

[0024] The ion implantation conditions at this time are, for example, arsenic (As) as the ion species and 5×10 15 cm -2 A suitable example of ion implantation conditions is a temperature of about 1000° C. and an implantation energy of about 80 keV. After removing the resist, annealing is performed in an N 2 gas atmosphere at about 1000° C. for about 100 minutes.

[0025] Next, as shown in FIG. 6, an interlayer insulating film 21 made of, for example, a PSG (Phosphorous Silicate Glass) film is formed on the surface 1a of the semiconductor wafer by, for example, a CVD method. The interlayer insulating film 21 is formed so as to cover, for example, the N-type drift region 11 (1s), the P-type field region 13, the P-type body region 14, and the N+-type semiconductor region 15. The thickness of the interlayer insulating film 21 is, for example, approximately 0.6 μm. Suitable materials for the interlayer insulating film 21 include, in addition to a PSG film, a BPSG (Boro Phospho Silicate Glass) film, an NSG (Non-doped Silicate Glass) film, an SOG (Spin-On-Glass) film, a silicon oxide (SiO2) film, or a composite film thereof.

[0026] Next, anisotropic dry etching is performed using the resist pattern as a mask to form contact holes (openings) 22 in the interlayer insulating film 21. Suitable examples of gases for this anisotropic dry etching include a mixed gas of argon (Ar) gas, trifluoromethane (CHF) gas, and tetrafluoromethane (CF) gas.

[0027] Next, to reduce damage to the semiconductor substrate surface due to dry etching, after removing the resist, the contact hole 22 and the semiconductor substrate 1s are etched by SEZ wet etching using the interlayer insulating film 21 as a mask. A suitable example of an etching solution for SEZ wet etching is nitric acid (HNO3):hydrogen fluoride (HF) = 200:1. Alternatively, instead of SEZ wet etching, the contact hole 22 and the semiconductor substrate 1s may be etched by dry etching. A suitable example of a gas for this dry etching is a mixed gas of oxygen (O2) gas and tetrafluoromethane (CF4) gas.

[0028] Next, as shown in Fig. 7, a metal layer 23 such as an anode electrode AE ​​is formed. Specifically, for example, the following procedure is performed. First, an aluminum-based metal film (for example, a few percent silicon added, the remainder aluminum) is formed by, for example, sputtering over the entire surface 1a of the semiconductor wafer so as to fill the contact holes 22. The thickness of the aluminum-based metal film is, for example, about 5 µm.

[0029] Next, a metal layer 23 made of an aluminum-based metal film is formed by dry etching using a resist pattern as a mask. Suitable examples of gases for this dry etching include chlorine (Cl) / boron trichloride (BCl) gas.

[0030] As a result, in the cell region 2a, an anode electrode AE ​​is formed inside the contact hole 22 and on the interlayer insulating film 21. In the scribe region 3, electrode pads 42, 43 are formed inside the contact hole 22 and on the interlayer insulating film 21. Here, the metal layer 23 in the contact hole 22 is referred to as a contact portion.

[0031] The anode electrode AE ​​is electrically connected to the P-type body region 14 formed in the cell region 2a. The electrode pad 42 is electrically connected to the P-type body region 14 formed in the scribe region 3, and the electrode pad 43 is electrically connected to the N+ type semiconductor region 15 formed in the scribe region 3.

[0032] Next, an insulating film is formed on the anode electrode as a passivation film, which is made of an organic film containing, for example, polyimide as a main component, and has a thickness of, for example, about 2.5 μm to 10 μm.

[0033] Next, the insulating film is patterned by dry etching using the resist pattern as a mask to form an opening that penetrates the insulating film and reaches the anode electrode AE, and an anode pad is formed by the portion of the anode electrode AE ​​exposed in the opening.

[0034] Next, the back surface 1b of the semiconductor wafer is subjected to a backgrinding process to reduce the thickness from, for example, about 800 μm to, for example, about 30 μm to 200 μm as needed. For example, if the withstand voltage is about 600 V, the final thickness is about 70 μm. Also, chemical etching or the like is performed to remove damage to the back surface 1b as needed.

[0035] Next, a cathode electrode 24 electrically connected to the N-type drift region 11 (1s) is formed on the back surface 1b of the semiconductor wafer by, for example, sputtering. Thereafter, the semiconductor substrate 1s is divided into semiconductor chip regions 2 by dicing or the like, and sealed in a package as necessary, thereby nearly completing the semiconductor chip as a semiconductor device.

[0036] (Regarding the formation of silicon pits in semiconductor devices) Fig. 8 shows the VI characteristics of a semiconductor device when silicon pits occur and when no silicon pits occur. Fig. 9 is a schematic diagram of a silicon pit formed in a semiconductor device. Fig. 10 is a flowchart of a related method for fabricating a semiconductor device. Fig. 11 is a cross-sectional view of a related process for fabricating a semiconductor device.

[0037] As shown in Figure 8, when the VI characteristics of related semiconductor devices were measured, good diodes like C, in which the current rose sharply at a certain voltage, and defective diodes like A and B, in which the current leaked and rose more gradually, were found. The defective diodes had silicon pits, holes in the silicon. Therefore, diodes A and B, which had silicon pits, were found to be defective, while diode C was found to be good.

[0038] As shown in Figure 9, silicon pits were sometimes formed in good products, but the silicon pits did not reach the depletion layer. For example, if the depletion layer edge is 0.5 μm, the silicon pits in good products were 0.5 μm deep or less, as shown in the middle or right, while the silicon pits in defective products exceeded 0.5 μm and reached 1 μm.

[0039] As shown in Figures 10 and 11, silicon pits are thought to occur as follows. First, an anode contact is opened by dry etching (step S1001). An opening is formed by selectively removing an insulating film, such as an interlayer insulating film, on a semiconductor substrate. Then, as shown in the top diagram of Figure 11, a damaged layer 1101 is formed on the P-type body region 14 in the opening. The damaged layer 1101 is an unterminated layer, such as silicon suboxide.

[0040] Next, the damaged layer is removed by light etching (step S1002). As shown in the second diagram from the top of FIG. 11, the damaged layer 1101 is removed. Next, an AlSi electrode is formed (step S1003). As shown in the third diagram from the top of FIG. 11, an anode electrode AE ​​is formed from AlSi. At this time, a groove 1102 reaching the silicon may be formed.

[0041] Finally, after the anode is formed, silicon pits are formed by the penetration of alkaline solution into the grooves 1102 during the polyimide formation process. The penetrated chemical solution is then evaporated during the subsequent heat treatment process. In addition, an electrode is reflowed and embedded in the silicon pits (step S1004). As shown in the bottom diagram of Figure 11, the silicon pits are formed, reaching the N-type drift region 11.

[0042] In such a case, it is believed that leakage current occurs, and therefore a method for manufacturing a semiconductor device that suppresses the generation of silicon pits is required.

[0043] (Explanation of First Manufacturing Method of Semiconductor Device of the Present Disclosure) Fig. 12 is a diagram showing the relationship between light etching time and VF characteristics. Fig. 13 is a flowchart of a method for manufacturing a semiconductor device according to the present disclosure. Fig. 14 is a cross-sectional view of a first manufacturing step of a semiconductor device according to the present disclosure. The first manufacturing method of a semiconductor device according to the present disclosure will be described with reference to Figs. 13 and 14.

[0044] The inventors have discovered that silicon pits occur when the damaged layer is removed in step S1002 in a related method for fabricating a semiconductor device. Furthermore, as shown in Figure 12, the VF characteristic, which is resistance, can be reduced by performing light etching for 10 to 20 seconds, but the VF characteristic can be further reduced without light etching.

[0045] Therefore, as shown in FIG. 13, in the first method for fabricating a semiconductor device of the present disclosure, an anode contact opening is performed by dry etching (step S1301). As shown in the top diagram of FIG. 14, a damaged layer 1101 is formed due to the anode opening. Next, light etching for removing the damaged layer is skipped (step S1302). As shown in the second diagram from the top of FIG. 14, the damaged layer 1101 is left. Next, an AlSi electrode is formed (step S1303). As shown in the third diagram from the top of FIG. 14, an anode electrode AE ​​is formed.

[0046] Finally, an alkaline solution penetrates during the polyimide formation process, but the penetrated chemical solution evaporates during the subsequent heat treatment process (step S1304). As shown in the bottom diagram of Figure 14, no silicon pits are generated in the semiconductor device.

[0047] In this way, a method for manufacturing a semiconductor device can be provided in which a metal film is formed while leaving a damaged layer on the surface of the semiconductor substrate in order to suppress the occurrence of silicon pits that occur when polyimide is formed after the metal film is formed.

[0048] The semiconductor device thus fabricated includes an insulating film selectively disposed on the semiconductor substrate, an electrode formed of a metal film selectively disposed on the semiconductor substrate, and polyimide on the electrode. The semiconductor device also includes a damaged layer formed when the insulating film is selectively removed under the electrode.

[0049] (Explanation of Second Manufacturing Method of Semiconductor Device of the Present Disclosure) FIG. 15 is a cross-sectional view of a second manufacturing process of a semiconductor device of the present disclosure. FIG. 16 is a cross-sectional view showing the principle of silicon pit generation. FIG. 17 is a diagram showing the relationship between the width and depth of a silicon pit. FIG. 18 is a diagram showing the path of current flow when a probe is applied to a position where a silicon pit has occurred. FIG. 19 is a diagram showing the path of current flow when a bonding wire is applied to a position where a silicon pit has occurred. FIG. 20 is a diagram showing considerations regarding the spacing between silicon pits. FIG. 21 is a diagram showing the results of a simulation of the relationship between the spacing between silicon pits and VR characteristics. A method of manufacturing a second semiconductor device of the present disclosure will be described with reference to FIGS. 15 to 21.

[0050] The second method for fabricating a semiconductor device according to the present disclosure involves controlling the occurrence of silicon pits. As shown in the top diagram of FIG. 15, a damaged layer 1101 is formed in the opening for the anode electrode contact. Next, as shown in the second diagram from the top of FIG. 15, a mask 1103 is formed to selectively remove the damaged layer 1101. The light etching time is preferably 10 to 20 seconds.

[0051] Next, as shown in the third diagram from the top in Figure 15, an anode electrode AE ​​is formed. At this time, a groove 1102 is formed in the anode electrode AE, reaching the silicon. Next, as shown in the bottom diagram in Figure 15, after forming polyimide, the anode electrode is reflowed to form silicon pits. However, silicon pits are not formed in areas where the damaged layer has not been removed, and the silicon pits are formed selectively.

[0052] By selectively removing the damaged layer in this manner, a method for manufacturing a semiconductor device in which the generation of silicon pits is controlled can be achieved, and a semiconductor device can be obtained.

[0053] 16 shows the etching of silicon due to the penetration of an alkaline solution. As shown in FIG. 16, when the damaged layer 1101 is opened, the P-type body region 14 is tangent to the surface. -1It is etched at an angle of √2 = 54.7°. This is because if the surface has a plane orientation of {100}, the side surface has a plane orientation of {111}. If the depth is D, then as shown in Figure 17, D is expressed as D = opening size X × tan(54.7°) / 2. In other words, if the size X at which the damaged layer is removed is 2 × thickness to the depletion layer / tan(54.7°), the silicon pit will not reach the depletion layer.

[0054] Therefore, it is preferable that the area where the damaged layer has been removed be smaller than the thickness of the depletion layer of the semiconductor device × 2 / tan(54.7°). For example, if the depletion layer begins at 500 nm, it is preferable that the area where the damaged layer has been removed have a width of 708 nm. In this way, by controlling the width of the damaged layer to be removed, the depth of the silicon pit can be controlled.

[0055] As shown in Figure 18, a wafer test probe 1801 may be placed in the area where silicon pits occur. As shown in Figure 12, due to the VF characteristics, current flows more easily when the etching time is zero, and current flows less easily when light etching is performed. Therefore, by placing the probe 1801 in the area where selectively formed silicon pits occur, it is possible to prevent current concentration due to the probe 1801. For this reason, it is advisable to align the area where the damaged layer 1101 has been selectively removed with the area where the probe 1801 is placed.

[0056] 19, a bonding wire 1901 may be placed in the region where silicon pits are generated. By placing the bonding wire 1901 in the region where selectively formed silicon pits are generated, it is possible to prevent current concentration due to the bonding wire 1901, as with the probe 1801. For this reason, it is preferable that the region where the damaged layer 1101 has been selectively removed is aligned with the region where the bonding wire 1901 is placed.

[0057] The pit spacing will be considered with reference to Figures 20 and 21. As shown in Figures 20 and 21, when simulations are performed with different pit spacings, the electric field concentration at the tips of the silicon pits creates an avalanche point, resulting in a decrease in breakdown voltage that depends on the pit shape. As shown in Figure 21, the simulations reveal that the VR characteristic, which is the breakdown voltage characteristic, increases when the pit spacing is 10 μm or less, for example, 5 μm. When the pit spacing is narrow, the field plate effect is exerted, which reduces the electric field at the tips of the pits, improving the breakdown voltage characteristic. Therefore, as shown in Figure 20, it is recommended to selectively remove the damaged layer to set the pit spacing to 10 μm or less, preferably 5 μm or less.

[0058] (Description of the second semiconductor device of the present disclosure) Fig. 22 is a top view of a second semiconductor device of the present disclosure. Fig. 23 is a cross-sectional view taken along line XXI-XXI of the semiconductor device of Fig. 22. The second semiconductor device of the present disclosure will be described with reference to Figs. 22 and 23.

[0059] As shown in Figures 22 and 23, near the edge of the anode electrode AE, carriers flow from the surrounding structure during recovery operation, so current is more likely to concentrate there than in the anode electrode AE. Therefore, to prevent current concentration, a light etching process is performed near the edge of the anode electrode AE. In other words, the area where the damaged layer 1101 has been removed is aligned with the edge of the anode electrode AE. In this way, damage during recovery operation is suppressed. The vicinity of the edge is, for example, a range of approximately 5 µm to 100 µm from the edge.

[0060] For example, the semiconductor device according to the above embodiments may be configured such that the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. are reversed. Therefore, when one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0061] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0062] 11 N-type drift region, 13 P-type field region, 14 P-type body region, 15 N+ type semiconductor region, 21 interlayer insulating film, 22 contact hole, 23 metal layer, 24 cathode electrode, 100 semiconductor device, 101 anode pad, 102 polyimide, 201 N+ type semiconductor region, 1101 damaged layer, 1102 trench, 1103 mask, 1801 probe, 1901 bonding wire, AE anode electrode, 1s semiconductor substrate

Claims

1. forming an insulating film on a semiconductor substrate; Selectively removing the insulating film; forming a metal film on the semiconductor substrate while leaving a damaged layer on the surface of the semiconductor substrate that is generated when the insulating film is selectively removed; selectively removing the metal film to form an electrode; forming a polyimide film on the electrode;

2. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising selectively removing a damaged layer on the surface of said semiconductor substrate, which is generated when said insulating film is selectively removed.

3. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the region from which the damaged layer has been removed is smaller than a thickness of a depletion layer of the semiconductor device×2 / tan(54.7°).

4. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the damaged layer is removed by wet etching for 10 to 20 seconds.

5. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a probe or a bonding wire for a wafer test is placed in the region where the damaged layer has been removed.

6. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the interval between the regions where the damaged layer has been removed is 5 [mu]m or less.

7. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the region from which the damaged layer is removed is in the vicinity of an end portion of the electrode.

8. an insulating film selectively disposed on a semiconductor substrate; an electrode formed of a metal film selectively disposed on the semiconductor substrate; a polyimide on the electrode, The semiconductor device further comprises a damaged layer formed under the electrode when the insulating film is selectively removed.

9. 9. The semiconductor device according to claim 8, wherein the damaged layer is selectively removed.

10. 10. The semiconductor device according to claim 9, wherein the area from which the damaged layer has been removed is smaller than a thickness of a depletion layer of the semiconductor device×2 / tan(54.7°).

11. 10. The semiconductor device according to claim 9, wherein a probe or a bonding wire for a wafer test is placed in the region where the damaged layer has been removed.

12. 10. The semiconductor device according to claim 9, wherein the interval between the regions where the damaged layer has been removed is 5 [mu]m or less.

13. 10. The semiconductor device according to claim 9, wherein the region from which the damaged layer has been removed is in the vicinity of an end of the electrode.

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