Light-emitting element driving device, light-emitting system, backlight, and display device

Abstract

The power supply voltage supplied to the light emitting section can be adjusted more appropriately. [Solution] A light-emitting element driving device (1) comprises a monitor unit (MT) that monitors the voltage of a connection terminal (CH) where a drive current is in an on state and stores the monitoring result, an output unit (OUT) that outputs a terminal voltage detection signal indicating whether the voltage of the connection terminal of at least one channel is lower than a reference voltage based on the stored monitoring result, an output terminal (SUMFB) that outputs the terminal voltage detection signal to the outside, an input terminal (SUMFB), and a control signal generation unit (5) that generates a control signal used for feedback control of a power supply circuit (3) that generates a power supply voltage based on a signal input to the input terminal and the stored monitoring result, wherein the on state of the drive current is controlled during one cycle of a synchronization signal (VSYNC), and the control signal generation unit updates the control signal when the next cycle of the synchronization signal starts.

Description

[Technical Field]

[0001] The present disclosure relates to a light emitting element driving device. [Background technology]

[0002] Conventionally, Patent Document 1 discloses a light-emitting element driving device that has connection terminals for multiple channels to be connected to a light-emitting unit consisting of one or more light-emitting elements, and is configured to be able to supply drive current to the light-emitting unit via the connection terminals for each channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 153668

[0004] [overview] A power supply voltage output from a power supply circuit is commonly applied to the light emitting units of the multiple channels. The light emitting element driving device includes an FB terminal for supplying a feedback signal to the power supply circuit, and a control block having a function of adjusting the power supply voltage through the FB terminal based on the voltage of the connection terminal of each channel.

[0005] One aspect of the present disclosure is a light-emitting element driving device used in a light-emitting system in which at least one channel of a light-emitting unit including at least one light-emitting element is provided, a connection terminal configured to be connectable to a low potential end of the light-emitting unit of at least one channel; a monitor unit that monitors the voltage of the connection terminal to which the drive current is turned on and stores the monitoring result; an output unit configured to output a terminal voltage detection signal indicating whether the voltage of the connection terminal of at least one channel is lower than a reference voltage based on the stored monitoring result; an output terminal configured to output the terminal voltage detection signal to an external device; an input terminal configured to be connectable to the output terminal of another light-emitting element driving device; a control signal generating unit configured to generate a control signal used for feedback control of a power supply circuit configured to generate a power supply voltage to be applied to a high potential end of the light emitting unit, based on the signal input to the input terminal and the held monitoring result; Equipped with The ON state of the drive current is controlled in one cycle of a synchronization signal, The control signal generating section is configured to update the control signal when the next cycle of the synchronization signal starts. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing the configuration of a light-emitting system. [Figure 2] FIG. 2 is a diagram showing an example of a light emitting system configured using a plurality of light emitting element driving devices. [Figure 3] FIG. 3 is a diagram showing an example of a system using a plurality of light-emitting element driving devices according to a comparative example. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of the FB current generating unit. [Figure 5] FIG. 5 is a timing chart showing a first operation example in a system using a light emitting element driving device according to a comparative example. [Figure 6] FIG. 6 is a timing chart showing a second operation example in a system using a light emitting element driving device according to a comparative example. [Figure 7] FIG. 7 is a diagram showing an example of a system using a plurality of light-emitting element driving devices according to the first embodiment. [Figure 8] FIG. 8 is a timing chart showing a first operation example in the system using the light emitting element driving device according to the first embodiment. [Figure 9] FIG. 9 is a timing chart showing a second operation example in the system using the light emitting element driving device according to the first embodiment. [Figure 10]FIG. 10 is a diagram showing an example of a system using a plurality of light emitting element driving devices according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing an example of a system using a plurality of light emitting element driving devices according to the third embodiment. [Figure 12] FIG. 12 is a diagram showing the configuration of a light emitting system using a light emitting element driving device according to the fourth embodiment. [Figure 13] FIG. 13 is a diagram showing the internal configuration of the light emitting element driving device 1 according to the fourth embodiment. [Figure 14] FIG. 14 is a diagram illustrating a time-division light emission operation. [Figure 15] FIG. 15 is a diagram showing an example of the configuration of a liquid crystal display device. [Figure 16] FIG. 16 is a diagram showing an example of an in-vehicle display.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <Lighting system> FIG. 1 is a diagram showing the configuration of a light emitting system SYS. The light emitting system SYS includes a light emitting element driving device 1, an MCU (Micro Controller Unit) 2 that controls the light emitting element driving device 1, a plurality of light emitting units LL that are driven by the light emitting element driving device 1, and a power supply circuit 3 that outputs a power supply voltage Vout. The power supply voltage Vout is a positive DC voltage. The light emitting element driving device 1 has a terminal VINSW that receives the power supply voltage Vout as an external terminal, and is driven based on the power supply voltage Vout. Note that a current setting resistor R ISET are also included in the components of the light-emitting system SYS.

[0009] The light-emitting element driving device 1 is a semiconductor device configured to be able to drive light-emitting units LL[1] to LL[n] of multiple channels (n channels). Each of the light-emitting units LL[1] to LL[n] includes one or more light-emitting elements. In the example of FIG. 1, the light-emitting elements are LEDs (light-emitting diodes). In the following description, the light-emitting elements are described as LEDs as an example. In other words, the light-emitting element driving device functions as an LED driving device. The high potential terminals (anodes) of the light-emitting units LL[1] to LL[n] are connected to the application terminal of the power supply voltage Vout.

[0010] The light-emitting element driving device 1 has connection terminals CH[1] to CH[n] as external terminals for establishing electrical connection with the outside. The low potential ends (cathode) of the light-emitting units LL[1] to LL[n] are connected to the connection terminals CH[1] to CH[n], respectively. The light-emitting element driving device 1 includes a driver block 10. The driver block 10 has current drivers DRV[1] to DRV[n]. The current drivers DRV[1] to DRV[n] are connected to the connection terminals CH[1] to CH[n], respectively. The current drivers DRV[1] to DRV[n] control the driving current I that flows to each of the light-emitting units LL[1] to LL[n] via the connection terminals CH[1] to CH[n], respectively. LED [1] to I LED [n] is generated.

[0011] The light-emitting element driving device 1 includes a control block 11. The control block 11 comprehensively controls the operation of each component in the light-emitting element driving device 1. The control block 11 can individually turn on or off the current drivers DRV[1] to DRV[n]. In addition, during normal light-emitting operation, the control block 11 has the function of adjusting the power supply voltage Vout output from the power supply circuit 3 through the terminal FB (feedback terminal) based on the terminal voltages of the connection terminals CH[1] to CH[n]. Such feedback control will be described in detail later.

[0012] The light-emitting element driving device 1 has a terminal SYNC as an external terminal. A synchronization signal VSYNC is input to the terminal SYNC from the outside. The current drivers DRV[1] to DRV[n] operate based on the rising edge of the synchronization signal VSYNC.

[0013] The light-emitting element driving device 1 includes a terminal SUMFB as an external terminal. The terminal SUMFB is a terminal used when a plurality of light-emitting element driving devices 1 are used, and will be described in detail later.

[0014] The light-emitting element driving device 1 and the MCU 2 are capable of two-way communication via a communication wire. This two-way communication allows the MCU 2 to send any command to the light-emitting element driving device 1, and the light-emitting element driving device 1 to send a response signal to the received command to the MCU 2. Any communication method may be used between the light-emitting element driving device 1 and the MCU 2, and may be, for example, one that complies with SPI (Serial Peripheral Interface).

[0015] The light emitting element driving device 1 is also provided with a terminal GND and a terminal ISET as external terminals. The terminal GND is connected to a ground terminal (a terminal to which a ground potential is applied). ISET A current setting resistor R ISET One end of the resistor is connected to the terminal ISET, and the other end of the resistor R ISET The other end of the control block 11 is connected to the ground terminal. ISET Based on the value of and the command from MCU2, the drive current I LED [1]~I LED

[24] The size can be set individually.

[0016] FIG. 2 is a diagram showing an example of a light emitting system configured using a plurality of light emitting element driving devices 1. FIG. 2 shows a light emitting system SYS2 configured using two light emitting element driving devices 1 as an example. Of the plurality of light emitting element driving devices 1, one functions as a main and the rest function as sub. In other words, the configuration of the main and sub light emitting element driving devices 1 is the same. In FIG. 2, a main light emitting element driving device 1_M and a sub light emitting element driving device 1_S are provided. The plurality of light emitting element driving devices 1 respectively drive light emitting units LL[1] to LL[n]. A power supply voltage Vout is applied to the high potential end (anode) of each set of light emitting units LL[1] to LL[n].

[0017] The MCU 2 communicates with the control blocks 11 of the light emitting element driving devices 1_M and 1_S. The synchronization signal VSYNC is input to the terminals SYNC of the light emitting element driving devices 1_M and 1_S. In each of the light emitting element driving devices 1_M and 1_S, the current drivers DRV[1] to DRV[n] in the driver block 10 operate based on the rising edge of the synchronization signal VSYNC.

[0018] The terminals SUMFB of the light-emitting element driving devices 1_M and 1_S are connected together. In the sub light-emitting element driving device 1_S, a signal resulting from monitoring the terminal voltages of the connection terminals CH[1] to CH[n] of the light-emitting element driving device 1_S is output from the control block 11 to the outside via the terminal SUMFB. In the main light-emitting element driving device 1_M, the signal output from the terminal SUMFB of the light-emitting element driving device 1_S is input to its own terminal SUMFB. The control block 11 in the light-emitting element driving device 1_M adjusts the power supply voltage Vout of the power supply circuit 3 via the terminal FB based on the result of monitoring the terminal voltages of the connection terminals CH[1] to CH[n] of the light-emitting element driving device 1_M and the signal input to the terminal SUMFB. This allows the power supply voltage Vout to be adjusted according to the terminal voltages of the connection terminals CH[1] to CH[n] of the multiple light-emitting element driving devices 1.

[0019] <Comparative Example> Here, before describing the embodiments of the present disclosure described later, a comparative example will be described for comparison, which will make the problems to be solved more clear.

[0020] 3 is a diagram showing an example of a system using a plurality of light-emitting element driving devices 1 according to a comparative example. In FIG. 3, a main light-emitting element driving device 1_M and a sub light-emitting element driving device 1_S are used. The internal circuit configuration of the light-emitting element driving device 1 shown in FIG. 3 is the internal configuration of a control block 11 (the same applies to FIGS. 7, 10, 11, and 13 described later).

[0021] The light-emitting element driving device 1 (control block 11) includes comparators CP[1] to CP[n], an NMOS transistor M1, a pull-up resistor Rp, a latch processing unit 4, an FB (feedback) current generating unit 5, a delay circuit 6, and an OR gate 7.

[0022] The inverting input terminal (-) of each of the comparators CP[1] to CP[n] is connected to the connection terminal CH[1] to CH[n], respectively. The non-inverting input terminal (+) of each of the comparators CP[1] to CP[n] is connected to the application terminal of the reference voltage Vref. As a result, each of the comparators CP[1] to CP[n] compares the terminal voltage of each of the connection terminals CH[1] to CH[n] with the reference voltage Vref and outputs the comparison result. The comparison result corresponds to the monitoring result of the terminal voltage of each of the connection terminals CH[1] to CH[n].

[0023] The OR gate 7 receives the outputs of the comparators CP[1] to CP[n]. The NMOS transistor M1 is configured by an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). The gate of the NMOS transistor M1 is connected to the output terminal of the OR gate 7. The source of the NMOS transistor M1 is connected to the ground terminal. The drain of the NMOS transistor M1 is connected to one terminal of the pull-up resistor Rp and the terminal SUMFB. The other terminal of the pull-up resistor Rp is connected to the application terminal of the power supply voltage Vdd. The NMOS transistor M1 configures an output section with an open drain configuration.

[0024] The terminals SUMFB of the main light-emitting element driving device 1_M and the sub light-emitting element driving device 1_S are connected. When the terminal voltage of at least one of the connection terminals CH[1] to CH[n] in the light-emitting element driving device 1_S is lower than the reference voltage Vref, the output of the OR gate 7 becomes high level, the NMOS transistor M1 is turned on, and the terminal voltage detection signal Sdet output from the terminal SUMFB becomes low level. In this case, in the main light-emitting element driving device 1_M, the voltage of the terminal SUMFB (terminal voltage detection signal Sdet) becomes low level regardless of the terminal voltage state of the connection terminals CH[1] to CH[n].

[0025] On the other hand, if all of the terminal voltages of the connection terminals CH[1] to CH[n] in the light-emitting element driving device 1_S are equal to or higher than the reference voltage Vref, the output of the OR gate 7 becomes low level, and the NMOS transistor M1 is turned off. In this case, in the main light-emitting element driving device 1_M, the voltage of the terminal SUMFB (terminal voltage detection signal Sdet) becomes low level or high level depending on the state of the terminal voltages of the connection terminals CH[1] to CH[n].

[0026] In other words, if the terminal voltage of at least one of the connection terminals CH[1] to CH[n] in the light-emitting element driving devices 1_M and 1_S is lower than the reference voltage Vref, the voltage of the terminal SUMFB in the light-emitting element driving device 1_M becomes low level, and if all of the terminal voltages of the connection terminals CH[1] to CH[n] in the light-emitting element driving devices 1_M and 1_S are higher than the reference voltage Vref, the voltage of the terminal SUMFB in the light-emitting element driving device 1_M becomes high level.

[0027] The latch processing unit 4, FB current generation unit 5, and delay circuit 6 are disabled in the sub light-emitting element driving device 1_S (hatched in FIG. 3). The latch processing unit 4 latches (holds) the voltage of the terminal SUMFB using the latch signal SA as a trigger. The latch processing unit 4 outputs a latch signal SUMFB_LATCH as the latch result.

[0028] 4 shows a configuration example of the FB current generating unit 5. The FB current generating unit 5 has a DAC (DA converter) 51 and a constant current circuit 52. The DAC 51 sets DAC data (digital value) in accordance with the latch signal SUMFB_LATCH, converts the set DAC data into an analog voltage VA, and outputs it to the constant current circuit 52. A synchronization signal VSYNC is also input to the DAC 51. The DAC 51 updates the DAC data using the synchronization signal VSYNC as a trigger.

[0029] The constant current circuit 52 generates a constant current, FB current Ifb, in response to an analog voltage VA serving as a current command value. The FB current Ifb flows via a terminal FB. The constant current circuit 52 has an error amplifier 52A, an output transistor 52B, and a resistor 52C. The analog voltage VA output from the DAC 51 is applied to a non-inverting input terminal of the error amplifier 52A. The output terminal of the error amplifier 52A is connected to the gate of the output transistor 52B, which is an N-channel MOSFET. The source of the output transistor 52B is connected to the inverting input terminal of the error amplifier 52A and one terminal of the resistor 52C. The other terminal of the resistor 52C is connected to the ground terminal. The drain of the output transistor 52B is connected to the terminal FB.

[0030] As shown in FIG. 4, the power supply circuit 3 (also shown in FIGS. 1 and 2) includes a DC / DC converter 3A and feedback resistors R1 to R3. The feedback resistors R1 to R3 are connected in series between an application terminal of a power supply voltage Vout output from the DC / DC converter 3A and a ground terminal. Specifically, the application terminal of the power supply voltage Vout is connected to one terminal of the feedback resistor R1. The other terminal of the feedback resistor R1 is connected to one terminal of a feedback resistor R2 at a node N1. The other terminal of the feedback resistor R2 is connected to one terminal of a feedback resistor R3 at a node N2. The other terminal of the feedback resistor R3 is connected to the ground terminal. The node N1 is connected to a terminal FB. With this configuration, the FB current Ifb generated by the constant current circuit 52 in response to the analog voltage VA is drawn from the node N1 via the terminal FB. A feedback voltage Vfb is generated at the node N2 in response to the FB current Ifb. The DC / DC converter 3A controls the power supply voltage Vout so that the feedback voltage Vfb matches a predetermined reference voltage.

[0031] When the latch signal SUMFB_LATCH is at a low level, the terminal voltage of at least one of the connection terminals CH[1] to CH[n] in the light-emitting element driving devices 1_M and 1_S is insufficient, so the DAC 51 sets the DAC data to increase the analog voltage VA in response to a trigger from the synchronization signal VSYNC, thereby increasing the FB current Ifb and adjusting the power supply voltage Vout to increase.

[0032] On the other hand, when the latch signal SUMFB_LATCH is at a high level, all of the terminal voltages of the connection terminals CH[1] to CH[n] in the light-emitting element driving devices 1_M and 1_S are sufficient, so that the DAC 51 is triggered by the synchronization signal VSYNC to set the DAC data so that the analog voltage VA is lower than the current value, thereby reducing the FB current Ifb and adjusting the power supply voltage Vout to decrease.

[0033] 3, the delay circuit 6 delays the synchronization signal VSYNC to generate a synchronization signal VSYNC_DLY, which is input to the latch processing unit 4. The latch processing unit 4 releases the latch using the synchronization signal VSYNC_DLY as a trigger.

[0034] Here, the light emitting element driving device 1 is provided with a phase shift function that shifts the timing at which the main and sub light emitting units are driven. The following describes the problems that arise in the comparative example when such a phase shift function is enabled.

[0035] 5 is a timing chart showing a first operation example of the system using the light emitting element driving device 1 according to the comparative example shown in FIG. 5. In FIG. 5, from the top, the synchronization signal VSYNC, the main driving current I LED (M), the terminal voltage VLED(M) of the connection terminal CH in the main, the output signal SB(M) of the OR gate 7 in the main, and the drive current I LED (S), the terminal voltage VLED(S) of the connection terminal CH in the sub, the output signal SB(S) of the OR gate 7 in the sub, the terminal voltage detection signal Sdet (voltage of the terminal SUMFB), the latch signal SA(M) in the main, the latch signal SUMFB_LATCH(M) in the main, and the DAC data DAC_DT set in DAC51.

[0036] First, the synchronization signal VSYNC rises at timing t1. Based on this rising edge, the drive current I LED (M) and drive current I LED (S) flows. Here, the phase shift function causes the drive current I LED (M) and drive current I LED The timing of (S) flow is off.

[0037] After timing t1, at timing t2, the drive current I LED Here, the drive current I (M) starts to flow from timing t2 in all of the main connection terminals CH[1] to CH[n]. LEDflows. At this time, the terminal voltage VLED(M) of the connection terminal CH in the main drops. Here, it is assumed that the terminal voltage VLED(M) of at least one of the connection terminals CH[1] to CH[n] is lower than the reference voltage Vref. As a result, the output signal SB(M) of the OR gate 7 in the main becomes high level, and the terminal voltage detection signal Sdet becomes low level.

[0038] The latch signal SA(M) in the main is the drive current I LED The latch signal SA(M) is generated so that it rises within a predetermined period (hatched) from timing t1 while the latch signal SA(M) is flowing. When the latch signal SA(M) rises (timing t3), this triggers the latch processing unit 4 in the main to latch the terminal voltage detection signal Sdet. Therefore, the latch signal SUMFB_LATCH(M) in the main falls to low level.

[0039] After that, at timing t4, the drive current I LED (M) stops flowing (stop of drive current), the terminal voltage VLED(M) becomes equal to or higher than the reference voltage Vref, the output signal SB(M) becomes low level, and the terminal voltage detection signal Sdet returns to high level.

[0040] Then, at timing t5, the drive current I LED Here, the drive current I (S) starts to flow from timing t5 in all of the connection terminals CH[1] to CH[n] in the sub. LED At this time, the terminal voltage VLED(S) of the connection terminal CH in the sub drops. Here, it is assumed that all of the terminal voltages VLED(S) of the connection terminals CH[1] to CH[n] are equal to or higher than the reference voltage Vref. As a result, the output signal SB(S) of the OR gate 7 in the sub becomes low level, and the terminal voltage detection signal Sdet is maintained at high level.

[0041] After that, when the synchronization signal VSYNC rises again at timing t6 (the start of the next cycle of VSYNC), this triggers the DAC 51 to update the DAC data. Here, because the latch signal SUMFB_LATCH(M) is at a low level, the DAC data is updated so that the analog voltage VA increases. As a result, the power supply voltage Vout is adjusted to increase.

[0042] The rising edge of the synchronization signal VSYNC is delayed by the delay circuit 6, and the delayed rising edge occurs at timing t7, which triggers the latch processing unit 4 to release the latch.

[0043] In this way, in the example shown in Figure 5, it is possible to detect that the terminal voltage at the connection terminal CH in the main is insufficient and latch the terminal voltage detection signal Sdet, so that this can be reflected when updating the DAC data, which is triggered by the rising edge of the synchronization signal VSYNC.

[0044] Next, a second operation example of the system using the light emitting element driving device 1 according to the comparative example shown in FIG. 3 is shown in FIG. 6. Here, differences from the example in FIG. 5 are explained. In the example in FIG. 6, at timing t2, the driving current I LED When (M) flows, the terminal voltage VLED(M) at the main drops but remains above the reference voltage Vref. This causes the terminal voltage detection signal Sdet to go high, and even if the terminal voltage detection signal Sdet is latched at timing t3, the latch signal SUMFB_LATCH(M) remains high.

[0045] In Figure 6, at timing t5, the drive current I LEDWhen (S) flows, the terminal voltage VLED(M) at the sub-terminal drops and becomes lower than the reference voltage Vref. This causes the terminal voltage detection signal Sdet to go low, but because latching has already been performed, the low level of the terminal voltage detection signal Sdet at this point is ignored. Therefore, at timing t6 when the synchronization signal VSNC rises, the latch signal SUMFB_LATCH(M) is high, the DAC data is updated so that the analog voltage VA decreases, and the power supply voltage Vout is adjusted to decrease.

[0046] In the configuration of the comparative example, latching can only be performed when a drive current flows to the connection terminal CH of the main light-emitting element driving device 1_M. Therefore, when there is a shortage of terminal voltage at the connection terminal CH of the sub light-emitting element driving device 1_S, as in the example of Figure 6, the terminal voltage detection signal Sdet, which is the detection result, cannot be latched, the DAC data cannot be properly updated, and the power supply voltage Vout cannot be properly adjusted.

[0047] First Embodiment In view of the above-mentioned problems, the following embodiment is implemented.

[0048] 7 is a diagram showing an example of a system using a plurality of light emitting element driving devices 1 according to the first embodiment. In FIG. 7, a main light emitting element driving device 1_M and a sub light emitting element driving device 1_S are used.

[0049] The light-emitting element driving device 1 (control block 11) according to this embodiment includes comparators CP[1] to CP[n], latch processing units 4[1] to 4[n], an FB current generating unit 5, a delay circuit 6, an OR gate 7, an NMOS transistor M1, and a pull-up resistor Rp.

[0050] The comparators CP[1] to CP[n] are similar to those in the comparative example, and each compares the terminal voltage of each of the connection terminals CH[1] to CH[n] with the reference voltage Vref and outputs the comparison result. The comparison result corresponds to the monitoring result of the terminal voltage of each of the connection terminals CH[1] to CH[n].

[0051] The output signals SB[1] to SB[n] of the comparators CP[1] to CP[n] are input to the latch processing units 4[1] to 4[n], respectively. The latch processing units 4[1] to 4[n] latch the output signals SB[1] to SB[n] using the latch signals SA[1] to SA[n] as triggers. The latch processing units 4[1] to 4[n] output latch signals SB_LATCH[1] to SB_LATCH[n] as the latch results, respectively.

[0052] The output unit OUT has an OR gate 7, an NMOS transistor M1, and a pull-up resistor Rp. The latch signals SB_LATCH[1] to SB_LATCH[n] are input to the OR gate 7. The output of the OR gate 7 is input to the gate of the NMOS transistor M1. The connection relationship between the NMOS transistor M1, the pull-up resistor Rp, and the SUMFB terminal is the same as in the comparative example, and the NMOS transistor M1 configures the output unit OUT with an open-drain configuration.

[0053] A terminal voltage detection signal Sdet, which is a voltage generated at the terminal SUMFB, is input to the FB current generation unit 5. In this embodiment, instead of the latch signal SUMFB_LATCH in Fig. 4, the terminal voltage detection signal Sdet is input to the FB current generation unit 5. As a result, the DAC data is updated based on the terminal voltage detection signal Sdet, and the FB current Ifb is generated.

[0054] The delay circuit 6 is provided in common to the latch processing units 4[1] to 4[n], delays the synchronization signal VSYNC, and inputs the synchronization signal VSYNC_DLY to the latch processing units 4[1] to 4[n]. The latch processing units 4[1] to 4[n] release the latch using the synchronization signal VSYNC_DLY as a trigger.

[0055] In this way, the comparators CP[1] to CP[n] and the latch processing units 4[1] to 4[n] constitute a monitor unit MT that monitors the voltages of the connection terminals CH[1] to CH[n] and stores the monitoring results. The monitor unit MT also includes a delay circuit 6.

[0056] 7, the main light-emitting element driving device 1_M and the sub light-emitting element driving device 1_S, each having the configuration described above, are connected by connecting their SUMFB terminals. Note that the FB current generating unit 5 is disabled in the sub light-emitting element driving device 1_S.

[0057] Next, the operation of the system according to this embodiment will be described. Fig. 8 is a timing chart showing a first operation example of the system using the light emitting element driving device 1 according to this embodiment. Fig. 8 shows an example corresponding to the example according to the comparative example shown in Fig. 5 described above.

[0058] In FIG. 8, from the top to bottom, the synchronization signal VSYNC, the main drive current I LED (M), the terminal voltage VLED(M) of the connection terminal CH in the main, the output signal SB(M) of the comparator CP in the main, the latch signal SA(M) in the main, the latch signal SB_LATCH(M) in the main, the drive current I in the sub LED (S), the terminal voltage VLED(S) of the connection terminal CH in the sub, the output signal SB(S) of the comparator CP in the sub, the latch signal SA(S) in the sub, the latch signal SB_LATCH(S) in the sub, the terminal voltage detection signal Sdet (the voltage of the terminal SUMFB), and the DAC data DAC_DT set in the FB current generation unit 5.

[0059] First, at timing t11, the synchronization signal VSYNC rises. Based on this rising edge, the drive current I LED (M) and drive current I LED (S) flows. Here, the phase shift function causes the drive current I LED (M) and drive current I LEDThe timing of (S) flow is off.

[0060] After timing t11, at timing t12, the drive current I LED Here, the drive current I (M) starts to flow from timing t12 in all of the main connection terminals CH[1] to CH[n]. LED However, the drive current I LED The period during which this signal flows may differ for each channel (the same applies below). At this time, the terminal voltage VLED(M) of the connection terminal CH in the main drops. Here, it is assumed that the terminal voltage VLED(M) of at least one of the connection terminals CH[1] to CH[n] is lower than the reference voltage Vref. As a result, the output signal SB(M) in the main output from the comparator CP corresponding to the channel whose terminal voltage VLED(M) has become lower than the reference voltage Vref becomes high level.

[0061] The latch signal SA(M) in the main is the drive current I LED The latch signal SA(M) is generated so that it rises within a predetermined period (hatched) from timing t12 while the main output signal SB(M) is flowing. When the latch signal SA(M) rises (timing t13), this triggers the main latch processing units 4[1] to 4[n] to latch the output signals SB[1] to SB[n]. Therefore, the main latch signal SUMFB_LATCH(M), which has latched the main output signal SB(M) that has gone high, rises to high level.

[0062] As a result, the output of the OR gate 7 in the main becomes high level, the NMOS transistor M1 is turned on, and the terminal voltage detection signal Sdet falls to low level.

[0063] After that, at timing t14, the drive current I LED(M) stops flowing (the drive current stops), the terminal voltage VLED(M) becomes equal to or higher than the reference voltage Vref, and the output signal SB(M) goes low. However, since it is latched, the output of the OR gate 7 remains high, and the terminal voltage detection signal Sdet remains low.

[0064] Then, at timing t15, the drive current I LED Here, the drive current I (S) starts to flow from timing t15 in all of the connection terminals CH[1] to CH[n] in the sub. LED At this time, the terminal voltage VLED(S) of the connection terminal CH in the sub drops. Here, it is assumed that all of the terminal voltages VLED(S) of the connection terminals CH[1] to CH[n] are equal to or higher than the reference voltage Vref. This causes the output signal SB(S) in the sub to go low.

[0065] The latch signal SA(S) in the sub is the drive current I LED The latch signal SA(S) is generated so that it rises within a predetermined period (hatched) from timing t15 while the OR gate 7 in the sub is flowing. When the latch signal SA(S) rises (timing t16), this triggers the latch processing units 4[1] to 4[n] in the sub to latch the output signals SB[1] to SB[n]. Therefore, the latch signal SUMFB_LATCH(S) in the sub goes low. This causes the output of the OR gate 7 in the sub to go low, turning off the NMOS transistor M1.

[0066] After that, when the synchronization signal VSYNC rises again at timing t17 (the start of the next cycle of VSYNC), this triggers the DAC 51 in the FB current generator 5 to update the DAC data. Here, because the terminal voltage detection signal Sdet is at a low level, the DAC data is updated so as to increase the analog voltage VA. As a result, the power supply voltage Vout is adjusted to increase.

[0067] The rising edge of the synchronization signal VSYNC is delayed by the delay circuit 6, and a delayed rising edge occurs at timing t18, which triggers the latch processing units 4[1] to 4[n] to release the latch.

[0068] In this way, in the example shown in Figure 8, by latching the results of monitoring that a shortage of terminal voltage has occurred at the connection terminal CH in the main, the terminal voltage detection signal Sdet can be latched, and this can be reflected when updating the DAC data, which is triggered by the rising edge of the synchronization signal VSYNC.

[0069] Next, a second operation example of the system using the light emitting element driving device 1 according to this embodiment is shown in Fig. 9. Fig. 9 shows an example corresponding to the example shown in Fig. 6 according to the comparative example described above. Here, differences from the example in Fig. 8 will be described.

[0070] In the example of Figure 9, the main drive current I LED When (M) flows, the terminal voltage VLED(M) in the main drops but remains above the reference voltage Vref. This causes the output signal SB(M) in the main to go low, and even if the output signal SB(M) is latched at timing t13, the latch signal SB_LATCH(M) remains low. Therefore, the output of the OR gate 7 in the main goes low, the NMOS transistor M1 is turned off, and the terminal voltage detection signal Sdet is high.

[0071] In Fig. 9, at timing t15, the drive current I LED When (S) flows, the terminal voltage VLED(M) in the sub drops and becomes lower than the reference voltage Vref. This causes the output signal SB(S) in the sub to go high, and at timing t16 the output signal SB(S) is latched, so the latch signal SB_LATCH(S) goes high. Therefore, the output of the OR gate 7 in the sub goes high, the NMOS transistor M1 is turned on, and the terminal voltage detection signal Sdet goes low.

[0072] As a result, at timing t17 when the synchronization signal VSNC rises, the terminal voltage detection signal Sdet is at low level, the DAC data is updated so that the analog voltage VA increases, and the power supply voltage Vout is adjusted to increase.

[0073] In this way, in this embodiment, each of the main and sub light-emitting element driving devices 1 latches the monitoring result of the terminal voltage VLED when a driving current flows through its own connection terminal CH. Therefore, even in cases where there are problems with the operation in the comparative example, the insufficient voltage at the connection terminal CH can be reflected in the terminal voltage detection signal Sdet, and the power supply voltage Vout can be appropriately adjusted.

[0074] In the configuration of this embodiment shown in FIG. 7, a latch processing unit is provided for each comparator, so even if the timing at which the drive current flows differs between channels, the monitor result of the terminal voltage VLED is latched for each channel, so that a deficiency in the terminal voltage VLED can be reflected in the terminal voltage detection signal Sdet.

[0075] Second Embodiment FIG. 10 is a diagram showing an example of the configuration of a system using a light-emitting element driving device 1 according to the second embodiment. A difference from the first embodiment is that in this embodiment, the monitor unit MT includes comparators CP[1] to CP[n], an OR gate 7, one latch processing unit 4, and a delay circuit 6. The outputs of the comparators CP[1] to CP[n] are input to the OR gate 7. The latch processing unit 4 latches the output signal SB of the OR gate 7 and outputs a latch signal SB_LATCH to the gate of the NMOS transistor M1. In this embodiment, the output unit OUT includes an NMOS transistor M1 and a pull-up resistor Rp.

[0076] With this configuration, under conditions where drive currents flow at the same timing between channels in the same light-emitting element driving device 1, the monitor results of the terminal voltage VLED are latched in each of the main and sub light-emitting element driving devices 1, so that a deficiency in the terminal voltage VLED can be reflected in the terminal voltage detection signal Sdet. According to this embodiment, only one latch processing circuit is required compared to the first embodiment, which is advantageous in terms of circuit area.

[0077] Third Embodiment 11 is a diagram showing an example of the configuration of a system using a light emitting element driving device 1 according to the third embodiment. The difference from the first embodiment is that the light emitting element driving device 1 of this embodiment has an output terminal SUMOUT and an input terminal SUMIN as external terminals, and further has OR gates 71 to 73 as internal components. In this embodiment, the output unit OUT has OR gates 71 and 73.

[0078] The OR gate 71 receives the latch signals SB_LATCH[1] to SB_LATCHn] output from the latch processing units 4[1] to 4[n], respectively. The output terminal of the OR gate 71 is connected to a first input terminal of an OR gate 73, and the input terminal SUMIN is connected to a second input terminal of the OR gate 73. The output terminal of the OR gate 73 is connected to an output terminal SUMOUT. The output terminal of the OR gate 71 is connected to a first input terminal of an OR gate 72, and the input terminal SUMIN is connected to a second input terminal of the OR gate 72. The output of the OR gate 72 is input to the FB current generating unit 5.

[0079] In the configuration example of FIG. 11, a main light-emitting element driving device 1_M and sub light-emitting element driving devices 1_S are provided, so the output terminal SUMOUT of the light-emitting element driving device 1_S is connected to the input terminal SUMIN of the light-emitting element driving device 1_M. If two or more sub light-emitting element driving devices 1_S are provided, the output terminal SUMOUT is connected to the input terminal SUMIN of each light-emitting element driving device 1_S in turn. In other words, a daisy chain connection is made. The input terminal SUMIN of the light-emitting element driving device 1_S at the end is connected to the ground terminal.

[0080] According to this configuration, in each sub light-emitting element driving device 1_S, the logical sum of the latch signals SB_LATCH[1] to SB_LATCH[n] is output from the OR gate 71, the output of the OR gate 71 and the signal of the ground or the SUMIN terminal from the previous stage are input to the OR gate 73, and the logical sum of the inputs is input as the terminal voltage detection signal Sdet from the output terminal SUMOUT to the input terminal SUMIN of the next stage. Note that the FB current generating unit 5 in the sub light-emitting element driving device 1_S is disabled.

[0081] In the main light-emitting element driving device 1_M, the output of the OR gate 71 and the signal at the input terminal SUMIN are input to the OR gate 72, and the logical sum of the inputs is input to the FB current generating unit 5.

[0082] Therefore, if the terminal voltage VLED of at least one connection terminal CH in at least one of the main light-emitting element driving device 1_M and the sub light-emitting element driving device 1_S becomes insufficient, the corresponding latch signal SB_LATCH causes the output of the OR gate 72 in the main light-emitting element driving device 1_M to go high. In this embodiment, when the output of the OR gate 72 is high, the DAC 51 in the FB current generating unit 5 updates the DAC data to increase the analog voltage VA, thereby increasing the FB current Ifb and adjusting the power supply voltage Vout to increase. This allows the power supply voltage Vout to be appropriately adjusted.

[0083] The configuration of the second embodiment may be applied to this embodiment. That is, instead of the output of the OR gate 71, the latch signal SB_LATCH in the light-emitting element driving device 1 (FIG. 10) according to the second embodiment may be input to each of the OR gates 72 and 73.

[0084] <Fourth embodiment> FIG. 12 is a diagram showing the configuration of a light emitting system SYS using a light emitting element driving device 1 according to the fourth embodiment.

[0085] Here, it is assumed that a total of (n×m) light-emitting units LL are provided in the light-emitting system SYS as the plurality of light-emitting units LL, and the total (n×m) light-emitting units LL are represented by the symbol "LL[1,1] to LL[n,m]." Any one of the light-emitting units LL[1,1] to LL[n,m] is expressed as light-emitting unit LL[i,j], where i is an integer that satisfies "1≦i≦n" and j is an integer that satisfies "1≦j≦m." In the light-emitting system SYS and the light-emitting element driving device 1, first to n-th channels are set, and light-emitting units LL[i,1] to LL[i,m] belong to the i-th channel. Furthermore, the light-emitting units LL[1,1] to LL[n,m] can be classified into first to m-th groups, and light-emitting units LL[1,j] to LL[n,j] belong to the j-th group.

[0086] The light-emitting element driving device 1 is provided with connection terminals CH[1] to CH[n] equal to the total number of channels. The connection terminal CH[i] belongs to the i-th channel. The connection terminal CH[i] is a light-emitting element connection terminal to which the light-emitting elements LL[i,1] to LL[i,m] belonging to the i-th channel should be connected.

[0087] The light-emitting system SYS is provided with switches SW[1] to SW[m] equal to the total number of groups. The switch SW[j] is a switch corresponding to the jth group. One end of each of the switches SW[1] to SW[m] is commonly connected to an application terminal of the power supply voltage Vout. The other end of the switch SW[j] is commonly connected to each high-potential end (anode) of the light-emitting units LL[1,j] to LL[n,j] belonging to the jth group. The low-potential ends of the light-emitting units LL[i,1] to LL[i,m] belonging to the i-th channel are commonly connected to a wiring 8[i]. The wiring 8[i] is connected to a connection terminal CH[i].

[0088] The light emitting element driving device 1 includes a driver block 10 and a control block 11. The driver block 10 includes current drivers DRV[1] to DRV[n]. The current driver DRV[i] belongs to the i-th channel. That is, the driver block 10 includes a current driver for each channel. The current drivers DRV[1] to DRV[n] have the same configuration and function. In each channel, the current driver DRV[i] includes a constant current circuit, and in normal light emitting operation, under the control of the control block 11, a drive current I flows from the connection terminal CH[i] toward the ground terminal. LED [i] flows through the connection terminal CH[1]. LED When [1] flows through the light-emitting section LL[1,j], the light-emitting section LL[1,j] emits light, and the driving current I LED When [2] flows to the light emitting unit LL[2,j], the light emitting unit LL[2,j] emits light. The same applies to other driving currents and other light emitting units.

[0089] The control block 11 comprehensively controls the operation of each component within the light-emitting element drive device 1. The light-emitting element drive device 1 is provided with terminals GC[1] to GC[m] as external terminals connected to the control terminals of the switches SW[1] to SW[m]. The control block 11 can individually turn the switches SW[1] to SW[m] on or off via the terminals GC[1] to GC[m]. For example, a P-channel MOSFET can be used as each of the switches SW[1] to SW[m]. In this case, a power supply voltage Vout is supplied to the source of each MOSFET serving as the switches SW[1] to SW[m], and the drain of the MOSFET serving as the switch SW[j] is commonly connected to the high-potential terminals of the light-emitting units LL[1,j] to LL[n,j]. The control block 11 controls the gate voltage of each MOSFET serving as the switches SW[1] to SW[m] via the terminals GC[1] to GC[m].

[0090] The light emitting element driving device 1 shown in Fig. 12 is provided with a terminal SUMFB and a terminal SYNC, as in the previously described embodiment. Fig. 13 is a diagram showing the internal configuration of the control block 11 in the light emitting element driving device 1 according to this embodiment.

[0091] As shown in FIG. 13, comparators CP[1] to CP[n] are provided for the connection terminals CH[1] to CH[n], respectively. Latch processing units 4[i,1] to 4[i,m] are provided for the comparator CP[i] of the i-th channel. In this embodiment, the monitor unit MT has comparators CP[1] to CP[n] and latch processing units 4[1,1] to 4[n,m]. The output unit OUT has an OR gate 700, an NMOS transistor M1, and a pull-up resistor Rp. In the monitor unit MT, one delay circuit 6 is provided for each of the latch processing units 4[1,1] to 4[n,m].

[0092] Each of the latch processing units 4[i,1] to 4[i,m] latches the output of the comparator CP[i] using the latch signals SA[i,1] to SA[i,m] as a trigger. The latch results of each of the latch processing units 4[1,1] to 4[n,m] are input to an OR gate 700. The output terminal of the OR gate 700 is connected to the gate of the NMOS transistor M1. The configurations of the NMOS transistor M1, pull-up resistor Rp, FB current generating unit 5, and terminal SUMFB are the same as those in the first embodiment.

[0093] A time-division light-emitting operation, which is one type of normal light-emitting operation, will be described with reference to Fig. 14. Fig. 14 is a timing chart showing an example of the time-division light-emitting operation. In Fig. 14, from the top to bottom, there are a synchronization signal VSYNC, gate voltages PGATE1 to PGATEm of the switches SW[1] to SW[m], and a drive current I LED [1]~I LED The waveforms of the DAC data DAC_DT and the DAC signal [n] are shown below. The switch SW is assumed to be a P-channel MOSFET.

[0094] In the time-division light emission operation, a unit period Tu having a predetermined length is set. The unit period Tu is set repeatedly at a predetermined cycle. Furthermore, each unit period Tu is divided into m parts to set a first divided period T1 to an m-th divided period Tm. In the control block 11, in each of the first divided period T1 to the m-th divided period Tm, the gate voltages PGATE1 to PGATEm are set to a low level, and the switches SW[1] to SW[m] are set to an on state. That is, in the j-th divided period, of the switches SW[1] to SW[m], only the switch SW[j] is set to an on state, and the other (m-1) switches are set to an off state (the gate voltage PGATE is set to a high level). Therefore, during the jth division period, the power supply voltage Vout is supplied only to the high potential end of the light-emitting units LL[1,j] to LL[n,j] of the jth group among the first to mth groups via the switch SW[j], and only the light-emitting units LL[1,j] to LL[n,j] are able to emit light.

[0095] The control block 11 PWM-drives the current driver DRV for each channel in each of the first divided period T1 to the m-th divided period Tm. PWM is an abbreviation for pulse width modulation. In the PWM drive in each divided period, a drive current I LED The time width (in other words, the time length) during which the drive current I LED [1]~I LED The time width for which [n] is supplied is individually PWM controlled. As a result, the corresponding light-emitting unit LL emits pulsed light in each divided period, and the average brightness of the total (n × m) light-emitting units LL is individually adjusted through the control of the time width.

[0096] 13, when the switch SW of the j-th group is in the ON state and the drive current of the i-th channel is in the ON state, the latch signal SA[i,j] is used as a trigger to cause the latch processing unit [i,j] to latch the output of the comparator CP[i]. As a result, when the switch SW of the j-th group is in the ON state and the drive current of the i-th channel is in the ON state and the terminal voltage of the connection terminal CH[i] becomes insufficient, the output of the OR gate 700 becomes high level and the NMOS transistor M1 is turned on.

[0097] Here, when a plurality of light-emitting element driving devices 1 according to this embodiment are used, the SUMFB terminals of the main light-emitting element driving device 1 and the sub light-emitting element driving device 1 are connected to each other, as in the first embodiment described above. The FB current generating unit 5 in the sub light-emitting element driving device 1 is disabled. As a result, when the terminal voltage of the connection terminal CH becomes insufficient in either the main light-emitting element driving device 1 or the sub light-emitting element driving device 1, the signal of the SUMFB terminal is set to low level and transmitted to the FB current generating unit 5 in the main light-emitting element driving device 1. Therefore, the FB current generating unit 5 is triggered by the start of the next cycle of the synchronization signal VSYNC (the falling edge timing of VSYNC in FIG. 14), and updates the DAC data according to the signal of the SUMFB terminal and adjusts the power supply voltage Vout.

[0098] <Application to liquid crystal display devices (LCDs)> A liquid crystal display device will be described as an example of an application of the light emitting element driving device according to the embodiment described above. An example of the configuration of a liquid crystal display device is shown in Fig. 15. The configuration shown in Fig. 15 is a so-called direct type configuration.

[0099] 15 includes a backlight 91 and a liquid crystal panel 92. The backlight 91 is an illumination device (an example of a light-emitting device) that illuminates the liquid crystal panel 92 from behind. The backlight 91 includes a light source unit 911, a phosphor sheet 912, a diffusion plate 913, and optical sheets 914.

[0100] The light source unit 911 includes a light-emitting unit LL and a substrate on which the light-emitting unit is mounted, and the light-emitting element driving device for driving the light-emitting unit LL can be the same as that of the above-described embodiment. As in the above-described embodiment, a plurality of light-emitting element driving devices are provided, and a light-emitting unit LL is provided for each light-emitting element driving device.

[0101] The light-emitting unit LL emits blue light (monochromatic), for example. The phosphor sheet 912 transmits a portion of the blue light from the light source unit 911 and absorbs the other portion of the blue light to emit yellow light. In the backlight 91, the monochromatic light-emitting unit LL is combined with the phosphor sheet 912 to emit a synthesized white light. The diffusion plate 913 diffuses the light from the phosphor sheet 912. The optical sheets 914 impart a predetermined optical effect to the light from the diffusion plate 913 and emit it toward the liquid crystal panel 92.

[0102] The light emitting sections LL are arranged in a matrix in accordance with the divided display areas of the liquid crystal panel 92. The brightness of each light emitting section LL is adjusted by PWM driving, making local dimming possible.

[0103] <About in-vehicle displays> The liquid crystal display device to which the light-emitting element driving device according to the embodiment described above is applied is particularly suitable for use as an in-vehicle display. The in-vehicle display is provided on the dashboard in front of the driver's seat of a vehicle, for example, as in-vehicle display Y shown in Fig. 16. The in-vehicle display Y can display various images such as car navigation information, captured images of the area behind the vehicle, a speedometer, a tachometer, a fuel gauge, a fuel consumption meter, and a shift position, and can convey various information to the user.

[0104] The screens of in-vehicle displays are becoming larger and larger, but the light-emitting element driving device according to the above-mentioned embodiments (particularly the fourth embodiment) allows a single light-emitting element driving device to control a large number of light-emitting sections (divided display areas), thereby significantly reducing the number of light-emitting element driving devices installed and the mounting area.

[0105] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0106] For example, the FB control signal generated by the FB current generating unit in the above-described embodiment was an FB current drawn from a node to which a feedback resistor in a power supply circuit is connected, but this is not limited to this, and the FB control signal may be, for example, a control signal for varying a reference voltage to be compared with a feedback voltage in a DC / DC converter.

[0107] <Additional Notes> As described above, one aspect of the present disclosure is a light-emitting element driving device (1) used in a light-emitting system in which at least one channel of a light-emitting unit (LL) including at least one light-emitting element is provided, a connection terminal (CH) configured to be connectable to a low potential end of the light emitting unit of at least one channel; a monitor unit (MT) that monitors the voltage of the connection terminal to which the drive current is turned on and stores the monitoring result; an output unit (OUT) configured to output a terminal voltage detection signal (Sdet) indicating whether the voltage of the connection terminal of at least one channel is lower than a reference voltage (Vref) based on the stored monitoring result; an output terminal (SUMFB) configured to output the terminal voltage detection signal to the outside; an input terminal (SUMFB) configured to be connectable to the output terminal of another light-emitting element driving device; a control signal generating unit (5) configured to generate a control signal (Ifb) used for feedback control of a power supply circuit (3) configured to generate a power supply voltage (Vout) to be applied to a high potential end of the light emitting unit based on a signal input to the input terminal and the stored monitoring result; Equipped with The ON state of the drive current is controlled in one cycle of a synchronization signal (VSYNC), The control signal generating section is configured to update the control signal when the next cycle of the synchronization signal starts (first configuration, FIG. 7).

[0108] According to this configuration, when a plurality of light emitting element driving devices are used, the power supply voltage supplied to the light emitting section can be more appropriately adjusted based on the voltage at the connection terminal.

[0109] In the first configuration, the output terminal and the input terminal are the same terminal, The output section may have a configuration including a transistor (M1) having a first end connected to a pull-up resistor (Rp) and the output terminal and a second end connected to a ground end (second configuration, FIG. 7).

[0110] In the second configuration, the transistor may be an N-channel MOSFET, so that the output section has an open-drain configuration (third configuration).

[0111] In the first configuration, the output terminal (SUMOUT) and the input terminal (SUMIN) are separate terminals, The output unit may be configured to include a first logic circuit (71, 73) configured to receive the held monitoring result and the signal of the input terminal and to output the terminal voltage detection signal (fourth configuration, FIG. 11).

[0112] In the fourth configuration, the first logic circuit a first OR gate (71) configured to receive the held monitoring result; A second OR gate (73) configured to receive the output of the first OR gate and the signal at the input terminal and to output the terminal voltage detection signal may be provided (fifth configuration).

[0113] In addition, in any one of the first to fifth configurations, the monitor unit a comparator (CP) configured to compare the voltage of the connection terminal with a reference voltage; A latch processing unit (4) configured to latch the output of the comparator using a latch signal (SA) as a trigger may be provided (sixth configuration).

[0114] In the sixth configuration, the comparators (CP[1] to CP[n]) may be provided for each of the connection terminals for a plurality of channels (seventh configuration).

[0115] In the seventh configuration, the latch processing unit (4[1] to 4[n]) may be provided for each channel of the connection terminal (eighth configuration, FIG. 7).

[0116] In the seventh configuration, the latch processing unit (4) is provided for each of the plurality of channels, The monitor unit may have a configuration including a second logic circuit (7) configured to receive the outputs of the plurality of comparators and to output an output signal to the latch processing unit (ninth configuration, FIG. 10).

[0117] In addition, in any one of the sixth to ninth configurations, the monitor unit has a delay circuit (6) configured to delay the synchronization signal, The latch processing unit may be configured to release the latch based on the delayed synchronization signal (tenth configuration).

[0118] In any one of the first to tenth configurations, the connection terminal is provided with a plurality of channels, The light-emitting element driving device includes a current driver (DRV) provided for each channel of the connection terminal, In the light-emitting system, a plurality of switches (SW) are provided, which are connected between an application terminal of the power supply voltage and a high potential terminal of the light-emitting unit of each channel and are configured to be on / off controlled by the light-emitting element drive device; The monitor section may be configured to monitor the voltage of the connection terminal when the current driver is in an on state and the switch is in an on state (eleventh configuration, FIGS. 12 and 13).

[0119] In addition, in any one of the first to eleventh configurations, the control signal generation unit includes a DA converter (51) configured to update digital data when the next cycle of the synchronization signal starts, The control signal may be updated based on the analog signal (VA) output from the DA converter (twelfth configuration, FIG. 4).

[0120] In the twelfth configuration, the power supply circuit has feedback resistors (R1, R2, R3) connected between an application terminal of the power supply voltage and a ground terminal, The control signal generating unit may be configured to have a constant current circuit (52) configured to generate, as the control signal, a current signal (Ifb) extracted from a node (N1) at which the feedback resistors are connected, based on the analog signal (13th configuration).

[0121] Furthermore, one aspect of the present disclosure is a light-emitting system (14th configuration) comprising a plurality of light-emitting element driving devices having any one of the configurations 1 to 13 above, the light-emitting unit, and the power supply circuit.

[0122] Furthermore, one aspect of the present disclosure is a light-emitting element driving device including a plurality of light-emitting element driving devices having any one of the first to thirteenth configurations; a light source unit (911) having the light emitting units arranged in a matrix; The backlight (91) includes at least one optical member (912-914) to which light emitted from the light source section is incident (15th configuration).

[0123] Furthermore, one aspect of the present disclosure is a backlight having the fifteenth configuration described above, and a display panel (92) onto which light emitted from the backlight is incident (16th configuration). [Industrial Applicability]

[0124] The present disclosure can be used, for example, in vehicle displays. [Explanation of symbols]

[0125] 1,1_M,1_S Light emitting element driving device 2. MCU 3 Power circuit 3A DC / DC converter 4 Latch processing section 5 FB current generation section 6 Delay Circuit 7. OR Gate 8 Wiring 10 Driver Block 11 Control Blocks 52 Constant current circuit 52A Error Amplifier 52B output transistor 52C resistance 71~73 OR gate 91 Backlight 92 LCD panel 700 OR gates 911 Light source section 912 Phosphor Sheet 913 Diffuser 914 Optical sheets CH connection terminal CP Comparator DRV Current Driver LL light-emitting part M1 NMOS transistor MT monitor section OUT Output section Rp pull-up resistor R1~R3 ​​Feedback resistors RISET current setting resistor SW switch SYS,SYS Light Emitting System X LCD display device Y In-vehicle display

Claims

1. A light emitting element driving device used in a light emitting system in which at least one channel of a light emitting unit including at least one light emitting element is provided, a connection terminal configured to be connectable to a low potential end of the light-emitting unit of at least one channel; a monitor unit that monitors the voltage of the connection terminal to which the drive current is turned on and stores the monitoring result; an output unit configured to output a terminal voltage detection signal indicating whether the voltage of the connection terminal of at least one channel is lower than a reference voltage based on the stored monitoring result; an output terminal configured to output the terminal voltage detection signal to an external device; an input terminal configured to be connectable to the output terminal of another light-emitting element driving device; a control signal generating unit configured to generate a control signal used for feedback control of a power supply circuit configured to generate a power supply voltage to be applied to a high potential end of the light emitting unit, based on the signal input to the input terminal and the held monitoring result; Equipped with The ON state of the drive current is controlled in one cycle of a synchronization signal, The control signal generating unit updates the control signal when the next cycle of the synchronization signal starts.

2. the output terminal and the input terminal are the same terminal, 2. The light-emitting element driving device according to claim 1, wherein the output section has a transistor having a first end connected to a pull-up resistor and the output terminal and a second end connected to a ground end.

3. 3. The light-emitting element driving device according to claim 2, wherein the transistor is an N-channel MOSFET, and the output section has an open-drain configuration.

4. the output terminal and the input terminal are separate terminals, 2. The light-emitting element driving device according to claim 1, wherein the output section has a first logic circuit configured to receive the held monitoring result and the signal at the input terminal and to output the terminal voltage detection signal.

5. The first logic circuit a first OR gate configured to receive the held monitoring result; 5. The light emitting element driving device according to claim 4, further comprising: a second OR gate configured to receive the output of said first OR gate and the signal at said input terminal, and to output said terminal voltage detection signal.

6. The monitor unit a comparator configured to compare the voltage of the connection terminal with a reference voltage; 2. The light emitting element driving device according to claim 1, further comprising: a latch processing section configured to latch the output of the comparator using a latch signal as a trigger.

7. 7. The light emitting element driving device according to claim 6, wherein the comparator is provided for each of the connection terminals for a plurality of channels.

8. 8. The light-emitting element driving device according to claim 7, wherein the latch processing section is provided for each channel of the connection terminal.

9. the latch processing unit is provided for each of the plurality of channels, 8. The light emitting element driving device according to claim 7, wherein the monitor section has a second logic circuit configured to receive the outputs of the plurality of comparators and to output an output signal to the latch processing section.

10. the monitor unit has a delay circuit configured to delay the synchronization signal; 7. The light emitting element driving device according to claim 6, wherein the latch processing unit releases the latch based on the delayed synchronization signal.

11. The connection terminal is provided with a plurality of channels, the light-emitting element driving device includes a current driver provided for each channel of the connection terminal; In the light-emitting system, a plurality of switches are provided, each of which is connected between an application terminal of the power supply voltage and a high potential terminal of the light-emitting unit of each channel, and is configured to be controlled to be turned on and off by the light-emitting element drive device; 2. The light-emitting element driving device according to claim 1, wherein said monitor section monitors the voltage of said connection terminal when said current driver is in an on state and said switch is in an on state.

12. the control signal generation unit has a DA converter configured to update digital data when a next cycle of the synchronization signal starts; 2. The light emitting element driving device according to claim 1, wherein the control signal is updated based on an analog signal output from the DA converter.

13. the power supply circuit has a feedback resistor connected between an application terminal of the power supply voltage and a ground terminal; 13. The light-emitting element driving device according to claim 12, wherein the control signal generating section has a constant current circuit configured to generate, as the control signal, a current signal extracted from a node at which the feedback resistors are connected, based on the analog signal.

14. A light emitting system comprising: a plurality of light emitting element driving devices according to claim 1; the light emitting unit; and the power supply circuit.

15. a plurality of light-emitting element driving devices according to any one of claims 1 to 13; a light source unit having the light emitting units arranged in a matrix; and at least one optical member onto which light emitted from the light source unit is incident.

16. A backlight according to claim 15; a display panel onto which light emitted from the backlight is incident.

Images