Semiconductor device and semiconductor module

Abstract

In a semiconductor module, the sealing resin for protecting the semiconductor device may peel off from the front surface electrodes of the semiconductor device under high temperature conditions. [Solution] In a semiconductor module, a semiconductor device (100) comprises a protective film (150) provided above the front surface of a semiconductor substrate (10) and a front surface electrode (emitter electrode (52)) provided above the front surface of the semiconductor substrate, and the front surface electrode has a plurality of bonding areas (50-1) and a plurality of test areas (50-2) for testing exposed by a plurality of openings (151, 152, 153) provided in the protective film, and when viewed from above the semiconductor substrate, the area of ​​each test area is smaller than the area of ​​each bonding area.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a semiconductor module. [Background technology]

[0002] Patent Document 1 describes that a bidirectional switching device 100 includes first transistor regions 101a, 101b, and 101c and second transistor regions 102a, 102b, and 102c, and includes first source electrode pads 161a and 161b and second source electrode pads 162a and 162b corresponding to the respective transistor regions, which are provided outside source electrodes 20a to 20d. [Prior art document] [Patent documents] [Patent Document 1] JP 2019-169492 A Summary of the Invention [Problem to be solved by the invention]

[0003] In a semiconductor module, the sealing resin for protecting the semiconductor device may peel off from the front surface electrodes of the semiconductor device under high temperature conditions. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device comprising: a protective film provided above a front surface of a semiconductor substrate; and a front surface electrode provided above the front surface of the semiconductor substrate, the front surface electrode having a plurality of bonding regions and a plurality of test regions for testing exposed by a plurality of openings provided in the protective film, and the area of ​​each test region is smaller than the area of ​​each bonding region when viewed from above the semiconductor substrate.

[0005] In the above semiconductor device, the plurality of test regions may be arranged in a central portion of the semiconductor substrate along a predetermined first direction when viewed from above the semiconductor substrate.

[0006] In any of the semiconductor devices described above, the bonding regions may include a first group of bonding regions and a second group of bonding regions arranged in the first direction, and the test regions may be arranged between the first group of bonding regions and the second group of bonding regions.

[0007] In any of the above semiconductor devices, the first direction may be a longitudinal direction of the semiconductor substrate.

[0008] In any of the semiconductor devices described above, the protective film may have a non-opening portion between the first bonding region group and the second bonding region group, and at least a part of the non-opening portion may be provided above the front surface electrodes.

[0009] Any of the above semiconductor devices may include a plurality of gate trench portions provided on the front surface of the semiconductor substrate, and a gate runner portion electrically connected to the plurality of gate trench portions and extending between the plurality of bonding regions in a second direction different from the first direction.

[0010] Any of the above semiconductor devices may include a temperature sensing section disposed in the center of the semiconductor substrate.

[0011] In any of the above semiconductor devices, the temperature sensing unit may be provided between the plurality of test regions when viewed from above the semiconductor substrate.

[0012] In any of the above semiconductor devices, the plurality of test areas may include a first group of test areas and a second group of test areas arranged in the first direction, and the temperature sensing unit may be provided between the first group of test areas and the second group of test areas in a top view of the semiconductor substrate.

[0013] In any of the semiconductor devices described above, the plurality of bonding regions may include a first bonding region and a second bonding region connected to the first bonding region by a bonding wire, and the protective film may have a non-opening portion provided between the first bonding region and the second bonding region when viewed from above on the semiconductor substrate.

[0014] In any of the above semiconductor devices, an area of ​​the first bonding region may be different from an area of ​​the second bonding region when viewed from above the semiconductor substrate.

[0015] Any of the above semiconductor devices may include a back electrode containing nickel provided on a back surface of the semiconductor substrate.

[0016] In any of the above semiconductor devices, the back electrode may have a thickness of 1.0 μm or more and 2.0 μm or less.

[0017] In a second aspect of the present invention, there is provided a semiconductor module including the semiconductor device according to the first aspect.

[0018] In the above semiconductor module, an area of ​​a bonding region for relaying the bonding wire may be smaller than an area of ​​a bonding region where the bonding wire terminates, in a top view of the semiconductor substrate.

[0019] Any of the above semiconductor modules may include a sealing resin provided above the semiconductor device.

[0020] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0021] [Figure 1] 1 shows an example of the layout of components on the front surface of a semiconductor device 100 according to an embodiment. [Figure 2]An example of the arrangement of emitter electrodes 52 provided on the front surface of the semiconductor device 100 is shown. [Figure 3] An example of the arrangement of the protective film 150 provided on the front surface of the semiconductor device 100 is shown. [Figure 4] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 5] An example of a cross section taken along line aa' in FIG. 4 is shown. [Figure 6] FIG. 2 is a top view illustrating an example of a semiconductor module 300 according to an embodiment. [Figure 7] An example of the bb' cross section of FIG. 6 is shown. [Figure 8] 1 shows an example of a top view of a semiconductor module 300. [Figure 9] 10 shows another example of a top view of the semiconductor module 300. [Figure 10] 1 shows an example of the arrangement of a protective film 1150 provided in a semiconductor device 1100 according to a comparative example. [Figure 11] 13 shows an example of a top view of a semiconductor module 1300 according to a comparative example. [Figure 12] FIG. 13 is a cross-sectional analysis diagram of a semiconductor module 1300 in which cracks have occurred in the bonding wires and the sealing resin. [Figure 13] This is a focused ion beam scanning electron microscope (FIB-SEM) image of an enlarged area (1) of the c-c' cross section of Figure 12. DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0023] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface, and the other surface is referred to as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0024] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0025] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0026] The region from the center of the semiconductor substrate in the depth direction to the front surface of the semiconductor substrate may be referred to as the front surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the back surface of the semiconductor substrate may be referred to as the back surface side.

[0027] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0028] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0029] FIG. 1 shows an example of the arrangement of components on the front surface of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a semiconductor substrate 10, a gate pad 170 and its test pad 171, a current sense pad 172 and its test pad 173, a temperature sensor 178, an anode pad 174 and a cathode pad 176 electrically connected to the temperature sensor 178, and their respective test pads 175 and 177. The area where the gate pad 170 and its test pad 171, the current sense pad 172 and its test pad 173, the anode pad 174 and its test pad 175, and the cathode pad 176 and its test pad 177 are provided may be collectively referred to as the pad area. The pad area in this example may be provided between an active section 120 (described later) and an edge 102-3.

[0030] The semiconductor substrate 10 has an edge 102. In this example, the edge 102 may include an edge 102-1, an edge 102-2, an edge 102-3, and an edge 102-4. In this specification, the direction of one edge 102-3 of the semiconductor substrate 10 in the top view of FIG. 1 is defined as the X-axis, and the direction perpendicular to the X-axis is defined as the Y-axis. In this example, the X-axis is taken in the direction of the edge 102-3 and the edge 102-4, and the Y-axis is taken in the direction of the edge 102-1 and the edge 102-2. In this example, the Y-axis may be the longitudinal direction of the semiconductor substrate 10. Furthermore, a direction perpendicular to the X-axis direction and the Y-axis direction, which forms a right-handed system, is referred to as the Z-axis direction. In this example, the temperature sensor 178 is provided in the +Z-axis direction of the semiconductor substrate 10.

[0031] The semiconductor substrate 10 is made of a semiconductor material such as silicon or a compound semiconductor. The side of the semiconductor substrate 10 on which the temperature sensing unit 178 is provided is referred to as the front surface, and the opposite surface is referred to as the back surface. In this specification, the direction connecting the front surface and the back surface of the semiconductor substrate 10 is referred to as the depth direction. In this example, the semiconductor substrate 10 has a substantially rectangular shape on the front surface, but may have a different shape.

[0032] The semiconductor substrate 10 has an active portion 120. The active portion 120 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is turned on. A gate conductive portion 44 (described later) of the active portion 120 is electrically connected to a gate pad 170 by a gate wiring portion (described later).

[0033] The active section 120 may be divided into active sections 120-1, 120-2, and 120-3 in top view. In this example, the active sections 120-1, 120-2, and 120-3 are arranged in this order from the positive side to the negative side in the Y-axis direction.

[0034] The active portion 120-1 in this example is provided extending in the X-axis direction between the end sides 102-1 and 102-2. The active portions 120-2 and 120-3 in this example are separated in the X-axis direction by a separation portion 90 that extends from near a center Ac of the front surface of the semiconductor substrate 10 toward the negative side in the Y-axis direction. In other words, the separation portion 90 may be a region in which no active portion 120 is provided. Here, the center Ac is the geometric center of gravity of the active portion 120 in a top view. The active portion 120-2 may partially extend in the X-axis direction and be partially separated in the X-axis direction by the separation portion 90. The active portion 120-2 may be provided on either side of a temperature sensing unit 178, which will be described later.

[0035] The active section 120 of this example is provided with a transistor section 70 including a transistor element such as an IGBT (insulated gate bipolar transistor) and a diode section 80 including a diode element such as an FWD (freewheel diode). The transistor section 70 and the diode section 80 form an RC-IGBT (reverse conducting IGBT).

[0036] 1, in the active section 120, the region where the transistor section 70 is arranged is marked with the symbol "I", and the region where the diode section 80 is arranged is marked with the symbol "F". In this example, the transistor sections 70 and diode sections 80 extend in the X-axis direction and are arranged alternately in the Y-axis direction in each region of the active section 120. Note that the active section 120 in this example may be an IGBT or a MOSFET (insulated gate field effect transistor).

[0037] Semiconductor device 100 has an edge termination structure 130 on the front surface between the outer periphery of active section 120 and edge 102. Edge termination structure 130 has, for example, a guard ring provided in an annular shape surrounding active section 120, a field plate, or a structure combining these.

[0038] The temperature sensing unit 178 may be disposed in the isolation unit 90. The isolation unit 90 does not include the active unit 120. In the semiconductor device 100, the vicinity of the center Ac of the front surface of the semiconductor substrate 10 is likely to heat up due to heat generated from the switching elements formed in the active unit 120. By providing the temperature sensing unit 178 in the isolation unit 90, including the vicinity of the center Ac, the temperature of the transistor unit 70 can be monitored. This makes it possible to prevent the transistor unit 70 from overheating beyond the junction temperature, which is within the normal operating temperature range.

[0039] The temperature sensing section 178 may be provided by a temperature sensing diode. The temperature sensing section 178 may be provided by a PN junction diode made of polycrystalline silicon that is provided above the semiconductor substrate 10 via an insulating film.

[0040] The anode pad 174 is connected to the temperature sensor 178 via an anode wiring 182. The cathode pad 176 is connected to the temperature sensor 178 via a cathode wiring 180. The cathode pad 176 and the anode pad 174 are electrodes containing a metal such as aluminum. The anode and cathode of the temperature sensor diode are connected to the anode pad 174 and the cathode pad 176 via metal anode wiring and cathode wiring, respectively.

[0041] The current sense pad 172 is electrically connected to the current sense unit. The current sense pad 172 is an example of a front surface electrode. The current sense unit has a structure similar to that of the transistor unit 70 of the active unit 120, and simulates the operation of the transistor unit 70. A current proportional to the current flowing through the transistor unit 70 flows through the current sense unit. This allows the current flowing through the transistor unit 70 to be monitored.

[0042] FIG. 2 shows an example of the arrangement of emitter electrodes 52 provided on the front surface of semiconductor device 100. FIG. 2 also shows a gate runner portion 48, an anode wiring 182, and a cathode wiring 180 as examples of wiring connected to the pad region. Emitter electrode 52 is provided using a metal conductor such as aluminum. In this example, emitter electrode 52 is set to an emitter potential, which is a predetermined reference potential. Alternatively, the emitter potential may be set to a ground potential.

[0043] The emitter electrode 52 is formed of a conductive material containing metal. For example, the emitter electrode 52 is formed of aluminum or an alloy containing aluminum as a main component (such as an alloy of aluminum-silicon or aluminum-silicon-copper). The emitter electrode 52, like the current sense pad 172, is an example of a front surface electrode. Each electrode may have a barrier metal formed of titanium or a titanium compound below the region formed of aluminum or the like.

[0044] In FIG. 2, the emitter electrode 52 is disposed in the hatched region. The emitter electrode 52 may be divided into emitter electrodes 52-1, 52-2, and 52-3 in top view. In this example, the emitter electrodes 52-2 and 52-3 are provided corresponding to the active portions 120-1, 120-2, and 120-3, respectively. The emitter electrode 52 is not provided above the separation portion 90 that separates at least a portion of the active portion 120-2 in the Y-axis direction. Similarly, the emitter electrode 52 is not provided above the pad region.

[0045] In this example, the gate runner portion 48 may be disposed to surround the active portion 120 when viewed from above on the semiconductor substrate 10. The gate runner portion 48 may have branches extending in the X-axis direction between the emitter electrodes 52. The X-axis direction is an example of the second direction. The gate runner portion 48 may be a wiring formed of a conductive material such as impurity-doped polysilicon or metal. Furthermore, the gate runner portion 48 may be a wiring formed of impurity-doped polysilicon and electrically connected to a conductive material such as metal through a contact hole formed in an interlayer insulating film provided on the upper surface of the wiring. The gate runner portion 48 supplies a gate voltage applied to the gate pad 170 to the transistor portion 70. The gate runner portion 48 may be disposed above a well region 17, which will be described later.

[0046] In this example, the emitter electrode 52 is provided in a range that does not overlap the gate runner portion 48, but it may overlap the gate runner portion 48. In this case, an insulating film is provided between the emitter electrode 52 and the gate runner portion 48. An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10, but this is omitted in FIG. 2. The gate runner portion 48 is connected to the gate conductive portion in the gate trench portion of the transistor portion 70 on the front surface of the semiconductor substrate 10.

[0047] The anode wiring 182 and the cathode wiring 180 in this example may be provided by extending the separation section 90 from the temperature sensing section 178. The anode wiring 182 and the cathode wiring 180 are connected to the anode and cathode of the temperature sensing section 178, respectively. The anode wiring 182 and the cathode wiring 180 may be wiring containing a metal such as aluminum. The anode wiring 182 and the cathode wiring 180 are examples of temperature sensing wiring.

[0048] The cathode pad 176 of this example is connected to a temperature sensor 178 via a cathode wiring 180. The anode pad 174 of this example is connected to the temperature sensor 178 via an anode wiring 182.

[0049] FIG. 3 shows an example of the arrangement of a protective film 150 provided above the front surface of the semiconductor device 100. In this example, the protective film 150 is formed of polyimide. In FIG. 3, the outline of the region where the protective film 150 is arranged is indicated by a solid line and hatched with diagonal lines. Furthermore, FIG. 3 indicates the outline of the region where the emitter electrode 52 is arranged by a dashed line, and indicates the outline of the region in the separation portion 90 where the temperature sensor 178 and the temperature sensor wiring are arranged by a solid line. The protective film 150 may be in contact with the upper surface of the emitter electrode 52.

[0050] The protective film 150 of this example may have an opening 151 that exposes a portion of the upper surface of the pad in the pad region, openings 152 and 153 that expose a portion of the upper surface of the emitter electrode 52, and a non-opening 154. The protective film 150 of this example has a plurality of openings 151. The plurality of openings 151 allow wires and the like to be connected to the upper surfaces of the gate pad 170, the current sense pad 172, the anode pad 174, and the cathode pad 176.

[0051] In this example, the protective film 150 is provided with a plurality of openings 152 and a plurality of openings 153. The emitter electrode 52 has a plurality of bonding regions 50 and a plurality of test regions 51 exposed by the plurality of openings 152 and the plurality of openings 153, respectively. The bonding regions 50 may be used as regions for joining bonding wires in a semiconductor module. The test regions 51 may be used as regions for connecting probes or the like for wafer testing.

[0052] The multiple openings 152 may be arranged in a matrix when viewed from above on the semiconductor substrate 10. In this example, two rows of openings 152 arranged in the Y-axis direction face each other in the X-axis direction with the separation portion 90 at the center, and the multiple bonding regions 50 have a group of first bonding regions 50-1 and a group of second bonding regions 50-2 arranged in the Y-axis direction, and these groups face each other in the X-axis direction with the separation portion 90 at the center.

[0053] The Y-axis direction is an example of a predetermined first direction, and may be the longitudinal direction of the semiconductor substrate 10. In Fig. 3, the bonding region 50 provided on the negative side of the separation portion 90 in the X-axis direction is shown as a first bonding region 50-1, and the bonding region 50 provided on the positive side of the separation portion 90 in the X-axis direction is shown as a second bonding region 50-2.

[0054] The plurality of openings 153 may be arranged in the center of the semiconductor substrate 10 along the Y-axis direction when viewed from above. The number of the plurality of openings 153 may be smaller than the number of the plurality of openings 152. The plurality of test regions 51 may be provided in the center of the semiconductor substrate 10 along the Y-axis direction when viewed from above. Here, the center of the semiconductor substrate 10 refers to the separation portion 90 and the range obtained by extending the separation portion 90 in the Y-axis direction. In other words, the center of the semiconductor substrate 10 refers to the center of the semiconductor substrate 10 in the X-axis direction and its vicinity when viewed from above. In this example, the plurality of test regions 51 are arranged between the group of first bonding regions 50-1 and the group of second bonding regions 50-2 arranged in the Y-axis direction when viewed from above.

[0055] In this example, two rows of openings 153 are arranged in the Y-axis direction, and the multiple test areas 51 include a group of first test areas 51-1 and a group of second test areas 51-2 arranged in the Y-axis direction. In one example, each of the group of first test areas 51-1 and the group of second test areas 51-2 includes five first test areas 51. FIG. 3 shows the test area 51 provided on the negative side of the temperature sensor 178 in the X-axis direction as the first test area 51-1, and the test area 51 provided on the positive side of the temperature sensor 178 in the X-axis direction as the second test area 51-2. The test areas 51 in this example are not provided near the gate runner section 48.

[0056] The temperature sensing unit 178 of this example may be provided between the group of first test areas 51-1 and the group of second test areas 51-2 when viewed from above the semiconductor substrate 10. The temperature sensing unit 178 of this example may be provided between multiple test areas 51 when viewed from above the semiconductor substrate 10. In other words, the temperature sensing unit 178 may be disposed between any two of the multiple test areas 51 when viewed from above the semiconductor substrate 10.

[0057] In a top view of the semiconductor substrate 10, the area of ​​each test region 51 is smaller than the area of ​​each bonding region 50. The size of each side of the test region 51 may be smaller than the size of each side of the bonding region 50. In the longitudinal direction of the semiconductor substrate 10, the width of the test region 51 may be smaller than the width of the bonding region 50. In the lateral direction of the semiconductor substrate 10, the width of the test region 51 may be smaller than the width of the bonding region 50. In a top view of the semiconductor substrate 10, the area of ​​each test region 51 may be 5% to 20% of the area of ​​the bonding region 50.

[0058] In conventional wafer testing, a probe or the like is connected to the bonding region of the emitter electrode to measure wiring resistance, etc. However, when reliability testing of the semiconductor module is performed under high temperature conditions, for example, the sealing resin of the semiconductor module may peel off from the top surface of the emitter electrode. Since the probe impression formed during the wafer testing remains on the top surface of the emitter electrode, the sealing resin of the semiconductor module may peel off even more easily.

[0059] In the semiconductor device 100 of this example, the emitter electrode 52 has a test area 51 provided separately from the bonding area 50, and the area of ​​the test area 51 is smaller than the area of ​​the bonding area 50, so that the sealing resin of the semiconductor module can be prevented from peeling off from the upper surface of the emitter electrode in the bonding area 50.

[0060] The non-opening 154 is a region other than the openings in the protective film 150. The non-opening 154 in this example may be provided between the group of first bonding regions 50-1 and the group of second bonding regions 50-2. The non-opening 154 in this example may be provided above the gate runner portion 48, the temperature sensing portion 178, the anode wiring 182, and the cathode wiring 180. At least a portion of the non-opening 154 in this example may be provided above the emitter electrode 52.

[0061] The sealing resin of a semiconductor module may peel off from the upper surface of the emitter electrode, for example, when a reliability test of the semiconductor module is performed under high-temperature conditions. It is known that the sealing resin of a semiconductor module is prone to peeling in the peripheral region. On the other hand, the polyimide protective film 150 has higher adhesion to the sealing resin of the semiconductor module than the emitter electrode 52 made of aluminum or an alloy mainly containing aluminum.

[0062] The pad region in this example is provided between the active portion 120-3 and the edge 102-3. The region between the active portion 120-3 and the edge 102-3 is covered by the non-opening portion 154, except for the pad region exposed by the multiple openings 151. In the semiconductor device 100 of this example, the test region 51 is provided in the center of the semiconductor substrate 10 rather than in the pad region, thereby preventing an increase in the opening ratio in the peripheral region. This prevents a decrease in the area ratio where the sealing resin and polyimide are in contact in the peripheral region of the semiconductor module 300, and prevents peeling of the sealing resin of the semiconductor module.

[0063] 4 shows an example of a top view of the semiconductor device 100. Fig. 4 shows the vicinity of the X-axis direction positive end of the active portion 120-1. The semiconductor device 100 of this example includes a semiconductor substrate 10 having a transistor portion 70 including a transistor element such as an IGBT, and a diode portion 80 including a diode element such as a free wheel diode (FWD).

[0064] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 17, an emitter region 12, a base region 14, and a contact region 15, which are provided inside the front surface side of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0065] The emitter electrode 52 is provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a front surface electrode. FIG. 4 shows the area where the emitter electrode 52 is provided. An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10, but is not shown in FIG. 4. In this example, contact holes 54 and 56 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In FIG. 4, each contact hole is hatched with diagonal lines.

[0066] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 17, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 via a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 via a contact hole 56.

[0067] A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided above the front surface of the semiconductor substrate 10. An insulating film is provided between the connection portion 25 and the front surface of the semiconductor substrate 10.

[0068] The emitter electrode 52 may have a barrier metal made of titanium or a titanium compound below a region made of aluminum or the like. The emitter electrode 52 may have a plug made of tungsten or the like in the contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate 10, and may be formed by embedding tungsten so as to be in contact with the barrier metal.

[0069] The plug in this example is provided in a contact hole 54 that contacts the contact region 15 or the base region 14. A P++-type plug region having a higher doping concentration than the contact region 15 may be provided below the contact hole 54 in which the plug is provided. This improves the contact resistance between the barrier metal and the contact region 15. The improvement in contact resistance by the plug region improves the latch-up tolerance in the operation of the transistor section 70, and can suppress increases in conduction loss and switching loss in the operation of the diode section 80.

[0070] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction.

[0071] In this example, the arrangement direction of the trench portions is the Y-axis direction, and the extension direction perpendicular to the arrangement direction is the X-axis direction. The gate trench portion 40 in this example may have two extension portions 39 (parts of the trench that are linear along the extension direction) that extend along the extension direction, and a connection portion 41 that connects the two extension portions 39.

[0072] At least a portion of the connection portion 41 may be curved in top view. The connection portion 41 connects the ends of the two extension portions 39 in the Y-axis direction to the gate runner portion 48. By making the connection portion 41 curved, electric field concentration at the ends can be alleviated more effectively than if the connection portion 41 were completed at the extension portion 39.

[0073] In the transistor section 70, the dummy trench section 30 is provided between the respective extension portions 39 of the gate trench section 40. In the example of Fig. 4, one dummy trench section 30 is provided between the respective extension portions 39, but two or more dummy trench sections 30 may be provided.

[0074] Furthermore, the dummy trench portion 30 does not have to be provided between the extension portions 39, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-state voltage.

[0075] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have an extension portion 29 and a connection portion 31, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 4 has only dummy trench portions 30 having connection portions 31 arranged therein, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have connection portions 31.

[0076] An insulating film is provided between the gate runner portion 48 and the front surface of the semiconductor substrate 10. The gate runner portion 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The gate runner portion 48 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0077] Well region 17 is provided closer to the front surface of semiconductor substrate 10 than drift region 18, which will be described later. In this example, well region 17 is P+ type. In this example, well region 17 is provided in edge termination structure 130 and isolation portion 90. Well region 17 is also provided in a predetermined range extending from the outer periphery to the interior of active portion 120-1, active portion 120-2, and active portion 120-3. Well region 17 is electrically connected to emitter electrode 52. Well region 17 is provided from the front surface of semiconductor substrate 10 to a position deeper than the lower end of base region 14.

[0078] The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the X-axis direction are provided in the well region 17 when viewed from above. That is, at the ends of each trench portion in the X-axis direction, the bottom of each trench portion in the depth direction (-Z-axis direction) is covered by the well region 17. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0079] A mesa portion is provided between adjacent trench portions in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the trench portion.

[0080] The mesa portion in this example is sandwiched between adjacent trench portions in the Y-axis direction, and is provided on the front surface of the semiconductor substrate 10, extending in the X-axis direction along the trenches.

[0081] Each mesa portion has a base region 14. In each mesa portion, at least one of an emitter region 12 and a contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the base region 14 is P-type, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The base region 14 is provided in contact with the well region 17. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0082] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0083] The contact regions 15 and emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portions (X-axis direction).

[0084] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (X-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0085] The mesa portion of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80. The base region 14 of the diode portion 80 operates as an anode.

[0086] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in regions sandwiched between the base regions 14 in the extension direction (X-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center in the arrangement direction (Y-axis direction) of the mesa portions.

[0087] In the diode section 80, an N+ type cathode region 82 is provided on the rear surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in an area of ​​the rear surface of the semiconductor substrate where the cathode region 82 is not provided. In Figure 4, the boundary between the cathode region 82 and the collector region 22 is indicated by a dashed line.

[0088] Fig. 5 shows an example of the aa' cross section of Fig. 4. The aa' cross section is an XZ plane that passes through the transistor section 70 and part of the diode section 80, and passes through the emitter region 12 in the transistor section 70.

[0089] In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10, and the emitter electrode 52 is provided above the interlayer insulating film 38. A protective film 150 is provided above the emitter electrode 52, but is omitted in FIG. 5 .

[0090] The drift region 18 is a region provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0091] The buffer region 20 is a region provided below the drift region 18. In this example, the buffer region 20 has the same conductivity type as the drift region 18, for example, N+ type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0092] The collector region 22 is a region of a different conductivity type from the drift region 18, provided below the buffer region 20 in the transistor section 70. The cathode region 82 is a region of the same conductivity type as the drift region 18, provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0093] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The collector electrode 24 is an example of a back surface electrode. In this example, the collector electrode 24 contains nickel. The thickness of the collector electrode 24 in this example may be 1.0 μm or more and 2.0 μm or less.

[0094] The base region 14 is a region of a different conductivity type from the drift region 18, which is provided above the drift region 18 in the mesa portion. In this example, the base region 14 is, for example, a P-type. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may also be provided in contact with the dummy trench portion 30.

[0095] The emitter region 12 is provided between the base region 14 and the front surface 21 of the semiconductor substrate 10. In this example, the emitter region 12 is provided in the mesa portion of the transistor portion 70, but is not provided in the mesa portion of the diode portion 80. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0096] 5, the contact regions 15 are provided alternately with the emitter regions 12 in the mesa portion of the transistor section 70. The contact regions 15 may be provided to a position deeper in the semiconductor substrate 10 than the emitter regions 12.

[0097] The accumulation region 16 is a region that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. In this example, the accumulation region 16 has the same conductivity type as the drift region 18, and is, for example, N+ type. In this example, the accumulation region 16 is provided only in the transistor section 70, but may also be provided in the diode section 80. Furthermore, the accumulation region 16 may be provided in multiple stages.

[0098] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0099] One or more gate trenches 40 and one or more dummy trenches 30 are provided in the front surface 21 of the semiconductor substrate 10. Each trench extends from the front surface 21 of the semiconductor substrate 10 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18.

[0100] Note that the trench portion penetrating the doping region is not limited to a case where the trench portion is formed after the doping region is formed, but also includes a case where the trench portion is formed and then the doping region is formed between the trench portions.

[0101] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21 of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0102] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa side, across the gate insulating film 42, in the depth direction (-Z-axis direction) of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0103] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side of the semiconductor substrate 10. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0104] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. The contact holes 54 and 56 may be provided to penetrate the interlayer insulating film 38.

[0105] 6 is a top view showing an example of a semiconductor module 300 according to the embodiment. The semiconductor module 300 of this example includes a plurality of semiconductor devices 100, a resin case 310, an insulating substrate 200, a wiring pattern 260, bonding wires 280, and a lead frame 290.

[0106] The resin case 310 of this example may be provided so as to surround a space that houses the semiconductor device 100. The semiconductor device 100 may be the semiconductor device 100 shown in FIGS. 1 to 5. The resin case 310 of this example may house two semiconductor devices 100 of different sizes. A sealing resin 240 is provided above the semiconductor device 100, but is omitted in FIG. 6.

[0107] Resin case 310 of this example may be molded from a resin such as a thermosetting resin that can be formed by injection molding, or an ultraviolet-curing resin that can be formed by UV molding, etc. The resin may include one or more polymer materials selected from, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, acrylic resin, etc.

[0108] The insulating substrate 200 of this example may be provided in a resin case 310. The insulating substrate 200 of this example may be provided by laminating a resin insulating layer 210 on a base substrate 215. The base substrate 215 is, for example, a copper plate. A cooler may be provided on the lower surface of the base substrate 215.

[0109] The semiconductor device 100 is electrically connected to an electric circuit provided inside the semiconductor module 300. The semiconductor device 100 of this example is electrically connected to at least one of the wiring pattern 260 and the lead frame 290. In the example of FIG. 6, the front surface electrode of the semiconductor device 100 and the lead frame 290 are electrically connected via a bonding wire 280.

[0110] The wiring pattern 260 and the lead frame 290 are part of an electric circuit. The wiring pattern 260 and the lead frame 290 may be electrically connected to each other. The electric circuit provided in the semiconductor module 300 may include other electric elements.

[0111] The wiring pattern 260 in this example may be provided on the upper surface of the insulating substrate 200. The wiring pattern 260 is, for example, a copper plate or an aluminum plate. The wiring pattern 260 in this example may be formed by bonding a plated copper plate or aluminum plate to the insulating substrate 200 directly or via a brazing material layer.

[0112] The semiconductor device 100 is provided on the upper surface of the wiring pattern 260 of this example. A joint (not shown) such as solder may be provided between the semiconductor device 100 of this example and the wiring pattern 260. The semiconductor device 100 of this example may be protected by a sealing resin 240 filled in the resin case 310. The sealing resin 240 is made of an insulating material such as silicone gel.

[0113] The lead frame 290 of this example electrically connects the inside and outside of the resin case 310. The lead frame 290 of this example may be formed of a conductive material such as copper. The lead frame 290 of this example may be provided so as to protrude from the side wall of the resin case 310 to the outside.

[0114] The semiconductor device 100 of this example is connected to a wiring pattern 260 by a back surface electrode (collector electrode 24), and is connected to a plurality of bonding wires 280 by a front surface electrode (emitter electrode 52).

[0115] 7 shows an example of the b-b' cross section of FIG. 6. The bonding wire 280 of this example extends in the X-axis direction and electrically connects the semiconductor device 100 and the lead frame 290. The bonding wire 280 of this example is connected to the bonding region 50 (see FIG. 3, etc.) on the upper surface of the emitter electrode 52 of the semiconductor device 100. The bonding wire 280 may be crimped to the upper surface of the emitter electrode 52, or may be fixed by a fixing member such as solder. The bonding wire 280 connects at least two bonding regions 50.

[0116] Fig. 8 shows an example of a top view of the semiconductor module 300. Fig. 8 shows an example of the arrangement of the protective film 150 provided on the front surface of the semiconductor device 100, similar to Fig. 3 .

[0117] 8, each bonding wire 280 electrically connects a first bonding region 50-1 and a second bonding region 50-2 that face each other in the X-axis direction. In this example, the bonding wire 280 may be crimped to the bonding region 50, or may be fixed with a fixing member such as solder. A fixing portion 282, which is the region where the bonding wire 280 is fixed to the bonding region 50, is indicated by a black oval in FIG. 8. In this example, the fixing portion 282 is spaced 50 μm or more from the end of the bonding region 50.

[0118] 8, the bonding wire 280 is relayed at the fixed portion 282 of the second bonding region 50-2 and terminates at the fixed portion 282 of the first bonding region 50-1. In the X-axis direction, the width W1 of the first bonding region 50-1 may be the same as the width W2 of the second bonding region 50-2. Therefore, in this example, when viewed from above on the semiconductor substrate 10, the area of ​​the first bonding region 50-1 may be the same as the area of ​​the second bonding region 50-2.

[0119] 9 shows another example of a top view of the semiconductor module 300. Here, the description will be omitted for the matters common to FIG. 8, and the differences will be mainly described.

[0120] In this example, the area of ​​the first bonding region 50-1 may be different from the area of ​​the second bonding region 50-2. In the X-axis direction, the width W2 of the second bonding region 50-2 may be smaller than the width W1 of the first bonding region 50-1. Therefore, in this example, in a top view of the semiconductor substrate 10, the area of ​​the second bonding region 50-2 may be smaller than the area of ​​the first bonding region 50-1.

[0121] In a top view of the semiconductor substrate 10, the area of ​​the fixing portion 282 of the first bonding region 50-1 may be larger than the area of ​​the fixing portion 282 of the second bonding region 50-2 in order to terminate the bonding wire 280. Therefore, in a top view of the semiconductor substrate 10, the area of ​​the second bonding region 50-2 is reduced to reduce the opening ratio of the protective film 150. This increases the area ratio where the sealing resin 240 and polyimide are in contact, making it possible to prevent peeling of the sealing resin 240.

[0122] 10 shows an example of the arrangement of a protective film 1150 provided in a semiconductor device 1100 according to a comparative example. The protective film 1150 of the comparative example differs from the protective film 150 described in FIG. 3 in that it has a higher opening ratio. Here, a description of the points in common with FIG. 3 will be omitted, and the description will focus on the differences.

[0123] The protective film 1150 of the comparative example has an opening 151 that exposes a part of the upper surface of the pad in the pad region, an opening 152 that exposes a part of the upper surface of the emitter electrode 52, and a non-opening 154. In other words, the protective film 1150 of the comparative example does not have the opening 153 that exposes the test region 51 of FIG.

[0124] Since the semiconductor device 1100 according to the comparative example does not have a test region 51, a probe or the like for a wafer test is connected to the upper surface of the emitter electrode 52 in the bonding region 50. Since the probe impression formed during the wafer test remains on the upper surface of the emitter electrode 52, there is a risk that the sealing resin of the semiconductor module may peel off more easily.

[0125] Furthermore, in the semiconductor device 1100 according to the comparative example, the non-openings 154 are provided above the gate runner portions 48 that extend in the X-axis direction between the active portions 120, but are not provided to extend above the active portions 120. Therefore, the opening ratio of the protective film 1150 according to the comparative example is higher than the opening ratio of the protective film 150 in Fig. 3, and therefore the area ratio where the sealing resin of the semiconductor module and the polyimide come into contact is low, and peeling of the sealing resin of the semiconductor module is likely to occur.

[0126] Fig. 11 shows an example of a top view of a semiconductor module 1300 according to a comparative example. The semiconductor module 1300 according to the comparative example differs from the semiconductor module 300 shown in Fig. 8 in that it includes the semiconductor device 1100 shown in Fig. 11, but the other configurations are the same.

[0127] Fig. 12 is a cross-sectional analysis diagram of a semiconductor module 1300 in which cracks have occurred in the bonding wire and the sealing resin. Fig. 13 shows a focused ion beam scanning electron microscope (FIB-SEM) image enlarging region (1) of the c-c' cross section of Fig. 12. In Fig. 12, a bonding wire 280 extends from the negative side to the positive side in the X-axis direction and is fixed to the front surface of the semiconductor device 100 by two fixing portions 282.

[0128] A reliability test was conducted on the semiconductor module 1300. In the reliability test, a cycle of raising and lowering the junction temperature by passing a current through the semiconductor module is repeated to measure the product defect rate. As a result of the reliability test, peeling or cracks occurred in the sealing resin 240 in areas (1) to (3) shown in FIG. 12.

[0129] Region (1) is near the fixing portion 282 on the outer periphery (negative side in the X-axis direction) of the semiconductor module 1300. Here, peeling occurred between the sealing resin 240 and the semiconductor device 1100 (upper surface of the emitter electrode 52). The end of the bonding wire 280 in region (1) is connected to the lead frame 290 in the Z-axis direction.

[0130] Region (2) is a region between the fixing portions 282 where the bonding wire 280 is spaced apart from the semiconductor device 1100. Here, the bonding wire 280 is spaced apart from the semiconductor device 1100 (the upper surface of the emitter electrode 52), and thermal or mechanical load is unlikely to be applied thereto, so peeling does not occur between the semiconductor device 1100 (the upper surface of the emitter electrode 52) and the sealing resin 240.

[0131] Region (3) is near the fixing portion 282 on the inner side (positive side in the X-axis direction) of the semiconductor module 1300. Here, peeling occurred between the sealing resin 240 and the semiconductor device 1100 (upper surface of the emitter electrode 52). The bonding wire 280 in region (3) is the terminal end of the bonding wire 280.

[0132] Peeling occurred in regions (1) and (3), causing the bonding wire 280 to shift position, resulting in cracks in the sealing resin 240 (white triangles in the c-c' cross-sectional analysis diagram in Figure 13). In addition, the cracks increased the bonding area of ​​the bonding wire 280, which in turn increased the resistance of the bonding point, resulting in an increase in the amount of heat generated, causing cracks in the bonding wire 280 in region (1) (black triangles in the enlarged view of region (1) in Figure 13).

[0133] In the semiconductor module 300 according to the embodiment, the emitter electrode 52 of the semiconductor device 100 has a test area 51 provided separately from the bonding area 50, and the area of ​​the test area 51 is smaller than the area of ​​the bonding area 50, so that the sealing resin 240 of the semiconductor module 300 can be prevented from peeling off from the upper surface of the emitter electrode in the bonding area 50.

[0134] In the semiconductor module 300 according to the embodiment, the test region 51 of the semiconductor device 100 is not provided in the pad region but in the central portion of the semiconductor substrate 10, thereby preventing an increase in the ratio of openings in the peripheral region. This prevents a decrease in the area ratio where the sealing resin and polyimide are in contact in the peripheral region of the semiconductor module 300, and can prevent peeling of the sealing resin 240 of the semiconductor module 300.

[0135] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0136] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0137] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 29 extension portion, 30 dummy trench portion, 31 connection portion, 32 dummy insulating film, 34 dummy conductive portion , 38...interlayer insulating film, 39...extension portion, 40...gate trench portion, 41...connection portion, 42...gate insulating film, 44...gate conductive portion, 48...gate runner portion, 50...bonding region, 51...test region, 52...emitter electrode, 54...contact hole, 56...contact hole, 70...transistor portion, 80...diode portion, 82...cathode region, 90...isolation portion, 100... Semiconductor device, 102 edge, 120 active portion, 130 edge termination structure, 150 protective film, 151 opening, 152 opening, 153 opening, 154 non-opening, 170 gate pad, 171 test pad, 172 current sense pad, 173 test pad, 174 anode pad, 175 test pad, 176 cathode pad, 177 test pad, 1 78...Temperature sensing section, 180...Cathode wiring, 182...Anode wiring, 200...Insulating substrate, 210...Insulating layer, 215...Base substrate, 240...Sealing resin, 260...Wiring pattern, 280...Bonding wire, 282...Fixing section, 290...Lead frame, 300...Semiconductor module, 310...Resin case, 1100...Semiconductor device, 1150...Protective film, 1300...Semiconductor module

Claims

1. a protective film provided above the front surface of the semiconductor substrate; a front surface electrode provided above the front surface of the semiconductor substrate; Equipped with The front surface electrode is a plurality of bonding areas and a plurality of test areas exposed by a plurality of openings provided in the protective film; When viewed from above, the area of ​​each test region is smaller than the area of ​​each bonding region. Semiconductor device.

2. When viewed from above, the plurality of test regions are arranged in a central portion of the semiconductor substrate along a predetermined first direction. The semiconductor device according to claim 1 .

3. the plurality of bonding regions include a first group of bonding regions and a second group of bonding regions arranged in the first direction; The plurality of test areas are arranged between the first group of bonding areas and the second group of bonding areas. The semiconductor device according to claim 2 .

4. The first direction is the longitudinal direction of the semiconductor substrate. The semiconductor device according to claim 3 .

5. The protective film has a non-opening portion between the first bonding region group and the second bonding region group, and at least a part of the non-opening portion is provided above the front surface electrodes. The semiconductor device according to claim 3 .

6. a plurality of gate trenches provided on a front surface of the semiconductor substrate; a gate runner portion electrically connected to the plurality of gate trench portions and extending between the plurality of bonding regions in a second direction different from the first direction; The semiconductor device according to claim 3 .

7. A temperature sensor is provided at the center of the semiconductor substrate. The semiconductor device according to claim 2 .

8. When viewed from above, the temperature sensing unit is provided between the plurality of test areas. The semiconductor device according to claim 7 .

9. the plurality of test areas include a first test area group and a second test area group arranged in the first direction; When viewed from above, the temperature sensing unit is provided between the first test area group and the second test area group. The semiconductor device according to claim 7 .

10. the plurality of bonding regions include a first bonding region and a second bonding region connected to the first bonding region by a bonding wire; The protective film has a non-opening portion provided between the first bonding region and the second bonding region when viewed from above the semiconductor substrate. The semiconductor device according to claim 1 .

11. When viewed from above, the area of ​​the first bonding region is different from the area of ​​the second bonding region. The semiconductor device according to claim 10.

12. a back electrode containing nickel provided on the back surface of the semiconductor substrate; The semiconductor device according to claim 1 .

13. The thickness of the back electrode is 1.0 μm or more and 2.0 μm or less. The semiconductor device according to claim 12.

14. A semiconductor module comprising the semiconductor device according to claim 1 .

15. a bonding wire connecting at least two of the plurality of bonding regions; The semiconductor module according to claim 14.

16. In a top view of the semiconductor substrate, the area of ​​the bonding region where the bonding wire is relayed is smaller than the area of ​​the bonding region where the bonding wire is terminated. The semiconductor module according to claim 15.

17. A sealing resin is provided above the semiconductor device. The semiconductor module according to claim 14.

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