Method for manufacturing a wiring board

Abstract

To provide a wiring board having via conductors with good connection reliability. [Solution] A wiring board according to an embodiment includes the steps of forming an insulating layer (111) on a conductor layer (121), irradiating the insulating layer (111) with laser light to form a through hole (11a) that penetrates the insulating layer (111) in the thickness direction and exposes the conductor layer (121), cleaning the inner surface of the through hole (11a), forming a metal film layer on the inner surface of the through hole (11a), and filling the through hole (11a) with a plating film layer to form a via conductor. The cleaning is performed by ion gun treatment, and the ion gun treatment includes forming a recess RE on the surface of the conductor layer (121) exposed in the through hole (11a).

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board. A resin insulating layer having a protective film on its surface, which is formed on a first conductor layer, is irradiated with laser light to form openings for via conductors. After the openings are formed, the interiors of the openings are cleaned with plasma, and after cleaning, the protective film is removed from the resin insulating layer, and the via conductors are formed in the openings. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-39312 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method for manufacturing a printed wiring board disclosed in Patent Document 1, the inside of an opening formed in a resin insulating layer is cleaned with plasma. It is thought that the cleaning by plasma may prevent desired adhesion between the inner surface of the opening (the bottom surface formed by the first conductor layer and the inner wall surface formed by the resin insulating layer) and the via conductor, resulting in a loss of connection reliability of the via conductor. [Means for solving the problem]

[0005] The method for manufacturing a wiring board of the present invention includes forming an insulating layer on a conductor layer, irradiating the insulating layer with laser light to form a through hole that penetrates the insulating layer in a thickness direction and exposes the conductor layer, cleaning the inner surface of the through hole, forming a metal film layer on the inner surface of the through hole, and filling the through hole with a plating film layer to form a via conductor. The cleaning is performed by ion gun treatment, and the ion gun treatment includes forming a recess in the surface of the conductor layer exposed in the through hole.

[0006] According to an embodiment of the present invention, the inside of the through hole is cleaned by ion gun treatment to form a recess, which is thought to make it possible to provide a wiring substrate having via conductors with good connection reliability relatively easily. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention. [Figure 2] An enlarged view of region II in Figure 1. [Figure 3A] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3B] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3C] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3D] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3E] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3F] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3G] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3H] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3I] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3J] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3K] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3L] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3M] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 3N] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] A wiring board manufactured by a wiring board manufacturing method according to an embodiment will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board to be manufactured. Note that the illustrated wiring board 1 is merely an example of a wiring board manufactured by the manufacturing method according to an embodiment. The layered structure of the manufactured wiring board and the number of conductor layers and insulating layers are not limited to the layered structure of the wiring board 1 shown in FIG. 1 and the number of conductor layers and insulating layers included in the wiring board 1. Furthermore, the referenced drawings are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0009] The wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite the first surface 1F) that are perpendicular to its thickness direction. The wiring board 1 has insulating layers 11 and conductor layers 12 that are alternately stacked. The conductor layers 12 that face each other across one insulating layer 11 are connected by via conductors 13. In the illustrated example, the conductor layer 12 that constitutes a part of the first surface 1F is formed in a pattern having a plurality of conductor pads 12fp. The conductor layer 12 that constitutes a part of the second surface 1B is formed in a pattern having a plurality of conductor pads 12bp.

[0010] 1, the first surface 1F side of the wiring board 1 will be referred to as the "top" or "upper side," and the second surface 1B side of the wiring board 1 will be referred to as the "bottom" or "lower side." Furthermore, in each component that makes up the wiring board 1, the surface facing the first surface 1F side of the wiring board 1 will also be referred to as the "top surface," and the surface facing the second surface 1B side of the wiring board 1 will also be referred to as the "bottom surface."

[0011] The insulating layer 11 may be formed using an insulating resin such as an epoxy resin or a phenol resin. The insulating layer 11 may contain any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). In the wiring board 1, the thickness of the insulating layer 11 is, for example, 5 μm to 15 μm. The insulating layer 11 may contain an inorganic filler such as fine particles made of silica (SiO2), alumina, or mullite. The insulating layer 11 may also contain a core material (reinforcing material) made of glass fiber, aramid fiber, or the like.

[0012] Examples of conductors constituting the conductor layer 12 and the via conductors 13 include copper and nickel, and copper is preferably used. The conductor layer 12 and the via conductors 13 have a multilayer structure. The conductor layer 12 and the via conductors 13 have a two-layer structure including a metal film layer 12a, which is preferably a sputtered film layer or an electroless copper plating film layer containing copper or a copper alloy, and a plating film layer 12b, which is preferably an electrolytic copper plating film layer.

[0013] Via conductors 13 that penetrate insulating layer 11 in the thickness direction are formed by filling through holes 11a that penetrate insulating layer 11 with a conductor. In the example of Fig. 1, via conductors 13 are formed integrally with the conductor layer 12 provided above them. Therefore, via conductors 13 and conductor layer 12 are formed by the same metal film layer 12a and plating film layer 12b.

[0014] In the example of FIG. 1, the wiring board 1 includes a solder resist layer Rf formed on the uppermost insulating layer 11 and conductor layer 12, and a solder resist layer Rb formed below the lowermost insulating layer 11 and conductor layer 12. The solder resist layers Rf and Rb are formed using, for example, photosensitive polyimide resin or epoxy resin. An opening Rfa is formed in the solder resist layer Rf, and the conductor pad 12fp is exposed from the opening Rfa. An opening Rba is formed in the solder resist layer Rb, and the conductor pad 12bp is exposed from the opening Rba.

[0015] In the wiring board 1, the thickness of the conductor layer 12 is, for example, 2 μm to 8 μm. The conductor layer 12 included in the wiring board 1 is patterned to have a predetermined conductor pattern and may have relatively fine, high-density circuit wiring. When the conductor layer 12 is formed to include relatively fine wiring, it may be preferable that the via conductors 13 connecting the conductor layers 12 facing each other via the insulating layer 11 have a relatively small diameter and that the via conductors 13 are formed at a fine pitch. When via conductors 13 with a relatively small diameter are formed, small-diameter through holes 11a may be formed in the insulating layer 11.

[0016] Specifically, the diameter of the through hole 11a (diameter of the via conductor 13) formed in the insulating layer 11 may be, for example, 5 μm or more and 30 μm or less. Although the term "diameter" is used, the planar shapes of the through hole 11a and the via conductor 13 are not necessarily limited to circular. The term "diameter" used with respect to the through hole 11a and the via conductor 13 means the distance between the longest two points on the periphery of the through hole 11a and the via conductor 13 on the upper surface of the insulating layer 11 through which the through hole 11a and the via conductor 13 penetrate.

[0017] Next, the configuration of via conductors 13 included in wiring board 1 (particularly the connection structure between via conductors 13 and conductor layer 12) will be described in detail with reference to Fig. 2. Note that, for ease of explanation, in the description with reference to Fig. 2, the lowermost conductor layer among the conductor layers shown in Fig. 2 will be referred to as first conductor layer 121, and the insulating layer formed in contact with the surface of first conductor layer 121 will be referred to as first insulating layer 111. Furthermore, the conductor layer formed in contact with the upper surface of first insulating layer 111 will be referred to as second conductor layer 122, and the insulating layer formed on first insulating layer 111 exposed from second conductor layer 122 and the conductor pattern of second conductor layer 122 will be referred to as second insulating layer 112.

[0018] FIG. 2 shows an enlarged view of region II surrounded by a dashed line in FIG. 1. At the connection portion between the via conductor 13 and the first conductor layer 121, the via conductor 13 is fitted into the first conductor layer 121. Specifically, the portion of the first conductor layer 121 exposed in the through hole 11a is recessed downward compared to the portion of the first conductor layer 121 covered by the first insulating layer 111. That is, a recess RE is formed in the portion of the first conductor layer 121 exposed in the through hole 11a. The recess RE is formed in a cleaning process for the inner surface of the through hole 11a, as will be described in detail later in the description of the manufacturing method for the wiring board. The recess RE may have a depth of 10 nm or more and 2000 nm or less (the shortest distance between the top surface of the first conductor layer 121 and the bottom surface of the recess RE).

[0019] The metal film layer 12a constituting the via conductor 13 is formed along the inner surface of the recessed portion RE. That is, the via conductor 13 and the first conductor layer 121 are connected over a wider area than when the first conductor layer 121 is formed flat without the recessed portion RE. Therefore, the via conductor 13 and the first conductor layer 121 are adhered relatively firmly to each other, and peeling at the connection can be suppressed. The connection between the via conductor 13 and the first conductor layer 121 can have relatively high connection reliability.

[0020] As will be described in detail later in the description of the manufacturing method for the wiring board, cleaning the inner surface of the through hole 11a forms the inner wall surface of the through hole 11a penetrating the first insulating layer 111 with a relatively small surface roughness. The surface roughness of the inner wall surface of the through hole 11a is, for example, 0.6 μm or less in arithmetic mean roughness. Because the surface roughness of the inner wall surface of the through hole 11a is relatively small, the metal film layer 12a formed along the inner wall surface of the through hole 11a can be formed with a more uniform thickness. In particular, when the metal film layer 12a is a sputtered film formed by sputtering, a large surface roughness on the inner wall surface of the through hole 11a can cause poor formation of the metal film layer 12a and result in peeling from the inner wall surface of the via conductor 13. In contrast, forming the metal film layer 12a with a uniform thickness on an inner wall surface with a small surface roughness is believed to achieve better adhesion between the via conductor 13 and the inner wall surface of the through hole 11a.

[0021] Furthermore, as will be described later in the description of the manufacturing method for the wiring board, the upper surface of the first insulating layer 111 is formed as a flat surface with a relatively small surface roughness by processing the inner surface of the through hole 11a and the upper surface of the first insulating layer 111. The surface roughness of the upper surface of the first insulating layer 111 is 0.1 μm or less in arithmetic mean roughness. Because the surface roughness of the upper surface of the first insulating layer 111 is relatively small, the metal film layer 12a formed in contact with the upper surface of the first insulating layer 111 can be formed to a more uniform thickness. It is believed that the conductor pattern of the second conductor layer 122 formed in contact with the upper surface of the first insulating layer 111 can be formed to dimensions that are more faithful to the design values.

[0022] 3A to 3N, a method for manufacturing a wiring board according to an embodiment will be described using, as an example, the case where wiring board 1 shown in Fig. 1 is manufactured. Note that, unless otherwise specified, each component formed in the manufacturing method described below can be formed using the material exemplified as the material of the corresponding component in the description of wiring board 1 in Fig. 1.

[0023] In the following description of the manufacturing method for wiring board 1, the side closer to the core material GS constituting the support substrate SP will be referred to as the "bottom" or "lower side," and the side farther from the support substrate SP will be referred to as the "top" or "upper side." Therefore, the surface of each element constituting wiring board 1 facing the support substrate SP will be referred to as the "lower surface," and the surface facing away from the support substrate SP will also be referred to as the "upper surface." Also, in the description of the manufacturing method, for ease of explanation, as in the description of the wiring board with reference to FIG. 2, the conductor layer closest to the support substrate SP will be referred to as the first conductor layer 121, the insulating layer formed in contact with the first conductor layer 121 will be referred to as the first insulating layer 111, the conductor layer formed on the first insulating layer 111 will be referred to as the second conductor layer 122, and the insulating layer formed on the first insulating layer 111 will be referred to as the second insulating layer 112.

[0024] First, as shown in FIG. 3A, a support substrate SP is prepared. In the wiring substrate manufacturing method of this embodiment, the support substrate SP used has excellent flatness on two surfaces perpendicular to its thickness direction. The support substrate SP includes a core material GS, such as a glass substrate, a first metal film layer ML1 laminated on both surfaces of the core material GS, and a second metal film layer ML2 laminated on the first metal film layer ML1 via an adhesive layer AL. The first and second metal film layers ML1 and ML2 are metal film layers formed by, for example, electroless plating or sputtering. Although the first and second metal film layers ML1 and ML2 are depicted as single layers in the illustration, they may include multiple layers. For example, the first and second metal film layers ML1 and ML2 may each have a two-layer structure composed of a titanium layer and a copper layer. The adhesive layer AL may include, for example, an azobenzene-based polymer adhesive that can be attached and detached by light irradiation. The support substrate SP may include a silicon substrate, a metal substrate, or a ceramic substrate as a core material GS in addition to a glass substrate.

[0025] Next, as shown in FIG. 3B, a first conductor layer 121 having a plurality of conductor pads 12bp is formed on the support substrate SP. In forming the first conductor layer 121 in contact with the support substrate SP, for example, a plating resist is formed on the second metal film layer ML2, and openings corresponding to the formation areas of the pattern of the conductor pads 12bp are formed in the plating resist by, for example, photolithography. Next, a plating film layer is formed in the openings by electrolytic plating using the second metal film layer ML2 as a seed layer. After the plating film layer is formed, the plating resist is removed, resulting in the state shown in FIG. 3B.

[0026] 3C, a first insulating layer 111 is laminated to cover the upper and side surfaces of the first conductor layer 121 and the surface of the support substrate SP exposed from the conductor pattern of the first conductor layer 121. For example, an insulating resin such as epoxy resin or phenol resin can be used as the first insulating layer 111. Fluorine resin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI) may also be used. The first insulating layer 111 is formed by thermocompression bonding these resins formed into a film shape. A protective film PF, such as a polyethylene terephthalate (PET) film, is provided on the upper surface of the film-like resin that constitutes the first insulating layer 111.

[0027] 3C and 3D to 3N, which will be referred to below, show stacks formed on one surface of the support substrate SP, and do not show stacks that may be formed on the opposite surface. However, the opposite surface of the support substrate SP may also have stacks in the same manner and number, or may have conductor layers and insulating layers in a manner and number different from those on one surface, or may not have such conductor layers and insulating layers.

[0028] Next, the protective film PF is removed from the first insulating layer 111. The entire upper surface of the first insulating layer 111 is exposed. For example, UV (ultraviolet) laser light is irradiated onto the upper surface of the first insulating layer 111 at the formation position of the via conductor 13 (see FIG. 1), thereby forming the through hole 11a as shown in FIG. 3D. The UV laser light may have a wavelength of 100 nm or more and 500 nm or less. By directly irradiating the upper surface of the first insulating layer 111 with laser light after the protective film PF has been removed and the upper surface of the first insulating layer 111 is exposed, the through hole 11a with a relatively small diameter can be formed more accurately. The through hole 11a may be formed so that its diameter at the surface (upper surface) of the first insulating layer 111 is, for example, 5 μm or more and 30 μm or less.

[0029] Next, as shown in FIG. 3E, which is an enlarged view of the region e surrounded by the dashed line in FIG. 3D, cleaning is performed to remove smears (process-induced defects) that have occurred on the inner surface of the through-hole 11a. The cleaning is performed by ion gun treatment. Here, "ion gun treatment" refers to a processing method in which a source gas supplied from an ion source is converted into plasma in a vacuum, and the plasma ions i are collided with the object to be processed (here, the upper surface of the first insulating layer 111 and the inner surface of the through-hole 11a). For example, argon is used as the source gas for the ion gun treatment, and in this case, the ions i are argon ions with a valence of 1.

[0030] In the ion gun treatment, ions i collide with the upper surface of the first insulating layer 111 and the inner surface (inner wall surface and bottom surface) of the through hole 11a. The ion gun treatment removes smears inside the through hole 11a. In addition, the upper surface of the first insulating layer 111 and the inner surface of the through hole 11a are etched by the ions i. Specifically, the upper surface of the first conductor layer 121 exposed inside the through hole 11a is scraped downward, resulting in the formation of a recess RE. The recess RE can be formed so that its depth (the shortest distance between the upper surface of the first conductor layer 121 and the bottom surface of the recess RE) is 10 nm or more and 2000 nm or less.

[0031] Ion gun processing can form a relatively smooth surface (i.e., a relatively small surface roughness) of the surface to be processed compared to, for example, plasma etching using oxygen plasma or wet etching using a chemical solution. For example, when plasma etching using oxygen plasma is performed, the exposed upper surface of the first insulating layer 111 and the inner wall surface of the through hole 11a are formed with a relatively large surface roughness. Therefore, to form the upper surface of the first insulating layer 111 with a relatively small surface roughness, it is necessary to cover the upper surface of the first insulating layer 111 with a protective film PF or the like. In contrast, when ion gun processing is performed, the upper surface of the first insulating layer 111 does not need to be covered with a protective film PF or the like, and the upper surface of the first insulating layer 111 is formed relatively smoothly, for example, with a surface roughness of 0.1 μm or less in arithmetic mean roughness. Furthermore, when ion gun treatment is performed, the smear inside the through hole 11a is effectively removed, while the inner wall surface of the through hole 11a is formed relatively smoothly; for example, the inner wall surface of the through hole 11a is formed so that the surface roughness is 0.15 μm or more and 0.6 μm or less in arithmetic mean roughness.

[0032] 3F, a metal film layer 12a is formed by sputtering on the inner wall of the through hole 11a and the surface of the first insulating layer 111. In forming the metal film layer 12a, copper or a copper alloy is used as a sputtering target, and the metal film layer 12a can be formed as a sputtered film containing copper or a copper alloy. As described above, a recess RE is formed in the portion of the first conductor layer 121 exposed inside the through hole 11a, and the metal film layer 12a formed on the inner surface of the through hole 11a and the first conductor layer 121 are in close contact over a relatively wide area.

[0033] As described above, the inner wall surface of through hole 11a and the upper surface of first insulating layer 111 are formed as surfaces with relatively small surface roughness. Therefore, metal film layer 12a formed on the inner wall surface of through hole 11a and the upper surface of first insulating layer 111 can be formed as a sputtered film with a uniform thickness with relatively little variation.

[0034] 3G, a dry film resist containing, for example, a photosensitive epoxy resin is adhered onto the metal film layer 12a to form a resist layer RL. Subsequently, the resist layer RL is exposed and developed to form a resist pattern having openings RLo corresponding to the conductor pattern of the second conductor layer 122 (see FIG. 1) to be formed on the first insulating layer 111.

[0035] Next, as shown in FIG. 3H, a plating film layer 12b is formed in the opening RLo of the resist layer RL by electrolytic plating using the metal film layer 12a as a power supply layer. The interior of the through hole 11a is completely filled with the plating film 12b, forming the via conductor 13. The formed via conductor 13 and the first conductor layer 121 are connected over a relatively large area. Therefore, the via conductor 13 and the first conductor layer 121 adhere relatively firmly to each other. Furthermore, since the surface roughness of the inner wall surface of the through hole 11a is relatively small, the via conductor 13 can be formed to have good adhesion to the inner wall surface of the through hole 11a.

[0036] Next, the resist layer RL is removed using a stripping solution. Removal of the resist layer RL exposes the side surfaces of the plating film layer 12b. After the resist layer RL is removed, the portions of the metal film layer 12a that are not covered by the plating film layer 12b are removed by etching. As shown in FIG. 3I, a second conductor layer 122 having a two-layer structure consisting of the metal film layer 12a and the plating film layer 12b is formed. Because the upper surface of the first insulating layer 111 has a relatively small surface roughness, removal of the metal film layer 12a by etching is more reliable, and defects such as short circuits in the conductor pattern of the second conductor layer 122 can be suppressed. Furthermore, the metal film layer 12a formed on the upper surface of the first insulating layer 111 has a more uniform thickness. Therefore, it is believed that the conductor pattern of the second conductor layer 122 can be formed to dimensions that are more faithful to the design values.

[0037] Next, as shown in Figure 3J, a second insulating layer 112 is formed on the second conductor layer 122 and the first insulating layer 111 exposed from the conductor pattern of the second conductor layer 122 in a manner similar to the method for forming the first insulating layer 111, and further, a conductor layer 12 is formed on the second insulating layer 112 in a manner similar to the method for forming the second conductor layer 122.

[0038] 3K, a desired number of insulating layers 11 and conductor layers 12 are stacked on the conductor layer 12 and the second insulating layer 112 in a manner similar to the method for forming the first insulating layer 111 and the second conductor layer 122. The uppermost conductor layer 12 is formed in a pattern including conductor pads 12fp.

[0039] Next, as shown in FIG. 3L, a solder resist layer Rf is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 11 and the conductor layer 12, and openings Rfa that define the conductor pads 12fp are formed using photolithography techniques.

[0040] Next, as shown in FIG. 3M, the support substrate SP is removed. The lower surface of the second metal film layer ML2 below the conductor pad 12bp is exposed. In removing the support substrate SP, the adhesive layer AL is softened by, for example, irradiating it with laser light, and then the second metal film layer ML2 of the support substrate SP is peeled off.

[0041] Next, the second metal film layer ML2 is removed by etching, exposing the lower surfaces of the conductor pads 12bp and the first insulating layer 111. A solder resist layer Rb is formed on the lower surfaces of the conductor pads 12bp and the first insulating layer 111 by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the first insulating layer 111 and the first conductor layer 121. Openings Rba that define the conductor pads 12bp are formed in the solder resist layer Rb by photolithography. This completes the manufacture of the wiring board 1.

[0042] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to Figures 3A to 3N, and the conditions and order thereof may be changed as desired. The method for manufacturing a wiring board according to the embodiment may include at least the steps of forming a via conductor by irradiating an insulating layer on a conductor layer with laser light to form a through hole, and cleaning the surface of the insulating layer and the inner surface of the through hole by ion gun treatment to form a recess in the surface of the conductor layer. Depending on the structure of the wiring board to be manufactured, some steps may be omitted, or other steps may be added. [Explanation of symbols]

[0043] 1. Wiring board 11 Insulating layer 12 Conductor layer 13 Via conductor 111 First insulating layer 112 Second insulating layer 121 First conductor layer 122 Second conductor layer 12a Metal film layer 12b Plating film layer 1F, 1st floor 1B 2nd side i ion PF protective film Rf, Rb solder resist layer RE recess

Claims

1. Forming an insulating layer on a conductive layer, By irradiating the insulating layer with laser light, through-holes are formed that penetrate the insulating layer in the thickness direction and expose the conductive layer. To clean the inner surface of the through hole, Forming a metal film layer on the inner surface of the through hole, A via conductor is formed by filling the aforementioned through-hole with a plating film layer, A method for manufacturing a wiring board, including, The cleaning is performed by ion gun treatment. The ion gun treatment includes forming a recess in the surface of the conductive layer exposed in the through-hole.

2. 2. The method for manufacturing a wiring board according to claim 1, wherein the source gas for the ion gun treatment contains argon.

3. 2. The method for manufacturing a wiring board according to claim 1, wherein the metal film layer is formed by sputtering.

4. 4. The method for manufacturing a wiring board according to claim 3, wherein the metal film layer contains copper or a copper alloy.

5. A method for manufacturing a wiring board according to claim 1, wherein the laser light is UV laser light.

6. 2. The method for manufacturing a wiring board according to claim 1, Forming the insulating layer includes forming an insulating layer having a protective film on the surface opposite to the conductor layer, The method further includes removing the protective film before irradiating it with the laser light.

7. A method for manufacturing a wiring board according to claim 6, wherein the ion gun treatment includes cleaning the surface of the insulating layer from which the protective film has been removed.

8. A method for manufacturing a wiring board according to claim 1, wherein the through-hole is formed such that the diameter of the through-hole is 5 μm or more and 30 μm or less.

9. A method for manufacturing a wiring board according to claim 1, wherein the surface roughness of the inner wall surface of the through hole after the ion gun treatment is performed is 0.15 μm or more and 0.6 μm or less in terms of arithmetic mean roughness.

10. A method for manufacturing a wiring board according to claim 1, wherein the recess is formed to have a depth of 10 nm or more and 2000 nm or less.

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