wiring board

Abstract

To provide a wiring board having high quality. [Solution] In one embodiment, a wiring board has a multilayer core substrate and build-up layers. The multilayer core substrate includes a central insulating layer, first and second resin substrates, first and second outer insulating layers, through-hole conductors, a surface conductor layer, and connecting conductors, and a component is disposed thereon. The through-hole conductors consist of a through hole, a first via conductor, and a second via conductor. The through hole is a hole that penetrates the first resin substrate, the central insulating layer, and the second resin substrate. An inner wall conductor layer is formed on the inner wall of the hole. First and second lid conductors are formed on the first and second resin substrates. The first via conductor is formed in the first outer insulating layer and connects the first surface conductor layer to the first lid conductor. The second via conductor is formed in the second outer insulating layer and connects the second surface conductor layer to the second lid conductor. An opening is formed through the first resin substrate, and the non-electrode surface of the component is disposed on the central insulating layer exposed from the opening, and the electrode surface is connected by the connecting conductor in the first outer insulating layer.

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board including a multilayer core substrate, an opening extending from a first surface to a second surface of the multilayer core substrate, an electronic component housed in the opening, and a build-up layer including an interlayer resin insulating layer formed on the multilayer core substrate. It also discloses that the gap between the substrate and the component in the opening of the multilayer core substrate is filled with resin or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-185564 Summary of the Invention

[0004] [Problem of Patent Document 1] In the printed wiring board of Patent Document 1, the opening is a through hole that extends from the first surface to the second surface of the multilayer core substrate. Therefore, it is considered necessary to fill a certain amount of resin into the gap between the substrate and the component in the opening. Furthermore, if the amount of resin filled is insufficient, it is considered possible that a gap will form in the opening, causing a problem. Conversely, if the amount of resin filled is excessive, it is considered that the component will be covered, preventing successful via formation with the component. [Means for solving the problem]

[0005] The wiring board of the present invention comprises a multilayer core substrate and a build-up layer formed on the multilayer core substrate by insulating layers and conductor layers. The multilayer core substrate includes a multilayer insulating layer, through-hole conductors, surface conductor layers, and connecting conductors, and components are arranged on it. The multilayer insulating layer comprises a central insulating layer, a resin substrate, and an outer insulating layer. A first resin substrate is formed on a first surface of the central insulating layer, a first outer insulating layer is formed on the first resin substrate, and a first surface conductor layer is formed on the first outer insulating layer. A second resin substrate is formed on a second surface of the central insulating layer, a second outer insulating layer is formed on the second resin substrate, and a second surface conductor layer is formed on the second outer insulating layer. The through-hole conductor comprises a through hole, a first via conductor, and a second via conductor. The through hole is a hole that penetrates the first resin substrate, the central insulating layer, and the second resin substrate, and an inner wall conductor layer is formed on the inner wall of the hole, a first lid conductor is formed on the first resin substrate, and a second lid conductor is formed on the second resin substrate. The first via conductor penetrates the first outer insulating layer and is formed in a hole exposing the first lid conductor, connecting the first surface conductor layer and the first lid conductor. The second via conductor penetrates the second outer insulating layer and is formed in a hole exposing the second lid conductor, connecting the second surface conductor layer and the second lid conductor. The component has an electrode surface and a non-electrode surface opposite the electrode surface. An opening is formed through the first resin substrate, the non-electrode surface of the component is placed on the first surface of the central insulating layer exposed from the opening, and the electrode surface is connected by the connecting conductor of the first outer insulating layer.

[0006] In the wiring board of the embodiment of the present invention, the opening for accommodating the component penetrates the first resin substrate but does not penetrate the multilayer core substrate. This allows for a reduced amount of resin to be used to fill the gap between the substrate and the component in the opening. Furthermore, the through-hole penetrates the first resin substrate, the central insulating layer, and the second resin substrate. The length of the through-hole is shorter than in the past, ensuring stability during signal transmission within the through-hole. Furthermore, the use of a multilayer core substrate allows for the use of built-in components without any limitations on thickness, etc. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a wiring board according to an embodiment. [Figure 2] Enlarged view of part II in Figure 1. [Figure 3A] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3B] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3C] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3D] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3E] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3F] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3G] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3H] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3I] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3J] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 3K] 5A to 5C are cross-sectional views schematically showing a method for manufacturing a wiring board according to an embodiment. [Figure 4] FIG. 10 is a cross-sectional view schematically showing a wiring board according to a first modified example. [Figure 5A] 10A and 10B are cross-sectional views schematically showing a method for manufacturing a wiring board according to a second modified example. [Figure 5B] 10A and 10B are cross-sectional views schematically showing a method for manufacturing a wiring board according to a second modified example. [Figure 5C] 10A and 10B are cross-sectional views schematically showing a method for manufacturing a wiring board according to a second modified example. [Figure 5D] 10A and 10B are cross-sectional views schematically showing a method for manufacturing a wiring board according to a second modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Embodiment] Fig. 1 is a cross-sectional view showing a wiring board 1 of an embodiment. As shown in Fig. 1, the wiring board 1 has a multilayer core substrate 100, a first buildup layer 110, and a second buildup layer 120. The first buildup layer 110 is formed on a first surface 100F of the multilayer core substrate 100. The second buildup layer 120 is formed on a second surface 100S of the multilayer core substrate 100.

[0009] The first buildup layer 110 is configured by alternately forming insulating layers 111 and conductor layers 112 on the first surface 100F of the multilayer core substrate 100. The second buildup layer 120 is configured by alternately forming insulating layers 121 and conductor layers 122 on the second surface 100S of the multilayer core substrate 100. In the example of FIG. 1 , the first buildup layer 110 is configured by two insulating layers 111 and two conductor layers 112, and the second buildup layer 120 is configured by two insulating layers 121 and two conductor layers 122. Each insulating layer 111 has via conductors 113 formed therein, which connect the conductor layer on the insulating layer 111 to the conductor layer below it. Each insulating layer 121 has via conductors 123 formed therein, which connect the conductor layer on the insulating layer 121 to the conductor layer below it.

[0010] The multilayer core substrate 100 includes a multilayer insulating layer 90, through-hole conductors 91, surface conductor layers (first surface conductor layer 41 and second surface conductor layer 51), and connecting conductors 43. A component 70 is arranged within the multilayer core substrate 100. The multilayer insulating layer 90 includes a central insulating layer 10, a first resin substrate 20, a second resin substrate 30, a first outer insulating layer 40, and a second outer insulating layer 50. The first resin substrate 20 is formed on a first surface 10F of the central insulating layer 10. The second resin substrate 30 is formed on a second surface 10S of the central insulating layer 10. The central insulating layer 10 is sandwiched between the first resin substrate 20 and the second resin substrate 30.

[0011] A first internal conductor layer 21 is formed on a first surface of the first resin substrate 20, and a first internal conductor layer 22 is formed on a second surface of the first resin substrate 20. In other words, the first internal conductor layer 22 is formed on the central insulating layer 10 side, and the first internal conductor layer 21 is formed on the opposite side of the central insulating layer 10. The first internal conductor layer 21 also includes a first lid conductor 23. The first internal conductor layer 22 also includes a component placement conductor layer 24. A second internal conductor layer 31 is formed on a first surface of the second resin substrate 30, and a second internal conductor layer 32 is formed on a second surface of the second resin substrate 30. In other words, the second internal conductor layer 32 is formed on the central insulating layer 10 side, and the second internal conductor layer 31 is formed on the opposite side of the central insulating layer 10. The second internal conductor layer 31 also includes a second lid conductor 33. The first internal conductor layer 22 and the second internal conductor layer 32 may or may not be embedded in the central insulating layer 10 .

[0012] An opening 25 is formed in the first resin substrate 20, penetrating the first resin substrate 20. The opening 25 exposes the component placement conductor layer 24. A component 70 is housed in the opening 25. The component 70 is an electronic component. The component 70 is, for example, a capacitor. The component 70 may also be an inductor, an IVR, or the like. In a modified example, a plurality of components 70 may be housed in the opening 25. The component 70 has an electrode surface 71 and a non-electrode surface 72 opposite the electrode surface 71. The non-electrode surface 72 of the component 70 is placed on the component placement conductor layer 24 exposed from the opening 25. That is, the non-electrode surface 72 of the component 70 is placed on the first surface 10F of the central insulating layer 10 exposed from the opening 25. The electrode surface 71 of the component 70 faces the first outer insulating layer 40. The electrode surface 71 is connected to the connecting conductor 43 of the first outer insulating layer 40. The gap between the inner surface of the opening 25 and the component 70 is filled with an embedded resin 73. The potting resin 73 is, for example, a thermosetting resin. The potting resin 73 may be a photocurable resin. The potting resin 73 is provided separately from the first resin substrate 20 and the first outer insulating layer 40.

[0013] The first outer insulating layer 40 is formed on the first resin substrate 20. A first surface conductor layer 41 is formed on a first surface of the first outer insulating layer 40. A connecting conductor 43 is formed in the first outer insulating layer 40. The connecting conductor 43 is formed in a hole 40b that penetrates the first outer insulating layer 40 and exposes the electrode surface 71 of the component 70. The connecting conductor 43 connects the first surface conductor layer 41 and the electrode surface 71 of the component 70.

[0014] The second outer insulating layer 50 is formed on the second resin substrate 30. A second surface conductor layer 51 is formed on the second surface of the second outer insulating layer 50. In the wiring board 1, the first internal conductor layers 21 and 22, the first surface conductor layer 41, the second internal conductor layers 31 and 32, the second surface conductor layer 51, the conductor layer 112 in the first buildup layer 110, and the conductor layer 122 in the second buildup layer 120 may have any conductor pattern. Each of these conductor layers is shown in FIG. 1 as having a simple single-layer structure for ease of viewing, but may have a multi-layer structure of two or more layers, as will be described in detail below with reference to FIG. 2.

[0015] The internal conductor layers, which are the first internal conductor layer 21 and the second internal conductor layer 31, are formed in the through holes 60 of the multilayer core substrate 100. By forming the internal conductor layers in the through holes 60, the internal conductor layers penetrate the multilayer core substrate 100, ensuring stability when transmitting signal lines. In this case, the size, thickness, material, etc. of the internal conductor layers are not limited. The internal conductor layers may be formed as the first internal conductor layer 21 and the second internal conductor layer 31, or as either the first internal conductor layer 21 or the second internal conductor layer 31. Forming the internal conductor layers as the first internal conductor layer 21 and the second internal conductor layer 31 makes it easier to ensure stability when transmitting signal lines. Furthermore, forming the first internal conductor layer 21 and the second internal conductor layer 31 ensures the strength of the multilayer core substrate 100.

[0016] In the description of the wiring board 1 of this embodiment, the side farther from the central insulating layer 10 in the thickness direction of the wiring board 1 is referred to as the "upper side" or "upper," or simply "upper," and the side closer to the central insulating layer 10 is referred to as the "lower side" or "lower," or simply "lower." Furthermore, in each conductor layer and each insulating layer, the surface facing away from the central insulating layer 10 is referred to as the "upper surface," and the surface facing the central insulating layer 10 is referred to as the "lower surface." Therefore, for example, in the description of the first buildup layer 110 and the second buildup layer 120, the side farther from the multilayer core substrate 100 is referred to as the "upper side," "upper," or simply "upper," and the side closer to the multilayer core substrate 100 is referred to as the "lower side," "lower," or simply "lower." In the description of the wiring board 1 of this embodiment, each conductor layer and each insulating layer may be referred to as the "first surface" or the "second surface." In this case, the first surface is described as the upper surface for convenience, but it may be either the upper surface or the lower surface.

[0017] The insulating layers and resin substrates constituting the multilayer insulating layer 90 of the present invention are formed by impregnating a core material, which serves as a reinforcing material, with an insulating resin and then curing it. Examples of insulating resins that can be used include epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin. Examples of reinforcing materials include glass fiber, aramid fiber, glass nonwoven fabric, and aramid nonwoven fabric. By including a core material in the insulating layers and resin substrate, a wiring board 1 is provided that is highly rigid and suppresses warping. Meanwhile, the insulating layers 111 and 121 used as build-up layers are preferably formed from an insulating resin that does not contain a core material. This is because an insulating resin that does not contain a core material is suitable for via formation. Each insulating layer may also contain an inorganic filler such as silica.

[0018] The through-hole conductor 91 is made up of a through-hole 60, a first via conductor 42, and a second via conductor 52. The through-hole conductor 91 connects the first surface conductor layer 41 and the second surface conductor layer 51.

[0019] The through hole 60 is composed of an inner wall conductor layer 61 formed on the inner wall of the through hole 60a and a filler 62 filling the through hole 60a. The inner wall conductor layer 61 is formed on the inner wall of the through hole 60a, which penetrates the first resin substrate 20, the central insulating layer 10, and the second resin substrate 30. The filler 62 fills the through hole 60a. A first lid conductor 23 connected to the inner wall conductor layer 61 is formed at the end of the through hole 60 facing the first resin substrate 20. The first lid conductor 23 covers the end of the filler 62 facing the first resin substrate 20. A second lid conductor 33 connected to the inner wall conductor layer 61 is formed at the end of the through hole 60 facing the second resin substrate 30. The second lid conductor 33 covers the end of the filler 62 facing the second resin substrate 30.

[0020] The first via conductor 42 is formed in a hole 40a that penetrates the first outer insulating layer 40 and exposes the first lid conductor 23. The first via conductor 42 connects the first surface conductor layer 41 and the first lid conductor 23. The second via conductor 52 is formed in a hole 50a that penetrates the second outer insulating layer 50 and exposes the second lid conductor 33. The second via conductor 52 connects the second surface conductor layer 51 and the second lid conductor 33.

[0021] A first buildup layer 110 and a second buildup layer 120 are formed on a multilayer core substrate 100 of the wiring board 1. The first buildup layer 110 is formed on a first surface 100F of the multilayer core substrate 100. The second buildup layer 120 is formed on a second surface 100S of the multilayer core substrate 100. In the illustrated example, the first buildup layer 110 and the second buildup layer 120 each include two conductor layers and two insulating layers, but they may also include three or more conductor layers and three or more insulating layers, or may include only one conductor layer and one insulating layer.

[0022] The conductor layer 112 on the surface side of the first buildup layer 110, which is the outermost layer of the wiring board 1, and the conductor layer 122 on the surface side of the second buildup layer 120, which is the outermost layer of the wiring board 1, include connection pads 112a, 122a used for mounting external electronic components, a motherboard (not shown), etc. When electronic components are mounted, bumps (not shown) made of any metal such as solder, copper, or tin are formed on the connection pads 112a, 122a.

[0023] The structure of the conductors included in the wiring board 1 will be described in detail with reference to Fig. 2. Fig. 2 shows an enlarged view of part II in Fig. 1.

[0024] As shown in Fig. 2, the first internal conductor layer 22 is formed of a metal foil 22a formed on the lower surface (second surface) of the first resin substrate 20. A component placement conductor layer 24 is formed on the first internal conductor layer 22. The second internal conductor layer 32 is formed of a metal foil 32a formed on the upper surface (first surface) of the second resin substrate 30. The first internal conductor layer 22 and the second internal conductor layer 32 have a single-layer structure made of the metal foils 22a, 32a, but may have a multi-layer structure made of two or more layers. The type of metal in the metal foils 22a, 32a is not particularly limited, but it is preferable to use one containing copper as the main component.

[0025] Here, the conductor layer of the present invention is formed by any combination of a metal foil layer, a seed layer, and an electroplated layer. The metal foil layer is a conductor layer patterned starting from a metal foil formed on an insulating layer. The type of metal in the metal foil is not particularly limited, but it is preferable to use one mainly composed of copper. The seed layer is a conductor layer patterned by forming a seed film such as an electroless plated film or a sputtered film on the entire surface of the substrate. The type of metal in the seed film is not particularly limited, but it is preferable to use one mainly composed of copper, nickel, or titanium. The electroplated layer is a conductor layer patterned by forming a resist pattern on the seed film formed on the substrate, and then depositing an electroplated film on the non-resist areas. The type of metal in the electroplated film is not particularly limited, but it is preferable to use one mainly composed of copper.

[0026] On the other hand, the first internal conductor layer 21 is formed by a metal foil layer 21a formed on the upper surface (first surface) of the first resin substrate 20, a seed layer 21b on the metal foil layer 21a, an electrolytic plated layer 21c on the seed layer 21b, a seed layer 21d on the electrolytic plated layer 21c, and an electrolytic plated layer 21e on the seed layer 21d. The first internal conductor layer 21 has a five-layer structure made up of the metal foil layer 21a, the seed layer 21b, the electrolytic plated layer 21c, the seed layer 21d, and the electrolytic plated layer 21e. The first cover conductor 23 is formed by the seed layer 21d and the electrolytic plated film 21e. Similarly, the second internal conductor layer 31 is formed by a metal foil layer 31a formed on the upper surface (first surface) of the second resin substrate 30, a seed layer 31b on the metal foil layer 31a, an electrolytic plated layer 31c on the seed layer 31b, a seed layer 31d on the electrolytic plated layer 31c, and an electrolytic plated layer 31e on the seed layer 31d. The second internal conductor layer 31 has a five-layer structure made up of the metal foil layer 31a, the seed layer 31b, the electrolytic plated layer 31c, the seed layer 31d, and the electrolytic plated layer 31e. The second cover conductor 33 is formed by the seed layer 31d and the electrolytic plated layer 31e.

[0027] The inner wall conductor layer 61 of the through hole 60 is formed by a seed layer 61b formed on the inner wall surface of the through hole 60a and an electroplated layer 61c on the seed layer 61b. The seed layer 61b is common to the seed layers 21b and 31b and is formed simultaneously with the seed layers 21b and 31b. The electroplated layer 61c is common to the electroplated layers 21c and 31c and is formed simultaneously with the electroplated layers 21c and 31c. The inside of the through hole 60 is filled with a filler 62. The filler 62 is formed using an insulating material containing a resin such as epoxy, acrylic, or phenol. Alternatively, the filler 62 may be a solidified conductive paste or conductive ink containing conductive particles such as silver particles. Filling the inside of the through hole 60 with the filler 62 enables the formation of a via conductor directly above the through hole 60. A first cover conductor 23 and a second cover conductor 33 are formed on the end surface of the filler 62 so as to cover the end surface of the filler 62.

[0028] The first surface conductor layer 41 is formed of a metal foil layer 41a formed on the upper surface (first surface) of the first outer insulating layer 40, a seed layer 41b on the metal foil layer 41a, and an electrolytic plated layer 41c on the seed layer 41b. The first surface conductor layer 41 has a three-layer structure made up of the metal foil layer 41a, the seed layer 41b, and the electrolytic plated layer 41c. Similarly, the second surface conductor layer 51 is formed of a metal foil layer 51a formed on the upper surface of the second outer insulating layer 50, a seed layer 51b on the metal foil layer 51a, and an electrolytic plated layer 51c on the seed layer 51b. The second surface conductor layer 51 has a three-layer structure made up of the metal foil layer 51a, the seed layer 51b, and the electrolytic plated layer 51c.

[0029] The first via conductor 42 is formed in a hole 40a that penetrates the first outer insulating layer 40 and exposes the first lid conductor 23. The first via conductor 42 is formed by a seed layer 41b formed on the inner wall surface of the hole 40a and on the first lid conductor 23, and an electrolytic plating layer 41c formed on the seed layer 41b and filling the hole 40a. The seed layer 41b and electrolytic plating layer 41c that form the first via conductor 42 are the same as the seed layer 41b and electrolytic plating layer 41c that form the first surface conductor layer 41. The first surface conductor layer 41 and the first via conductor 42 are formed simultaneously. Similarly, the second via conductor 52 is formed in a hole 50a that penetrates the second outer insulating layer 50 and exposes the second lid conductor 33. The second via conductor 52 is formed by a seed layer 51b formed on the inner wall surface of the hole 50a and on the second lid conductor 33, and an electrolytic plating layer 51c formed on the seed layer 51b and filling the hole 50a. The seed layer 51b and electrolytic plating layer 51c that form the second via conductor 52 are common to the seed layer 51b and electrolytic plating layer 51c that form the second surface conductor layer 51. The second surface conductor layer 51 and the second via conductor 52 are formed simultaneously.

[0030] The connecting conductor 43 is formed in a hole 40b that penetrates the first outer insulating layer 40 and exposes the electrode surface 71 of the component 70. The connecting conductor 43 is formed by a seed layer 41b that is formed on the inner wall surface of the hole 40b and on the electrode surface 71, and an electrolytic plating layer 41c that is formed on the seed layer 41b and fills the hole 40b. The seed layer 41b and electrolytic plating layer 41c that form the connecting conductor 43 are the same as the seed layer 41b and electrolytic plating layer 41c that form the first surface conductor layer 41 and the first via conductor 42. The first surface conductor layer 41, the first via conductor 42, and the connecting conductor 43 are formed simultaneously.

[0031] The conductor layers 112, 122 in the first buildup layer 110 and the second buildup layer 120 are formed without using metal foil. The conductor layer 112 is formed of a seed layer 112b and an electrolytically plated layer 112c. Similarly, the conductor layer 122 is formed of a seed layer 122b and an electrolytically plated layer 122c.

[0032] Via conductor 113 in first buildup layer 110 is formed of seed layer 112b and electrolytic plated layer 112c. Seed layer 112b and electrolytic plated layer 112c of via conductor 113 are common to seed layer 112b and electrolytic plated layer 112c of conductor layer 112. Similarly, via conductor 123 in second buildup layer 120 is formed of seed layer 122b and electrolytic plated layer 122c. Seed layer 122b and electrolytic plated layer 122c of via conductor 123 are common to seed layer 122b and electrolytic plated layer 122c of conductor layer 122.

[0033] [Method for manufacturing wiring board 1 according to the embodiment] 3A to 3K show a manufacturing method of the wiring board 1 of the embodiment. FIGS. 3A to 3K are cross-sectional views. As shown in FIG. 3A, a first resin substrate 20 is prepared, having a metal foil 21a formed on its upper surface (first surface) and a first internal conductor layer 22 formed on its lower surface (second surface). The first resin substrate 20 is prepared from a double-sided copper-clad laminate, in which metal foils 21a and 22a are formed on both sides of a resin substrate containing a core material. The first internal conductor layer 22 having a desired conductor pattern is formed by a subtractive method, such as etching the metal foil 22a using a mask on which wiring is drawn. The first internal conductor layer 22 also includes a component placement conductor layer 24. Similarly, a second resin substrate 30 is prepared, having a metal foil 31a formed on its upper surface (first surface) and a second internal conductor layer 32 formed on its lower surface (second surface).

[0034] 3B, a first resin substrate 20, a prepreg 10p that will become the central insulating layer 10 upon curing, and a second resin substrate 30 are arranged. Specifically, the first resin substrate 20 is arranged on the first surface 10pF side of the prepreg 10p that will become the central insulating layer 10, and the second resin substrate 30 is arranged on the second surface 10pS side of the prepreg 10p. The first internal conductor layer 22 faces the first surface 10pF. The second internal conductor layer 32 faces the second surface 10pS.

[0035] The first resin substrate 20, prepreg 10p, and second resin substrate 30 are heat-pressed together. As shown in FIG. 3C, the prepreg 10p is cured to form the central insulating layer 10. After pressing, the first internal conductor layer 22 is embedded in the first surface 10F of the central insulating layer 10. The second internal conductor layer 32 is embedded in the second surface 10S of the central insulating layer 10. As a result, an intermediate substrate 2 is formed that includes the central insulating layer 10, the first resin substrate 20, and the second resin substrate 30. During the heat-pressing process, the pressure applied to the center in the pressure direction is concentrated and absorbed by the prepreg 10p, thereby ensuring good thickness uniformity. In other words, there is little risk of the first resin substrate 20 and the second resin substrate 30 losing their parallelism, resulting in a multilayer core substrate 100 with good flatness.

[0036] In this case, for convenience of explanation, the first resin substrate 20 and the second resin substrate 30 are assumed to have the same thickness, but the first resin substrate 20 and the second resin substrate 30 may have different thicknesses. Specifically, the thickness of the first resin substrate 20 on which the component 70 is disposed is made smaller than the thickness of the second resin substrate 30. This allows a component 70 with a small thickness to be disposed. Alternatively, conversely, the thickness of the first resin substrate 20 on which the component 70 is disposed is made larger than the thickness of the second resin substrate 30. This allows a component 70 with a large thickness to be disposed.

[0037] 3D, a through hole 60a is formed penetrating the metal foil 21a, the first resin substrate 20, the first internal conductor layer 22, the central insulating layer 10, the second internal conductor layer 32, the second resin substrate 30, and the metal foil 31a. The through hole 60a is formed by boring with a cutting device such as a drill. The through hole 60a may also be formed by irradiating with laser light.

[0038] As shown in FIG. 3E, a seed layer 21b is formed on the metal foil layer 21a. A seed layer 61b is formed on the inner wall of the through hole 60a. A seed layer 31b is formed on the metal foil layer 31a. The seed layers 21b, 31b, and 61b are formed by, for example, electroless plating or sputtering to form seed films. An electrolytic plated film is formed using the seed film as a power supply layer. Electrolytic plated films 21c, 31c, and 61c are formed on the seed film. Thereafter, an inner wall conductor layer 61 is formed by patterning the seed layer 61b and the electrolytic plated layer 61c.

[0039] The hollow portion of the through hole 60a is filled with a filler 62. For example, a resin such as epoxy, acrylic, or phenol is injected into one or both ends of the through hole. The filler 62 may be a conductive paste containing conductive particles such as silver particles, instead of an insulating resin such as epoxy resin. The insulating resin or conductive paste used for the filler 62, such as epoxy resin, is solidified by heating or other means as necessary to form the filler 62. The through hole 60 is formed within the through hole 60a by the inner wall conductor layer 61 and the filler 62. The end faces of the solidified filler 62 may be polished by any method, such as chemical polishing or mechanical polishing, as necessary. This polishing preferably makes each end face of the filler 62 approximately flush with the surfaces of the electroplated layers 21c and 31c.

[0040] Furthermore, seed layers 21d, 31d, and electrolytic plated layers 21e, 31e are formed in this order on the electrolytic plated layers 21c, 31c and the filler 62. The seed layers 21d, 31d and the electrolytic plated layers 21e, 31e are formed, for example, by the same method as the seed layers 21b, 31b and the electrolytic plated layers 21c, 31c. A five-layer structure of a metal foil layer 21a, a seed layer 21b, an electrolytic plated layer 21c, a seed layer 21d, and an electrolytic plated layer 21e is formed on the first resin substrate 20. A five-layer structure of a metal foil layer 31a, a seed layer 31b, an electrolytic plated layer 31c, a seed layer 31d, and an electrolytic plated layer 31e is formed on the second resin substrate 30. Thereafter, as shown in FIG. 3F, the first internal conductor layer 21 and the second internal conductor layer 31 having the desired conductor pattern are formed by a subtractive method, such as etching using a mask on which wiring is drawn. At the same time, a first lid conductor 23 consisting of a seed layer 21d and an electrolytic plated layer 21e is formed on the end of the filler 62 facing the first resin substrate 20. A second lid conductor 33 consisting of a seed layer 31d and an electrolytic plated layer 31e is formed on the end of the filler 62 facing the second resin substrate 30.

[0041] 3G, an opening 25 is formed through the first resin substrate 20 in an area of ​​the first resin substrate 20 where the component 70 will be accommodated. The opening 25 is formed, for example, by irradiation with laser light. The laser light removes the resin of the first resin substrate 20 but does not remove the component placement conductor layer 24. Therefore, the component placement conductor layer 24 is exposed at the bottom of the opening 25.

[0042] As shown in FIG. 3H, component 70 is placed in opening 25. The non-electrode surface 72 of component 70 is placed on component placement conductor layer 24 exposed from opening 25. At this time, component 70 is fixed onto component placement conductor layer 24 by providing an adhesive layer between non-electrode surface 72 of component 70 and component placement conductor layer 24. Electrode surface 71 of component 70 is flush with the top surface of first resin substrate 20. Note that electrode surface 71 of component 70 may be located below the top surface of first resin substrate 20.

[0043] As shown in FIG. 3I, the gap between the opening 25 of the first resin substrate 20 and the component 70 is filled with potting resin 73. The potting resin 73 is preferably a thermosetting resin or a photocurable resin. The potting resin 73 is cured. The component 70 is fixed in the opening 25.

[0044] As shown in FIG. 3J, a first outer insulating layer 40 made of prepreg 40p is placed on the first internal conductor layer 21. At this time, metal foil 41a is placed on the first outer insulating layer 40. A second outer insulating layer 50 made of prepreg 50p is placed on the second internal conductor layer 31. Metal foil 51a is placed on the second outer insulating layer 50. The metal foil 41a, first outer insulating layer 40, intermediate substrate 2, first outer insulating layer 50, and metal foil 51a are all hot-pressed together. The prepreg 40p is cured to form the first outer insulating layer 40. The prepreg 50p is cured to form the second outer insulating layer 50.

[0045] In the first outer insulating layer 40, a hole 40a is formed that penetrates the metal foil 41a and the insulating layer of the first outer insulating layer 40, exposing the first lid conductor 23. Furthermore, a hole 40b is formed that penetrates the metal foil 41a and the insulating layer of the first outer insulating layer 40, exposing the electrode surface 71 of the component 70. In the second outer insulating layer 50, a hole 50a is formed that penetrates the insulating layer of the second outer insulating layer 50, exposing the second lid conductor 33. The hole opening is formed, for example, using a laser beam of carbon dioxide gas or the like. A seed film is formed on the metal foil 41a, the inner surface of the hole 40a, and the inner surface of the hole 40b by electroless plating or sputtering. A seed film is also formed on the metal foil 51a and the inner surface of the hole 50a. An electrolytic plating film is formed on the seed film by electrolytic plating using the seed film as a power supply layer. The electrolytic plating film fills the holes 40a, 40b, and 50a. 3K, a subtractive process using a mask with a patterned wiring is then used to form a first surface conductor layer 41 having a desired conductor pattern, which is composed of a seed layer 41b and an electrolytically plated layer 41c, and a second surface conductor layer 51, which is composed of a seed layer 51b and an electrolytically plated layer 51c. At the same time, a first via conductor 42, a connecting conductor 43, and a second via conductor 52 are formed. The first surface conductor layer 41, the first via conductor 42, the connecting conductor 43, the second surface conductor layer 51, and the second via conductor 52 may also be formed by a semi-additive process (MSAP) using metal foils 41a and 51a. A multilayer insulating layer 90 is formed, which includes a central insulating layer 10, a first resin substrate 20, a second resin substrate 30, a first outer insulating layer 40, and a second outer insulating layer 50. A through-hole conductor 91 is formed, which includes the first via conductor 42, a through-hole 60, and the second via conductor 52. A multilayer core substrate 100 is formed, which includes a multilayer insulating layer 90, a first surface conductor layer 41, a second surface conductor layer 51, and through-hole conductors 91.

[0046] Insulating layers 111, 121 and conductor layers 112, 122 are alternately formed on both sides of the multilayer core substrate 100. A first buildup layer 110 is formed on the first surface 100F of the multilayer core substrate 100. A second buildup layer 120 is formed on the second surface 100S. For example, a film-like insulating resin (e.g., epoxy resin) that does not contain a reinforcing material is thermocompression-bonded to the first surface 100F and the second surface 100S to form the insulating layer 111 on the first surface 100F side of the two insulating layers 111 and the insulating layer 121 on the second surface 100S side of the two insulating layers 121. Through holes are formed in the insulating layers 111 and 121, respectively, at locations where the via conductors 113 and 123 are to be formed, using, for example, a carbon dioxide laser. A seed film made of a conductor such as copper is formed on the inner walls of the through holes and on the surfaces of the insulating layers 111 and 121 by electroless plating, sputtering, or the like. A seed film is used as a power supply layer, and a plating resist having openings for forming a conductor layer is formed, and an electrolytic plated film is then formed in the openings by electrolytic plating. Conductor layers 112 and 122, each consisting of the seed layer and the electrolytic plated layer, as well as via conductors 113 and 123, are formed through resist stripping and etching. That is, the conductor layer 112 on the first surface 100F side of the two conductor layers 112 and the conductor layer 122 on the second surface 100S side of the two conductor layers 122 are formed through a semi-additive process (SAP) that does not use a metal foil. Together with these conductor layers 112 and 122, via conductor 113 penetrating insulating layer 111 on the first surface 100F side and via conductor 123 penetrating insulating layer 121 on the second surface 100S side are formed.

[0047] Furthermore, the insulating layer 111 and insulating layer 121 on the surface side are formed in the same manner as the insulating layer 111 on the first surface 100F and the insulating layer 121 on the second surface 100S. The conductor layers 112 and 122 on the surface side are formed in the same manner as the conductor layer 112 on the first surface 100F and the conductor layer 122 on the second surface 100S. The via conductors 113 and 123 that penetrate the insulating layers 111 and 121 on the surface side, respectively, are formed in the same manner as the via conductor 113 that penetrates the insulating layer 111 on the first surface 100F and the via conductor 123 that penetrates the insulating layer 121 on the second surface 100S. In this manner, the first buildup layer 110 and the second buildup layer 120 are formed. As a result, the wiring board 1 (FIG. 1) of the embodiment is obtained.

[0048] In the wiring board 1 of the embodiment, the opening 25 that houses the component 70 penetrates the first resin substrate 20. The opening 25 does not penetrate the multilayer core substrate 100. This reduces the amount of embedded resin 73 required to fill the gap between the inner surface of the opening 25 and the component 70. Furthermore, in the wiring board 1 of the embodiment, the through hole 60 penetrates the first resin substrate 20, the central insulating layer 10, and the second resin substrate 30. The length of the through hole 60 is shorter than in conventional wiring boards. Stability is ensured during signal transmission.

[0049] [Modification example 1] 4 is a cross-sectional view showing wiring board 1 of modified example 1. As shown in FIG. 4, in modified example 1, the gap between the inner surface of opening 25 and component 70 is filled with a part of first outer insulating layer 40. In modified example 1, the potting resin filling the gap between the inner surface of opening 25 and component 70 is a part of first outer insulating layer 40.

[0050] The manufacturing method of the wiring board 1 of Modified Example 1 is almost the same as the manufacturing method of the embodiment. However, in Modified Example 1, after the component 70 is placed in the opening 25 as shown in FIG. 3H, a prepreg 40p that will become the first outer insulating layer 40 is placed on the first internal conductor layer 21. A metal foil 41a is placed on the prepreg 40p. A prepreg 50p that will become the second outer insulating layer 50 is placed on the second internal conductor layer 31. A metal foil 51a is placed on the prepreg 50p. The metal foil 41a, prepreg 40p, intermediate substrate 2, prepreg 50p, and metal foil 51a are all hot-pressed together. At this time, a portion of the prepreg 40p penetrates and fills the gap between the inner surface of the opening 25 and the component 70. The prepreg 40p is cured to form the first outer insulating layer 40. The prepreg 50p is cured to form the second outer insulating layer 50. The gap between the inner surface of the opening 25 and the component 70 is filled with a portion of the first outer insulating layer 40. The component 70 is fixed within the opening 25. Thereafter, a first surface conductor layer 41, a first via conductor 42, a connecting conductor 43, a second surface conductor layer 51, and a second via conductor 52 are formed using the same method as in the manufacturing method of the embodiment. The subsequent manufacturing steps are the same as in the manufacturing method of the embodiment. A multilayer insulating layer 90 is formed. A through-hole conductor 91 is formed, including the first via conductor 42, the through hole 60, and the second via conductor 52. A multilayer core substrate 100 is formed, including the multilayer insulating layer 90, the first surface conductor layer 41, the second surface conductor layer 51, and the through-hole conductor 91. A first buildup layer 110 and a second buildup layer 120 are formed. A wiring board 1 of modified example 1 (Figure 4) is obtained.

[0051] [Modification example 2] The wiring board 1 of the modified example 2 is similar to the wiring board 1 of the embodiment. In the modified example 2, the manufacturing method of the wiring board 1 is different from that of the embodiment. In the modified example 2, the components 70 are arranged before the intermediate board 2a (see FIG. 5D) is manufactured. The manufacturing method of the wiring board 1 of the modified example 2 is shown in FIGS. 5A to 5D. FIGS. 5A to 5D are cross-sectional views.

[0052] As shown in FIG. 5A, a first resin substrate 20 is prepared, having a metal foil 21a formed on its upper surface (first surface) and a first internal conductor layer 22 formed on its lower surface (second surface).

[0053] As shown in FIG. 5B , the metal foil 21a of the first resin substrate 20 is removed by etching or other methods from the area where the component 70 will be accommodated. An opening 25 is formed through the first resin substrate 20 in the area where the component 70 will be accommodated. The opening 25 is formed, for example, by irradiating it with laser light. The laser light removes the resin of the first resin substrate 20 but does not remove the component placement conductor layer 24. Therefore, the component placement conductor layer 24 is exposed at the bottom of the opening 25. The component 70 is placed in the opening 25. The non-electrode surface 72 of the component 70 is placed on the component placement conductor layer 24 exposed from the opening 25. At this time, the component 70 is fixed to the component placement conductor layer 24 by providing an adhesive layer between the non-electrode surface 72 of the component 70 and the component placement conductor layer 24. The electrode surface 71 of the component 70 is flush with the top surface of the first resin substrate 20. Note that the electrode surface 71 of the component 70 may be located below the top surface of the first resin substrate 20. Furthermore, a potting resin 73 is filled into the gap between the opening 25 of the first resin substrate 20 and the component 70. The potting resin 73 is preferably a thermosetting resin or a photocurable resin. The potting resin 73 is hardened. The component 70 is fixed in the opening 25.

[0054] As shown in Fig. 5C, a first resin substrate 20, a prepreg 10p that will become the central insulating layer 10 after hardening, and a second resin substrate 30 are arranged. Specifically, the first resin substrate 20 containing the component 70 is arranged on the first surface 10pF side of the prepreg 10p that will become the central insulating layer 10, and the second resin substrate 30 is arranged on the second surface 10pS side of the prepreg 10p. The first internal conductor layer 22 faces the first surface 10pF. The second internal conductor layer 32 faces the second surface 10pS.

[0055] As shown in FIG. 5D, the first resin substrate 20, prepreg 10p, and second resin substrate 30 are heat-pressed together. The prepreg 10p is cured to form the central insulating layer 10. After pressing, the first internal conductor layer 22 is embedded in the first surface 10F of the central insulating layer 10. The second internal conductor layer 32 is embedded in the second surface 10S of the central insulating layer 10. As a result, an intermediate substrate 2a is formed, which includes the central insulating layer 10, the first resin substrate 20, and the second resin substrate 30. In the heat-pressing process, the pressure applied to the center in the pressure direction is concentrated and absorbed by the prepreg 10p, thereby ensuring good thickness uniformity. In other words, there is little risk of the first resin substrate 20 and the second resin substrate 30 losing their parallelism, resulting in a multilayer core substrate 100 with good flatness.

[0056] After this, through holes 60 are formed in the intermediate substrate 2a in the same manner as in the embodiment. First internal conductor layers 21 and second internal conductor layers 31 having desired conductor patterns are formed. First cover conductors 23 and second cover conductors 33 are formed (see FIG. 3I).

[0057] As in the embodiment, a first outer insulating layer 40 and a second outer insulating layer 50 are formed (see FIG. 3J). A first surface conductor layer 41, a first via conductor 42, a connecting conductor 43, a second surface conductor layer 51, and a second via conductor 52 are formed (see FIG. 3K). A multilayer insulating layer 90 is formed, including a central insulating layer 10, a first resin substrate 20, a second resin substrate 30, the first outer insulating layer 40, and the second outer insulating layer 50. A through-hole conductor 91 is formed, including a first via conductor 42, a through-hole 60, and a second via conductor 52. A multilayer core substrate 100 is formed, including the multilayer insulating layer 90, the first surface conductor layer 41, the second surface conductor layer 51, and the through-hole conductor 91.

[0058] A first buildup layer 110 is formed on a first surface 100F of the multilayer core substrate 100. A second buildup layer 120 is formed on a second surface 100S. As a result, a wiring board 1 (FIG. 1) of the embodiment is obtained. [Explanation of symbols]

[0059] 1: Wiring board 10: Central insulating layer 20: First resin substrate 21: First internal conductor layer 22: First internal conductor layer 23: First cover conductor 24: Conductive layer for component placement 25:Aperture 30: Second resin substrate 31: Second internal conductor layer 32: Second internal conductor layer 33: Second cover conductor 40: First outer insulation layer 41: First surface conductor layer 42: First via conductor 43: Connecting conductor 50: Second outer insulation layer 51: Second surface conductor layer 52: Second via conductor 60:Through hole 60a: through hole 61: Inner wall conductor layer 62: Filling 70: Parts 71: Electrode surface 72: Non-electrode surface 73: Embedding resin 90: Multi-layer insulation layer 91:Through-hole conductor 100: Multilayer core board 110: First build-up layer 120: Second build-up layer

Claims

1. A wiring board having a multilayer core substrate and a build-up layer formed on the multilayer core substrate by an insulating layer and a conductor layer, The multilayer core substrate includes a multilayer insulating layer, a through-hole conductor, a surface conductor layer, and a connecting conductor, and components are disposed thereon; The multilayer insulating layer comprises a central insulating layer, a resin substrate, and an outer insulating layer; a first resin substrate is formed on a first surface of the central insulating layer, a first outer insulating layer is formed on the first resin substrate, and a first surface conductor layer is formed on the first outer insulating layer; a second resin substrate is formed on a second surface of the central insulating layer, a second outer insulating layer is formed on the second resin substrate, and a second surface conductor layer is formed on the second outer insulating layer; the through-hole conductor comprises a through-hole, a first via conductor, and a second via conductor; the through hole is a hole that penetrates the first resin substrate, the central insulating layer, and the second resin substrate, an inner wall conductor layer is formed on the inner wall of the hole, a first lid conductor is formed on the first resin substrate, and a second lid conductor is formed on the second resin substrate; the first via conductor is formed in a hole that penetrates the first outer insulating layer and exposes the first lid conductor, and connects the first surface conductor layer and the first lid conductor; the second via conductor is formed in a hole that penetrates the second outer insulating layer and exposes the second lid conductor, and connects the second surface conductor layer and the second lid conductor; the component comprises an electrode surface and a non-electrode surface opposite the electrode surface; An opening is formed through the first resin substrate, the non-electrode surface of the component is positioned on the first surface of the central insulating layer exposed from the opening, and the electrode surface is connected by the connecting conductor of the first outer insulating layer.

2. 2. The wiring board according to claim 1, wherein the electrode surface of the component is located on the same plane as the end of the through hole on the side of the first resin substrate.

3. 2. The wiring board according to claim 1, wherein a gap between the inner surface of the opening and the component is filled with a potting resin.

4. 4. The wiring board according to claim 3, wherein the potting resin is a part of the first outer insulating layer.

5. 2. The wiring board according to claim 1, wherein the through holes are filled with a filler containing a resin.

6. 2. The wiring board according to claim 1, wherein the central insulating layer, the first resin substrate, the second resin substrate, the first outer insulating layer, and the second outer insulating layer each include a core material.

7. 2. The wiring board of claim 1, An internal conductor layer is formed in the through hole of the multilayer core substrate.

8. 8. The wiring board of claim 7, the internal conductor layers are a first internal conductor layer and a second internal conductor layer, The first internal conductor layer is formed on the central insulating layer side of the first resin substrate and / or the second internal conductor layer is formed on the central insulating layer side of the second resin substrate.

9. 9. The wiring board of claim 8, The first inner conductor layer or the second inner conductor layer is embedded in the central insulating layer.

10. 9. The wiring board according to claim 8, wherein the first internal conductor layer has a component placement conductor circuit corresponding to an area in which the component is to be placed.

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