MEMORY SYSTEM AND CONTROL METHOD - Patent application

Abstract

This provides a memory system that efficiently performs data writing operations. [Solution] The information processing system 1 comprises a host and a memory system. The controller of the memory system, upon receiving a first write command from the host, begins receiving the first data associated with the first write command from the host. The controller selects the first page from among multiple physical pages of the NAND flash memory, from pages on which the second data has already been written and which have not yet undergone read verification. The controller performs read verification on the selected first page. The controller writes the received first data to the second page included in the destination block among multiple physical blocks.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to techniques for controlling non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread.

[0003] When writing data to the nonvolatile memory, the controller of the memory system executes a read-and-verify process to determine whether the data written to the nonvolatile memory can be read normally.

[0004] In a memory system, the read verify is performed, which increases the time required for the data write process.

[0005] Therefore, it is necessary to efficiently execute the data writing process. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2023 / 0134281 [Patent Document 2] US Patent Application Publication No. 2021 / 0295941 [Patent Document 3] US Patent Application Publication No. 2022 / 0139466 Summary of the Invention [Problem to be solved by the invention]

[0007] An embodiment of the present invention provides a memory system that can efficiently perform data write operations. [Means for solving the problem]

[0008] According to an embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of physical blocks, each of which is a unit of a data erase operation. The controller is electrically connected to the nonvolatile memory. The controller is configured to write data to the nonvolatile memory and to perform read verification to determine whether the data written in the nonvolatile memory can be read normally. Each of the plurality of physical blocks includes a plurality of physical pages, each of which is a unit of data writing and reading. In response to receiving a first write command from the host, the controller begins receiving first data associated with the first write command. The controller selects a first page from among the plurality of physical pages to which second data has already been written and to which read verification has not yet been performed. The controller performs read verification on the selected first page. The controller writes the received first data to a second page included in a write destination block among the plurality of physical blocks. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a memory chip included in the memory system according to the embodiment. [Figure 3] FIG. 2 is a diagram showing an example of a superblock managed in the memory system according to the embodiment. [Figure 4] FIG. 2 is a diagram showing an example of the functional configuration of a CPU included in the memory system according to the embodiment. [Figure 5] FIG. 10 is a diagram illustrating data transfer accompanying a data write process in a first comparative example. [Figure 6]FIG. 10 is a diagram illustrating data transfer accompanying a data write process in a second comparative example. [Figure 7] FIG. 10 is a diagram showing a write destination block in a second comparative example. [Figure 8] FIG. 2 is a diagram showing a first example of data transfer accompanying a data write process executed in the memory system according to the embodiment. [Figure 9] FIG. 2 is a diagram showing a write destination block and an active block in the memory system according to the embodiment. [Figure 10] FIG. 11 is a diagram illustrating data transfer accompanying a data write process in a third comparative example. [Figure 11] FIG. 10 is a diagram showing a second example of data transfer accompanying a data write process executed in the memory system according to the embodiment. [Figure 12] FIG. 10 is a diagram showing a third example of data transfer accompanying a data write process executed in the memory system according to the embodiment. [Figure 13] FIG. 10 is a sequence diagram showing the procedure of a data write process executed in an information processing system including a memory system according to an embodiment. [Figure 14] 10 is a flowchart showing the procedure of a data write process executed in the memory system according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment will be described with reference to the drawings. The configuration of an information processing system including a memory system according to an embodiment will be described below. Fig. 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system 3 according to an embodiment.

[0011] The information processing system 1 includes a host (host device) 2 and a memory system 3.

[0012] The host 2 is an information processing device configured to control the memory system 3. Examples of the host 2 include a personal computer, a server computer, a mobile terminal, or an in-vehicle device.

[0013] The memory system 3 is a semiconductor storage device configured to write data to and read data from a nonvolatile memory. The memory system 3 may be realized as, for example, an SD card or a solid-state drive (SSD).

[0014] Communication between the host 2 and the memory system 3 is performed via a bus 7. The bus 7 is a transmission path that connects the host 2 and the memory system 3. The bus 7 is, for example, a PCI express TM (PCIe TM The PCIe bus is a full-duplex transmission path. A full-duplex transmission path includes both a transmission path that sends data and input / output (I / O) commands from host 2 to memory system 3, and a transmission path that sends data and responses from memory system 3 to host 2. I / O commands are commands for writing data to or reading data from non-volatile memory. Examples of I / O commands include write commands and read commands.

[0015] A write command is a command that requests the writing of data to memory system 3. A write command includes information indicating the starting logical address, the size of the data associated with the write command (write data), and a data pointer. The starting logical address is the starting logical address of the logical address range corresponding to the write data. For example, a Logical Block Address (LBA) is used for this logical address. The size of the write data is represented, for example, by the number of LBAs (number of sectors) contained in the logical address range corresponding to the write data. The data pointer is the address indicating the storage location in memory 22 of host 2 where the write data is stored.

[0016] A read command is a command that requests reading of data from the memory system 3. The read command includes information indicating the starting logical address, the size of the data to be read (read data), and a data pointer. The starting logical address is the first logical address of the logical address range corresponding to the read data. The size of the read data is represented by the number of LBAs (number of sectors) included in the logical address range corresponding to the read data. The data pointer is an address that indicates the storage location in the memory 22 of the host 2 to which the read data should be transferred.

[0017] A standard for the logical interface connecting host 2 and memory system 3 is, for example, NVM express. TM (NVMe TM ) standard is used. In the NVMe standard interface, communication between the host 2 and the memory system 3 is performed using a pair of queues including at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ). This pair of queues is called a submission queue / completion queue pair (SQ / CQ pair).

[0018] When the host 2 issues an I / O command to the memory system 3, it stores the I / O command to be issued in a submission queue (SQ). The memory system 3 then receives the I / O command by accessing the submission queue (SQ) and fetching the I / O command. When processing related to the received command is completed, the memory system 3 stores a completion response corresponding to the processed command in a completion queue (CQ). The completion response includes, for example, information indicating that processing related to the corresponding command has been completed. The host 2 recognizes that processing related to the issued command has been completed by processing the completion response stored in the completion queue (CQ).

[0019] Next, we will describe an example configuration for host 2.

[0020] Host 2 includes a processor 21 and memory 22. The processor 21 and memory 22 are connected via a bus 20.

[0021] The processor 21 is, for example, a Central Processing Unit (CPU). The processor 21 executes software (host software) loaded into the memory 22. The host software is loaded into the memory 22 from the memory system 3 or another storage device connected to the host 2. The host software includes an operating system, a file system, a device driver, an application program, and the like. The processor 21 may also execute multiple applications.

[0022] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is, for example, a random access memory such as a dynamic random access memory (DRAM). A part of the storage area of ​​the memory 22 is used as a data buffer. The data buffer stores write data to be written to the memory system 3 by the host 2 or read data transferred from the memory system 3.

[0023] Next, we will describe an example configuration of memory system 3.

[0024] The memory system 3 includes a controller 4, NAND flash memory 5, and DRAM 6.

[0025] The controller 4 is a memory controller that controls the NAND flash memory 5. The controller 4 may be realized by a circuit such as a System-on-a-chip (SoC). The controller 4 is electrically connected to the NAND flash memory 5.

[0026] The NAND flash memory 5 is a non-volatile semiconductor memory. The NAND flash memory 5 includes a plurality of NAND chips. A NAND chip is also called, for example, a memory chip, flash die, or memory die. Each NAND chip includes a memory cell array having a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a two-dimensional flash memory or a three-dimensional flash memory.

[0027] DRAM 6 is a volatile memory. The memory area of ​​DRAM 6 is used, for example, to store information for managing the memory system 3. In addition, a portion of the memory area of ​​DRAM 6 may be used to temporarily store data to be written to the NAND flash memory 5, or data read from the NAND flash memory 5.

[0028] The controller 4 includes a host interface circuit (I / F) 41, a CPU 42, static RAM (SRAM) 43, a direct memory access controller (DMAC) 44, an ECC circuit 45, a NAND interface circuit (I / F) 46, and a DRAM interface circuit (I / F) 47. The host I / F 41, CPU 42, SRAM 43, DMAC 44, ECC circuit 45, NAND I / F 46, and DRAM I / F 47 are interconnected via an internal bus 40.

[0029] The host I / F 41 is an interface circuit configured to execute communication with the host 2. The host I / F 41 is, for example, a PCIe controller. The host I / F 41 receives various commands from the host 2. These commands are, for example, NVMe commands defined in the NVMe standard.

[0030] The CPU 42 is a processor. The CPU 42 controls the host I / F 41, the SRAM 43, the DMAC 44, the ECC circuit 45, the NAND I / F 46, and the DRAM I / F 47. Upon startup of the memory system 3, the CPU 42 loads a control program (firmware) from the NAND flash memory 5 or a ROM (not shown) into the SRAM 43. The CPU 42 then executes the loaded firmware to perform various processes. This firmware may be loaded into the DRAM 6 instead of the SRAM 43. The CPU 42 can execute command processing and the like to process various commands from the host 2. The operation of the CPU 42 is controlled by the firmware described above. Some or all of the command processing may be executed by dedicated hardware within the controller 4.

[0031] The SRAM 43 is a volatile memory. A part of the storage area of ​​the SRAM 43 is used as a working area for the CPU 42. Another part of the storage area of ​​the SRAM 43 can be used as a data buffer for temporarily storing data to be written to the NAND flash memory 5 or data read from the NAND flash memory 5.

[0032] DMAC44 is a circuit that performs direct memory access (DMA). DMAC44 performs data transfer between the host 2's memory 22 and SRAM43 or DRAM6.

[0033] The ECC circuit 45 executes encoding or decoding. The ECC circuit 45 executes encoding when data is written to the NAND flash memory 5. In encoding, the ECC circuit 45 adds a redundant code (parity) to the data to be written to the NAND flash memory 5. The redundant code is, for example, an error correction code (ECC). In addition, when data is read from the NAND flash memory 5, the ECC circuit 45 executes decoding. In decoding, the ECC circuit 45 executes error correction on the data read from the NAND flash memory 5. When executing error correction, the ECC circuit 45 uses the ECC added to this data.

[0034] The NAND I / F46 is a circuit that controls the NAND flash memory 5 under the control of the CPU 42. The NAND I / F46 is electrically connected to multiple NAND chips contained in the NAND flash memory 5.

[0035] Multiple NAND chips can operate independently. Therefore, the NAND chips function as a unit capable of operating in parallel. The NAND I / F 46 is connected to each of channels ch1 and ch2. The NAND I / F 46 is connected to one or more NAND chips via the corresponding channels. FIG. 1 illustrates a case in which one NAND chip is connected to each of channels ch1 and ch2. In this case, the NAND I / F 46 is connected to NAND chip #1 via channel ch1. The NAND I / F 46 is connected to NAND chip #2 via channel ch2. Here, the case in which the number of NAND chips in the NAND flash memory 5 is two and the number of channels is two has been described, but each may have three or more channels. Furthermore, two or more NAND chips may be connected to one channel.

[0036] In the configuration of the NAND flash memory 5 shown in Figure 1, the controller 4 can access NAND chips #1 and #2 in parallel using two channels. Therefore, the controller 4 can perform parallel data writing or reading operations on the two NAND chips. In this case, the number of parallel accesses is 2. Note that each of the NAND chips #1 and #2 may have a multi-plane configuration with multiple planes. For example, if each of the NAND chips #1 and #2 contains 4 planes, the controller 4 can perform parallel data writing or reading operations on up to 8 planes. In this case, the number of parallel accesses is 8.

[0037] Furthermore, this scenario assumes that the communication speed between host 2 and controller 4, performed by host I / F 41, is slower than the communication speed between controller 4 and NAND flash memory 5, performed by NAND I / F 46. In this case, when NAND I / F 46 sends data to NAND flash memory 5 based on a write command, it waits for the data to accumulate on controller 4.

[0038] The DRAM I / F 47 is a circuit configured to control the DRAM 6 under the control of the CPU 42 .

[0039] A portion of the memory area of ​​DRAM 6 may be used to store information for managing the memory system 3. For example, DRAM 6 includes an L2P table 61, a block management table 62, an active block list 63, a free block list 64, and a read-verify management information table 65.

[0040] The L2P table 61 is a table that manages the correspondence between logical addresses and physical addresses. A physical address is an address that indicates a storage location in the NAND flash memory 5. A physical address is also called a Physical Block Address (PBA) or a Memory Block Address (MBA). The L2P table 61 manages the correspondence between LBAs and PBAs, for example, on a sector-by-sector basis.

[0041] The block management table 62 is a table for managing physical blocks and superblocks in the memory system 3. The configuration of superblocks will be described later. The block management table 62 includes, for example, information on bad blocks among the physical blocks in the memory system 3, and information on the multiple physical blocks that make up each superblock. A bad block is a block from which data cannot be read or written normally. A bad block may also be called a bad block.

[0042] The active block list 63 is a list of superblocks that contain at least valid data. Valid data is data stored in a memory location indicated by a physical address associated with a logical address. For example, data stored in a memory location indicated by a PBA referenced by the L2P table 61 is valid data. Valid data is also data that may be read by the host 2. The superblocks managed in the active block list 63 are superblocks that are assigned as write destination blocks or superblocks for which writing has been completed, and that store one or more valid data. The superblocks managed in the active block list 63 may be referred to as active blocks, for example.

[0043] The free block list 64 is a list of superblocks that store only invalid data. Invalid data is data stored in a storage location indicated by a physical address that is not associated with a logical address. For example, data stored in a storage location indicated by a PBA that is not referenced by the L2P table 61 is invalid data. Invalid data is also data that can no longer be read from host 2. Superblocks managed in the free block list 64 are superblocks that can be rewritten with new data by performing a data erasure process. Superblocks managed in the free block list 64 are, for example, called free blocks. Free blocks are superblocks that can be used again to write data.

[0044] The read verification management information table 65 is a table that manages read verification management information. Read verification management information is information that shows the progress of read verification performed on superpages to which data has been written. The structure of superpages will be described later. For example, the read verification management information is the superblock number that indicates the superblock to which read verification is performed. Alternatively, the read verification management information may be the superblock number that indicates the superblock to which read verification is performed and the superpage number that indicates the superpage to which the next read verification will be performed.

[0045] Next, an example of the internal configuration of a NAND chip will be described. Fig. 2 is a diagram showing an example of the configuration of a NAND chip included in memory system 3 according to the embodiment. In Fig. 2, NAND chip #1 is used as an example for explanation, but NAND chip #2 may also have a similar configuration to NAND chip #1.

[0046] NAND chip #1 includes four planes (plane PLN1, plane PLN2, plane PLN3, and plane PLN4) and four peripheral circuits corresponding to each of the four planes (peripheral circuit 50-1, peripheral circuit 50-2, peripheral circuit 50-3, and peripheral circuit 50-4).

[0047] Each of the planes PLN1, PLN2, PLN3, and PLN4 includes a memory cell array. The memory cell array of each of the planes PLN1, PLN2, PLN3, and PLN4 includes physical blocks BLK1 to BLKx. Each of the physical blocks is a unit of a data erase operation. Each of the physical blocks BLK1 to BLKx is also referred to as a flash block or a memory block. Each of the physical blocks BLK1 to BLKx includes pages P1 to Py. Each of the pages P1 to Py is a unit of a data write operation and a data read operation. Each of the pages P1 to Py includes, for example, a plurality of memory cells connected to the same word line.

[0048] Each of the peripheral circuits 50-1, 50-2, 50-3, and 50-4 controls the memory cell array of the corresponding plane. The peripheral circuit 50-1 corresponds to the plane PLN1. The peripheral circuit 50-2 corresponds to the plane PLN2. The peripheral circuit 50-3 corresponds to the plane PLN3. The peripheral circuit 50-4 corresponds to the plane PLN4. Each of the peripheral circuits 50-1, 50-2, 50-3, and 50-4 includes, for example, a row decoder, a column decoder, a sense amplifier, and a page buffer. Each of the peripheral circuits 50-1, 50-2, 50-3, and 50-4 performs a data write operation, a data read operation, or a data erase operation on the memory cell array of the corresponding plane in response to receiving an address and a command from the NAND interface 46.

[0049] Next, a description will be given of superblocks and superpages. FIG. 3 is a block diagram showing an example of the configuration of a superblock in a memory system 3 according to an embodiment. The memory system 3 configures a superblock, which is a collection of physical blocks. The collection of physical blocks that configure a superblock is, for example, a collection of physical blocks selected one by one from planes that can operate in parallel. A superblock is also referred to as a logical block or a block group. A superpage is a collection of physical pages of each of the multiple physical blocks that configure a superblock. A superpage is also referred to as a logical page or a page group. Here, a description will be given of a case where a superblock is configured by physical blocks selected one by one from each of the four planes included in NAND chip #1.

[0050] One superblock includes a total of four physical blocks, one selected from each plane of NAND chip #1. If the NAND flash memory 5 has multiple NAND chips that can operate in parallel, one superblock may also be configured to include physical blocks selected one from each plane of other NAND chips.

[0051] 3 illustrates one superblock #5 including four physical blocks, where superblock #5 is composed of physical block BLK5 of planes PLN1, PLN2, PLN3, and PLN4 of NAND chip #1.

[0052] The controller 4 can execute data erasure processing in units of superblocks. That is, the controller 4 executes data erasure processing on superblock #5 when all data in superblock #5 is invalid data. In the data erasure processing on superblock #5, a data erasure operation is executed on each of the physical blocks BLK5 included in superblock #5.

[0053] Furthermore, the controller 4 can perform data writing operations in parallel on multiple physical blocks BLK5 that constitute the superblock #5. In this data writing operation, the controller 4 writes data to a superpage, which is a set of physical pages, one selected from each of the multiple physical blocks BLK5. At this time, the controller 4 can write parity, which is used in data recovery when data is read, to at least one of the multiple physical pages that constitute the superpage.

[0054] 3, a set of physical pages #2 of each of the physical blocks that make up superblock #5 constitutes superpage #2. For example, parity for restoring data stored in superpage #2 can be written to physical page 2 of physical block BLK5 of plane PLN4.

[0055] Next, a description will be given of an example of the functional configuration of the CPU 42. Fig. 4 is a block diagram showing an example of the functional configuration of the CPU 42 included in the memory system 3 according to the embodiment.

[0056] The CPU 42 executes firmware to function as a write control circuit 421 and a read verify control circuit 422. Some or all of these functions may be realized by dedicated hardware within the controller 4.

[0057] The write control circuit 421 controls the process of writing data to the NAND flash memory 5. In response to receiving a write command from the host 2, the write control circuit 421 executes the process of writing data.

[0058] In the data write process, the write control circuit 421 first receives from the host 2 the data and LBA associated with the write command received from the host 2.

[0059] The write control circuit 421 then transfers the data received from the host to the NAND flash memory 5 and instructs it to write the data.

[0060] Here, the write control circuit 421 receives data from the host 2 via the host I / F 41. The write control circuit 421 also transmits data to the NAND flash memory 5 via the NAND I / F 46. Therefore, if the data transfer speed at the NAND I / F 46 is faster than the data transfer speed at the host I / F 41, the NAND I / F 46 transfers data to the NAND flash memory 5 each time the data size for the write unit is completed, while waiting for the data to be received at the host I / F 41. In other words, a state of waiting to receive data occurs at the NAND I / F 46.

[0061] Then, when the data is written to the NAND flash memory 5, the write control circuit 421 updates the L2P table 61 so that the LBA specified by the received write command corresponds to the physical address indicating the storage location in the NAND flash memory 5 where the data is written. Then, the write control circuit 421 transmits to the host 2 a completion response corresponding to the processed write command.

[0062] The read verify control circuit 422 is a circuit that controls read verify in the memory system 3. In read verify, the read verify control circuit 422 determines whether the data written in the NAND flash memory 5 can be read normally.

[0063] In read verify, first, the read verify control circuit 422 selects a superpage to be read verified from among superpages to which data has already been written. The read verify control circuit 422 selects the superpage to be read verified based on, for example, read verify management information. Furthermore, if the memory system 3 uses physical pages instead of superpages as the write unit, the read verify control circuit 422 may select a physical page as the read verify target.

[0064] The read verify control circuit 422 reads data from the selected page to be read verified. The ECC circuit 45 then performs a decoding process on the read data. If the data is not read correctly and the read data contains more error bits than a predetermined number, the ECC circuit 45 performs error correction on the data, for example, using parity stored in the NAND flash memory 5. The parity may be stored in a free storage area of ​​the SRAM 43 or the DRAM 6 instead of being stored in the NAND flash memory 5.

[0065] Next, the data write process in the first comparative example will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining data transfer accompanying the data write process in the first comparative example. In the first comparative example, it is assumed that read verify is not executed in the data write process.

[0066] The transfer rate of the host I / F is 100MB / s. The transfer rate of the NAND I / F is 800MB / s. In other words, the transfer rate of the NAND I / F is 8 times the transfer rate of the host I / F.

[0067] Also, assume that the write destination superblock is made up of four physical blocks, and therefore the write destination superpage is made up of four physical pages.

[0068] The NAND flash memory 5 executes TLC writing, which writes 3 bits of data per memory cell. At this time, if the size of data written per page is 16 KB, 48 KB (16 KB × 3) of data is TLC written per physical page.

[0069] Therefore, data is written in parallel to the four physical pages that make up the superpage, so at least 192 KB (48 KB x 4) of data is associated with one write command.

[0070] The NAND interface sends 16KB of write data to the NAND flash memory when the amount of write data received from the host reaches 16KB. In other words, the NAND interface sends write data in page sizes. Because the transfer rate of the NAND interface is faster than that of the host interface, the NAND interface must wait for the size of the write data received from the host interface to reach 16KB before sending the next write data to the NAND flash memory.

[0071] NAND flash memory performs data writing after 12 transfers of 16KB of data have been performed and 192KB of data has been received. The period during which data writing is being performed is represented by Wait. While data writing is being performed, the NAND interface cannot send data to the NAND flash memory. During data writing, program operations are executed in parallel for the four physical pages contained in the superpage.

[0072] Once the host interface has finished transferring the write data associated with the first write command, it begins transferring the write data associated with the second write command. Furthermore, in NAND flash memory, even while the program operation corresponding to the first write command is being executed, the host interface continues to receive the data associated with the next write command.

[0073] When the program operation corresponding to the first write command is completed, the NAND I / F starts transferring the write data associated with the second write command to the NAND flash memory. Because several pages of write data are received from the host while the program operation is being executed, the NAND I / F can continuously transmit several pages of write data to the NAND flash memory after the program operation is completed.

[0074] For the data associated with the next write command, when the write data received from the host reaches 16 KB, the NAND I / F transfers the 16 KB of write data to the NAND flash memory.

[0075] Then, when 192 KB of write data is received as a result of repeated transfer of 16 KB of write data, the NAND flash memory executes a program operation to write the received data.

[0076] In this way, if the transfer rate of the NAND I / F is faster than the transfer rate of the host I / F, it is necessary to wait until the write data reaches 16 KB in the NAND I / F.

[0077] Next, it is assumed that a read verify is executed to determine whether or not the data written to the NAND flash memory can be read normally.

[0078] In the second comparative example, immediately after data is written to the NAND flash memory, a read verify is executed on the written data. Figure 6 is a diagram illustrating data transfer accompanying the data write process in the second comparative example.

[0079] In Figure 6, similar to Figure 5, two write commands are sent from the host to the memory system.

[0080] First, the controller receives 192KB of data associated with the first write command via the host interface. Then, each time the received data reaches 16KB, the controller transfers the data to the NAND flash memory via the NAND interface. When the received data reaches 192KB, the NAND flash memory executes a program operation to write the data.

[0081] Once the program operation in the NAND flash memory is complete, the controller performs a read-verify operation (RV1). At this time, the controller selects the superpage to which data was written by the previous program operation as the target for read-verify operation (RV1). In other words, data written to the NAND flash memory is read-verified by the controller immediately after the program operation.

[0082] In ReadVerify RV1, the controller reads the data written based on the first write command from the NAND flash memory. The controller then determines whether or not the read data is error-correctable.

[0083] Furthermore, once the host interface has completed transferring the write data associated with the first write command to the NAND flash memory, it begins transferring the write data associated with the second write command to the NAND flash memory. Therefore, while the program operation and read verification corresponding to the first write command are being performed in the NAND flash memory, the host interface is receiving the data associated with the next write command.

[0084] Once the NAND interface completes the program operation and read verification corresponding to the first write command, it begins transferring the write data associated with the second write command to the NAND flash memory. Since several pages of write data are received from the host while the program operation and read verification are being performed, the NAND interface can send several pages of write data sequentially to the NAND flash memory after the read verification is complete.

[0085] For the data associated with the next write command, when the write data received from the host reaches 16 KB, the NAND I / F transfers the 16 KB of write data to the NAND flash memory.

[0086] Then, when 192 KB of write data is received as a result of repeated transfer of 16 KB of write data, the NAND flash memory executes a program operation to write the received data.

[0087] Once the program operation in the NAND flash memory is complete, the controller performs a read-verify RV2. At this time, the controller selects the superpage to which data was written by the previous program operation as the target for read-verify RV2. In other words, data written to the NAND flash memory undergoes read-verification by the controller immediately after the program operation.

[0088] In ReadVerify RV2, the controller reads the data written based on the second write command from the NAND flash memory. The controller then determines whether the read data is error-correctable.

[0089] In this way, when read verify is executed immediately after the program operation, the timing at which the process corresponding to the write command is completed is the timing at which read verify is completed. In the second comparative example, the timing at which read verify RV2 is completed is the timing at which the process corresponding to the write command is completed.

[0090] Therefore, the processing corresponding to the write command in the second comparative example is longer than the processing corresponding to the write command in the first comparative example by the processing time of read verify RV2.

[0091] In recent years, there have been an increasing number of opportunities to handle large amounts of data. This has led to a demand for faster data writing speeds. However, delays in data writing time, such as those described in the second comparative example, cannot be ignored.

[0092] The relationship between the superpage where the data write process is executed and the superpage that is the target of the read verify will be described with reference to Fig. 7. Fig. 7 is a diagram showing a write destination block in the second comparative example.

[0093] 7 shows superblock #0, which is the write destination block. Here, superblock #0 is composed of four physical blocks, one selected from each of the four planes. Of the multiple logical pages in the write destination block, superpages #1 to #4 are superpages to which data has already been written.

[0094] Here, it is assumed that the controller receives from the host a write command for writing write data of a size corresponding to one superpage.

[0095] At this time, the controller selects superpage #5 as the next superpage to write to. When the controller receives the data to be written to superpage #5, it writes the data to superpage #5.

[0096] Then, when the controller has completed writing data to superpage #5, it selects superpage #5 and executes read verify.

[0097] The controller reads data from superpage #5 to determine whether error correction is possible. If the number of error bits in the read data exceeds a threshold, the controller determines that error correction is not possible. In this case, the controller uses parity or other methods to restore the read data.

[0098] In contrast to this, in the memory system 3 according to the embodiment, after receiving a write command and before transferring data to the NAND flash memory 5, read verification is executed.

[0099] 8 is a diagram showing a first example of data transfer accompanying a data write process executed in the memory system 3 according to the embodiment. Here, as in the first and second comparative examples described above, it is assumed that the transfer rate of the host I / F 41 is 100 MB / s and the transfer rate of the NAND I / F 46 is 800 MB / s.

[0100] The host 2 sends two write commands to the memory system 3 .

[0101] In response to receiving the first write command from the host 2, the host I / F 41 of the controller 4 starts receiving the write data associated with the received write command.

[0102] Furthermore, in response to receiving the first write command W1, the read verify control circuit 422 of the controller 4 starts a read verify RV1. The superpage into which data is to be written based on the first write command W1 is assumed to be superpage L1.

[0103] In this read verify RV1, the read verify control circuit 422 selects a page to be read verified from among the superpages to which writing has already been completed. For example, the read verify control circuit 422 selects, as the target of read verify, a superpage corresponding to the same superpage number as superpage L1 from among the multiple superpages in the previous write destination block. Alternatively, the read verify control circuit 422 selects, as the target of read verify, an arbitrary superpage from among the active blocks or write destination blocks registered in the active block list 63.

[0104] The controller 4 reads data from the selected superpage that is the target of read verification. The size of the data to be read is, for example, 192 KB. The ECC circuit 45 of the controller 4 determines whether the read data is error correctable.

[0105] When the read verify RV1 is completed, the NAND I / F 46 of the controller 4 starts transferring the write data associated with the first write command to the NAND flash memory 5. Because several pages of write data are received from the host 2 while the read verify RV1 is being executed, the NAND I / F 46 can continuously transmit several pages of write data to the NAND flash memory 5 after the read verify RV1 is completed.

[0106] In this way, the controller 4 executes read verify RV1 while data is being transferred from the host 2 to the controller 4. In other words, it is possible to make the execution period of read verify RV1 overlap with the period during which data is transferred from the host 2 to the controller 4. This makes it possible to avoid the time required to process the first write command becoming longer even when read verify RV1 is executed.

[0107] Then, when the data received from the host 2 reaches 16KB, the write control circuit 421 instructs the NAND flash memory 5 to write the data. The NAND I / F 46 transfers 16KB of write data to the NAND flash memory 5. After the transfer of 16KB of write data is repeated, the NAND flash memory 5 receives 192KB of write data and executes a program operation to write the received data.

[0108] Then, once the program operation corresponding to the first write command is completed, the read verify control circuit 422 starts read verify RV2 corresponding to the second write command.

[0109] In this read-verify RV2, the read-verify control circuit 422 selects the page to be read-verified from the superpages that have already been written to, similar to read-verify RV1. For example, the read-verify control circuit 422 selects the superpage to be read-verified that corresponds to the same superpage number as the superpage to which data should be written based on the second write command in the previous write destination block.

[0110] The controller 4 reads data from the selected superpage that is the target of read verification. The size of the data to be read is, for example, 192 KB. The ECC circuit 45 of the controller 4 determines whether the read data is error correctable.

[0111] Furthermore, once the transfer of the write data associated with the first write command is complete, the host I / F41 begins transferring the write data associated with the second write command. Therefore, even while the program operation and read-verify RV2 corresponding to the first write command are being executed in the NAND flash memory 5, the host I / F41 is still receiving the data associated with the next write command.

[0112] When read verify RV2 is completed, the write control circuit 421 instructs the NAND flash memory 5 to write data. Then, the NAND I / F 46 starts transferring the write data associated with the second write command to the NAND flash memory 5. Because several pages of write data have been received from the host 2 while read verify RV2 is being executed, the NAND I / F 46 can continuously transmit several pages of write data to the NAND flash memory 5 after read verify RV2 is completed.

[0113] When the data received from the host 2 reaches 16 KB, the NAND I / F 46 transfers 16 KB of write data to the NAND flash memory 5. When 192 KB of write data is received as a result of repeated transfer of 16 KB of write data, the NAND flash memory 5 executes a program operation to write the received data.

[0114] In this way, the controller 4 also executes read verify RV2 while data is being transferred from the host 2 to the controller 4. In other words, it is possible to make the execution period of read verify RV2 overlap with the period during which data is transferred from the host 2 to the controller 4. This also makes it possible to avoid the processing time for the second write command being longer even if read verify RV2 is executed.

[0115] In this way, in the memory system 3 according to the embodiment, by performing read verify immediately before executing the data write process, it is possible to prevent the time required for the data write process from becoming long.

[0116] The relationship between the superpage on which data writing is performed and the superpage targeted for read verification will be explained with reference to Figure 9. Figure 9 is a diagram showing the destination block and active block in the memory system 3 according to this embodiment.

[0117] Superblock #0 is the block to write to. Within superblock #0, superpages #0 through #4 are superpages that already have data written to them. Superpage #5 of superblock #0 is the superpage to which data should be written next.

[0118] Superblock #1 is the block that was previously allocated as the write destination block before superblock #0. Superblock #1 is an active block that contains at least valid data.

[0119] Here, superpage #5 of superblock 0, which is the block to be written to, is designated as the superpage to which data should be written next.

[0120] At this time, when the read-verify control circuit 422 of the controller 4 receives a write command, it designates superpage #5 of superblock 1, which is an active block where data has already been written, as the page to be read-verified. For example, the read-verify control circuit 422 designates superblock 1 based on the block number that specifies the superblock included in the read-verify management information, and selects superpage #5, which has the same page number as the superpage to be written to. Here, the read-verify management information includes, for example, the block number corresponding to the block immediately preceding the block to which data was written, or a block other than the block to which data was written.

[0121] The read verify control circuit 422 may also select any superpage in the write destination block to which data has already been written as the superpage to be read verified. For example, when writing data to superpage #5 of superblock #0, the read verify control circuit 422 executes read verification on superpage #1 of superblock #0. In this case, the read verify management information includes not only the block number indicating superblock #0 but also the page number corresponding to superpage #1.

[0122] In this way, the read verify control circuit 422 of the controller 4 of the memory system 3 in the first example selects the target of read verify from among the superpages to which data has been written. In other words, the controller 4 does not need to execute read verify immediately after executing the data write process.

[0123] Next, a case where data is written to two NAND chips connected to different channels will be described.

[0124] First, we will describe a third comparative example, in which read verification is performed immediately after writing data to two NAND chips connected to different channels, with reference to Figure 10. Figure 10 is a diagram illustrating the data transfer associated with the data writing process in the third comparative example.

[0125] Here, we assume that a first write command is issued to request data to NAND chip #1, and a second write command is issued to request data to NAND chip #2.

[0126] First, the controller's host interface begins receiving data associated with the received write command upon receiving the first write command.

[0127] The controller transfers the received data to NAND chip #1 via the NAND I / F every time the data reaches 16 KB. Then, when the received data reaches 192 KB, NAND chip #1 executes a program operation to write the data.

[0128] Furthermore, once the controller's host interface has finished receiving the data associated with the first write command, it begins receiving data associated with the second command. The controller then transfers the data to NAND chip #2 via the NAND interface every time the received data reaches 16KB. NAND chip #2 then executes a program operation to write the data when the received data reaches 192KB.

[0129] Once the data transfer to NAND chip #2 is complete, the controller performs a read-verify operation RV1 on NAND chip #1. In read-verify operation RV1, the controller reads the 192KB of data that was written immediately before. The controller determines whether error correction is possible for the read data. If error correction is not possible for the read data, the controller performs error correction on the read data using parity or other methods.

[0130] Then, once the program operation on NAND chip #2 is complete, the controller performs a read-verify RV2 on NAND chip #2. In read-verify RV2, the controller reads the 192KB of data that was written immediately before. The controller determines whether or not error correction is possible for the read data. If error correction is not possible for the read data, the controller performs error correction on the read data using parity or other methods.

[0131] In this way, even when data is written to two NAND chips, the timing at which the second write command is completed is the timing at which read verify RV2 is completed.

[0132] Therefore, the processing corresponding to the write command in the third comparative example is longer by the processing time of the read verify RV2 than when the read verify is not executed.

[0133] Next, a second example in which read verification is performed before writing data to two NAND chips connected to different channels will be described with reference to Fig. 11. Fig. 11 is a diagram illustrating a second example of data transfer accompanying a data write process performed in the memory system 3 according to the embodiment.

[0134] Here, we assume that a first write command is issued to request data to NAND chip #1, and a second write command is issued to request data to NAND chip #2.

[0135] First, in response to receiving the first write command, the host I / F 41 of the controller 4 starts receiving data associated with the received write command.

[0136] The read verify control circuit 422 of the controller 4 determines, as the target of read verify, a superpage in NAND chip #1 to which data has already been written and which is indicated by the read verify management information. For example, the read verify control circuit 422 determines, as the target of read verify, a superpage having the same page number as the superpage to which data associated with the first write command should be written, in the previous write destination block. The read verify control circuit 422 executes read verify RV1 on the determined superpage to be read verified.

[0137] When read verify RV1 is completed, the write control circuit 421 of the controller 4 transfers the received data to NAND chip #1 via the NAND I / F 46 each time the data reaches 16 KB. Then, when the received data reaches 192 KB, NAND chip #1 executes a program operation to write the data.

[0138] Furthermore, when the host I / F 41 of the controller 4 has completed receiving the write data associated with the first write command, it starts receiving the write data associated with the second write command.

[0139] The read verify control circuit 422 of the controller 4 determines, as the target of read verify, a page in NAND chip #2 to which data has already been written and which is indicated by the read verify management information. For example, the read verify control circuit 422 determines, as the target of read verify, a page having the same page number as the page to which data associated with the second write command should be written in the previous write destination block. The read verify control circuit 422 executes read verify RV2 on the determined page to be read verified.

[0140] In read verify RV2, the controller 4 reads 192 KB of data from the page to be read verified. The ECC circuit 45 of the controller 4 determines whether or not error correction is possible for the read data. If error correction is not possible for the read data, the controller 4 performs error correction for the read data using parity or the like.

[0141] When read verify RV2 is completed, the write control circuit 421 of the controller 4 transfers the received data to NAND chip #2 via the NAND I / F 46 each time the data reaches 16 KB. Then, when the received data reaches 192 KB, NAND chip #2 executes a program operation to write the data.

[0142] Thus, in the second example, compared to the third comparative example described with reference to Figure 10, the read-verify RV2 can be executed while the data associated with the second write command is being transferred from host 2 to controller 4. In other words, the execution period of read-verify RV2 can overlap with the period during which data is transferred from host 2 to controller 4. As a result, the memory system 3 in the second example can avoid a prolonged processing time for the second write command even when read-verify RV2 is executed.

[0143] In this way, in the memory system 3 according to the second example, even when data is written to two NAND chips, it is possible to prevent the time required for the data write process from becoming long.

[0144] Next, a third example will be described with reference to Figure 12, in which read verification is performed on three pages before writing data to two NAND chips, each connected to a different channel. Figure 12 is a diagram illustrating a third example of data transfer associated with a data writing process performed in the memory system 3 according to the embodiment.

[0145] Although FIG. 12 shows a case where read verification is performed on three pages, the number of pages on which read verification is performed may be two, or may be four or more.

[0146] Here, we assume that a first write command is issued to request data to NAND chip #1, and a second write command is issued to request data to NAND chip #2.

[0147] First, in response to receiving the first write command, the host I / F 41 of the controller 4 starts receiving data associated with the received write command.

[0148] The read verify control circuit 422 of the controller 4 determines a superpage in NAND chip #1 to which data has already been written and which is indicated by the read verify management information as the target of read verify. For example, the read verify control circuit 422 determines a superpage indicated by the block number and page number included in the read verify management information as the target of read verify. The read verify control circuit 422 executes read verify RV1 on the determined superpage to be read verified.

[0149] When the read verify RV1 is completed, the read verify control circuit 422 determines the superpage to be the target of the next read verify RV2 based on the read verify management information. The read verify control circuit 422 determines the superpage indicated by the read verify management information as the target of read verify. The read verify control circuit 422 executes read verify RV2 on the determined superpage to be read verified.

[0150] When read verify RV2 is completed, the read verify control circuit 422 determines the page to be the target of the next read verify RV3 based on the read verify management information. The read verify control circuit 422 determines the superpage indicated by the read verify management information as the target of read verify. The read verify control circuit 422 executes read verify RV3 on the determined superpage to be read verified.

[0151] Once read-verify RV3 is complete, the write control circuit 421 of controller 4 transfers data to NAND chip #1 via NAND I / F 46 whenever the data received from host 2 reaches 16KB. Then, when the received data reaches 192KB, NAND chip #1 executes a program operation to write the data.

[0152] Furthermore, once the host interface 41 of controller 4 has finished receiving the data associated with the first write command, it will start receiving data associated with the second command.

[0153] The read-verify control circuit 422 of controller 4 determines which superpages of NAND chip #2 that already have data written to them and are indicated by the read-verify management information will be targeted for read-verification. For example, the read-verify control circuit 422 determines which superpages to be targeted for read-verification are indicated by the block number and page number included in the read-verify management information. The read-verify control circuit 422 then performs read-verify RV4 on the determined superpages to be targeted for read-verification.

[0154] Once Read Verify RV4 is complete, the Read Verify control circuit 422 determines which pages will be the target of the next Read Verify RV5 based on the Read Verify management information. The Read Verify control circuit 422 determines which pages indicated by the Read Verify management information will be the target of Read Verify. The Read Verify control circuit 422 then performs Read Verify RV5 on the determined pages to be verified.

[0155] Once read verification RV5 is complete, the read verification control circuit 422 determines which pages will be the target of the next read verification RV6 based on the read verification management information. The read verification control circuit 422 determines the pages indicated by the read verification management information to be the target of read verification. The read verification control circuit 422 then performs read verification RV6 on the determined target pages.

[0156] When read verify RV6 is completed, the read verify control circuit 422 transfers the received data to NAND chip #2 via NAND I / F 46 each time the data reaches 16 KB. Then, when the received data reaches 192 KB, NAND chip #2 executes a program operation to write the data.

[0157] In this way, in the third example, even when writing data to two NAND chips, by performing a read verify immediately before executing the data write process, it is possible to avoid the time required for the data write process from becoming too long.

[0158] Next, a description will be given of the procedure of a data write process executed in the information processing system 1 including the host 2 and the memory system 3. Fig. 13 is a sequence diagram showing the procedure of a data write process executed in the information processing system 1 including the memory system 3 and the host 2 according to the embodiment.

[0159] First, host 2 sends a write command to controller 4 of memory system 3 (step S101).

[0160] Then, host 2 sends the data associated with the write command sent in S101 to controller 4 (step S102).

[0161] When the controller 4 receives the write command in S101, it executes read verification on the data already written to the NAND flash memory 5 (step S103). While FIG. 13 shows a case where the read verification in S103 is executed after the transfer of the write data in S102 has started, the read verification in S103 may start before the transfer of the write data in S102 has started. In the read verification, the controller 4 reads the data to be read verified from the NAND flash memory 5. Then, the controller 4 determines whether or not the read data is error correctable. If the error cannot be corrected, the controller 4 restores the read data using parity or the like.

[0162] The controller 4 transmits a program request to the NAND flash memory 5 to write data associated with the write command received in S101 (step S104). The controller 4 transmits write data to the NAND flash memory 5, for example, every time data of a size equivalent to a physical page is accumulated. Then, when the received write data reaches a data size at which a program operation can be executed, the NAND flash memory 5 executes the program operation.

[0163] Next, the procedure for data writing in the controller 4 will be described. Figure 14 is a flowchart showing the procedure for data writing performed in the memory system according to the embodiment.

[0164] The controller 4 of the memory system 3 receives a write command from the host 2 (step S201).

[0165] Controller 4 begins receiving data associated with the light command received in S201 (step S202).

[0166] The controller 4 determines the target page of the read verify (step S203). The controller 4 determines the target page of the read verify based on the read verify management information. For example, the controller 4 determines, as the target page of the read verify, the superpage having the same superpage number as the superpage to which data should be written based on the write command received in S201, among the previous write destination block.

[0167] The controller 4 executes read verification on the page to be read verified determined in S203 (step S204). In the read verification, the controller 4 reads the data to be read verified from the NAND flash memory 5. Then, the controller 4 determines whether or not the read data is error correctable. If the error cannot be corrected, the controller 4 restores the read data using parity or the like.

[0168] When the controller 4 completes receiving the data in S202, it writes the received data into the NAND flash memory 5 (step S205).

[0169] As described above, the controller 4 of the memory system 3 according to the embodiment executes read verification in response to receiving a write command during data write processing. After the read verification is completed, the controller 4 transmits the write data to the NAND flash memory 5. At this time, the controller 4 executes read verification on superpages for which writing has already been completed and for which read verification has not yet been executed.

[0170] After the read verify is completed, the controller 4 transmits the write data received from the host 2 to the NAND flash memory 5. The controller 4 transmits the write data to the NAND flash memory 5 every time the write data received from the host 2 reaches the size of the write unit.

[0171] In this way, in the memory system 3 according to the embodiment, the processing time for read verify is contained within the transfer time of write data from the host 2. In other words, the controller 4 can execute read verify while receiving write data from the host 2. This allows the controller 4 to reduce the time required for write processing compared to when read verify is executed after a program operation.

[0172] This allows the controller 4 to efficiently execute the data write process.

[0173] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0174] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...NAND flash memory, 6...DRAM, 21...processor, 22...memory, 41...host interface circuit, 42...CPU, 43...SRAM, 44...DMAC, 45...ECC circuit, 46...NAND interface circuit, 47...DRAM interface circuit, 61...L2P table, 62...block management table, 63...active block list, 64...free block list, 65...read verify management information table, 421...write control circuit, 422...read verify control circuit.

Claims

1. 1. A memory system connectable to a host, comprising: a nonvolatile memory including a plurality of physical blocks, each of which is a unit of a data erasure operation; a controller electrically connected to the nonvolatile memory and configured to write data to the nonvolatile memory and perform read verify to determine whether the data written in the nonvolatile memory can be read normally; each of the plurality of physical blocks includes a plurality of physical pages, each of which is a unit for writing and reading data; The controller In response to receiving a first write command from the host, initiates reception of first data associated with the first write command from the host; selecting a first page from among the plurality of physical pages, pages to which the second data has already been written and for which read verification has not been executed; performing a read verify on the selected first page; writing the received first data to a second page included in a write destination block among the plurality of physical blocks; It is configured as follows: Memory system.

2. The controller performing the read verify in parallel with receiving the first data associated with the first write command from the host; After the execution of the read verify is completed, the received first data is written to the second page. It is configured as follows:

10. The memory system of claim 1.

3. the first page belongs to a block in which the second data has been written, among the plurality of physical blocks, and has the same page number as the second page; 10. The memory system of claim 1.

4. The controller Instead of selecting the first page, select two or more third pages; performing the read verify on the selected two or more third pages; It is configured as follows:

10. The memory system of claim 1.

5. The controller managing management information including a block number indicating a block including the two or more third pages for which the read verification has been executed, and a page number corresponding to the third page; It is configured as follows:

5. The memory system of claim 4.

6. The controller If the second data cannot be read correctly from the first page in the read verify, the second data to be written to the first page is restored; performing an operation of writing the restored second data to the nonvolatile memory; It is configured as follows:

10. The memory system of claim 1.

7. The memory system is equivalent to an SD card.

10. The memory system of claim 1.

8. the non-volatile memory includes two or more chips each operable in parallel; each of the two or more chips includes the plurality of physical blocks; The controller in response to receiving from the host a second write command for writing third data to a first chip of the two or more chips and a third write command for writing fourth data to a second chip of the two or more chips, start receiving the third data associated with the second write command; selecting a fourth page from pages of the first chip on which writing of the fifth data has already been completed and on which read verification has not been executed; performing the read verify on the selected fourth page; writing the received third data to a fifth page that is a write destination page of a write destination block included in the first chip; When the reception of the third data is completed, the reception of the fourth data associated with the third write command is started; selecting a sixth page from pages of the second chip on which sixth data has already been written and on which read verification has not been performed; performing the read verify on the selected sixth page; writing the received fourth data to a seventh page that is a write destination page of a write destination block included in the second chip; It is configured as follows:

10. The memory system of claim 1.

9. The controller managing a plurality of logical blocks, each of which includes two or more physical blocks; each of the plurality of logical blocks includes a plurality of logical pages, each of the logical pages including two or more physical pages; Data is written in units of logical pages contained in the destination logical block, The controller selecting, instead of the first page, a first logical page from the plurality of logical pages, to which writing of seventh data has already been completed and to which read verification has not been executed, and executing read verification on the first logical page; the first data is written to a second logical page included in a write destination logical block among the plurality of logical blocks, instead of the second page; 10. The memory system of claim 1.

10. 1. A control method for controlling a memory system connectable to a host, comprising: In response to receiving a write command from the host, Initiating reception, by a controller of the memory system, of first data associated with the write command received from the host; selecting a first page from among a plurality of physical pages included in a nonvolatile memory of the memory system, the first page being a page to which second data has already been written and to which read verification has not been executed; performing a read verify on the selected first page; writing the received first data to a second page included in a write destination block among a plurality of physical blocks included in the nonvolatile memory; Control method.

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