Quantum device and method for manufacturing the same

Abstract

In quantum devices with Josephson junctions, the generation of TLS defects and the variation in their characteristics are suppressed. [Solution] A first superconductor film, a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, are sequentially formed by epitaxial growth on the (100) or (111) plane of a substrate having a cubic crystal structure. The second superconductor film, the first insulator film, and the third superconductor film are patterned to form a stack including the second superconductor film, the first insulator film, and the third superconductor film. The first superconductor film is patterned using the stack as a mask. After patterning the first superconductor film, the side surfaces of the stack are wet-etched. A second insulator film is formed to cover the wet-etched side surfaces of the stack. After forming the second insulator film, a fourth superconductor film is formed in contact with the third superconductor film. The stack forms a Josephson junction, and the first superconductor film has a lattice constant between that of the substrate and that of the second superconductor film.

Description

[Technical Field]

[0001] The disclosed technology relates to quantum devices and methods for manufacturing quantum devices. [Background technology]

[0002] Various methods have been proposed for the qubits that make up quantum computers. Among them, superconducting qubits, which are based on solid-state materials, are the ones that are leading the way in research and development. Superconducting qubits are being vigorously researched and developed by research institutes and companies around the world because of their compatibility with quantum coherence, a macroscopic quantum phenomenon in superconductors, and the integration technology that comes with being a solid-state device.

[0003] The following techniques are known for superconducting quantum bits with Josephson junctions. For example, Patent Document 1 describes a method of hydrogen-terminating a silicon substrate oriented in a plane parallel to its principal surface, first heating the hydrogen-terminated silicon substrate to remove hydrogen, forming a titanium nitride layer on the silicon substrate by sputtering while performing a second heating on the silicon substrate after hydrogen removal, and then forming a superconducting tunnel junction layer on the titanium nitride layer, which is made up of multiple layers including a niobium nitride layer connected to the titanium nitride layer.

[0004] Patent document 2 describes a chip surface-based device structure comprising a transmon qubit with a vertical Josephson junction including a first superconducting material, a tunnel barrier and a second superconducting material positioned in a via in a crystalline substrate, and a capacitor.

[0005] Patent Document 3 describes a vertical Josephson junction device including an epitaxial stack formed on a substrate, a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack. The second superconducting electrode is separated from the first superconducting electrode by a dielectric layer, and the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-213363 [Patent Document 2] Special Publication No. 2021-518654 [Patent Document 3] U.S. Patent Application Publication No. 2021 / 0320240 Summary of the Invention [Problem to be solved by the invention]

[0007] The large-scale integration of superconducting quantum bits requires element structures and integration technologies that prevent the shortening of the lifetime of individual quantum bits and suppress the characteristic variations between quantum bits. The disclosed technology aims to manufacture more precise Josephson junctions in quantum devices. [Means for solving the problem]

[0008] A method for manufacturing a quantum device according to the disclosed technology includes the following steps: forming a first superconductor film, a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, by epitaxial growth on a (100) or (111) plane of a substrate having a cubic crystal structure; patterning the second superconductor film, the first insulator film, and the third superconductor film to form a stack including the second superconductor film, the first insulator film, and the third superconductor film; patterning the first superconductor film using the stack as a mask; wet-etching a side surface of the stack after patterning the first superconductor film; forming a second insulator film that covers the wet-etched side surface of the stack; and forming a fourth superconductor film in contact with the third superconductor film after forming the second insulator film. The stack forms a Josephson junction, and the first superconductor film has a lattice constant that is between the lattice constant of the substrate and the lattice constant of the second superconductor film. [Effects of the Invention]

[0009] According to the disclosed technology, it is possible to suppress the occurrence of TLS defects and variations in characteristics in quantum devices having Josephson junctions. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a plan view illustrating an example of a configuration of a quantum device according to an embodiment of the disclosed technology. [Figure 1B] FIG. 1B is a cross-sectional view taken along line 1B-1B in FIG. 1A. [Figure 2A] 1 is a plan view showing an example of a method for manufacturing a quantum device according to an embodiment of the disclosed technique; [Figure 2B] FIG. 2B is a cross-sectional view taken along line 2B-2B in FIG. 2A. [Figure 3A] 1 is a plan view showing an example of a method for manufacturing a quantum device according to an embodiment of the disclosed technique; [Figure 3B] FIG. 3B is a cross-sectional view taken along line 3B-3B in FIG. 3A. [Figure 4A] 1 is a plan view showing an example of a method for manufacturing a quantum device according to an embodiment of the disclosed technique; [Figure 4B] FIG. 4B is a cross-sectional view taken along line 4B-4B in FIG. 4A. [Figure 5A] 1 is a plan view showing an example of a method for manufacturing a quantum device according to an embodiment of the disclosed technique; [Figure 5B] FIG. 5B is a cross-sectional view taken along line 5B-5B in FIG. 5A. [Figure 6A] 1 is a plan view showing an example of a method for manufacturing a quantum device according to an embodiment of the disclosed technique; [Figure 6B] FIG. 6B is a cross-sectional view taken along line 6B-6B in FIG. 6A. [Figure 7] 1 is a perspective view showing a schematic configuration of a single-crystal epitaxial stacked structure according to an embodiment of the disclosed technique; [Figure 8] FIG. 10 is a perspective view showing a schematic configuration of a single-crystal epitaxial stacked structure according to another embodiment of the disclosed technique. [Figure 9] 3 is a cross-sectional view showing the structure in the vicinity of the interface between the substrate and the first superconductor film. [Figure 10] FIG. 1 is a plan view showing an example of the configuration of a superconducting quantum circuit according to an embodiment of the disclosed technique. [Figure 11] FIG. 9 is an enlarged view of one of the basic units shown in FIG. 8. [Figure 12] FIG. 10 is an equivalent circuit diagram of a calculation block according to an embodiment of the disclosed technique. [Figure 13] FIG. 1 is a plan view showing an example of a quantum bit pattern according to an embodiment of the disclosed technique. [Figure 14] FIG. 1 is a cross-sectional view showing an example of a mounting form of a superconducting quantum circuit according to an embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant description will be omitted.

[0012] [First embodiment] A superconducting quantum bit is composed of a Josephson junction element, a nonlinear inductor, and a transmon, an LC resonant circuit including a capacitor. At least two of the non-equidistant discrete energy levels of the transmon are used as quantum bits. One of the factors limiting the lifetime (quantum coherence time) of a superconducting quantum bit is a two-level system (TLS) defect, which induces fluctuations in charge and critical current within the element or circuit. TLS defects are thought to arise due to dangling bonds and impurity defects within the insulator film that constitutes the Josephson junction element, surface oxides of the Josephson junction element, and the inclusion of oxides or impurities at the interface between the Josephson junction element and the electrode material.

[0013] A typical Josephson junction element is an Al / AlO thin film, which is an AlOX film sandwiched between two Al thin films. X / Al three-layer structure. This Al / AlO X A technique called shadow evaporation is used to manufacture Josephson junction devices using a three-layer Al / Al film structure. In this method, a resist mask with crossbar-shaped openings is first formed on the substrate by lithography. Next, a first layer of Al film is evaporated from one side of the crossbar at an angle to the substrate surface, and the surface of the first layer of Al film is oxidized in an O2 atmosphere to form AlO. X Next, the crossbar is rotated 90 degrees and a second layer of Al is evaporated from an oblique direction relative to the substrate surface. In this way, by utilizing the shadow of the sidewall of the resist mask, the Al is evaporated obliquely twice in different directions, forming an Al / AlO X The shadow evaporation method is widely used because it can easily obtain a three-layer film structure, but the Al film is polycrystalline and the AlO X The film becomes amorphous.

[0014] In Josephson junction devices formed by shadow deposition, the crystallinity of amorphous AlO is particularly random. XThe film contains many TLS defects. Furthermore, conventional Josephson junction devices often have a structure in which the Al film on the surface is exposed during or after fabrication. This structure is caused by the natural oxidation of the Al film surface, resulting in amorphous AlO X These factors can induce TLS defects, such as the formation of ions, the adsorption of impurity molecules in the atmosphere, and residual resist used in the manufacturing process. Furthermore, when the Al film of a Josephson junction device is polycrystalline, it is difficult to control its grain size and crystal orientation, and the AlO X This also affects the uniformity of the film quality. Non-uniformity in the film quality of each film that makes up a Josephson junction element can also cause variations in characteristics between elements. The disclosed technology aims to suppress the occurrence of TLS defects and variations in characteristics in quantum devices with Josephson junctions.

[0015] FIG. 1A is a plan view showing an example of the configuration of a quantum device 10 according to an embodiment of the disclosed technology. FIG. 1B is a cross-sectional view taken along line 1B-1B in FIG. 1A. The quantum device 10 constitutes a Josephson junction element. The quantum device 10 includes a substrate 11, a first superconductor film 12, a second superconductor film 13, a first insulator film 14, a third superconductor film 15, a second insulator film 16, and a fourth superconductor film 17. The first superconductor film 12, the second superconductor film 13, the third superconductor film 15, and the fourth superconductor film 17 each exhibit superconductivity at a temperature below a predetermined critical temperature.

[0016] The substrate 11 has a cubic crystal structure. The substrate 11 may be, for example, a single-crystal Si substrate. A first superconductor film 12, a second superconductor film 13, a first insulator film 14, and a third superconductor film 15, each having a cubic crystal structure, are sequentially formed by epitaxial growth on the (100) plane, which is the main surface of the substrate 11. That is, the

[0100] direction of each of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, and the third superconductor film 15 is parallel to the

[0100] direction of the substrate 11. Furthermore, the

[0001] direction of each of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, and the third superconductor film 15 is parallel to the

[0001] direction of the substrate 11. The first superconductor film 12, the second superconductor film 13, the first insulator film 14, and the third superconductor film 15 are formed by a vacuum integrated process in which these films are successively formed while the substrate 11 is held in a vacuum chamber. Physical deposition is used as the film formation method for these films.

[0017] The first superconductor film 12 functions as a lower line of the superconducting quantum circuit and also as a buffer layer that reduces the lattice mismatch between the substrate 11 and the second superconductor film 13. That is, the first superconductor film 12 has a lattice constant between that of the substrate 11 and that of the second superconductor film 13. When the substrate 11 is, for example, a Si substrate (a = 0.5430 nm) and the second superconductor film 13 is, for example, an Al film (a = 0.404 nm), the first superconductor film 12 may be, for example, a TiN film (a = 0.424 nm). When an Al film is formed directly on the surface of a Si substrate, the lattice mismatch is 26%. By providing a TiN film between the Si substrate and the Al film, the lattice mismatch can be reduced to 4.7%. This makes it possible to improve the crystallinity of the stack (hereinafter referred to as JJ stack 20) ​​that forms the Josephson junction and includes the second superconductor film 13, the first insulator film 14, and the third superconductor film 15. The first superconductor film 12 may be any superconductor film that has a cubic crystal structure and has a lattice mismatch with the JJ stack 20 of less than 10%. As a film that satisfies the above conditions, an NbN film or a TaN film can also be used in addition to a TiN film.

[0018] A JJ stack 20 including a second superconductor film 13, a first insulator film 14, and a third superconductor film 15 is provided on the (100) plane, which is the main surface of the first superconductor film 12. The JJ stack 20 has a configuration in which an extremely thin insulator film is sandwiched between two superconductor films, thereby forming a Josephson junction. The second superconductor film 13 and the third superconductor film 15 may each be, for example, an Al film. The first insulator film 14 may be, for example, an AlN film.

[0019] The second insulator film 16 covers the side surfaces of the JJ stack 20. The second insulator film 16 functions as a protective layer that protects the JJ stack 20 by enclosing the JJ stack 20. The second insulator film 16 also covers the upper surface and part of the side surfaces of the first superconductor film 12. The second insulator film 16 has an opening 16A that exposes the upper surface of the JJ stack 20 (third superconductor film 15). The second insulator film 16 does not necessarily have to be a single-crystalline film, and may be a polycrystalline film or an amorphous film. The second insulator film 16 may be, for example, an AlN film.

[0020] The fourth superconductor film 17 is in contact with the upper surface of the third superconductor film 15 exposed at the opening 16A of the second insulator film 16. The fourth superconductor film 17 functions as an upper line of the superconducting quantum circuit and also as a cap layer covering the upper surface of the JJ stack 20. When the fourth superconductor film 17 is patterned by lift-off using a resist, it is preferable to form the fourth superconductor film 17 at room temperature to avoid deformation of the resist. In this case, it is preferable that the fourth superconductor film 17 has a film quality that exhibits a superconducting transition even when formed at room temperature. For example, an NbTiN film, an Nb film, a Ta film, or an NbN film can be used as the fourth superconductor film 17.

[0021] The JJ stack 20 is completely sealed by the second insulator film 16 covering its side surface and the fourth superconductor film 17 covering its top surface. Therefore, the JJ stack 20 is not exposed to the atmosphere, and the risks of natural oxidation and impurity adsorption are suppressed.

[0022] A method for manufacturing a quantum device will be described below. Figures 2A, 3A, 4A, 5A, and 6A are each plan views showing an example of a method for manufacturing quantum device 10. Figure 2B is a cross-sectional view taken along line 2B-2B in Figure 2A. Figure 3B is a cross-sectional view taken along line 3B-3B in Figure 3A. Figure 4B is a cross-sectional view taken along line 4B-4B in Figure 4A. Figure 5B is a cross-sectional view taken along line 5B-5B in Figure 5A. Figure 6B is a cross-sectional view taken along line 6B-6B in Figure 6A.

[0023] <Substrate surface treatment> A substrate 11 having a cubic crystal structure is prepared. Here, a case where a Si(100) substrate is used as the substrate 11 is exemplified. The Si(100) substrate is immersed in acetone, then in isopropyl alcohol, and ultrasonically cleaned. After that, it is immersed in 5% hydrofluoric acid for 5 minutes, and finally rinsed with ultrapure water. These treatments remove the native oxide film on the surface of the Si(100) substrate, and a stable Si surface state where Si is terminated with H is formed. Next, the Si(100) substrate that has been subjected to the above treatment is quickly placed in an ultrahigh vacuum (basic vacuum: 10 -8 The sample is then placed in a vacuum chamber (on the order of Pa) and heated at 250°C for at least 3 hours to degas the sample. After the degassing process, the vacuum level is reduced to 10 -6 While maintaining pressure on the order of Pa, the Si(100) substrate is heated to over 1000°C for several seconds, and this flashing process is repeated two to three times. This process removes the native oxide film remaining on the Si(100) substrate surface, resulting in a Si(100)-2x1 reconstructed surface with improved flatness at the atomic level.

[0024] <Deposition of the first superconductor film> Next, on the (100) plane which is the main surface of the Si(100) substrate subjected to the above surface treatment, a first superconductor film 12 constituting the lower circuit of the superconducting quantum circuit is formed by an epitaxial growth method. As a result, on the (100) plane of the substrate 11, the first superconductor film 12 is formed in a state where the crystal orientation is aligned with respect to the substrate 11 (FIGS. 2A and 2B). Here, the case where a TiN(100) film (crystal structure: NaCl type, a = 0.424 nm) is used as the first superconductor film 12 is exemplified.

[0025] The TiN(100) film can be formed, for example, by a pulsed laser deposition (PLD) method. Specifically, for example, N2 gas with a flow rate of 3 sccm is introduced, and in a vacuum chamber controlled to a total pressure of, for example, about 5×10 -2 Pa, a TiN(100) film is formed on a Si(100) substrate held at, for example, 950°C. In PLD, a pulsed laser (for example, energy density: 2.0 J / cm 2 , frequency: 1 Hz) is irradiated onto a TiN sintered body target oppositely disposed at a position about 5 cm away from the Si(100) substrate to generate a plume, thereby forming a TiN(100) film. The film formation rate is set to, for example, about 1.5 nm / min, and a TiN(100) film with a thickness of about 100 nm is formed.

[0026] The film formation method of the TiN(100) film is not limited to the PLD method, and it is also possible to use a molecular beam epitaxy (MBE) method, a sputtering method, etc. Further, as the first superconductor film 12, it is also possible to use a NbN(100) film (crystal structure: NaCl type, a = 0.445 nm) or a TaN(100) film (crystal structure: NaCl type, a = 0.442 nm) having a cubic crystal structure and a lattice mismatch with the JJ laminate 20 of less than 10%.

[0027] <Film formation of JJ laminate> Next, a second superconductor film 13, a first insulator film 14, and a third superconductor film 15 are sequentially formed by epitaxial growth on the (100) plane, which is the main surface of the TiN(100) film. As a result, a JJ stack 20 is formed on the (100) plane of the first superconductor film 12 with its crystal orientation aligned with that of the first superconductor film 12 (FIGS. 2A and 2B). Here, an example is shown in which Al(100) films (crystal structure: fcc, a=0.404 nm) are used as the second superconductor film 13 and the third superconductor film 15, and an AlN(100) film (crystal structure: NaCl type, a=0.407 nm) is used as the first insulator film 14.

[0028] The Al(100) film as the second superconductor film 13 can be formed by, for example, the MBE method. -6 In a vacuum chamber controlled to less than Pa, an Al(100) film is formed by electron beam evaporation on a Si(100) substrate with a TiN(100) film maintained at, for example, 100°C. The film formation rate is set to, for example, about 20 nm / min, and an Al(100) film with a thickness of, for example, about 50 nm is formed.

[0029] The substrate temperature during Al film deposition is preferably selected between -50°C and 400°C. Substrate heating provides the kinetic energy for migration of Al evaporated particles on the substrate surface. The substrate temperature is preferably adjusted according to the deposition rate. For example, if the deposition rate is low and the kinetic energy of the Al evaporated particles is insufficient, it is preferable to set the substrate temperature higher to promote two-dimensional epitaxial growth of the Al(100) film.

[0030] When an Al film is deposited directly on a Si(100) substrate, the lattice mismatch between Al and Si is as large as 26%, resulting in the Al film being deposited in a polycrystalline state. On the other hand, when an Al film is deposited with a TiN(100) film sandwiched between the Si(100) substrate and the Al film, the lattice mismatch between Al and TiN is as small as 4.7%, enabling epitaxial growth of the Al(100) film. In other words, the TiN(100) film serving as the first superconductor film 12, which functions as the lower line, also functions as a buffer layer to reduce the lattice mismatch between the Si(100) substrate (substrate 11) and the Al(100) film (second superconductor film 13).

[0031] Next, an AlN(100) film is formed as the first insulator film 14 on the (100) plane, which is the main surface of the Al(100) film as the second superconductor film 13. The AlN(100) film can be formed by, for example, the PLD method. Specifically, N2 gas is introduced at a flow rate of, for example, 3 sccm, and the total pressure is, for example, about 5 × 10 -2 In a vacuum chamber controlled at 100 Pa, an AlN(100) film is formed on a Si(100) substrate with an Al(100) film / TiN(100) film maintained at 100°C. In PLD, a pulsed laser (for example, energy density: 1.0 J / cm) is applied to an AlN sintered compact target placed facing the Si(100) substrate at a distance of about 5 cm. 2 The AlN(100) film is formed by generating a plume by irradiating the laser beam (frequency: 1 Hz). The film formation rate is set to, for example, about 0.5 nm / min, and an AlN(100) film with a thickness of, for example, about 1.5 nm is formed.

[0032] Next, an Al(100) film is formed as the third superconductor film 15 on the (100) plane, which is the main surface of the AlN(100) film as the first insulator film 14. The Al(100) film as the third superconductor film 15 can be formed by, for example, the MBE method, similar to the Al(100) film as the second superconductor film 13. Here too, the film formation rate is set to, for example, about 20 nm / min, and an Al(100) film with a thickness of, for example, about 50 nm is formed.

[0033] <Formation of the third insulating film> Next, a third insulator film 18 is formed on the (100) plane which is the main surface of the third superconductor film 15 by epitaxial growth. Thereby, on the (100) plane of the third superconductor film 15, the third insulator film 18 is formed in a state where the crystal orientation is aligned with respect to the third superconductor film 15 (FIGS. 2A and 2B). Here, as the third insulator film 18, the case of using an AlN(100) film (crystal structure: NaCl type, a = 0.407 nm) is exemplified. The AlN(100) film can be formed, for example, by the PLD method. The film thickness of the AlN(100) film is set to about 10 nm. The third insulator film 18 functions as a protective layer for protecting the upper surface of the JJ laminate 20.

[0034] FIG. 7 is a perspective view showing a schematic configuration of a single crystal epitaxial laminate obtained by going through each of the above steps. The substrate 11, the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 each have a cubic crystal structure. Each film formed on the (100) plane of the substrate 11 is formed by epitaxial growth. That is, the

[0100] direction of each of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 is parallel to the

[0100] direction of the substrate. The

[0001] direction of each of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 is parallel to the

[0001] direction of the substrate. The formation of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 is performed by a vacuum integrated process in which these films are continuously formed while holding the substrate 11 in a vacuum chamber.

[0035] <Etching of JJ laminate 1> Next, the JJ laminate 20 is partially etched to expose the first superconductor film 12 (FIGS. 3A and 3B). Specifically, the JJ laminate 20 and the third insulator film 18 covering it are processed into an island shape with a size (tens of μm square) sufficiently larger than the final size (hundreds of nm square) of the JJ laminate 20 by photolithography and dry etching.

[0036] A resist (not shown) applied by spin coating on the surface of the substrate 11 is patterned by photolithography, for example, into an island shape with a side length of 20 μm. Next, by dry etching using reactive ion etching (RIE), the second superconductor film 13 (Al film), the first insulator film 14 (AlN film), the third superconductor film 15 (Al film), and the third insulator film 18 (AlN film) are etched to process the JJ stack 20 into an island pattern with a side length of 20 μm, for example.

[0037] In RIE, for example, BCl3 gas is introduced as a reaction gas, the total pressure is controlled to, for example, 10 Pa, and the high-frequency power is set to, for example, 100 W. According to RIE using BCl3 gas, the selectivity of the AlN / AL / AlN / AL film with respect to the TiN film can be increased, so that the AlN / AL / AlN / AL film can be etched without substantially etching the TiN film. By etching the JJ stack 20 and the third insulator film 18, the surface of the first superconductor film 12 is exposed. Note that the etching in this step is not limited to dry etching and may be wet etching.

[0038] <Patterning of the first superconductor film> Next, the TiN film as the exposed first superconductor film 12 is patterned by etching (FIGS. 4A and 4B). Specifically, the TiN film is patterned by dry etching using RIE to form the lower circuit of the superconducting quantum circuit. In RIE, CF4 gas is introduced as a reaction gas, the total pressure is controlled to, for example, 10 Pa, and the high-frequency power is set to, for example, 100 W.

[0039] <Etching of the JJ stack 2> Next, the JJ stack 20 is patterned by wet etching (FIGS. 5A and 5B). That is, by performing the second etching on the JJ stack 20 and the third insulator film 18 by wet etching, the JJ stack 20 is microfabricated into the final size (a few hundred nm square).

[0040] A resist 30 is spin-coated onto the surface of the substrate 11, and a mask pattern, e.g., 150 nm square islands, corresponding to the final pattern of the JJ stack 20 is formed in the resist 30 by electron beam lithography. The resist 30 is used not only as a mask for wet etching of the JJ stack 20 in this process but also as a mask for patterning the second insulator film 16 by lift-off in a subsequent process. Therefore, the mask pattern of the resist 30 also corresponds to the pattern of the second insulator film 16. The resist 30 may be a two-layer resist. In a two-layer resist, an overhang structure can be formed in which the edge of the upper resist layer protrudes beyond the lower resist layer. This facilitates lift-off of the second insulator film 16. For example, ZEP520A-7 (manufactured by Nippon Zeon Corporation) can be used as the upper resist layer, and Copolymer MMA(8.5)MMA EL11 (manufactured by Kayaku Advanced Materials) can be used as the lower resist layer. As an etchant for wet etching the JJ stack 20 and the third insulator film 18, for example, a mixed acid solution (H3PO4:HNO3:CH3COOH:H2O=74:3:3:20%) can be used. After wet etching the JJ stack 20 and the third insulator film 18, a rinse process is performed with ultrapure water. The resist 30 used in this process is left unremoved and proceeds to the next process.

[0041] Here, if the JJ stack 20 is formed by conventional shadow deposition using a resist mask with crossbar-shaped openings, etching for patterning the JJ stack 20 is not required. On the other hand, the JJ stack 20 according to this embodiment is formed by epitaxial growth, and therefore etching for patterning the JJ stack 20 is required. As described above, in this embodiment, the JJ stack 20 is patterned by two etching steps, and the second etching step is wet etching. The reason for patterning the JJ stack 20 by two etching steps is that it is difficult to finely process the JJ stack by a single etching step. A first etching step (RIE) is used to roughly cut out small pieces of the JJ stack 20, and a second etching step (wet etching) is used to process the JJ stack 20 to its final size, thereby enabling the formation of a fine pattern. Furthermore, wet etching in the second etching step makes it possible to remove residues adhering to the sidewalls of the JJ stack 20.

[0042] <Formation of second insulating film> Next, a second insulating film 16 is formed to cover the side surfaces of the JJ stack 20 (FIGS. 6A and 6B). Here, an example is shown in which an AlN film is used as the second insulating film 16. The AlN film is formed by, for example, PLD using the resist 30 used for wet etching the JJ stack 20 in the previous step. Specifically, N2 gas is introduced, and the total pressure is, for example, about 5×10 -2 In a vacuum chamber controlled at 25°C, for example, an AlN film is formed on a substrate 11 with a resist, which is maintained at 25°C. In PLD, a pulsed laser (for example, energy density: 2.0 J / cm) is applied to an AlN sintered compact target placed facing the substrate 11 at a distance of about 5 cm. 2 The AlN film is formed by irradiating the second insulating film 16 with a laser beam (frequency: 10 Hz) to generate a plume. The film formation rate is set to, for example, about 25 nm / min, and an AlN film with a thickness of, for example, about 250 nm is formed. The AlN film as the second insulating film 16 does not necessarily have to be a single-crystalline film, and may be a polycrystalline film or an amorphous film.

[0043] The resist 30 has an opening that surrounds the periphery of the JJ stack 20, and the exposed portion in this opening is covered with an AlN film. Next, the AlN film is patterned by lift-off, which removes the AlN film deposited on the surface of the resist 30 together with the resist 30. The AlN film serving as the second insulator film 16 covers the side surfaces of the JJ stack 20, enclosing the JJ stack 20. The second insulator film 16 functions as a protective layer that protects the side surfaces of the JJ stack 20. The JJ stack 20 is completely sealed by the two protective layers of the second insulator film 16 and the third insulator film 18.

[0044] <Formation of the fourth superconducting film> Next, a fourth superconductor film 17 is formed in contact with the third superconductor film 15 (FIGS. 1A and 1B). Specifically, first, a resist (not shown) is applied by spin coating, and a mask pattern is formed on this resist by photolithography. This resist is used as a mask for removing the third insulator film 18 by etching and patterning the fourth superconductor film 17 by lift-off. For example, TLOR-P003HP (manufactured by Tokyo Ohka Kogyo Co., Ltd.), which can form an overhang structure with a single layer, can be used as the resist.

[0045] Next, the substrate 11 is introduced into a vacuum chamber, and the third insulator film 18 is removed by Ar ion milling using the resist as a mask. This exposes the surface of the third superconductor film 15. In the Ar ion milling, Ar gas is introduced into the vacuum chamber, and the total pressure is, for example, 5×10 -3 The ion acceleration voltage is set to, for example, 1.0 kV, and the ion beam current is set to, for example, 100 μA.

[0046] After removing the third insulator film 18, a fourth superconductor film 17 is formed in the same vacuum chamber without exposing the substrate 11 to the atmosphere. Here, a case where an NbTiN film is used as the fourth superconductor film 17 is exemplified. The NbTiN film can be formed by, for example, the PLD method. Specifically, N2 gas is introduced, and the total pressure is, for example, about 5 × 10-2 In a vacuum chamber controlled at 25°C, for example, a NbTiN film is formed on a substrate 11 with a resist, which is maintained at 25°C. In PLD, a pulse laser (for example, energy density: 2.0 J / cm) is applied to a NbTi sintered compact target placed facing the substrate 11 at a distance of about 5 cm. 2 A plume is generated by irradiating the laser beam (frequency: 10 Hz). The NbTi particles are ablated and nitrided in an N2 atmosphere to form an NbTiN film. The deposition rate is set to, for example, approximately 20 nm / min, and an NbTiN film with a thickness of, for example, approximately 350 nm is deposited.

[0047] Next, the NbTiN film is patterned by lift-off, which removes the NbTiN film deposited on the surface of the resist together with the resist. It should be noted that, in addition to the NbTiN film, an Nb film, a Ta film, or an NbN film can also be used as the fourth superconductor film 17. Through the above steps, the quantum device 10 is completed.

[0048] In Josephson junction devices formed by conventional shadow deposition, the crystallinity of amorphous AlO is random. X The Al film contains many TLS defects. Furthermore, conventional Josephson junction devices often have a structure in which the Al film on the surface is exposed during or after fabrication. This structure is caused by the natural oxidation of the Al film surface, resulting in amorphous AlO X These factors can induce TLS defects, such as the formation of ions, the adsorption of impurity molecules in the atmosphere, and residual resist used in the manufacturing process. Furthermore, when the Al film of a Josephson junction device is polycrystalline, it is difficult to control its grain size and crystal orientation, and the AlO X This also affects the uniformity of the film quality. Non-uniformity in the film quality of each film constituting a Josephson junction element can also cause variations in the characteristics between elements.

[0049] According to a manufacturing method according to an embodiment of the disclosed technology, a first superconductor film 12, a second superconductor film 13, a first insulator film 14, and a third superconductor film 15, each having a cubic crystal structure, are sequentially formed by epitaxial growth on the (100) plane of a substrate 11 having a cubic crystal structure. This makes it possible to suppress the occurrence of TLS defects and characteristic variations due to crystallinity disturbances in the second superconductor film 13, the first insulator film 14, and the third superconductor film 15, which constitute the JJ stack 20. Furthermore, by forming each of the above films using an integrated vacuum process, it is possible to avoid the inclusion of impurities. This makes it possible to suppress the occurrence of TLS defects due to the inclusion of impurities.

[0050] The side surfaces of the JJ stack 20 are covered with the second insulator film 16, and the top surface of the JJ stack 20 is covered with the fourth superconductor film 17. This prevents the JJ stack 20 from being exposed to the atmosphere after fabrication, making it possible to suppress fluctuations in device characteristics over time due to the progression of natural oxidation.

[0051] Furthermore, the upper surface of the JJ stack 20 is covered with the third insulator film 18 from immediately after the formation of each of the constituent films until the formation of the fourth superconductor film 17. This prevents the surface of the superconductor film from being oxidized by lithography and etching, which are repeatedly performed in the manufacturing process, and prevents direct adhesion of organic contaminants such as resist. This makes it possible to suppress the occurrence of TLS defects.

[0052] Furthermore, the first superconductor film 12 has a lattice constant between the lattice constants of the substrate 11 and the second superconductor film 13. This reduces the lattice mismatch between the substrate 11 and the second superconductor film 13, thereby improving the crystallinity of the JJ stack 20.

[0053] The JJ stack 20 is patterned by two etching steps. The first etching step is a rough process for cutting out small pieces of the JJ stack 20, and the second etching step is a process for processing the JJ stack 20 to the final size, thereby enabling the formation of a fine pattern. Furthermore, by performing the second etching step as wet etching, it is possible to remove residues adhering to the sidewalls of the JJ stack 20.

[0054] [Second embodiment] 8 is a perspective view showing a schematic configuration of a single crystal epitaxial stacked structure according to a second embodiment of the disclosed technique. The single crystal epitaxial stacked structure according to the second embodiment differs from the single crystal epitaxial stacked structure according to the first embodiment (FIG. 7) in the crystal orientation of the substrate 11 and the films formed on the substrate 11.

[0055] In the single crystal epitaxial stack structure according to the second embodiment, the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 are provided on the (111) plane of the substrate 11. The

[0111] direction of each of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 is parallel to the

[0111] direction of the substrate 11. The [11-2] direction of each of the first superconductor film 12, the second superconductor film 13, the first insulator film 14, the third superconductor film 15, and the third insulator film 18 is parallel to the [11-2] direction of the substrate 11.

[0056] The single crystal epitaxial stack structure according to the second embodiment is obtained through the steps of surface treatment of the substrate 11, deposition of the first superconductor film 12, deposition of the JJ stack 20, and formation of the third insulator film 18, as in the first embodiment described above.

[0057] In the surface treatment process of the substrate 11, the Si(111) substrate is subjected to cleaning, rinsing, degassing, and flushing in this order, resulting in a Si(111)-7x7 reconstructed surface with improved flatness at the atomic level.

[0058] In the step of forming the first superconductor film 12, the first superconductor film 12 constituting the lower line of the superconducting quantum circuit is formed by epitaxial growth on the (111) plane, which is the main surface of the surface-treated substrate 11. As a result, the first superconductor film 12 is formed on the (111) plane of the substrate 11 with its crystal orientation aligned with that of the substrate 11. The first superconductor film 12 may be, for example, a TiN(111) film.

[0059] In the process of forming the JJ stack 20, the second superconductor film 13, the first insulator film 14, and the third superconductor film 15 are sequentially formed by epitaxial growth on the (111) plane, which is the main surface of the first superconductor film 12. As a result, the JJ stack 20 is formed on the (111) plane of the first superconductor film 12 with its crystal orientation aligned with that of the first superconductor film 12. The second superconductor film 13 and the third superconductor film 15 may be, for example, Al(111) films, and the first insulator film 14 may be, for example, an AlN(111) film.

[0060] In the step of forming the third insulator film 18, the third insulator film 18 is formed by epitaxial growth on the (111) plane, which is the main surface of the third superconductor film 15. As a result, the third insulator film 18 is formed on the (111) plane of the third superconductor film 15 with its crystal orientation aligned with that of the third superconductor film 15. The third insulator film 18 may be, for example, an AlN (111) film.

[0061] Thereafter, as in the first embodiment, the steps of etching the JJ stack 20 (first time), patterning the first superconductor film 12, etching the JJ stack 20 (second time), forming the second insulator film 16, and forming the fourth superconductor film 17 are performed, thereby obtaining a quantum device having a structure similar to that of the quantum device 10 according to the first embodiment (see Figures 1A and 1B).

[0062] 9 is a cross-sectional view showing the structure near the interface between the substrate 11 and the first superconductor film 12. In the initial stage of crystal growth of a TiN film as the first superconductor film 12 on a Si substrate as the substrate 11, titanium silicide (TiSi X It has been reported that nucleation points 19 of TiSi are formed at the TiN / Si interface (T. Brat et al., J. Vac. Sci. Technol B 5, 1741 (1987)). X It is believed that the formation of nucleation points 19 enables the epitaxial growth of TiN films on Si substrates (R. Sun et al., IEEE Trans. Appl. Supercond, 25, 1101204 (2015)).

[0063] TiSi X The nucleation points 19 may also be a factor in reducing the flatness of the TiN / Si interface (particularly the Si surface side). In the patterning process of the first superconductor film 12, the first superconductor film 12 is partially removed, exposing the surface of the substrate 11 with reduced flatness. The reduction in the flatness of the surface of the substrate 11 may lead to an increase in TLS defects. The substrate 11 is used as a capacitor for a superconducting quantum bit, and a reduction in the flatness of the substrate 11 increases the dielectric loss of the superconducting quantum circuit, which may result in a limit to the lifetime (quantum coherence time) of the superconducting quantum bit.

[0064] To form a TiN film on a Si substrate by epitaxial growth, TiSi is required at the TiN / Si interface. X Although it is necessary to form nucleation points 19 of TiSi, it is preferable to moderately suppress their density. X The nucleation points 19 are likely to occur on chemically active crystal faces. In other words, by epitaxially growing a TiN film on a crystal face of Si with a relatively low surface energy, TiSi XIt is possible to suppress the density of nucleation points19. For example, first-principles simulations (G.-H. Lu et al., Surface Science 588, 61 (2005)) have shown that the surface energy of the Si(100)-2x1 reconstructed surface is 94.1 meV / Å. 2 °, and the surface energy of the Si(111)-7x7 reconstructed surface is 88.6 meV / Å 2 The TiN film is epitaxially grown on the (111) plane, which has the lowest surface energy among the crystal planes of the Si substrate. X It is possible to moderately suppress the density of the nucleation points 19.

[0065] As described above, the method for manufacturing a quantum device according to the second embodiment includes the steps of epitaxially growing a first superconductor film 12, a second superconductor film 13, a first insulator film 14, and a third superconductor film 15, each of which has a cubic crystal structure, on the (111) face of a substrate 11 having a cubic crystal structure.

[0066] According to the method for manufacturing a quantum device according to the second embodiment, TiSi X It is possible to suppress the density of the nucleation points 19. This makes it possible to ensure the flatness of the substrate 11 and to suppress the occurrence of TLS defects.

[0067] In the above description, the TiSi film generated when the first superconductor film 12 is a TiN film is used. X However, even when the first superconductor film 12 is an NbN film or a TaN film, nucleation points for alleviating the lattice mismatch with the substrate 11 may occur. Even in this case, the density of nucleation points can be suppressed by epitaxially growing the first superconductor film 12 on the (111) plane of the substrate 11.

[0068] [Third embodiment] 10 is a plan view showing an example of the configuration of a superconducting quantum circuit 100 according to the third embodiment of the disclosed technique. The superconducting quantum circuit 100 according to this embodiment has four quantum bits 1 as basic units 110. The superconducting quantum circuit 100 has a plurality of basic units 110 arranged in a lattice pattern on the surface of a substrate 130. The quantum bits 1 have Josephson junction devices, which are the quantum devices 10 according to the first embodiment described above.

[0069] FIG. 11 is an enlarged view of one of the basic units 110 shown in FIG. 10. The four quantum bits 1 that make up one basic unit 110 are arranged at positions corresponding to the four vertices of a square, and a readout electrode 40 is located at the center of the square. One readout electrode 40 is shared by the four quantum bits 1. A resonator 2 and a filter 3 are provided on each path from the four quantum bits 1 to the readout electrode 40. Each quantum bit 1 is connected to an adjacent quantum bit 1 via a capacitor 50. As a result, each quantum bit 1 creates a quantum entangled state with the adjacent quantum bit 1 to perform a quantum operation.

[0070] 12 is an equivalent circuit diagram of an operation block including one quantum bit 1, one resonator 2, and one filter 3. The quantum bit 1 forms a coherent two-level system using superconductivity and performs quantum operations using nonlinear energy. The quantum bit 1 has a transmon in which a Josephson junction element, which is the quantum device 10 according to the first embodiment described above, and a capacitor 5 are connected in parallel.

[0071] The resonator 2 is connected to the quantum bit 1 via a capacitor. The resonator 2 interacts with the quantum bit 1 to read out a response signal indicating the state of the quantum bit 1. The resonator 2 has a resonant circuit in which a superconducting inductor 6 and a capacitor 7 are connected in parallel. The filter 3 is connected to the resonator 2 via a capacitor. The filter 3 suppresses the signal at the frequency of the quantum bit 1 from relaxing to the readout port 14. Like the resonator 2, the filter 3 has a resonant circuit in which a superconducting inductor 8 and a capacitor 9 are connected in parallel.

[0072] A control electrode 41, a ground electrode 42, and a readout electrode 40 are connected to the operation block. A control signal for controlling the quantum bit 1 is input to the control electrode 41. Note that the control electrode 41 and the ground electrode 42 are not shown in Figures 10 and 11. The state of the quantum bit 1 is controlled by the control signal input to the control electrode 41. A response signal indicating the state of the quantum bit 1 is read out from the readout electrode 40. The ground electrode 42 is connected to an external ground potential. The ground potential applied to the ground electrode 42 is common to the ground of each part of the operation block.

[0073] FIG. 13 is a plan view showing an example of the pattern of a quantum bit 1. The quantum bit 1 includes a circular inner electrode 61 and an annular outer electrode 62 surrounding the inner electrode 61. That is, the quantum bit 1 has a concentric pattern. The quantum bit 1 has a quantum device 10 (Josephson junction device) provided between the inner electrode 61 and the outer electrode 62. One of the first superconductor film 12 constituting the lower line of the quantum device 10 and the fourth superconductor film 17 constituting the upper line is connected to the inner electrode 61, and the other is connected to the outer electrode 62. The inner electrode 61 also functions as one electrode of a capacitor 5, and the outer electrode 62 also functions as the other electrode of the capacitor 5. A transmon is formed by the quantum device 10 (Josephson junction device) and the capacitor 5 connected in parallel between the inner electrode 61 and the outer electrode 62.

[0074] FIG. 14 is a cross-sectional view showing an example of an implementation of a superconducting quantum circuit 100. The superconducting quantum circuit 100 has, for example, a silicon substrate as a substrate 130. The substrate 130 may also serve as the substrate 11 of the quantum device 10. A quantum bit 1, a resonator 2, and a filter 3 are provided on a first surface S1 of the substrate 130, and a control electrode 41 is provided on a second surface S2 of the substrate 130. The control electrode 41 is provided directly below the quantum bit 1. A control signal input from a control probe 121 abutting against the control electrode 41 acts on the quantum bit 1 via the substrate 130. The readout electrode 40 and the ground electrode 42 each have a through-electrode structure that penetrates the substrate 130. A response signal output via the resonator 2 and the filter 3 is read out by a readout probe 120 abutting against the readout electrode 40 from the second surface S2 side. A ground potential is applied to each part of the superconducting quantum circuit 100 via a ground probe 122 that is in contact with the ground electrode 42 from the second surface S2 side.

[0075] According to the superconducting quantum circuit 100 according to an embodiment of the disclosed technology, the occurrence of TLS defects and variations in characteristics in Josephson junction devices are suppressed, thereby improving performance regarding the lifetime (quantum coherence time) of the quantum bit 1 and suppressing the occurrence of errors.

[0076] The following additional notes are disclosed regarding the above first and second embodiments. (Appendix 1) a step of epitaxially growing a first superconductor film, a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, on a (100) or (111) face of a substrate having a cubic crystal structure; forming a stack including the second superconductor film, the first insulator film, and the third superconductor film by patterning the second superconductor film, the first insulator film, and the third superconductor film; patterning the first superconductor film using the laminate as a mask; wet-etching a side surface of the laminate after patterning the first superconductor film; forming a second insulating film covering the wet-etched side surface of the laminate; forming a fourth superconductor film in contact with the third superconductor film after forming the second insulator film; Including, the stack forms a Josephson junction; The first superconductor film has a lattice constant between the lattice constant of the substrate and the lattice constant of the second superconductor film. A method for manufacturing quantum devices.

[0077] (Appendix 2) forming a third insulator film covering a surface of the third superconductor film before forming the laminate; removing the third insulator film after forming the second insulator film and before forming the fourth superconductor film; The method of claim 1 further comprising:

[0078] (Appendix 3) The first superconductor film, the second superconductor film, the first insulator film, the third superconductor film, and the third insulator film are successively formed while the substrate is held in a vacuum chamber. The manufacturing method described in Appendix 2.

[0079] (Appendix 4) The lattice mismatch between the first superconductor film and the second superconductor film is less than 10%. 10. The method of any one of claims 1 to 3.

[0080] (Appendix 5) the substrate is a Si substrate, the second superconductor film and the third superconductor film are each an Al film; The first insulating film is an AlN film. 5. The method of any one of claims 1 to 4.

[0081] (Appendix 6) The first superconductor film is a TiN film, a NbN film, or a TaN film. 6. The method of any one of claims 1 to 5.

[0082] (Appendix 7) The second insulating film is an AlN film. 7. The method of any one of claims 1 to 6.

[0083] (Appendix 8) The fourth superconductor film is a NbTiN film, a Nb film, a Ta film, or a NbN film. 8. The method of any one of claims 1 to 7.

[0084] (Appendix 9) The second insulator film is formed while leaving the resist (30, FIG. 5B) used in the step of wet etching the side surface of the laminate, and the second insulator film deposited on the resist is removed together with the resist, thereby patterning the second insulator film. 10. The method of any one of claims 1 to 8.

[0085] (Appendix 10) a substrate having a cubic crystal structure; a first superconductor film having a cubic crystal structure provided on a (100) plane of the substrate; a laminate including a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, provided on a surface of the first superconductor film; a second insulating film covering a side surface of the laminate; a fourth superconductor film in contact with the third superconductor film; Includes the stack forms a Josephson junction; the first superconductor film has a lattice constant between the lattice constant of the substrate and the lattice constant of the second superconductor film; the <0100> direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the <0100> direction of the substrate; The <0001> direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the <0001> direction of the substrate. Quantum devices.

[0086] (Appendix 11) a substrate having a cubic crystal structure; a first superconductor film having a cubic crystal structure provided on a (111) plane of the substrate; a laminate including a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, provided on a surface of the first superconductor film; a second insulating film covering a side surface of the laminate; a fourth superconductor film in contact with the third superconductor film; Includes the stack forms a Josephson junction; the first superconductor film has a lattice constant between the lattice constant of the substrate and the lattice constant of the second superconductor film; the

[0111] direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the

[0111] direction of the substrate; The [11-2] direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the [11-2] direction of the substrate. Quantum devices.

[0087] (Appendix 12) The lattice mismatch between the first superconductor film and the second superconductor film is less than 10%. 12. The quantum device of claim 10 or 11.

[0088] (Appendix 13) the substrate is a Si substrate, the second superconductor film and the third superconductor film are each an Al film; The first insulating film is an AlN film. 13. The quantum device of any one of Supplementary Notes 10 to 12.

[0089] (Appendix 14) The first superconductor film is a TiN film, a NbN film, or a TaN film. 14. The quantum device of any one of Supplementary Notes 10 to 13.

[0090] (Appendix 15) The second insulating film is an AlN film. 15. The quantum device of any one of Supplementary Notes 10 to 14.

[0091] (Appendix 16) The fourth superconductor film is a NbTiN film, a Nb film, a Ta film, or a NbN film. 16. The quantum device of any one of Supplementary Notes 10 to 15. [Explanation of symbols]

[0092] 10 Quantum Devices 11 Circuit Board 12 First superconductor film 13 Second superconductor film 14 First insulating film 15 Third Superconductor Film 16 Second insulating film 17. Fourth Superconductor Film 18 Third insulating film 20 JJ laminate

Claims

1. a step of sequentially forming a first superconductor film, a second superconductor film, a first insulator film and a third superconductor film, each having a cubic crystal structure, on a (100) face or a (111) face of a substrate having a cubic crystal structure by an epitaxial growth method; forming a stack including the second superconductor film, the first insulator film, and the third superconductor film by patterning the second superconductor film, the first insulator film, and the third superconductor film; patterning the first superconductor film using the laminate as a mask; wet-etching a side surface of the laminate after patterning the first superconductor film; forming a second insulating film covering the wet-etched side surface of the laminate; forming a fourth superconductor film in contact with the third superconductor film after forming the second insulator film; Including, the stack forms a Josephson junction; The first superconductor film has a lattice constant between the lattice constant of the substrate and the lattice constant of the second superconductor film. A method for manufacturing quantum devices.

2. forming a third insulator film covering a surface of the third superconductor film before forming the laminate; removing the third insulator film after forming the second insulator film and before forming the fourth superconductor film; The method of claim 1 further comprising:

3. The first superconductor film, the second superconductor film, the first insulator film, the third superconductor film, and the third insulator film are successively formed while the substrate is held in a vacuum chamber. The method of claim 2.

4. The lattice mismatch between the first superconductor film and the second superconductor film is less than 10%. The method of claim 1.

5. the substrate is a Si substrate, the second superconductor film and the third superconductor film are each an Al film; The first insulating film is an AlN film. The method of claim 1.

6. The first superconductor film is a TiN film, an NbN film, or a TaN film. The method of claim 1.

7. The second insulating film is an AlN film. The method of claim 1.

8. The fourth superconductor film is a NbTiN film, a Nb film, a Ta film, or a NbN film. The method of claim 1.

9. The second insulating film is formed while leaving the resist used in the step of wet etching the side surface of the laminate, and the second insulating film deposited on the resist is removed together with the resist, thereby patterning the second insulating film. The method of claim 1.

10. a substrate having a cubic crystal structure; a first superconductor film having a cubic crystal structure provided on a (100) plane of the substrate; a laminate including a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, provided on a surface of the first superconductor film; a second insulating film covering a side surface of the laminate; a fourth superconductor film in contact with the third superconductor film; Includes the stack forms a Josephson junction; the first superconductor film has a lattice constant between the lattice constant of the substrate and the lattice constant of the second superconductor film; the [100] direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the [100] direction of the substrate; The [001] direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the [001] direction of the substrate. Quantum devices.

11. a substrate having a cubic crystal structure; a first superconductor film having a cubic crystal structure provided on a (111) plane of the substrate; a laminate including a second superconductor film, a first insulator film, and a third superconductor film, each having a cubic crystal structure, provided on a surface of the first superconductor film; a second insulating film covering a side surface of the laminate; a fourth superconductor film in contact with the third superconductor film; Includes the stack forms a Josephson junction; the first superconductor film has a lattice constant between the lattice constant of the substrate and the lattice constant of the second superconductor film; the [111] direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the [111] direction of the substrate; The [11-2] direction of each of the first superconductor film, the second superconductor film, the first insulator film, and the third superconductor film is parallel to the [11-2] direction of the substrate. Quantum devices.

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