Manufacturing method for semiconductor devices

Abstract

This invention provides a method for manufacturing a semiconductor device that eliminates the need for back-side tape and outer-peripheral tape protection during plating, thereby reducing man-hours and costs, and suppressing defects in processes after the plating process. [Solution] The method for manufacturing a semiconductor device includes: a first step of forming an element structure on the front surface of a first-conductivity semiconductor substrate 1; a second step of forming a gate insulating film 11 by thermal oxidation and depositing polysilicon to form a gate electrode 13; a third step of removing polysilicon 30 from the back surface of the semiconductor substrate 1 by thermal oxidation while leaving oxide films 31 formed on the back and sides of the semiconductor substrate 1; a fourth step of forming a surface electrode 16 on the element structure; and a fifth step of forming a plating film 20 on the surface electrode 16 while leaving oxide films 31 on the back and sides of the semiconductor substrate 1.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device.

Background Art

[0002] Conventionally, in the electroless plating process of Ni / Au on SiC, in order to prevent plating deposition other than the surface Al-Si electrode where plating is desired to be formed, a back tape and an outer peripheral tape are used to perform plating deposition prevention protection, and there is a method for manufacturing a semiconductor device in which a plating process is performed (see, for example, Patent Documents 1 and 2 below).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional method for manufacturing a semiconductor device, there are problems such as the man-hours for taping and peeling the back tape and the outer peripheral tape, and the cost of the tape material. In addition, the adhesive of the outer peripheral tape and the back tape flow out to the next process while attached, causing problems in the next process.

[0005] An object of this disclosure is to provide a method for manufacturing a semiconductor device that eliminates the problems caused by the above-described conventional technology, eliminates the need for back tape and outer peripheral tape protection during plating, reduces man-hours and costs, and suppresses problems in the processes after the plating process.

Means for Solving the Problems

[0006] To solve the above-mentioned problems and achieve the objectives of this disclosure, the method for manufacturing a semiconductor device according to this disclosure has the following features. First, a first step is performed to form an element structure on the front surface of a semiconductor substrate of a first conductivity type. Next, a second step is performed to form a gate electrode by forming a gate insulating film by thermal oxidation and depositing polysilicon. Next, a third step is performed to remove polysilicon from the back surface of the semiconductor substrate while leaving the oxide film formed on the back surface and sides of the semiconductor substrate by thermal oxidation. Next, a fourth step is performed to form a surface electrode on the element structure. Next, a fifth step is performed to deposit a plating film on the surface electrode while leaving the oxide film on the back surface and sides of the semiconductor substrate.

[0007] According to the disclosure described above, in order to prevent plating deposition, the plating film is formed while leaving the oxide film on the back and sides of the silicon carbide substrate. As a result, the plating film is not formed on the SiC exposed portion of the silicon carbide substrate. Therefore, tape protection on the back and sides during plating becomes unnecessary, reducing labor and material costs. [Effects of the Invention]

[0008] The semiconductor device manufacturing method described herein eliminates the need for back surface tape and outer edge tape protection during plating, thereby reducing man-hours and costs, and suppressing defects in processes after the plating process. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing the active structure of a semiconductor device according to an embodiment. [Figure 2] This is a flowchart showing the method for manufacturing a semiconductor device according to an embodiment. [Figure 3] This is a schematic cross-sectional view (part 1) showing the state of a semiconductor device during the manufacturing process according to the embodiment. [Figure 4] This is a schematic cross-sectional view (part 2) showing the semiconductor device according to the embodiment in the process of being manufactured. [Figure 5]This is a schematic cross-sectional view (part 3) showing the semiconductor device according to the embodiment in the process of being manufactured. [Figure 6] This is a schematic cross-sectional view (part 4) showing the state of a semiconductor device during the manufacturing process according to the embodiment. [Figure 7] This is a schematic cross-sectional view (part 5) showing the state of a semiconductor device during the manufacturing process according to the embodiment. [Figure 8] This is a flowchart showing a conventional method for manufacturing semiconductor devices. [Figure 9] This is a schematic cross-sectional view (part 1) showing the manufacturing process of a conventional semiconductor device. [Figure 10] A schematic cross-sectional view (part 2) showing the manufacturing process of a conventional semiconductor device. [Figure 11] This is a schematic cross-sectional view (part 3) showing the manufacturing process of a conventional semiconductor device. [Figure 12] This is a schematic cross-sectional view (part 4) showing the manufacturing process of a conventional semiconductor device. [Figure 13] This is a schematic cross-sectional view (part 5) showing the manufacturing process of a conventional semiconductor device. [Figure 14] This is a schematic cross-sectional view (part 6) showing the manufacturing process of a conventional semiconductor device. [Modes for carrying out the invention]

[0010] <Summary of the embodiments of this disclosure> To solve the above-mentioned problems and achieve the objectives of this disclosure, the method for manufacturing a semiconductor device according to this disclosure has the following features. First, a first step is performed to form an element structure on the front surface of a semiconductor substrate of a first conductivity type. Next, a second step is performed to form a gate electrode by forming a gate insulating film by thermal oxidation and depositing polysilicon. Next, a third step is performed to remove polysilicon from the back surface of the semiconductor substrate while leaving the oxide film formed on the back surface and sides of the semiconductor substrate by thermal oxidation. Next, a fourth step is performed to form a surface electrode on the element structure. Next, a fifth step is performed to deposit a plating film on the surface electrode while leaving the oxide film on the back surface and sides of the semiconductor substrate.

[0011] According to the disclosure described above, in order to prevent plating deposition, the plating film is formed while leaving the oxide film on the back and sides of the silicon carbide substrate. As a result, the plating film is not formed on the SiC exposed portion of the silicon carbide substrate. Therefore, tape protection on the back and sides during plating becomes unnecessary, reducing labor and material costs.

[0012] Furthermore, the method for manufacturing a semiconductor device according to this disclosure is characterized in that, in the above-mentioned disclosure, a sixth step is included, after the fifth step, in which the oxide film on the back and side surfaces of the semiconductor substrate is removed.

[0013] Furthermore, the method for manufacturing a semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the thickness of the oxide film on the back surface and side surface of the semiconductor substrate is 50 nm or more and 1000 nm or less.

[0014] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure is characterized in that, in the third step described above, polysilicon on the back surface of the semiconductor substrate is removed by dry etching, and the selectivity ratio in dry etching (etch rate of polysilicon / etch rate of SiO2) is 4.5 or more and 5.5 or less.

[0015] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure is characterized in that, in the fifth step described above, an electroless plating process is used to form a nickel (Ni) plating film and a gold (Au) plating film as the plating film.

[0016] <Knowledge forming the basis of this disclosure> First, we will explain the problems with conventional semiconductor device manufacturing methods. Figure 8 is a flowchart of a conventional semiconductor device manufacturing method. Figures 9 to 14 are schematic cross-sectional views showing the state of a conventional semiconductor device during manufacturing. In conventional semiconductor device manufacturing methods, first, n is added to the silicon carbide substrate 110. - Type drift region, p-type base region, p ++ Type contact area, n ++ An element structure consisting of a type source region and the like is formed (step S101). Next, a gate insulating film is deposited by thermal oxidation, and a gate electrode 113 is formed by depositing polysilicon (Poly-Si) (step S102). Next, the oxide film and polysilicon on the back surface formed by thermal oxidation and polysilicon deposition are removed (step S103). Next, an Al-Si film 116, which will become the surface electrode, is formed by sputtering or the like (step S104). The state up to this point is shown in Figure 9.

[0017] Next, the back tape 132 is applied to the entire back surface of the silicon carbide substrate 110 (step S105). This stage is shown in Figure 10. Next, the side tape 133 is applied to the outer circumference of the silicon carbide substrate 110 (step S106). This stage is shown in Figure 11.

[0018] Next, a nickel (Ni) plating layer is laminated over the entire front surface of the silicon carbide substrate 110, and then a gold (Au) plating layer is laminated over the entire surface of the nickel plating layer to form a plating film 120 (step S107). This stage is shown in Figure 12. Next, the side tape 133 is peeled off from the outer periphery of the silicon carbide substrate 110 (step S108). This stage is shown in Figure 13. Next, the back tape 132 is peeled off from the back surface of the silicon carbide substrate 110 (step S109). This stage is shown in Figure 14. If, for example, a UV (Ultra Violet) film is used as the back tape 132 and side tape 133, the back tape 132 and side tape 133 can be peeled off by irradiating them with UV light.

[0019] If silicon carbide (SiC) is directly subjected to nickel (Ni) / gold (Au) electroless plating, a Ni / Au film with poor adhesion is formed, and this film may detach into the plating tank, potentially leading to a reduction in the lifespan of the plating tank and a decrease in plating quality, such as abnormal plating deposition. For this reason, conventionally, when performing Ni / Au electroless plating on SiC, protective measures are taken to prevent plating deposition on surfaces other than the Al-Si electrode where plating is to be formed, using back tape 132 and outer tape 133. After plating, ultraviolet (UV) light is irradiated to remove the back tape 132 and outer tape 133.

[0020] However, conventional semiconductor device manufacturing methods have the problem of incurring labor costs for applying and removing back tape 132 and outer tape 133 to protect the back and sides, as well as the cost of materials for back tape 132 and outer tape 133. Furthermore, there is the problem that the adhesive of the outer tape 133 may remain attached and flow into the next process, causing errors due to steps during glass mounting in the WSS (wafer support system). In addition, there is the problem that the back tape 132 may remain attached and flow into the subsequent process, causing problems that prevent conductivity from being obtained during testing and thus prevent measurement of electrical characteristics.

[0021] Preferred embodiments of the method for manufacturing a semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p mean that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p mean that they have a higher and lower impurity concentration than layers or regions without these signs, respectively. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. It is preferable to include up to 5% in the description of the same or equivalent components to account for manufacturing variations.

[0022] (Embodiment) The semiconductor device according to this disclosure is constructed using a wide-bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated using silicon carbide (SiC) as the wide-bandgap semiconductor will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example. Figure 1 is a cross-sectional view showing the active structure of the silicon carbide semiconductor device according to the embodiment.

[0023] The silicon carbide semiconductor device 70 according to this embodiment comprises an active region 50 and an edge termination region (not shown) surrounding the active region 50, on a semiconductor substrate made of silicon carbide (hereinafter referred to as the silicon carbide substrate (semiconductor substrate (semiconductor chip))). The active region 50 is the region through which current flows when it is in the ON state. The edge termination region is the region that mitigates the electric field on the front surface side of the substrate in the drift region and maintains the breakdown voltage.

[0024] As shown in Figure 1, the silicon carbide substrate is made of n + Mold support substrate (n + On the front surface of a silicon carbide substrate (a first-conductivity semiconductor substrate) 1, n made of silicon carbide is placed. - Type drift region 2 and n - n of the drift region 2 +On the surface of the silicon carbide substrate 1 on the side opposite to one side, there is a p-type base region 5 made of silicon carbide. n + The n-type silicon carbide substrate 1 functions as a drain region. Also, n - Between the n-type drift region 2 and the n + type silicon carbide substrate 1, for example, n + a buffer layer or the like for reducing the growth of crystal defects from the n-type silicon carbide substrate 1 may be provided.

[0025] n + The n-type silicon carbide substrate 1 is a single-crystal silicon carbide substrate. n - The n-type drift region 2 is n + at a lower impurity concentration than the n-type silicon carbide substrate 1. n - The n-type drift region 2 reaches up to the p-type base region 5 and contacts the p-type base region 5 and the p + type sub-region 4 described later, and reaches up to a trench 25 described later in a direction parallel to the front surface of the semiconductor substrate and contacts the gate insulating film 11. n - The n-type drift region 2, for example, has an impurity concentration of 5×10 16 cm -3 or less and a thickness of 5.0 μm or more.

[0026] Also, n - An n-type high-concentration region (not shown) may be provided between the n-type drift region 2 and the p-type base region 5. When the n-type high-concentration region is provided, in the p + type sub-regions 4 adjacent to each other described later, they contact these regions, extend in a direction parallel to the front surface of the semiconductor substrate and reach up to the trench 25, and contact the gate insulating film 11. The n-type high-concentration region contacts the p-type base region 5 on the upper surface and the n - type drift region 2 on the lower surface. The impurity concentration of the n-type high-concentration region is n + lower than that of the n-type silicon carbide substrate 1 and n - higher than that of the n-type drift region 2.

[0027] n +A drain electrode 17, which serves as a back electrode, is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide substrate) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the drain electrode 17.

[0028] A trench structure is formed on the first main surface side (p-type base region 5 side) of the silicon carbide substrate. Specifically, the trench 25 is n + From the surface opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide substrate), the n-type base region 5 penetrates through the n-type base region 5. - The drift region 2 (or the n-type high-concentration region if one is provided) is reached.

[0029] A gate insulating film 11 is formed along the inner wall of the trench 25, at the bottom and side walls of the trench 25, and a gate electrode 13 is formed inside the gate insulating film 11 within the trench 25. The gate insulating film 11 makes the gate electrode 13 n - It is insulated from the type drift region 2 and the p-type base region 5. A portion of the gate electrode 13 may protrude from above the trench 25 (the side on which the source electrode pad 16, described later, is provided) toward the source electrode pad 16.

[0030] n - n of the drift region 2 + On the surface layer opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide substrate), the upper p + A type subregion 4a is provided. Upper part p + The molded subregion 4a is provided, for example, between the trenches 25. Also, n - Within the drift region 2, upper p + Lower part p in contact with the bottom of subregion 4a + A molded portion area 4b is provided. Also, at the bottom of the trench 25, p + A mold region 26 is provided. p is in contact with the bottom of the trench 25. + The mold region 26 is located opposite the bottom of the trench 25 in the depth direction (from the source electrode pad 16 to the back electrode). The upper part between the trenches 25 p +Type subregion 4a and lower p + The type subregion 4b is combined with p + This becomes type subregion 4.

[0031] p + The width of the mold region 26 is the same as or wider than the width of the trench 25. Also, the lower part p + The width of type subregion 4b is the upper part p + The width of the mold subregion 4a is the same as or wider than that. The bottom of the trench 25 is p + It may reach the type region 26, or the p-type base region 5 and p + n sandwiched between type region 26 - It may be located within the type drift region 2.

[0032] Inside the p-type base region 5, on the first main surface side of the silicon carbide substrate, n ++ Type source region 7 and p ++ A type contact region 6 is selectively provided. Also, n ++ Type source region 7 and p ++ The contact regions 6 are in contact with each other.

[0033] The interlayer insulating film 14 is provided over the entire surface of the first main surface side of the silicon carbide substrate, covering the gate electrode 13 embedded in the trench 25. The interlayer insulating film 14 is composed of NSG and BPSG. Contact holes are opened in the interlayer insulating film 14, and at the bottom of the contact holes, n ++ Type source region 7 and p ++ A source electrode 18 is provided that is in contact with the type contact region 6. The source electrode 18 is n ++ Type source region 7 and p ++It contacts the type contact region 6. The source electrode 18 is electrically insulated from the gate electrode 13 by an interlayer insulating film 14. A source electrode pad (main electrode) 16 made of an Al-Si film is provided on the source electrode 18. The Al-Si film may be an Al-Si alloy. A barrier metal 15 may be provided between the source electrode 18 and the interlayer insulating film 14 to prevent the diffusion of metal atoms, etc., from the source electrode pad (main electrode) 16 side to the gate electrode 13 side. As another example, the barrier metal 15 may not be provided on the interlayer insulating film 14 but only inside the contact hole, or the barrier metal 15 may not be provided at all. Furthermore, as yet another example, the source electrode 18 may not be provided and the barrier metal 15 may be n ++ Type source region 7 and p ++ It may be in contact with the contact area 6.

[0034] A plating film 20 is provided on the upper part of the source electrode pad 16. The plating film 20 may be selectively provided at the openings of a protective film (not shown) provided on the upper part of the source electrode pad 16. Solder (not shown) may be selectively provided on the surface side of the plating film 20. The plating film 20 is, for example, a Ni / Au plating film. Pin-shaped electrodes (not shown), which are wiring materials for extracting the potential of the source electrode 18 to the outside, are provided on the solder. The pin-shaped electrodes have a needle shape and are joined to the source electrode pad 16 in an upright position. In Figure 1, only two MOS gate (insulating gate consisting of metal-oxide-semiconductor) structures are shown in the active region 50, but many more MOS gate structures may be arranged in parallel.

[0035] (Method for manufacturing a silicon carbide semiconductor device according to an embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to the embodiment will be described. Figure 2 shows a flowchart of the method for manufacturing a silicon carbide semiconductor device according to the embodiment. Figures 3 to 7 are schematic cross-sectional views showing the state of the semiconductor device during manufacturing according to the embodiment. In Figures 3 to 7, the detailed element structure within the silicon carbide substrate 10, the interlayer insulating film 14, and the barrier metal 15 are omitted.

[0036] First, the semiconductor device structure is formed as follows (Step S1: First step). + On the front surface of the silicon carbide substrate 1, n - Type drift region 2 is epitaxially grown. Next, n - A p-type base region 5 is epitaxially grown on the front surface of the type drift region 2. The p-type base region 5 may also be formed by ion implantation. - An n-type high-concentration region may be formed between the p-type drift region 2 and the p-type base region 5.

[0037] Next, by photolithography and ion implantation of p-type impurities, the p-type region (p + Type subregion 4, p ++ Type contact area 6, p + A n-type region (26) is formed, and n is produced by photolithography and ion implantation of n-type impurities. ++ A type source region 7 is formed. Next, n - A heat treatment is performed to activate the impurities ion-implanted in the type drift region 2 and the p-type base region 5. This heat treatment for impurity activation may be performed after each impurity ion implantation or all at once.

[0038] Next, n ++ A trench-forming mask having predetermined openings is formed on the surface of the mold source region 7 by photolithography, for example, with an oxide film. Next, dry etching is performed. ++ The source region 7 and the base region 5 of type p penetrate through, + A trench 25 is formed that reaches the mold subregion 4. Next, the trench-forming mask is removed.

[0039] After forming the trench 25, isotropic etching may be performed to remove damage to the trench 25, or sacrificial oxidation may be performed to round the corners of the bottom and opening of the trench 25. Either isotropic etching or sacrificial oxidation may be performed alone. Alternatively, sacrificial oxidation may be performed after isotropic etching. This allows for a clean surface of silicon carbide, and by rounding the corners, electric field concentration at the bottom and opening of the trench 25 can be suppressed.

[0040] Next, n ++ Type source region 7 and p ++ A gate insulating film 11 is formed along the surface of the mold contact region 6 and the bottom and side walls of the trench 25. This gate insulating film 11 may be formed by thermal oxidation at a temperature of about 1300°C in an oxygen-containing gas atmosphere. Alternatively, this gate insulating film 11 may be formed by deposition by a chemical reaction such as high-temperature oxide (HTO).

[0041] Next, polysilicon doped with, for example, phosphorus by CVD is provided on the gate insulating film 11. This polysilicon may be formed to fill the trench 25. The gate electrode 13 is formed by patterning this polysilicon by photolithography and leaving it inside the trench 25 (Step S2: Second step).

[0042] During the thermal oxidation process for forming the gate insulating film 11, an oxide film 31 is formed on the back and sides of the silicon carbide substrate 10. During the deposition of polysilicon for forming the gate electrode 13, a backside polysilicon 30 is formed on the back of the silicon carbide substrate 10. This state is shown in Figure 3.

[0043] Next, the polysilicon 30 on the back surface is removed (Step S3: Third step). Here, only the polysilicon 30 on the back surface is removed by dry etching, leaving the oxide film 31. The state up to this point is shown in Figure 4. In the dry etching to remove the polysilicon 30 on the back surface, by setting the selectivity ratio (etch rate of polysilicon / etch rate of SiO2) to about 5, for example, between 4.5 and 5.5, it is possible to remove only the polysilicon 30 on the back surface while leaving the oxide film 31. The selectivity ratio can also be improved by lowering the RF output. The oxide film 31 preferably has a thickness of 50 nm to 1000 nm in order to prevent plating deposition. Polysilicon may also be formed on the side walls of the silicon carbide substrate 10, in which case the polysilicon on the side walls may be removed in the same way.

[0044] Here, when a plating process was performed on a wafer with an oxide film 31 with a thickness of 1000 nm, no plating film growth was observed on the oxide film 31 surface (back and side), confirming that the oxide film 31 functions as a mask to prevent the deposition of plating.

[0045] Next, a film of, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 11 and the gate electrode 13, thereby forming an interlayer insulating film 14. Next, the interlayer insulating film 14 and the gate insulating film 11 are patterned by photolithography. ++ Type source region 7 and p ++ A contact hole is formed, exposing the type contact region 6. Next, a conductive film, such as nickel, which will become the source electrode 18, is deposited inside the contact hole and on the interlayer insulating film 14, for example, by sputtering. Then, heat treatment at about 1000°C is performed to selectively react the conductive film with silicon carbide, and the unreacted portion of the conductive film is selectively removed, leaving the source electrode 18 only inside the contact hole. ++ Type source region 7 and p ++ The contact area 6 and the source electrode 18 are brought into contact.

[0046] Next, a Ti film is deposited on the surface of the source electrode 18 and the interlayer insulating film 14, and then a TiN film is deposited on the surface of the Ti film to form a barrier metal. Next, a metal film that will become the source electrode pad 16 is deposited on the source electrode 18 and the interlayer insulating film 14 on the front surface of the silicon carbide semiconductor substrate, for example by sputtering. The Al-Si film is, for example, aluminum (Al-Si) containing silicon at a ratio of 1%. The source electrode pad 16 may also be formed from an Al metal film other than an Al film or an Al-Si film. Next, the Al-Si film is patterned to form the source electrode pad 16 that will become the surface electrode (Step S4: 4th step). The state up to this point is shown in Figure 5. Conductive films for forming surface electrodes, etc., are not formed on the side walls and back surface of the silicon carbide substrate 10. For example, when depositing a metal film by sputtering, the back surface of the silicon carbide substrate 10 is fixed to the stage of the apparatus and therefore not deposited, and the sides are also covered by the apparatus cover and therefore not deposited.

[0047] Next, the Al-Si film surface is pre-treated for plating in an etching tank or zincate treatment tank. Then, a plating film 20 is formed on the Al-Si film by electroless Ni plating and Au plating (Step S5: 5th step). The state up to this point is shown in Figure 6.

[0048] Next, a glass support material is attached to the surface of the silicon carbide substrate 10, and the oxide film 31 on the back and sides of the silicon carbide substrate 10 is removed by dry etching or wet etching (step S6). The state up to this point is shown in Figure 7. Since the presence of the oxide film 31 on the back surface makes back grinding (BG) of the wearer difficult, the oxide film 31 on the back surface is removed before the BG process. For this reason, it is not necessary to remove the oxide film 31 on the sides.

[0049] In this embodiment, in order to prevent plating deposition, the plating film 20 is formed while leaving the oxide film 31 on the back and sides of the silicon carbide substrate 10. As a result, the plating film 20 is not formed on the SiC exposed portion of the silicon carbide substrate 10. Therefore, tape protection on the back and sides during plating becomes unnecessary, reducing labor and material costs. Furthermore, while it is physically impossible to completely prevent plating from penetrating the tape with tape protection, protection by the oxide film 31 has a higher function as a plating deposition prevention agent compared to protection with tape, enabling improved quality.

[0050] Furthermore, since the outer perimeter tape is not attached to the side surface of the silicon carbide substrate 10, it is possible to prevent the problem of adhesive residue remaining when the outer perimeter tape is peeled off, which can cause errors due to steps during the subsequent glass mounting of the WSS. Also, since the back surface tape is not attached to the back surface of the silicon carbide substrate 10, it is possible to prevent the problem of the back surface tape remaining attached and flowing into subsequent processes, which can prevent conductivity from being established during testing and thus prevent the measurement of electrical characteristics.

[0051] Next, the front surface of the silicon carbide semiconductor substrate is covered and protected with a protective film (not shown), and then n + By polishing the silicon carbide substrate 1 from the back side (BG: Back Grind), n + The silicon carbide substrate 1 may be thinned to achieve the desired product thickness.

[0052] Next, a gate pad (not shown), a passivation film (not shown), and a drain electrode 17 are formed using a general method. The portion of the source electrode pad 16 that is exposed to the opening of the passivation film becomes the source pad. After that, the semiconductor wafer is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 70 shown in Figure 1.

[0053] As described above, according to the embodiment, in order to prevent plating deposition, the plating film is formed while leaving the oxide film on the back and sides of the silicon carbide substrate. As a result, the plating film is not formed on the SiC exposed portion of the silicon carbide substrate. Therefore, tape protection on the back and sides during plating becomes unnecessary, and labor and material costs can be reduced.

[0054] In summary, this disclosure can be modified in various ways without departing from the spirit of this disclosure, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc., can be set in various ways according to the required specifications. Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, this disclosure also holds true if the first conductivity type is p-type and the second conductivity type is n-type. In the case of Si (silicon) wafers, if the same process flow as for SiC wafers is used, it is possible to form an oxide film mask and prevent plating deposition. Furthermore, although the embodiments of this disclosure were described using a trench-type MOSFET as an example, it is not limited to this and can be applied to various semiconductor devices such as planar-type MOSFETs, MOS-type semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), and diodes. [Industrial applicability]

[0055] As described above, the method for manufacturing a semiconductor device according to this disclosure is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of symbols]

[0056] 1 n + Silicon carbide substrate 2 n - Type drift region 4 p + type subregion 4a upper p + type subregion 4b lower p + type subregion 5 p-type base region 6 p ++ Type Contact Area 7 n ++ Type source area 10, 110 silicon carbide substrate 11 Gate insulating film 13 gates 14 Interlayer insulating film 15 Barrier Metal 16. Source electrode pad (Al-Si film) 17 Drain electrode 18 Source electrodes 20, 120 Plating film 25 Trench 26 p + type area 30, 130 Polysilicon on the back 31 Oxide film 50 active area 70 Silicon Carbide Semiconductor Devices 132 Backing tape 133 Side tape

Claims

1. A first step of forming an element structure on the front surface of a first-conductivity semiconductor substrate, A second step involves forming a gate insulating film by thermal oxidation and then depositing polysilicon to form a gate electrode, A third step involves removing polysilicon from the back surface of the semiconductor substrate while leaving the oxide film formed on the back surface and sides of the semiconductor substrate by the thermal oxidation, A fourth step involves forming a surface electrode on the element structure, A fifth step involves forming a plating film on the surface electrode while leaving the oxide film on the back and sides of the semiconductor substrate, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

2. After the fifth step, The method for manufacturing a semiconductor device according to claim 1, further comprising a sixth step of removing the oxide film on the back and side surfaces of the semiconductor substrate.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that the thickness of the oxide film on the back surface and side surface of the semiconductor substrate is 50 nm or more and 1000 nm or less.

4. In the third step described above, The polysilicon on the back surface of the semiconductor substrate is removed by dry etching, and the selectivity ratio in dry etching (polysilicon etching rate / SiO 2 A method for manufacturing a semiconductor device according to claim 1, characterized in that the etching speed is 4.5 or more and 5.5 or less.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that in the fifth step, an electroless plating process is used to form a nickel (Ni) plating film and a gold (Au) plating film as plating films.

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