Semiconductor equipment

Abstract

To obtain a small semiconductor device with high voltage resistance, which combines a switching element with a protective element to protect it. [Solution] The device comprises a first n-type semiconductor region 11 formed on the surface side of a p-type semiconductor substrate 10, which serves as a common path for the current flowing to the switching element and the protection element; a common n-type contact region 12 formed on the first semiconductor region 11 with a high impurity concentration and connected to a common electrode 21 that serves as both the first main electrode and the first electrode on the protection element side; a second p-type semiconductor region 13 and a third p-type semiconductor region 14 locally formed in the first semiconductor region 11 at a location spaced apart from the common contact region 12; and a fourth n-type semiconductor region 15 locally formed in the second semiconductor region 13 in a plan view, with the second main electrode 22 connected to the fourth semiconductor region 15 and the second electrode 26 on the protection element side provided inside the third semiconductor region 14.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device comprising a lateral switching element and a protective element thereof. [Background technology]

[0002] Lateral LDMOS (laterally diffused MOS) transistors, which have a drift layer through which the on-current flows in the plane direction of the semiconductor layer, are preferred as power semiconductor elements because they can achieve high breakdown voltages. In this case, the length of the region where breakdown voltage should be ensured (high breakdown voltage region) along the electric field direction is set in the in-plane direction of the semiconductor layer so that breakdown voltage is ensured because the electric field strength is particularly high when the transistor is off.

[0003] Furthermore, as described in Patent Document 1, for example, a technique is used in which a protective element (e.g., a diode) is connected between the source and drain of the LDMOS, and when a surge voltage exceeding the withstand voltage is applied to the LDMOS, the protective element is broken down instead of the LDMOS to bypass the current and prevent damage to the LDMOS and the electrical circuit connected to it.

[0004] In this case, the breakdown voltage of this protective element (diode) is set high in correspondence with that of the LDMOS. For this reason, this diode is also horizontal, and like the LDMOS, a high breakdown voltage region is set to a certain size in the diode as well. In the technology described in Patent Document 1, an LDMOS is formed in one region on a plane, and the region constituting the diode is formed surrounding this LDMOS. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-319072 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As described above, in order to form both the LDMOS and the lateral protection element on a common semiconductor substrate and to achieve high breakdown voltage for both, a large total area is required for the combined region occupied by both. Alternatively, if the area is limited, the current capacity flowing through the LDMOS or the protection element cannot be increased, resulting in a decrease in protection function. For this reason, it has been difficult to obtain a small semiconductor device with high breakdown voltage that combines a switching element and a protection element to protect it.

[0007] This disclosure has been made in view of the aforementioned problems and aims to provide a semiconductor device that solves the above-mentioned problems. [Means for solving the problem]

[0008] This disclosure has the following structure in order to solve the above-mentioned problems. The semiconductor device of this disclosure is a semiconductor device formed on a semiconductor substrate, comprising: a switching element whose on / off state is controlled between a first main electrode on the high-potential side and a second main electrode on the low-potential side; and a protection element that, when the switching element is off, bypasses current between a first electrode on the high-potential side and a second electrode on the low-potential side of the protection element, wherein the semiconductor device comprises: a first semiconductor region of a second conductivity type opposite to the first conductivity type formed on the surface side of the semiconductor substrate of a first conductivity type; a common electrode that serves as both the first main electrode and the first electrode on the protection element side; and a common contact region of the second conductivity type formed locally on the first semiconductor region with a high impurity concentration and connected to the common electrode, in plan view The device comprises a second semiconductor region of a first conductivity type locally formed in the first semiconductor region spaced apart from the common contact region, a third semiconductor region of a first conductivity type locally formed in the first semiconductor region spaced apart from the common contact region and the second semiconductor region in a plan view, and a fourth semiconductor region of a second conductivity type locally formed in the second semiconductor region in a plan view, wherein one of the second semiconductor region and the third semiconductor region is formed so as to surround the other on the outside as seen from the common contact region, the fourth semiconductor region is connected to the second main electrode, and the third semiconductor region is connected to the second electrode on the protection element side. In a plan view, the fifth semiconductor region of the second conductivity type is provided within the third semiconductor region, and the second electrode on the protection element side may be connected to the fifth semiconductor region and the third semiconductor region. In a plan view, the second semiconductor region may be formed in an annular shape surrounding the common contact region. The other of the second and third semiconductor regions may be the third semiconductor region. The third semiconductor region may be divided into multiple sections in a planar view. The other of the second and third semiconductor regions is the third semiconductor region, and the first semiconductor region may be formed below the third semiconductor region, and deeper than the inside of the third semiconductor region in a plan view. The switching element may include a first control electrode formed on the second semiconductor region that controls the on / off state between the first main electrode and the second main electrode, and a second control electrode connected to the second semiconductor region. The device may also include an inter-element field plate that is electrically connected to any of the first control electrode, the second control electrode, or the third semiconductor region, and faces the surface of the first semiconductor region between the second and third semiconductor regions in a plan view, via an insulating layer. The first of the second and third semiconductor regions may be the third semiconductor region. The first semiconductor region does not necessarily have to be formed outside of the second semiconductor region or the third semiconductor region. [Effects of the Invention]

[0009] As described above, this disclosure provides a compact semiconductor device with high voltage resistance, which combines a switching element with a protective element to protect it. [Brief explanation of the drawing]

[0010] [Figure 1] This is a circuit diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 3] This is a top view showing the configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 4] This is a cross-sectional view showing the configuration of a first modified example of a semiconductor device according to an embodiment of the present disclosure. [Figure 5] This is a cross-sectional view showing the configuration of a second modified example of a semiconductor device according to an embodiment of the present disclosure. [Figure 6] This is a cross-sectional view showing the configuration of a third modified example of a semiconductor device according to an embodiment of the present disclosure. [Figure 7] This is a top view showing the configuration of a fourth modified example of the semiconductor device according to the embodiment of the present disclosure. [Figure 8] This is a top view showing the configuration of a fifth modified example of the semiconductor device according to the embodiment of the present disclosure. [Figure 9] This is a circuit diagram showing the configuration of a sixth modified example of the semiconductor device according to the embodiment of the present disclosure. [Figure 10] This is a circuit diagram showing the configuration of a seventh modified example of the semiconductor device according to the embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] The following describes a semiconductor device that is an embodiment of this disclosure. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the lengths of each part, etc., may differ from reality. Therefore, specific dimensions should be determined by referring to the following explanation. It should also be noted that there are parts where the relationships and ratios of dimensions differ between drawings. Furthermore, the embodiments shown below are illustrative examples of devices for realizing the technical idea of ​​this disclosure, and the technical idea of ​​this disclosure does not limit the shape, structure, arrangement, etc. of the components to those described below. Various modifications can be made to the embodiments of this invention within the scope of the claims. In this disclosure, terms such as "top" and "bottom" are used for convenience of description, and even if they are provided on the side surface, if they are substantially identical to the constituent elements of this disclosure, they fall within the scope of the rights of this disclosure. Also, "top" includes not only cases where it is formed in contact with the object, but also cases where it is formed through another layer. Furthermore, in this disclosure, "connection" is not limited to direct connection; even if a connection is made by interposing something such as a resistor, if it is substantially identical to the constituent elements of this disclosure, it falls within the scope of the rights of this disclosure.

[0012] Figure 1 is a circuit diagram showing the configuration of this semiconductor device 1. Here, an n-channel MOSFET (LDMOS) element (switching element) T1 and an npn bipolar transistor element (protection element) T2 are formed on a common semiconductor substrate. Here, the n-type layer (drift layer) connected to the drain (D: high-potential side electrode (first main electrode)) of element T1 and the collector layer (n-type layer) connected to the collector (C) of element T2 are common. The source (S: low-potential side electrode (second main electrode)), gate (G: first control electrode), and related structures are the same as those of a normal MOSFET. The potential VS of the source (S) is usually set to ground potential (GND), and when the potential VD of the drain (D) is set to a positive potential, the on / off switching of the current between the drain (D) and source (S) is controlled by the potential VG of the gate (G).

[0013] In this case, the potential VBG of the body layer (BG) of element T1 (MOSFET) may be equal to VS, but it may also be controlled independently of VS by applying a predetermined potential to the back gate electrode (second control electrode). This allows for adjustment of the characteristics of element T1.

[0014] Furthermore, element T2 is an npn bipolar transistor (npn transistor), and its collector (C: first electrode on the protection element side) is connected to the drain (D) of element T1, so the aforementioned VD is applied. Also, the potential of its emitter (E: second electrode on the protection element side) is set to VISO, the potential of the outer periphery of the element, which is close to the ground potential, similar to VBG. However, since the p-type layer that forms the base (B) and the n-type layer that forms the emitter (E) are actually short-circuited by wiring, element T2 actually operates with two terminals. With the VD and VISO potential settings described above, element T2 is normally off, but when VD becomes large, element T2 turns on and can flow a large current. This operation is similar to the breakdown in parasitic transistor operation. The characteristics of element T2, such as the on-voltage, will be described later in n + Layer 17 and n - Spacing of layer 11, p - Layer 14 and n -The impurity concentration in layer 11 and settings such as VISO can be finely adjusted.

[0015] If a positive voltage, such as a high-voltage surge, is applied to the drain (D) side while element T1 is off, element T1 may break down. The large current that flows during this breakdown is undesirable because it can cause damage to element T1 and the electrical circuit connected to it. By making the timing of element T2 turning on earlier than the timing of element T1's breakdown, the breakdown of element T1 can be suppressed. In other words, element T2 can be used as a protective element to protect element T1.

[0016] Note that VBG in element T1 and VISO in element T2 may be common (dashed line in the figure), or they may be adjusted individually. This can be easily achieved by connecting the wires. Furthermore, as will be described later, it is also possible to implement a structure in Figure 1 where either VBG or VISO automatically becomes GND.

[0017] Here, on the element T1 side, the planar region of the semiconductor layer where the electric field strength is high when off is the region between the gate (G) and drain (D), where the potential difference between its ends is particularly large. On the element T2 side, the region where the electric field strength is high when off is the region between the collector (C) and base (B). Therefore, in order to achieve high breakdown voltage, it is necessary to make each of these regions wide along the direction of the electric field. In Figure 1, the drain (D) of element T1 and the collector (C) of element T2 are common (potential VD), and in this semiconductor device 1, these regions (the breakdown voltage securing region J described later) are formed to overlap in a planar view. Therefore, in this semiconductor device 1, even when the breakdown voltage of elements T1 and T2 is set high, the overall size can be reduced.

[0018] Figure 2 is a cross-sectional view showing the structure of this semiconductor device 1. Here, a cross-section of the portion where the elements T1 and T2 in FIG. 1 are formed is shown, and these are formed on a p-type substrate (semiconductor substrate) 10 which is p-type (first conductivity type). Here, the range of the region (switching element region R1) functioning as the element T1, the region (protection element region R2) functioning as the element T2, and the breakdown voltage ensuring region J are also shown above. In this structure, the case where there is no broken line in FIG. 1 (when VBG in the element T1 and VISO in the element T — 2 are independently controlled) is described.

[0019] In the figure, an n - layer (first semiconductor region) 11 of low concentration and n-type (second conductivity type) is widely formed in the shape shown, and both the elements T1 and T2 in FIG. 1 are formed using this n - layer 11. In FIG. 2, the right side in the n - layer 11 is the low potential side (side close to the ground potential), and the left side is the high potential (for example, +1000 V or more) side. The depth of the n - layer 11 is not uniform, being deep on the high potential side and the low potential side, and shallow with a constant depth in the middle. The structure in which the n - layer 11 is deep on the high potential side and shallower with a constant depth on the lower potential side than this is effective in increasing the breakdown voltage of the n - layer 11. However, such a depth direction profile on the high potential side is set as appropriate.

[0020] In the figure, on the left side (high potential side) surface of the n - layer 11, an n + layer (common contact region) 12 which is a high concentration n-type layer is formed. The n + layer 12 functions as a contact layer in the drain (D) region of T1 and the collector (C) region of T2 in FIG. 1, and its potential is VD in FIG. 1. On the other hand, on the right side (low potential side) surface of the n - layer 11 in the figure, a p - layer (second semiconductor region) 13 and a p - layer (third semiconductor region) 14 are formed separated from each other, and the p- Layer 13 is used in element T1 and is shown on the right side of the figure, p - Layer 14 is used in element T2 and is provided on the left side in the figure. - The surface of layer 13 has a high concentration of n-type n + Layer (fourth semiconductor region) 15 is a high-concentration p-type + Layer 16 is locally formed on the left and right sides of the figure. On the other hand, p - On the surface of layer 14, similarly n + Layer (5th semiconductor region) 17, p + Layer 18 is locally formed on the left and right sides of the figure.

[0021] p - Layer 13 functions as the body layer of element T1 (MOSFET), p - The potential of layer 13 is considered to be VBG in Figure 1. + Layer 15 functions as the source (S) region of element T1, n + The potential of layer 15 is given by VS in Figure 1. + Layer 16 is formed for contact with the p-layer 13 which will be the body layer, + The potential of layer 16 is set to VBG. On the other hand, p - Layer 14 functions as the base (B) region of element T2, n + Layer 17 functions as the emitter (E) region of T2. + Layer 18 is the base p - Formed for contact with layer 14, p + layer 18, n + The potential of layer 17 is defined as VISO in Figure 1.

[0022] An interlayer insulating layer 20 made of a silicon oxide film is formed on the semiconductor substrate 10 on which this structure is formed, and each wiring is connected to the above layers through openings formed in the interlayer insulating layer 20, thereby realizing the circuit configuration shown in Figure 1. First, n + The drain electrode (common electrode) 21 of element T1 is connected to layer 12. As described above, the drain electrode 21, whose potential is VD in the figure, also serves as the collector electrode of element T2. +A source electrode (second main electrode) 22 with a potential of VS is connected to layer 15, and to its right in the figure, p + A back gate electrode (second control electrode) 23, whose potential is set to VBG, is connected to layer 16. As described above, in this semiconductor device 1, VS, VBG, and VISO in Figure 1 are controlled independently. Generally, the potential of the p-type substrate 10 is set to GND.

[0023] Also, n + n - p up to the point where layer 11 is exposed - On the surface of layer 13, a gate electrode (first control electrode) 25 is formed opposite via a gate oxide film 24 that is thinner than the interlayer insulating layer 20, with a potential of VG as shown in Figure 1. This structure forms a MOSFET element T1 that operates using a drain electrode 21, a source electrode 22, and a gate electrode 25 (and further a back gate electrode 23). In this MOSFET, when turned on, p - Layer 13 and n + n up to layer 12 - When an ON current flows through layer 11 and a high voltage is applied to the drain electrode 21 during the OFF state, the n in this region - At least a portion of layer 11 becomes depleted.

[0024] On the other hand, n + Layer 17, p + An emitter electrode (second electrode on the protection element side) 26, whose potential is set to VISO in Figure 1, is connected to layer 18. This forms element T2 in Figure 1. When element T1 is normally off, VISO in element T2 is also set to a potential close to ground potential and functions as part of element T2. - At least a portion of layer 11 becomes depleted. Therefore, the influence of element T2 on the operation of element T1 is small.

[0025] Furthermore, in Figure 2, p on the surface side - Layer 14 and n + n between layers 12 -Layer 11 becomes a region (voltage-breaking region) J where the electric field strength in the depletion layer formed when element T1 is off increases, and therefore the breakdown voltage must be ensured. Here, in order to ensure the breakdown voltage, n + Layer 17 and n + On the surface between layers 12, multiple field plates 30 are arranged along the left-right direction in the figure (the direction in which an electric field distribution is generated during use), via a silicon oxide film thicker than the gate oxide film 24. Of these, the field plate 30 on the highest potential side (left side in the figure) is connected to the drain electrode 21, and the field plate 30 on the lowest potential side (right side in the figure) is connected to the emitter electrode 26. Adjacent field plates 30 between these are connected by capacitive coupling with each other. + Layer 17 (potential VISO) and n + The potential is distributed between layers 12 (potential VD), thereby affecting the n of region J where the field plates 30 are arranged. - The surface potential of layer 11 is properly distributed, and localized increases in electric field strength are suppressed. The function of such a field plate 30 is described, for example, in Japanese Patent No. 3275964. In other words, this structure makes it possible to increase the breakdown voltage in the breakdown voltage region J.

[0026] In Figure 2, the leftmost field plate 30 is connected to the drain electrode 21, and the rightmost field plate 30 is connected to the emitter electrode 26, both via wirings formed in the interlayer insulating layer 20, thereby determining the potential of the field plates 30 at both ends as described above. However, for example, without providing such via wirings, the leftmost field plate and the drain electrode may be placed close together in the horizontal or vertical direction in the figure and capacitively coupled in the same way as between the other field plates. The same applies to the rightmost field plate 30 and the emitter electrode 26. In other words, as long as a similar effect can be obtained using the arrangement of field plates, the positional (connection, coupling) relationship between the field plates at the left and right (high potential side, low potential side) ends and the drain electrode (high potential side electrode) and emitter electrode (low potential side electrode) can be set as appropriate.

[0027] In reality, the thick silicon oxide film in region J where the field plate 30 is formed is formed as a LOCOS oxide film, so in reality, the semiconductor layer in this region (n - The surface of layer 11, etc., is p directly below the gate electrode 35. - These layers are located below the surface of layer 13, and these surfaces are not on the same plane. In Figure 2, the surfaces of the semiconductor layers are simplified to form a single plane. The same applies to the cross-sectional diagrams described later.

[0028] Furthermore, as mentioned above, gate electrode 25 is p - Although formed on layer 13, the gate electrode 25 is further p in Figure 2. - It extends towards layer 14, and in this portion, a thick silicon oxide film similar to that of the field plate 30 is formed via n - It faces the surface of layer 11. When element T1 is normally off, p - Layer 14 and n - The depletion layer extends from the interface with layer 11, but if VBG in element T1 and VISO in element T2 are controlled independently, p - Layer 13 and p - The potential of layer 14 is n - Because it is different from the potential of layer 11, n - p in layer 11 - Depletion layer and p extending from layer 13 - It is possible that the depletion layer extending from layer 14 may come into contact with it (punch-through). - The portion (inter-element field plate 251) that faces the surface of layer 11 and controls its surface potential in the same way as the field plate 30 is treated as part of the gate electrode 25 (or an extension of the gate electrode 25) - Layer 13 and p - By providing it between layers 14, punch-through can be made less likely to occur. A separate field plate may be provided as an inter-element field plate, distinct from the gate electrode.

[0029] In the structure shown in Figure 2, when a high voltage is applied to the drain electrode 21 while element T1 is off, n -Layer 11 becomes depleted. When the voltage of the drain electrode 21 is gradually increased, breakdown may occur in this depletion layer. The large current flowing during this breakdown causes damage to the element T1 and the electrical circuit connected thereto, which is not preferable. By making the timing at which the element T2 turns on earlier than the timing at which the element T1 is damaged, the destruction of the element T1 can be suppressed. That is, the element T2 can be used as a protection element for protecting the element T1. At this time, making the on-voltage of the element T2 lower than the breakdown voltage of the element T1 can be easily achieved, for example, by adjusting the impurity concentration of the p - layer 14.

[0030] Also, when the element T1 is on during normal operation, the lower side of the p - layer 14 in FIG. 2 becomes the path through which the on-current of the element T1 flows. Therefore, as shown in the figure, the n - layer on the lower side of the p - layer 14. To ensure a sufficient thickness of the n - layer on the lower side of the p - layer 11, it is preferable to form the n - layer 11 deeply. As described above, the n - layer 11 is formed shallowly at a constant depth in the breakdown voltage ensuring region J, but is formed deeper directly below the p - layer 14 and the p

[0031] FIG. 3 is a plan view of the semiconductor device 1 shown in FIG. 2 as viewed from above. The cross-section of FIG. 2 corresponds to the cross-section in the A-A direction in this figure. Here, the semiconductor device 1 has a circular shape centered on the n + layer 12 on the high potential side, and each layer (n + layer 12, n - layer 11, p - layer 13 and the n + layer 15 therein, p + layer 16, p - layer 14 and the n + layer 17 therein, p +The planar shape of layer 18) is described here, and each of the above layers on the surface of the semiconductor substrate used here has an annular shape. Each of the above electrodes and the like is connected corresponding to each layer as shown in FIG. 2. The gate electrode 25 is formed in an annular shape as well to directly control the on / off of the current path, but for the other electrodes, it is not necessary to have an annular shape like each layer. Also, for example, as long as the on / off of the current path can be controlled similarly, the gate electrode may also be divided in the circumferential direction.

[0032] As shown here, the semiconductor device 1 has a circular shape with the n + layer 12 as the center of the high potential side region and the low potential side region on the outer side in the radial direction. In the region R1 along the radial direction (switching element region), an element T1 which is a MOSFET is formed, and in a part of the inner side thereof, a region (protection element region) R2, an element T2 which is a npn transistor is formed. Since the region R2 can be provided overlapping the region R1 inside, compared with the technology described in Patent Document 1 and the like, this semiconductor device 1 can be miniaturized. Therefore, this semiconductor device 1 is a small semiconductor device with high breakdown voltage, in which an element T1 which is a switching element and an element T2 which is a protection element for protecting this are combined. An example in which the planar shape of each layer shown in FIG. 3 is changed will be described later. Also, the n + layer serving as the common contact region and the drain electrode serving as the common electrode may have a shape such as an annular shape when viewed planar, and actually, a semiconductor layer constituting these centers and a metal layer constituting the electrode are not formed. Even in this case, these centers are understood as the centers of a circle or the like constituting the outer shape.

[0033] A modification example (the first modification example) of the above semiconductor device 1 will be described. The circuit constituted by this semiconductor device 2 is the same as that in FIG. 1, but the structure on the semiconductor substrate for realizing this is different from that in FIG. 2. FIG. 4 is a cross-sectional view corresponding to FIG. 2 showing the structure of this semiconductor device 2. <000|0328> Here, the n - layer 11, the n + ​​The structure of layer 12 and drain electrode 21 is the same as in Figure 2. However, here the positional relationship of the structures related to elements T1 and T2 is reversed compared to the structure in Figure 2. That is, in Figure 4, the p constituting element T1 - Layer 13 and n within it + Layer 15, p + Layer 16 is located on the side closer to the drain electrode 21 (radially inward in Figure 3), and the element T2 is composed of p - Layer 14 and n within it + Layer 17, p + Layer 18 is formed on the side furthest from the drain electrode 21 (radially outward in Figure 3), and consequently, the source electrode 32, back gate electrode 33, and gate electrode 35 are also formed on the p - On the near side of layer 13, the emitter electrode 36 is p - They are provided on the far side of layer 14.

[0035] In this case as well, the field plate 30 is provided in the same manner as in Figure 2. Here, the field plate 30 on the highest potential side is connected to the drain electrode 21 in the same manner as in Figure 2, but the field plate 30 on the lowest potential side has a structure equivalent to the field plate 30 on the lowest potential side in Figure 2, by extending the gate electrode 35 to the field plate 30 on its left side, as shown in the figure.

[0036] Also, in this case, p - Layer 13 and p - An inter-element field plate 37 is provided between layers 14, and the inter-element field plate 37 is connected to the back gate electrode 33. The potential VBG applied to the back gate electrode 33 is also close to the ground potential, so the n in this part - Using the potential of layer 11 as a reference, the inter-element field plate 37 will be at a potential more negative than this, and the same effect as the inter-element field plate 251 in Figure 2 will be obtained. In this case as well, as described above, p -By adjusting the impurity concentration of layer 14, the on-voltage of element T2 can be made lower than the breakdown voltage of element T1. The inter-element field plate 37 has a potential that is VISO instead of the back gate electrode 33. + It may be connected to layer 18.

[0037] A further modification (second modification) of the semiconductor device 1 described above will now be explained. Figure 5 is a cross-sectional view corresponding to Figure 2, showing the structure of this semiconductor device 3.

[0038] In the structure shown in Figure 2, the outer p - Layer 13 is n - In contrast to the formation within layer 11, in Figure 5, n - Since the lower potential end (right side in the figure) of layer 11 is set to the higher potential side (left side in the figure) than the structure in Figure 2, n - Layer 11 is p - It is not formed outside of layer 13, n - p outside layer 11 - Layer 13 and the p-type substrate 10 are in direct contact. Therefore, VBG in Figure 1 is equal to GND, which is the potential of the p-type substrate 10. Aside from this point, the structure in Figure 5 is the same as the structure in Figure 2.

[0039] In this case, VBG at element T1 is set to GND. On the other hand, p - Layer 13 and p-type substrate 10 - Since there is no need to separate the components via layer 11, this semiconductor device 3 can be made smaller compared to the semiconductor device 1.

[0040] Similarly, Figure 6 is a cross-sectional view showing the structure of a semiconductor device 4 (third modified example) obtained by modifying the semiconductor device 2 in the same manner as the semiconductor device 3.

[0041] In the structure shown in Figure 4, the outer p - Layer 14 is n - In contrast to the formation within layer 11, in Figure 6, n -The lower potential end (right side in the figure) of layer 11 is set to the higher potential side (left side in the figure) than the structure in Figure 4, n - Layer 11 is p - It is not formed outside of layer 14, n - p outside layer 11 - Layer 14 and the p-type substrate 10 are in contact. Therefore, VISO in Figure 1 is equal to the potential GND of the p-type substrate 10. Aside from this point, the structure in Figure 6 is the same as the structure in Figure 4.

[0042] In this case, VISO in element T2 is set to GND. On the other hand, p - Layer 14 and p-type substrate 10 - Since separation via layer 11 is not required, this semiconductor device 4 can be made smaller compared to the semiconductor device 2.

[0043] The first to third modified examples (semiconductor devices 2 to 4) described above differed from semiconductor device 1 (Figure 2) in their cross-sectional structure (Figures 4 to 6). In contrast, the modified example described below differs from semiconductor device 1 (Figure 3) in its planar structure.

[0044] Figure 7 is a plan view corresponding to Figure 3, showing the structure of semiconductor device 5, which is a fourth modified example. In this semiconductor device 5, similar to semiconductor device 1, element T1(p - Layer 13 etc. is radially outward, element T2(p - Layer 14, etc., is formed radially inward. In Figure 3, p - Layer 14 and n within it + Layer 17, p + Layer 18 is p - Layer 13 and n within it + Layer 15, p + While layer 16 had a similar annular shape, in this semiconductor device 5, the p constituting element T1 is - Layer 14 and n within it + Layer 17, p + Layer 18 is divided into four sections in the circumferential direction. Therefore, in the structure of Figure 7, p in the circumferential direction -In Figure 7, four areas are formed where layer 14 is not present: the top, bottom, left, and right sides.

[0045] In the structure shown in Figure 3, p - Layer 14 is ring-shaped and p - Because it is inside layer 13, the current flowing through element T1 in element region R1 is p - n directly below layer 14 - It needs to flow within layer 11. As shown in Figure 7, adjacent p in the circumferential direction - Between the regions where layer 14 is formed, p - By providing a region where layer 14 is not formed, the on-current of element T1 can flow smoothly in this region. In other words, the on-current of element T1 formed radially outward from element T2 can be increased.

[0046] In the structure shown in Figure 7, the inter-element field plate 251 (p - Layer 13 and p - When a field plate is provided between layers 14, adjacent p in the circumferential direction - n between layers 14 - It is preferable to extend this field plate above layer 11. This allows adjacent p in the circumferential direction - The region between layers 14 is prevented from being blocked by the depletion layer, and this region can be effectively used as a current path as described above.

[0047] Furthermore, in the semiconductor device 6 (fifth modified example) shown in Figure 8, the divided p - n in layer 14 + Layer 17, p + Layer 18 is further subdivided. This allows for fine-tuning of the characteristics of element T2 (on-voltage, etc.).

[0048] In these semiconductor devices 5 and 6, p - Since the total area of ​​layer 14 (the base layer of element T2) is smaller than that of the semiconductor device 1, etc., there is a risk that the protective capability of element T2 will decrease. To address this, p -This can be addressed by methods such as lowering the on-voltage of element T2 by adjusting the impurity concentration in layer 14. On the other hand, as mentioned above, since the current path for the on-current of element T1 can be easily secured, the allowable on-current of element T1 can be made larger.

[0049] Furthermore, in the circuit of Figure 1, an npn transistor, element T2, was used as a protection element. However, a diode can also be used as element T2 in Figure 1 instead of the npn transistor. Figure 9 is a circuit diagram corresponding to Figure 1, showing the configuration of a semiconductor device 7 in a modified form (sixth modified form) using such a protection element element T3 (diode). In this case, the cathode (CA) of the diode that becomes element T3 is used instead of the collector (C) in Figure 1, and the anode (AN) is used instead of the emitter (E) in Figure 1. In this case, during normal operation when VD is positive, this diode is reverse-biased, so no current flows. However, when VD exceeds the diode's breakdown voltage, current flows, and element T1 is protected in the same way as when element T2 is used. Therefore, by setting the breakdown characteristics of this diode so that element T1 is protected, element T1 is protected.

[0050] In this case, for example in Figure 2, the n-type layer constituting the cathode (CA) is n - layer 11, n + Layer 12 can be used in the same way, and the p-type layer constituting the anode (AN) is p - Layer 14, p + Layer 18 can be used similarly, and n becomes the emitter (E). + Layer 17 is not formed. That is, in the semiconductor layer n + By making the structure the same as semiconductor devices 1 to 6 except for the absence of layer 17, the semiconductor device 7 shown in Figure 9 can be obtained. In this case, the breakdown voltage (breakdown characteristic) of element T3 is set to p - The concentration of impurities in layer 14 can be adjusted.

[0051] Furthermore, instead of an npn transistor, an n-channel MOSFET (LDMOS) similar to element T1 can be used as a protection element. Figure 10 shows the configuration of a semiconductor device 8 that is such a modified example (seventh modified example). The element (protection element) T4 used here is a MOSFET similar to element T1, and as shown in the figure, its source (S), gate (G), and back gate (BG) are connected. For example, if the interlayer insulating layer 20 directly beneath the rightmost field plate 30 in the figure, which is connected to the emitter electrode 26 in Figure 2, is made into a thinner gate oxide film 24, then this field plate 30 becomes the gate (G) of element T4 in Figure 10, and this becomes p + layer 18, n + This configuration can be easily realized by connecting layer 17 and emitter electrode 26. In the element T2 of the first to third modified examples (semiconductor devices 2 to 6) described above, the protective element T4 can be similarly realized by modifying the structure near the field plate.

[0052] Furthermore, the overall shape of the semiconductor device 1, etc., is circular, p - Each region of layer 13, etc., was given an annular shape. However, it is clear that even if these are not circular (annular), the same effect will be achieved if each region is annular (for example, an elliptical annular). Furthermore, if these regions are not closed annular, or n + It is also clear that a similar effect can be achieved even if at least one of layers 15 and 17 is arranged intermittently in the circumferential direction. For example, a similar effect can be achieved even if the structure in Figure 2 is uniformly extended perpendicular to the plane of the paper and each region is in the shape of a parallel strip. In these cases, the shape of the field plate provided in the pressure-bearing region is set appropriately accordingly. The same applies to the inter-element field plate.

[0053] However, as shown in Figure 3, etc., each layer (especially p - Layers 13 and 14) are n +By creating a ring shape centered on layer 12, the potential distribution can be made uniform in the circumferential direction, and the increase in electric field strength at specific points in the circumferential direction is suppressed, thus enabling high withstand voltage.

[0054] Furthermore, in the above example, multiple field plates 30 were used in the voltage-bearing region. However, if voltage can be ensured without using such field plates, it is not necessary to provide field plates in the voltage-bearing region. Alternatively, a well-known resistive field plate may be used instead of multiple field plates 30 in the voltage-bearing region. In this case, the structure of the semiconductor device becomes simpler. The same applies to inter-element field plates.

[0055] Furthermore, other layers can be added or removed as appropriate in the semiconductor layer. It is also clear that the same configuration can be applied even when all the p-type and n-type elements in the semiconductor are reversed in the above example. [Explanation of Symbols]

[0056] 1-8 Semiconductor devices 10 p-type substrate (semiconductor substrate) 11 n - Layer (first semiconductor region) 12 n + Layer (common contact area) 13 p - Layer (Second Semiconductor Region) 14 p - Layer (Third Semiconductor Region) 15 n + Layer (Fourth Semiconductor Region) Pages 16 and 18 + layer 17 n + Layer (5th semiconductor region) 20 interlayer insulating layer 21 Drain electrodes (common electrode, first main electrode, first electrode on the protection element side) 22, 32 Source electrode (second main electrode) 23, 33 Back gate electrode (second control electrode) 24 Gate oxide film 25, 35 Electrode gate (first control electrode) 26, 36 Emitter electrode (second electrode on the protection element side) 30 Field Plates 37, 251 Inter-element field plate AN Anode (Second electrode on the protection element side) B Bass BG Back gate (second control electrode) C Collector (Protection element side first electrode) CA cathode (first electrode on the protection element side) D drain (first main electrode: high-potential side electrode) E emitter (second electrode on the protection element side) G gate (first control electrode) S Source (Second main electrode: Low-potential side electrode) T1 element (switching element) T2, T3, T4 elements (protection elements)

Claims

1. A semiconductor device having a switching element formed on a semiconductor substrate, the switching of which is controlled between a first main electrode on the high-potential side and a second main electrode on the low-potential side, and a protection element that, when the switching element is off, bypasses the current between a first electrode on the high-potential side and a second electrode on the low-potential side of the protection element, A first semiconductor region of a second conductivity type, which is the opposite of the first conductivity type, is formed on the surface side of the semiconductor substrate of a first conductivity type, The first main electrode and the common electrode which also serves as the first electrode on the protection element side, A common contact region of the second conductivity type is formed locally on the first semiconductor region with a high impurity concentration and connected to the common electrode, In a plan view, the second semiconductor region of the first conductivity type is locally formed in the first semiconductor region which is spaced apart from the common contact region, In a plan view, the third semiconductor region of the first conductivity type is locally formed in the first semiconductor region, spaced apart from the common contact region and the second semiconductor region, In a plan view, the fourth semiconductor region of the second conductivity type is locally formed within the second semiconductor region, It is equipped with, One of the second semiconductor region and the third semiconductor region is formed so as to surround the other from the outside as seen from the common contact region. The fourth semiconductor region and the second main electrode are connected, A semiconductor device characterized in that the third semiconductor region and the second electrode on the protection element side are connected.

2. The semiconductor device according to claim 1, characterized in that, in a plan view, a fifth semiconductor region of the second conductivity type is provided within the third semiconductor region, and the second electrode on the protection element side is connected to the fifth semiconductor region and the third semiconductor region.

3. The semiconductor device according to claim 1 or 2, characterized in that, in a plan view, the second semiconductor region is formed in an annular shape surrounding the common contact region.

4. The semiconductor device according to claim 1 or 2, characterized in that the other of the second semiconductor region and the third semiconductor region is the third semiconductor region.

5. The semiconductor device according to claim 4, characterized in that the third semiconductor region is divided and provided in multiple locations in a plan view.

6. The semiconductor device according to claim 1, wherein the other of the second and third semiconductor regions is the third semiconductor region, and the first semiconductor region is formed deeper below the third semiconductor region than the inside of the third semiconductor region in a plan view.

7. In the switching element, a first control electrode is formed on the second semiconductor region to control the on / off state between the first main electrode and the second main electrode, A second control electrode connected to the second semiconductor region, A semiconductor device according to claim 1 or 2, characterized by comprising the above.

8. The semiconductor device according to claim 7, further comprising an inter-element field plate electrically connected to any of the first control electrode, the second control electrode, or the third semiconductor region, and facing the surface of the first semiconductor region between the second and third semiconductor regions in a plan view via an insulating layer.

9. The semiconductor device according to claim 1 or 2, characterized in that one of the second semiconductor region and the third semiconductor region is the third semiconductor region.

10. The semiconductor device according to claim 3, characterized in that the first semiconductor region is not formed outside of the second semiconductor region and the third semiconductor region.

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