Semiconductor equipment

Abstract

Reduce on-resistance. [Solution] The semiconductor device according to this embodiment comprises a silicon carbide layer, a first electrode, a plurality of second electrodes, a third electrode, a conductive layer, a first conductive member, a second conductive member, and a recess. The first electrode is provided on the first main surface of the silicon carbide layer, and the plurality of second electrodes are provided on the second main surface of the silicon carbide layer. The third electrode faces the second silicon carbide region of the silicon carbide layer via a first insulating region. The conductive layer is electrically connected to the plurality of second electrodes and has a first connection position and a second connection position on its upper surface. The first conductive member is connected to the first connection position and is electrically connected to the conductive layer. The second conductive member is connected to the second connection position and is electrically connected to the third electrode and the conductive layer. The recess is provided on the upper surface side of the conductive layer and is located on the opposite side of the first connection position, with the second connection position in between.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] In semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that utilize silicon carbide, it is known that a decrease in gate-source voltage increases the on-resistance. An increase in on-resistance is undesirable in semiconductor devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 7425943 [Patent Document 2] Patent No. 5755533 [Patent Document 3] Japanese Patent Publication No. 2024-34660 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device that can reduce on-resistance. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a silicon carbide layer, a first electrode, a plurality of second electrodes, a third electrode, a conductive layer, a first conduction member, a second conduction member, and a concave portion. The silicon carbide layer has a first main surface and a second main surface. The silicon carbide layer has a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type provided between the second main surface and the first silicon carbide region, and a third silicon carbide region of a first conductivity type provided between the second main surface and the second silicon carbide region. The first electrode is provided on the first main surface. The plurality of second electrodes are provided on the second main surface. The third electrode faces the second silicon carbide region through a first insulating region. The conductive layer is electrically connected to the plurality of second electrodes and has a first connection position and a second connection position on the upper surface. The first conduction member is connected to the first connection position and is electrically connected to the conductive layer. The second conduction member is connected to the second connection position and is electrically connected to the third electrode and the conductive layer. The concave portion is provided on the upper surface side of the conductive layer and is located on the opposite side of the first connection position with the second connection position interposed therebetween.

Brief Description of the Drawings

[0006] [Figure 1] It is a plan view of the semiconductor device according to the first embodiment. [Figure 2] It is a cross-sectional view taken along the line A-A of FIG. 1 in the semiconductor device according to the first embodiment. [Figure 3] It is a schematic plan view of the semiconductor device according to the first embodiment. [Figure 4] It is a plan view for explaining the flow of current in the semiconductor device according to the first embodiment. [Figure 5] It is a cross-sectional view for explaining the flow of current in the semiconductor device according to the first embodiment. [Figure 6] It is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 7A] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7B]This is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment, following Figure 7A. [Figure 7C] Figure 7B is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment. [Figure 8] This is a schematic plan view of a semiconductor device according to Modification 1 of the First Embodiment. [Figure 9] This is a schematic plan view of a semiconductor device according to a modified example 2 of the first embodiment. [Figure 10] This is a schematic plan view of a semiconductor device according to a modified example 3 of the first embodiment. [Figure 11] This is a cross-sectional view of the semiconductor device according to the second embodiment, along line AA in Figure 1. [Figure 12] This is a cross-sectional view of the semiconductor device according to the third embodiment, along line AA in Figure 1. [Figure 13] This is a cross-sectional view along line AA in Figure 1 of a semiconductor device according to a modified example of the third embodiment. [Figure 14] This is a schematic plan view of a semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0008] Furthermore, for the sake of explanation, the source electrode side is also referred to as "upper," and the drain electrode side as "lower." However, this notation is for convenience only and is unrelated to the direction of gravity.

[0009] Furthermore, in the following explanation, to represent the relative highs and lows of impurity concentrations in each conductivity type, n + , n, n -, and, p + , p, p - may be used for notation. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. These notations represent the relative high and low levels of the net impurity concentration after these impurities compensate for each other when both p-type and n-type impurities are included in each region. n-type, n + -type and n - -type are an example of the first conductivity type in the claims. p-type, p + -type and p - -type are an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. That is, the first conductivity type may be p-type.

[0010] Also, the impurity concentration of the semiconductor region can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative high and low levels of the impurity concentration can be determined, for example, from the high and low levels of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM).

[0011] Also, the planar shape and depth of the concave portion, etc., can be measured, for example, by analyzing the surface and cross-section of the semiconductor device using an optical microscope, a Transmission Electron Microscope (TEM), Energy dispersive X-ray spectroscopy (EDX), or a Scanning Electron Microscope (SEM).

[0012] In this specification, terms such as "identical" and "same," as well as dimensions and physical property values ​​used to specify shape, geometric conditions, physical properties, and their degrees, shall not be strictly interpreted, but shall be interpreted to include a range that allows for the expectation of similar functionality.

[0013] (First Embodiment) The semiconductor device 1 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a plan view of the semiconductor device 1 according to the first embodiment. Figure 2 is a cross-sectional view of the semiconductor device 1 according to the first embodiment along line AA in Figure 1. In Figure 1, the conductive members 41 and 42 are shown in the portion that is in contact with the upper surface of the conductive layer 30.

[0014] The semiconductor device 1 is, for example, a MOSFET. In this embodiment, the case in which the semiconductor device 1 is a vertical MOSFET having a planar gate structure will be described as an example. However, the semiconductor device 1 may also be a vertical MOSFET having a trench gate structure or the like.

[0015] As shown in Figure 2, the semiconductor device 1 according to this embodiment comprises a silicon carbide layer 2, a drain electrode 11, a plurality of source electrodes 12, a gate electrode 13, a conductive layer 30, a conductive member 41, a conductive member 42, a recess 51, a plurality of barrier metals 60, and an insulating region (first insulating region) 70.

[0016] The silicon carbide layer 2 comprises a bottom surface (first main surface) and an top surface (second main surface). Within the silicon carbide layer 2, there are drift regions (first silicon carbide region) 21, drain regions (first silicon carbide region) 22, base regions (second silicon carbide region) 23, and source regions (third silicon carbide region) 24. Details of each region will be described later.

[0017] The silicon carbide layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer placed thereon. The silicon carbide layer 2 is single-crystal silicon carbide (SiC). In this case, n-type impurities such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) are used, and p-type impurities such as aluminum (Al) or boron (B) are used.

[0018] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is provided on the lower surface of the silicon carbide layer 2, is in contact with the drain region 22, and is electrically connected to the drain region 22. The drain electrode 11 is an example of the first electrode in the claims. The drain electrode 11 is made of a material that includes at least one of the following: nickel (Ni), titanium (Ti), aluminum (Al), etc.

[0019] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is provided on the upper surface of the silicon carbide layer 2, is in contact with the base region 23 and the source region 24, and is electrically connected to the base region 23 and the source region 24. The source electrode 12 is an example of the second electrode in the claims. In this embodiment, a plurality of source electrodes 12 are provided on the upper surface of the silicon carbide layer 2. The source electrode 12 is made of a material that includes at least one of the following: nickel (Ni), titanium (Ti), aluminum (Al), etc.

[0020] The barrier metal 60 is provided on the source electrode 12. In this embodiment, multiple barrier metals 60 are provided on each of the multiple source electrodes 12. The barrier metal 60 is made of a material containing at least one of the following: titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride, tungsten nitride, or tantalum nitride.

[0021] Furthermore, in this embodiment, as shown in Figure 1, each of the multiple source electrodes 12 extends in one direction (the vertical direction in Figure 1) perpendicular to the thickness direction of the silicon carbide layer 2. That is, the multiple source electrodes 12 have a stripe-shaped planar shape. Note that the planar shape of the multiple source electrodes 12 is not limited to that shown in Figure 1. For example, at least some of the multiple source electrodes 12 may have a dot-shaped planar shape.

[0022] As shown in Figure 2, the insulating region 70 is provided on the upper surface of the silicon carbide layer 2. The insulating region 70 is provided so as to be sandwiched between the source electrodes 12. In this embodiment, the insulating region 70 is provided so as to be sandwiched between a two-layer structure consisting of the source electrodes 12 and the barrier metal 60 above it. The insulating region 70 is embedded in the conductive layer 30. The insulating region 70 is an insulating film containing, for example, silicon oxide or silicon nitride.

[0023] The gate electrode 13 functions as the gate electrode of the MOSFET. The gate electrode 13 is located within the insulating region 70 and is electrically insulated from the silicon carbide layer 2 by the insulating region 70. The gate electrode 13 receives the current I flowing between the drain electrode 11 and the source electrode 12. DS The (drain-source current) is controlled. The gate electrode 13 is an example of a third electrode in the claims. The gate electrode 13 is made of polysilicon containing p-type or n-type impurities, for example. When a voltage is applied to the gate electrode 13, a channel is formed in the base region 23, and carriers flow between the drift region 21 and the source region 24. This turns the MOSFET ON.

[0024] The conductive layer 30 is provided to embed a plurality of source electrodes 12 and is electrically connected to the plurality of source electrodes 12. In this embodiment, the conductive layer 30 embeds each of the plurality of source electrodes 12 via a plurality of barrier metals 60. In other words, the plurality of barrier metals 60 are provided between the plurality of source electrodes 12 and the conductive layer 30. The conductive layer 30 is made of a material containing at least one of the following: aluminum (Al), copper (Cu), titanium (Ti), and tungsten (W). The conductive layer 30 is also called the source metal. The conductive layer 30 may be made of the same material as the barrier metals 60, or it may be made of different materials.

[0025] As shown in Figures 1 and 2, the conductive layer 30 has a connection position P1 to which the conductive member 41 is connected and a connection position P2 to which the conductive member 42 is connected on its upper surface. That is, the conductive member 41 and the conductive member 42 are connected to the same conductive layer 30. Connection position P1 is an example of a first connection position in the claims. Connection position P2 is an example of a second connection position in the claims. Note that connection position P1 is the center of the portion of the upper surface of the conductive layer 30 that the conductive member 41 contacts (hereinafter also referred to as the "contact portion of the conductive member 41"), for example, the geometric centroid of that portion. Similarly, connection position P2 is the center of the portion of the upper surface of the conductive layer 30 that the conductive member 42 contacts (hereinafter also referred to as the "contact portion of the conductive member 42"), for example, the geometric centroid of that portion. Note that the shapes of the contact portions of the conductive member 41 and the conductive member 42 are not limited to those shown in Figure 1.

[0026] The conductive members 41 and 42 are wires or metal pieces, etc. If they are wires, their constituent material is, for example, aluminum or an aluminum alloy. If they are metal pieces, their constituent material is, for example, copper or a copper alloy. At least one of the conductive members 41 and 42 may be a bundle of multiple wires.

[0027] The conductive member 41 is electrically connected to the conductive layer 30. The conductive member 41 is connected to the current I flowing between the drain electrode 11 and the source electrode 12. DSCurrent flows. For example, the current that flows from the drain electrode 11 to the source electrode 12 passes through the conductive layer 30 and then flows into the conductive member 41. Conversely, the current that flows from the conductive member 41 to the conductive layer 30 then flows from the source electrode 12 to the drain electrode 11. The conductive member 41 is an example of the first conductive member in the claims. The conductive member 41 is also called a source wire or source force wire.

[0028] The conductive member 42 is electrically connected to the gate electrode 13 and the conductive layer 30. A current I is present between the conductive member 42 and the gate electrode 13. DS Drive voltage V for controlling DRV A voltage is applied. When such a conductive member 42 is connected, the conductive member 42 is not connected, and the drive voltage V is applied to the conductive member 41. DRV Compared to the case where a current is applied, the resistance of the conductive member 41 and the current I flowing through the conductive member 41 are different. DS This results in the voltage actually applied between the source electrode 12 and the gate electrode 13, i.e., the gate-source voltage V. GS However, the drive voltage V DRV It is possible to suppress the decrease below this level. Conductive member 42 is an example of a second conductive member in the claims. Conductive member 42 is also called a source sense wire. As shown in Figure 2, the diameter of conductive member 42 may be smaller than the diameter of conductive member 41.

[0029] The recess 51 is provided on the upper surface side of the conductive layer 30 and is located on the opposite side of connection position P1, with connection position P2 in between. The recess 51 is, for example, a portion of the conductive layer 30 that has been removed. As shown in Figure 1, in this embodiment, the planar shape of the recess 51 is a slit, i.e., a straight line. However, the planar shape of the recess 51 is not limited to a straight line, and may be any shape such as a dot shape, a wavy shape, or a zigzag shape.

[0030] As shown in Figure 2, in this embodiment, the top surface of some of the barrier metals 60a among the multiple barrier metals 60 is exposed at the bottom surface of the recess 51. Note that the bottom surface of the recess 51 does not need to reach the barrier metals 60.

[0031] Although not shown in the figures, a portion of the sealing material of the semiconductor device 1 may flow into the recess 51. That is, at least a portion of the recess 51 may be filled with the sealing material that seals the conductive layer 30, the conductive member 41, and the conductive member 42.

[0032] Furthermore, in the example shown in Figure 2, the recess 51 was located on the barrier metal 60. However, it is not limited to this; the recess 51 may be located on the insulating region 70, or it may be located across both the barrier metal 60 and the insulating region 70. In other words, the positional relationship between the recess 51 and the barrier metal 60 and the insulating region 70 is arbitrary. Also, in the example shown in Figure 1, the longitudinal direction of the recess 51 coincided with the extending direction of the source electrode 12. However, it is not limited to this; the longitudinal direction of the recess 51 may differ from the extending direction of the source electrode 12.

[0033] Here, the shape of the recess 51 will be described in more detail with reference to Figure 3. Figure 3 is a schematic plan view of the semiconductor device 1 according to the first embodiment. In Figure 3, the direction from connection position P2 to connection position P1 on the upper surface of the conductive layer 30 is defined as the U-axis direction, and the direction perpendicular to the U-axis direction on the upper surface of the conductive layer 30 is defined as the V-axis direction. The U-axis direction is an example of the first direction in the claims. The V-axis direction is an example of the second direction in the claims. In the examples of Figures 1 and 3, the U-axis direction from connection position P2 to connection position P1 is perpendicular to the extending direction of the source electrode 12. However, the U-axis direction may differ from the extending direction of the source electrode 12. For example, the U-axis direction may be parallel to the extending direction of the source electrode 12, or it may be oblique to it.

[0034] As shown in Figure 3, the recess 51 in this embodiment is symmetrical with respect to the straight line L1 passing through connection position P1 and connection position P2. That is, in Figure 3, the portion of the recess 51 above the straight line L1 and the portion below the straight line L1 have symmetrical shapes. Note that the recess 51 does not necessarily have to be symmetrical with respect to the straight line L1 passing through connection position P1 and connection position P2.

[0035] Furthermore, the longitudinal length of the recess 51 is greater than or equal to the width of the conductive member 42 connected to the upper surface of the conductive layer 30. More specifically, the length W1 of the recess 51 in the V-axis direction is greater than or equal to the length W2 of the portion of the conductive member 42 that is in contact with the upper surface of the conductive layer 30. In other words, the longitudinal length of the recess 51 is greater than or equal to the width of the contact portion of the conductive member 42.

[0036] The following describes an example of the internal structure of the silicon carbide layer 2, with reference to Figure 2. Note that the internal structure of the silicon carbide layer 2 is not limited to that described below. Furthermore, the internal structure of the silicon carbide layer 2 will be omitted in subsequent drawings as appropriate.

[0037] As shown in Figure 2, the silicon carbide layer 2 includes, for example, a drift region 21, a drain region 22, a base region 23, and a source region 24.

[0038] The drift region 21 functions as the drift region of the MOSFET. The drift region 21 is located above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, n - This is a semiconductor region of a certain shape. The n-type impurity concentration in the drift region 21 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 17 cm -3 The following applies:

[0039] The drain region 22 functions as the drain region of the MOSFET. The drain region 22 is located between the drift region 21 and the drain electrode 11. The drain region 22 is in contact with the drain electrode 11 and is in ohmic contact with the drain electrode 11. The drain region 22 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0040] The base region 23 functions as the base region of the MOSFET. The base region 23 is located above the drift region 21. The base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the base region 23 is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 21 cm -3 The following applies. In the example shown in Figure 2, the base region 23 has a first portion located below the source region 24, a second portion extending from the first portion toward the upper surface of the silicon carbide layer 2 and in contact with the source electrode 12, and a third portion extending from the first portion toward the upper surface of the silicon carbide layer 2 and in contact with the insulating region 70 below the gate electrode 13. Note that the second portion is p + It may also be a semiconductor region of a certain type. That is, the p-type impurity concentration in the second part may be higher than the p-type impurity concentrations in the first and third parts.

[0041] The source region 24 functions as the source region of the MOSFET. The source region 24 is located between the base region 23 and the source electrode 12. The source region 24 is in contact with the source electrode 12 and is in ohmic contact with the source electrode 12. The source region 24 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the source region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0042] The semiconductor device 1 may further include a field plate electrode (FP electrode) provided within the silicon carbide layer 2 via an insulating region. The FP electrode is electrically insulated from the silicon carbide layer 2 by the insulating region and is electrically connected to the source electrode 12. By providing such an FP electrode, when the MOSFET is in the off state, a depletion layer extends from the FP electrode to the surrounding drift region 21 due to the voltage applied between the drain electrode 11 and the source electrode 12. This depletion layer connects with the depletion layer of the adjacent FP electrode, making it possible to improve the breakdown voltage of the semiconductor device 1.

[0043] As described above, the semiconductor device 1 according to this embodiment comprises a silicon carbide layer 2, a drain electrode 11, a plurality of source electrodes 12, a gate electrode 13, a conductive layer 30, and a recess 51. The silicon carbide layer 2 has a lower surface and an upper surface. The drain electrode 11 is provided on the lower surface of the silicon carbide layer 2. The plurality of source electrodes 12 are provided on the upper surface of the silicon carbide layer 2. The gate electrode 13 is electrically insulated from the silicon carbide layer 2 by an insulating region 70, and the current I flowing between the drain electrode 11 and the plurality of source electrodes 12 DS The conductive layer 30 is provided so as to embed a plurality of source electrodes 12 and is electrically connected to the plurality of source electrodes 12. The conductive layer 30 has a connection position P1 to which a conductive member 41 is connected and a connection position P2 to which a conductive member 42 is connected on its upper surface. Current I is supplied to the conductive member 41. DS A drive voltage V flows between the conductive member 42 and the gate electrode 13. DRV The voltage is applied. The recess 51 is provided on the upper surface side of the conductive layer 30 and is located on the opposite side of connection position P1, with connection position P2 in between.

[0044] According to this embodiment, the on-resistance of the semiconductor device 1 can be reduced compared to the case in which the recess 51 is not provided. The effects of this embodiment will be described in detail below with reference to Figures 4 to 6. Figure 4 is a plan view illustrating the flow of current in the semiconductor device 1 according to the first embodiment. Figure 5 is a cross-sectional view illustrating the flow of current in the semiconductor device 1 according to the first embodiment, and is a cross-sectional view along line AA in Figure 1. Figure 6 is an equivalent circuit diagram of the semiconductor device 1 according to the first embodiment. In Figures 4 and 5, the symbol I schematically represents the path of current flowing from the drain electrode 11 to the conductive member 41 via the source electrode 12, barrier metal 60 and conductive layer 30. Also, in Figure 6, R M R represents the resistance caused by the conductive layer 30 between the source electrode 12 and the conductive member 41. F This represents the resistance of the conductive member 41.

[0045] As shown in Figure 5, when the semiconductor device 1, which is a MOSFET, is in the ON state, the current I first flows through the silicon carbide layer 2 from the drain electrode 11 towards the source electrode 12. Then, as shown in Figures 4 and 5, the current I that has passed through the source electrode 12 and the barrier metal 60 flows through the conductive layer 30 from the barrier metal 60 towards the connection position P1 of the conductive member 41.

[0046] In this embodiment, because the recess 51 is provided, as shown in Figure 4, of the current I flowing out from each source electrode 12 and flowing through the conductive layer 30, the current flowing from the opposite side of connection position P1 across connection position P2 to connection position P1 does not pass through connection position P2, but flows to connection position P1 in a way that bypasses connection position P2. In other words, the contact portion of the conductive member 42 is isolated from at least some of the currents I among the multiple currents I. As a result, the current passing through the contact portion of the conductive member 42 can be reduced compared to when the recess 51 is not provided. As a result, the voltage drop at the contact portion of the conductive member 42 can be suppressed. That is, as shown in Figure 6, the conductive member 42 is substantially isolated from the source electrode 12 and the resistor R M This results in a state of connection between the two. Therefore, according to this embodiment, the gate-source voltage V actually applied between the source electrode 12 and the gate electrode 13 is GS However, the drive voltage V DRV This can prevent the level from dropping further.

[0047] Generally, in semiconductor devices having a silicon carbide layer, the gate-source voltage V GS It is known that a decrease in the gate-source voltage V increases the on-resistance of the semiconductor device. Therefore, according to this embodiment, the gate-source voltage V is lower compared to the case where the recess 51 is not provided. GS This can suppress the decrease in the on-resistance of semiconductor device 1, thereby reducing the on-resistance of semiconductor device 1.

[0048] Furthermore, the current density within the conductive layer 30 increases as it approaches the conductive member 41. Therefore, when the conductive member 42 is close to the conductive member 41, the voltage drop at the contact portion of the conductive member 42 increases. According to this embodiment, by providing the recess 51, the on-resistance of the semiconductor device 1 can be effectively reduced when the conductive member 42 is close to the conductive member 41.

[0049] Furthermore, according to this embodiment, the recess 51 is symmetrical with respect to the straight line L1 passing through connection position P1 and connection position P2. As a result, for example in Figure 4, the components of the current flowing towards connection position P2 through the upper side of the recess 51 and the current flowing towards connection position P2 through the lower side of the recess 51 cancel each other out in the vertical direction. Therefore, the current passing through the contact portion of the conductive member 42 can be reduced.

[0050] Furthermore, in this embodiment, the longitudinal length of the recess 51 is greater than or equal to the width of the conductive member 42 connected to the upper surface of the conductive layer 30. This makes it possible to further reduce the current passing through the contact portion of the conductive member 42.

[0051] Furthermore, in this embodiment, conductive members 41 and 42 are connected to the same conductive layer 30. This suppresses the reduction in the area of ​​the conductive layer 30 that contributes to the conduction of current I, compared to, for example, the case where conductive member 41 is connected to the first conductive layer and conductive member 42 is connected to a second conductive layer that is physically separated from the first conductive layer. As a result, the on-resistance of the semiconductor device 1 can be further reduced.

[0052] <Manufacturing method for semiconductor device 1> Next, an example of a manufacturing method for the semiconductor device 1 according to this embodiment will be described with reference to Figures 7A to 7C. Figures 7A to 7C are cross-sectional views illustrating an example of the manufacturing process for the semiconductor device 1 according to the first embodiment, and are cross-sectional views along line AA in Figure 1.

[0053] First, as shown in Figure 7A, a semiconductor device component is prepared, comprising a silicon carbide layer 2, a source electrode 12, a gate electrode 13, a barrier metal 60, and an insulating region 70. Semiconductor regions, such as a drift region 21 (not shown), are formed within the silicon carbide layer 2.

[0054] Next, as shown in Figure 7B, a conductive layer 30 is formed on the upper surface of the silicon carbide layer 2 so as to embed the barrier metal 60 and the insulating region 70. Subsequently, although not shown, a drain electrode 11 is formed on the lower surface of the silicon carbide layer 2. Note that the drain electrode 11 may be formed before the conductive layer 30.

[0055] Next, as shown in Figure 7C, the portion of the conductive layer 30 located on top of the barrier metal 60a is removed by reactive ion etching (RIE) or the like. This forms a recess 51 on the upper surface of the conductive layer 30. The upper surface of the barrier metal 60a is exposed at the bottom of the recess 51.

[0056] Subsequently, although not shown in the diagram, one end of the conductive members 41 and 42 is connected to the upper surface of the conductive layer 30 using a bonding material such as solder, and the other ends of the conductive members 41 and 42 are connected to the inner leads of the lead frame. Then, the conductive layer 30, conductive members 41 and 42 are sealed with a sealing material.

[0057] The semiconductor device 1 according to this embodiment is manufactured through the above process.

[0058] In the manufacturing method of the semiconductor device 1 according to this embodiment, the conductive layer 30 may be made of a different material from the barrier metal 60. This facilitates the formation of the recess 51 in the process described with reference to Figure 7C. Specifically, it is possible to suppress the removal of the barrier metal 60 in the RIE for removing a portion of the conductive layer 30.

[0059] Below, several modifications of the first embodiment, in which the planar shape of the recess 51 is changed, will be described, focusing on the differences from the first embodiment. Each of the modifications described below, as with the first embodiment, can reduce the on-resistance of the semiconductor device compared to a case where the recess is not provided.

[0060] (Modification 1 of the first embodiment) Referring to Figure 8, a semiconductor device according to Modification 1 of the First Embodiment will be described. Figure 8 is a schematic plan view of the semiconductor device according to Modification 1 of the First Embodiment.

[0061] As shown in Figure 8, the semiconductor device according to this modified example includes a U-shaped recess, that is, a rectangular recess with one side removed. More specifically, in this modified example, the recess 51 has one end (the upper end in Figure 8) and the other end opposite to the first end (the lower end in Figure 8). The semiconductor device according to this modified example further includes a recess 52 provided on the upper surface side of the conductive layer 30 and connected to one end of the recess 51, and a recess 53 provided on the upper surface side of the conductive layer 30 and connected to the other end of the recess 51. Recess 52 is an example of the second recess in the claims. Recess 53 is an example of the third recess in the claims. The recess 51 in this modified example has the same shape as the recess 51 of the first embodiment described in Figure 3. Furthermore, the recesses 52 and 53 have a linear shape in which their longitudinal direction is perpendicular to the longitudinal direction (V-axis direction) of the recess 51.

[0062] The recess 53, together with the recess 52, sandwiches the connection position P2. That is, the recess 53 is located on the opposite side of the connection position P2 from the recess 52. This makes it possible to reduce the current passing through the contact portion of the conductive member 42.

[0063] Furthermore, the length W1 in the V-axis direction of the recesses formed by the recesses 51, 52, and 53 is longer than the length W2 in the V-axis direction of the conductive member 42. This allows for a reduction in the current passing through the contact portion of the conductive member 42.

[0064] Furthermore, the recesses formed by recesses 51, 52, and 53 are symmetrical with respect to the straight line L1 passing through connection position P1 and connection position P2. This makes it possible to further reduce the current passing through the contact portion of the conductive member 42.

[0065] Furthermore, recesses 52 and 53 extend toward the conductive member 41 side than the straight line L2, which passes through the connection position P2 and is perpendicular to the straight line L1. This makes it possible to further reduce the current passing through the contact portion of the conductive member 42.

[0066] Furthermore, recesses 51 and 52 may not be continuous, and a conductive layer 30 may be provided between recesses 51 and 52. Similarly, recesses 51 and 53 may not be continuous, and a conductive layer 30 may be provided between recesses 51 and 52.

[0067] (Modification 2 of the first embodiment) Referring to Figure 9, a semiconductor device according to Modification 2 of the First Embodiment will be described. Figure 9 is a schematic plan view of the semiconductor device according to Modification 2 of the First Embodiment.

[0068] As shown in Figure 9, the semiconductor device according to this modified example includes a U-shaped recess. More specifically, in this modified example, the recess 51 has one end (the upper end in Figure 9) and the other end opposite to the first end (the lower end in Figure 9). The semiconductor device according to this modified example further includes a recess 52 provided on the upper surface side of the conductive layer 30 and connected to one end of the recess 51, and a recess 53 provided on the upper surface side of the conductive layer 30 and connected to the other end of the recess 51. More specifically, the semiconductor device according to this modified example further includes a recess 52 connected to one end of the recess 51 via a connecting recess 54, and a recess 53 connected to the other end of the recess 51 via a connecting recess 55. The connecting recess 54 extends from one end of the recess 51 toward the connection position P1 and connects the recess 51 and the recess 52. The connecting recess 55 extends from the other end of the recess 51 toward the connection position P1 and connects the recess 51 and the recess 53. Furthermore, recesses 51 and 52 are continuous via a connecting recess 54, and recesses 51 and 53 are continuous via a connecting recess 55. Note that recess 51 in this modified example has a linear shape similar to recess 51 in the first embodiment described in Figure 3. However, the longitudinal length of recess 51A in this modified example is shorter than the longitudinal length W1 of recess 51 in the first embodiment. Also, recesses 52 and 53 have a linear shape in which the longitudinal direction is perpendicular to the longitudinal direction (V-axis direction) of recess 51.

[0069] Furthermore, in the example shown in Figure 9, both the connecting recess 54 and the connecting recess 55 are linear in shape. Also, the longitudinal directions of the connecting recess 54 and the connecting recess 55 are inclined at approximately 45° with respect to the longitudinal direction (V-axis direction) of the recess 51. However, the design is not limited to this, and the connecting recess 54 may be a curved shape, such as a circular arc, that smoothly connects the recess 51 and the recess 52. Similarly, the connecting recess 55 may be a curved shape that smoothly connects the recess 51 and the recess 53.

[0070] Furthermore, the recesses formed by recesses 51, 52, 53 and connecting recesses 54, 55 are symmetrical with respect to the straight line L1 passing through connection position P1 and connection position P2. This makes it possible to reduce the current passing through the contact portion of the conductive member 42.

[0071] (Modification 3 of the first embodiment) Referring to Figure 10, a semiconductor device according to Modification 3 of the First Embodiment will be described. Figure 10 is a schematic plan view of the semiconductor device according to Modification 3 of the First Embodiment.

[0072] As shown in Figure 10, the semiconductor device according to this modified example includes an I-shaped recess. More specifically, the semiconductor device according to this modified example further includes a recess 56 in addition to the recess 51.

[0073] The recess 56 is provided in the conductive layer 30 and is located on the opposite side of the connection position P2 from the recess 51, i.e., on the connection position P1 side. However, the recess 56 is located between the connection position P2 and the connection position P1. The recess 56 is an example of the fourth recess in the claims. In the example in Figure 10, the recess 56 is parallel to the recess 51 and has the same shape as the recess 51. That is, the longitudinal length of the recess 56 is equal to the longitudinal length W1 of the recess 51.

[0074] In this modified example, both recesses 51 and 56 are symmetrical with respect to the straight line L1 passing through connection point P1 and connection point P2. This makes it possible to further reduce the current passing through the contact portion of the conductive member 42.

[0075] (Second Embodiment) Referring to Figure 11, the semiconductor device 1A according to the second embodiment will be described. Figure 11 is a cross-sectional view of the semiconductor device 1A according to the second embodiment, along line AA in Figure 1. One of the differences between the first embodiment described above and this embodiment is the depth of the recess. The following description of this embodiment will focus on the differences from the first embodiment.

[0076] As shown in Figure 11, the semiconductor device 1A according to this embodiment includes a recess 51A instead of a recess 51. The recess 51A penetrates the barrier metal 60a. The top surfaces of some of the source electrodes 12a among the plurality of source electrodes 12 are exposed on the bottom surface of the recess 51A. The planar shape of the recess 51A is the same as the planar shape of the recess 51 in the first embodiment.

[0077] According to this embodiment, since the electrical resistance below the recess 51A increases due to the removal of the barrier metal 60a, the current passing through the contact portion of the conductive member 42 can be reduced.

[0078] The semiconductor device 1A according to this embodiment can be manufactured by changing the RIE conditions in the process described with reference to Figure 7C, among other methods of manufacturing the semiconductor device 1 according to the first embodiment described above. In this embodiment, the conductive layer 30 may be made of a different material from the plurality of source electrodes 12. This facilitates the formation of the recess 51A.

[0079] (Third embodiment) Referring to Figure 12, the semiconductor device 1B according to the third embodiment will be described. Figure 12 is a cross-sectional view of the semiconductor device according to the third embodiment along line AA in Figure 1. One of the differences between the first embodiment described above and this embodiment is the positional relationship between the recess and the insulating region 70. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0080] As shown in Figure 12, the semiconductor device 1B according to this embodiment includes a recess 51B instead of a recess 51. The bottom surface of the recess 51B exposes the upper surface of some of the insulating regions 70A among the plurality of insulating regions 70. The insulating region 70A is an example of the second insulating region in the claims. In the example in Figure 12, the width of the insulating region 70A (length in the left-right direction in Figure 12) is the same as the width of the other insulating regions 70. However, the width of the insulating region 70A may be different from the width of the other insulating regions 70. Furthermore, the planar shape of the recess 51B is the same as the planar shape of the recess 51 in the first embodiment.

[0081] A gate electrode 13 is not provided below the recess 51B. In this embodiment, a gate electrode 13 is not provided within the insulating region 70A.

[0082] According to this embodiment, the electrical resistance at the bottom surface of the recess 51B is increased, which allows the current passing through the contact portion of the conductive member 42 to be reduced.

[0083] The semiconductor device 1B according to this embodiment can be manufactured by changing the position where the conductive layer 30 is removed in the manufacturing process of the semiconductor device 1 according to the first embodiment described above, for example, in the process described with reference to Figure 7C.

[0084] According to the manufacturing method of the semiconductor device 1B of this embodiment, the risk of a short circuit between the conductive layer 30 and the gate electrode 13 can be reduced because the gate electrode 13 is not provided below the recess 51B.

[0085] In the example shown in Figure 12, the insulating region 70A has the same height as the other insulating regions 70. This allows the insulating region 70A to be formed together with the other insulating regions 70.

[0086] (Modified version of the third embodiment) Referring to Figure 13, a modified semiconductor device 1C according to the third embodiment will be described. Figure 13 is a cross-sectional view of the modified semiconductor device 1C according to the third embodiment, along line AA in Figure 1. One of the differences between the third embodiment described above and this modified embodiment is the configuration of the insulating region exposed on the bottom surface of the recess 51B. The following description of this modified embodiment will focus on the differences from the third embodiment.

[0087] As shown in Figure 13, in this modified example, the top surface of some of the insulating regions 70B among the multiple insulating regions 70 is exposed on the bottom surface of the recess 51B. The insulating region 70B is an example of the second insulating region in the claims.

[0088] Below the recess 51B, there is no gate electrode 13. More specifically, although two gate electrodes 13a are provided within the insulating region 70B, neither of the two gate electrodes 13a is located below the recess 51B.

[0089] According to this modified example, the electrical resistance below the recess 51B increases, which allows for a reduction in the current passing through the contact portion of the conductive member 42.

[0090] According to the manufacturing method of the semiconductor device 1C in this modified example, the risk of a short circuit between the conductive layer 30 and the gate electrode 13a can be reduced because the gate electrode 13a is not provided below the recess 51B.

[0091] (Fourth Embodiment) Referring to Figure 14, the semiconductor device 1D according to the fourth embodiment will be described. Figure 14 is a schematic plan view of the semiconductor device 1D according to the fourth embodiment. One of the differences between the first embodiment described above and this embodiment is the number of recesses 51. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0092] As shown in Figure 14, in the semiconductor device 1D according to this embodiment, the conductive layer 30A has regions to which conductive members 41 and 42 can be connected. That is, the conductive layer 30A has a connection region A1 to which conductive member 41 can be connected, and a plurality of connection regions A2 to which conductive members 42 can each be connected, on its upper surface. Connection region A1 is an example of a first connection region in the claims. Connection region A2 is an example of a second connection region in the claims.

[0093] A conductive member 41 is connected to any position within connection area A1. Similarly, a conductive member 42 is connected to any position within connection area A2.

[0094] In the example shown in Figure 14, the conductive layer 30A has one connection region A1 and multiple connection regions A2 on its upper surface. Connection region A1 has a larger area than each of the connection regions A2. In this case, for example, one or more conductive members 41 are connected at any position within connection region A1. On the other hand, one conductive member 42 is connected at any position within one of the multiple connection regions A2.

[0095] On the upper surface of the conductive layer 30A, multiple recesses 51 are provided on the opposite side of the connection region A1, with multiple connection regions A2 in between. Note that at least one of the multiple recesses 51 may be replaced with recesses such as those described in Modifications 1 to 3 of the first embodiment.

[0096] According to this embodiment, the degree of freedom in the bonding position of the conductive members 41 and 42 in the semiconductor device 1D can be improved. Furthermore, when connecting multiple conductive members 41, it is possible to suppress the increase in the resistance of the semiconductor device 1D due to the conductive members 41.

[0097] In the embodiments described above, the semiconductor device was described as a vertical MOSFET. However, it is not limited to this, and the semiconductor device may also be a vertical transistor such as an IGBT (Insulated Gate Bipolar Transistor).

[0098] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0099] 1 Semiconductor device 11 Drain electrode 12 Source electrodes 13 gates 2. Silicon carbide layer 21 Drift Region 22 Drain region 23 Base area 24 Source Area 30 Conductive layer 41,42 Conductive members 51, 52, 53, 56 recesses 54, 55 Connection recess 60 Barrier Metal 70 Insulation Area A1,A2 connection area P1, P2 connection location

Claims

1. Having a first main surface and a second main surface, The first silicon carbide region of the first conductive type, A second silicon carbide region of a second conductivity type is provided between the second main surface and the first silicon carbide region, A third silicon carbide region of the first conductivity type is provided between the second main surface and the second silicon carbide region, A silicon carbide layer having, The first electrode provided on the first main surface, Multiple second electrodes provided on the second main surface, A third electrode facing the second silicon carbide region via the first insulating region, A conductive layer electrically connected to the plurality of second electrodes, having a first connection position and a second connection position on its upper surface, A first conductive member connected to the first connection position and electrically connected to the conductive layer, A second conductive member connected to the second connection position and electrically connected to the third electrode and the conductive layer, A recess is provided on the upper surface side of the conductive layer and is located on the opposite side of the first connection position, with the second connection position in between, A semiconductor device equipped with a semiconductor device.

2. The device further comprises a barrier metal provided between at least some of the plurality of second electrodes and the conductive layer, The semiconductor device according to claim 1, wherein the upper surface of the barrier metal is exposed at the bottom surface of the recess.

3. The conductive layer is made of a material containing at least one of aluminum, copper, titanium, and tungsten. The semiconductor device according to claim 2, wherein the barrier metal is made of a material containing at least one of titanium, tungsten, tantalum, titanium nitride, tungsten nitride, and tantalum nitride.

4. The semiconductor device according to claim 3, wherein the conductive layer is made of a material different from the barrier metal.

5. The semiconductor device according to claim 1, wherein the upper surfaces of some of the second electrodes among the plurality of second electrodes are exposed on the bottom surface of the recess.

6. The silicon carbide layer further comprises a second insulating region provided on the upper surface of the silicon carbide layer, The semiconductor device according to claim 1, wherein the upper surface of the second insulating region is exposed on the bottom surface of the recess.

7. The semiconductor device according to claim 6, wherein the third electrode is not provided below the recess.

8. The semiconductor device according to claim 6, wherein the second insulating region has the same height as the first insulating region.

9. The recess has one end and the other end, The aforementioned semiconductor device is A second recess is provided on the upper surface side of the conductive layer and connected to one end of the recess, A third recess is provided on the upper surface side of the conductive layer, connected to the other end of the recess, and together with the second recess, sandwiches the second connection position. The semiconductor device according to claim 1, further comprising:

10. The semiconductor device according to claim 1, further comprising a fourth recess provided in the conductive layer and located on the opposite side of the recess from the second connection position.

11. The semiconductor device according to claim 1, wherein the recess is symmetrical with respect to a line passing through the first connection position and the second connection position.

12. The semiconductor device according to claim 1, wherein the length of the recess in the second direction perpendicular to the first direction toward the first connection position from the second connection position is greater than or equal to the length of the portion of the second conductive member that is in contact with the upper surface of the conductive layer in the second direction.

13. The conductive layer has a first connection region on its upper surface to which the first conductive member can be connected, and a plurality of second connection regions to which the second conductive members can each be connected. The semiconductor device according to any one of claims 1 to 12, wherein a plurality of recesses are provided on the upper surface of the conductive layer, on the side opposite to the first connection region, with the plurality of second connection regions in between.

14. The semiconductor device according to any one of claims 1 to 12, wherein at least a portion of the recess is filled with a sealing material that seals the conductive layer, the first conductive member, and the second conductive member.

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