Flash memory device and its programming method

Abstract

This invention provides a flash memory device and a method for programming the same. [Solution] The flash memory device includes a memory array and a memory control circuit. The memory array has a plurality of bit groups. The memory control circuit sequentially executes programming operations on the bit groups, and if a target bit group among the bit groups fails programming verification, the memory control circuit executes one or more programming verification cycles on the target bit group. Here, the target bit group is divided into M parts which are positive integers greater than 1, and it is determined whether the programming verification cycle executed on the target bit group is the first programming verification cycle. If the first programming verification cycle is executed on the target bit group, the memory control circuit sequentially executes programming on the M parts in the first programming time.

Description

Technical Field

[0001] The present invention relates to a control technique for a memory device, and more particularly, to a flash memory device and a programming method therefor for reducing a programming current generated during a programming operation.

Background Art

[0002] In the programming operation of a NOR type flash memory device, in addition to the programming time, the programming current flowing from the drain to the source of a memory cell is also an important parameter that can be used to save power consumption and is also important for green sustainable semiconductor manufacturing technology. When programming a specific number of memory cells, a regulator equipped with a charge pump circuit is used to provide a stable drain voltage (for example, 4 volts) for the memory cells and generate a programming current, so that the program can be successfully completed. However, the size of the area occupied by the charge pump circuit is proportional to the size of the peak programming current generated by all memory cells during programming and also affects the manufacturing cost of the product. Therefore, how to reduce the programming current generated during the programming operation of a NOR type flash memory device has become one of the important issues in this field.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a flash memory device and a programming method therefor that can dynamically adjust the number of bits (memory cells) programmed simultaneously during a programming verification cycle and the programming time used to reduce the programming current generated by the programming operation.

Means for Solving the Problems

[0004] The flash memory device of the present invention includes a memory array and a memory control circuit. The memory array has a plurality of bit groups. The memory control circuit is coupled to the memory array and configured to sequentially execute programming operations on the bit groups. If a target bit group among the bit groups fails programming verification, the memory control circuit executes one or more programming verification cycles on the target bit group, where the target bit group is divided into M parts, and M is a positive integer greater than 1. The memory control circuit determines whether the programming verification cycle to be executed on the target bit group is the first programming verification cycle. If the first programming verification cycle is executed on the target bit group, the memory control circuit sequentially executes programming on the M parts in the first programming time.

[0005] The present invention provides a programming method for a flash memory device, comprising: sequentially executing a programming operation for a plurality of bit groups; if a target bit group among the bit groups fails programming verification, executing one or more programming verification cycles for the target bit group, wherein the target bit group is divided into M parts, and M is a positive integer greater than 1; determining whether the programming verification cycle to be executed for the target bit group is the first programming verification cycle; and, if the first programming verification cycle is executed for the target bit group, sequentially executing programming for the M parts in the first programming time. [Effects of the Invention]

[0006] Based on the above, the flash memory device and its programming method of the present invention, when executing the first programming verification cycle for a target bit group, can sequentially execute programming on only one part of the bit group at once with a shorter programming time than conventional methods. This reduces the peak value of the program current generated during program operation and reduces the area occupied by the charge pump circuit.

[0007] To make the above-mentioned features and advantages of the present invention clearer and easier to understand, examples are given below and will be explained in detail with reference to the attached drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram showing a flash memory device according to one embodiment of the present invention. [Figure 2] This is a flowchart of the steps for a programming method for a flash memory device according to some embodiments of the present invention. [Figure 3] This is a flowchart of the steps for a programming method for a flash memory device according to some embodiments of the present invention. [Figure 4] This is a flowchart of the steps for a programming method for a flash memory device according to some embodiments of the present invention. [Modes for carrying out the invention]

[0009] Referring to Figure 1, a flash memory device 100 according to one embodiment of the present invention is, for example, of the NOR type and includes a memory array 110 and a memory control circuit 120. The memory array 110 includes a plurality of bit groups 112. Each bit group 112 consists of a plurality of bits to be programmed in a specific data pattern. Structurally, one bit corresponds to, for example, a memory cell in a memory tunnel oxide (ETOX) structure. Note that the present invention does not limit the number of bit groups 112 or the number of bits (memory cells) that constitute one bit group 112.

[0010] The memory control circuit 120 is coupled to the memory array 110. The memory control circuit 120 can sequentially execute programming operations on all bit groups 112. Specifically, the memory control circuit 120 can select a target bit group 114 from multiple bit groups 112 in the memory array 110 and execute a programming operation according to a received selection command CMD. In this embodiment, the target bit group 114 can be divided into M parts G1 to GM, where M is a positive integer greater than 1. For example, each part G1 to GM may contain 16 bits. Part G1 contains the most significant 16 bits of the target bit group 114, part G2 contains the 16 bits immediately following the bits of part G1 of the target bit group 114, and so on. However, the present invention does not limit the number of bits in each part G1 to GM, and those skilled in the art can make appropriate adjustments as needed.

[0011] The memory control circuit 120 may be, for example, a state machine, a central processing unit, or other programmable general-purpose or dedicated microprocessor, a digital signal processor, a programmable controller, a special-purpose integrated circuit, a programmable logic device, or other similar device, or a combination thereof. Alternatively, it may be a hardware circuit designed using a hardware description language or other conventional digital circuit design methods and implemented by a field-programmable logic gate array or a composite programmable logic device. Furthermore, although the memory control circuit 120 is shown as being located within the flash memory device 100 in Figure 1, the memory control circuit 120 may be a device independent of the flash memory device 100.

[0012] Optionally, the flash memory device 100 may further include a flag register 130. The flag register 130 is coupled to the memory control circuit 120 and used to store the time flag FT. The memory control circuit 120 can set the initial value of the time flag FT to a first value (for example, "0") each time a programming verification cycle is executed. Although the flag register 130 is shown as independent of the memory array 110 and the memory control circuit 120 in Figure 1, the flag register 130 may be integrated into the memory array 110 or the memory control circuit 120.

[0013] Referring to Figures 1 and 2 simultaneously, the programming method for the flash memory device of this embodiment can be applied to the flash memory device 100 shown in Figure 1. Hereinafter, each step of the programming method according to the embodiment of the present invention will be described with reference to each component of the flash memory device 100.

[0014] First, in step S200, the memory control circuit 120 sequentially executes programming operations on multiple bit groups 112. For example, the memory control circuit 120 can perform initialization and set one of all the programmable bit groups 112 in the memory array 110 (for example, the first bit group) as the target bit group 114.

[0015] Next, the memory control circuit 120 can compare the bit data (e.g., 32 bits) formed by the target bit group 114 with a specific data pattern (e.g., 32 bits) to determine whether the target bit group 114 passes programming verification. More specifically, in an example of programming verification, the memory control circuit 120 can determine whether the threshold voltage (Vth) of each bit (memory cell) in the target bit group 114 satisfies a predetermined range of each bit value in a specific data pattern. For example, if the bit value in the data pattern is "0", the corresponding threshold voltage must be greater than a preset programming verification reference voltage, and if the bit value in the data pattern is "1", the corresponding threshold voltage must be less than a preset programming verification reference voltage. The data patterns corresponding to each bit group 112 may be the same or different.

[0016] Therefore, if the target bit group 114 fails programming verification in step S202, the memory control circuit 120 can execute one or more programming verification cycles for the target bit group 114.

[0017] Next, in step S204, the memory control circuit 120 determines whether the programming verification cycle executed on the target bit group 114 is the first programming verification cycle. If the first programming verification cycle is executed on the target bit group 114, in step S206, the memory control circuit 120 sequentially executes programming on the M parts G1 to GM of the target bit group 114 during the first programming time. For example, the memory control circuit 120 may set the initial value of K to 1 and determine whether the K part GK of the target bit group 114 has one or more defective bits. If it does, the memory control circuit 120 applies a programming voltage Vprg to the defective bits in the K part GK during the first programming time, increments K (K=K+1), and continues the determination for the next part. If it does not have defective bits, the memory control circuit 120 directly increments K (K=K+1) and continues the determination for the next part. In this embodiment, a so-called "bad bit" refers to a bit (memory cell) within the target bit group 114 that fails programming verification. The programming voltage Vprg includes the voltage applied to the gate node, drain node, source node, and well area of ​​the bad bit, and in particular, the voltage applied to the drain node. For example, the voltage applied to the gate node may be 9 volts, the voltage applied to the drain node may be 4 volts, and the voltages applied to the source node and well area may be 0 volts, but the present invention is not limited thereto.

[0018] Furthermore, the memory control circuit 120 may repeat the above steps of determining whether the K-th portion GK has one or more bad bits and incrementing K, thereby continuing to determine the next portion until K becomes greater than M (all portions G1 to GM are determined).

[0019] On the other hand, when performing programming verification cycles other than the first (e.g., the second and third) on the target bit group 114, in step S208, the memory control circuit 120 simultaneously programs the M parts G1 to GM of the target bit group 114 with a second programming time that is longer than the first programming time. Specifically, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to all M faulty bits in the M parts G1 to GM during the second programming time. In actual applications, the first programming time is, for example, 0.2 microseconds, and the second programming time is, for example, 0.8 microseconds, both of which are shorter than the conventional programming time (e.g., 1 microsecond) used for a 32-bit bit group.

[0020] Observing the characteristics of a NOR-type flash memory device, the programming current generated by all bits (memory cells) during programming decreases over time. In this embodiment, since the number of bad bits is highest in the first programming verification cycle, the memory control circuit 120 applies the programming voltage Vprg to only the bad bits in one part GK of the target bit group 114 at once during the first programming time. This reduces the peak value of the programming current generated by all bad bits to which the programming voltage Vprg is applied simultaneously.

[0021] The number of faulty bits in programming verification cycles other than the first decreases as the number of programming verification cycles increases. Therefore, in programming verification cycles other than the first, the memory control circuit 120 simultaneously applies the programming voltage Vprg to all M faulty bits in the target bit group 114 (G1-GM) at once during the second programming time, thereby improving the speed of programming verification. In this way, the time spent on programming operations can be reduced while taking the programming current into consideration.

[0022] Hereinafter, the programming method of the present invention will be described in more detail using the embodiment shown in FIG. 3. Referring to FIGS. 1 and 3 simultaneously, the programming method of the flash memory device of this embodiment can be applied to the flash memory device 100 in FIG. 1. Hereinafter, each step of the programming method according to the embodiment of the present invention will be described with reference to each component of the flash memory device 100. In this embodiment, the description of the same or similar parts as in the description of FIG. 2 will be omitted. For the sake of simplicity of explanation, in this embodiment, it is assumed that the target bit group 114 is divided into two parts G1 to G2 (M is equal to 2).

[0023] First, in step S300, the memory control circuit 120 performs initialization and sets the first bit group among all the bit groups 112 to be programmed in the memory array 110 as the target bit group 114.

[0024] Next, in step S302, the memory control circuit 120 determines whether the target bit group 114 has passed the programming verification. If the target bit group 114 fails the programming verification, in step S304, the memory control circuit 120 determines whether the programming verification cycle executed for the target bit group 114 is the first programming verification cycle. Specifically, the memory control circuit 120 determines whether the programming verification cycle executed for the current target bit group 114 is the first programming verification cycle according to the time flag FT.

[0025] If the time flag FT is a first value (for example, "0"), the memory control circuit 120 can determine that the programming verification cycle currently executed on the target bit group 114 is the first programming verification cycle. Therefore, in step S306, the memory control circuit 120 determines whether the first portion G1 of the target bit group 114 has one or more bad bits. If it does, in step S308, the memory control circuit 120 applies a programming voltage Vprg to the bad bits in the first portion G1 for the duration of the first programming time, and then proceeds to S310. If it does not, it proceeds directly to S310 after step S306.

[0026] In step S310, the memory control circuit 120 determines whether the second portion G2 of the target bit group 114 has one or more bad bits. If it does, in step S312, the memory control circuit 120 applies a programming voltage Vprg to the bad bits in the second portion G2 for the duration of the first programming time, and then sets the time flag FT to a second value (for example, "1"), returns to step S302, and continues the second programming verification cycle. If it does not have bad bits, after step S310, the memory control circuit 120 sets the time flag FT to a second value, and returns to step S302.

[0027] In step S304, if the memory control circuit 120 determines that the time flag FT stored in the flag register 130 is not the first value (but the second value), the memory control circuit 120 can determine that the programming verification cycle to be executed on the current target bit group 114 is a programming verification cycle other than the first (for example, the second, third, etc.). Therefore, in step S314, the memory control circuit 120 simultaneously programs the two parts G1 to G2 of the target bit group 114 with a second programming time that is longer than the first programming time. Specifically, during the second programming time, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to all the faulty bits in the two parts G1 to G2. Then, the process returns to step S302 and continues with the next programming verification cycle.

[0028] On the other hand, in step S302, if the memory control circuit 120 determines that the target bit group 114 has passed the programming verification, in step S316, the memory control circuit 120 determines whether the target bit group 114 is the last bit group among all the bit groups 112 that are subject to programming. If so, the process proceeds to S318 and the programming operation of the memory array 110 is terminated. Otherwise, in step S320, the memory control circuit 120 sets the next bit group among the bit groups 112 as the target bit group 114, and then proceeds to S302 to continue the programming operation.

[0029] The programming method will be described below with reference to yet another embodiment. Referring simultaneously to Figures 1 and 4, the programming method for the flash memory device of this embodiment can be applied to the flash memory device 100 of Figure 1. The steps of the programming method according to the embodiment of the present invention will be described below with reference to each component of the flash memory device 100. In this embodiment, the description of parts that are the same or similar as those described in Figures 2 and 3 will be omitted. Similarly, in this embodiment, it is assumed that the target bit group 114 is divided into two parts G1 to G2 (where M is equal to 2).

[0030] First, in step S400, the memory control circuit 120 performs initialization and sets the first bit group from all the programmable bit groups 112 in the memory array 110 as the target bit group 114.

[0031] Next, in step S402, the memory control circuit 120 determines whether the target bit group 114 has passed the programming verification. If the target bit group 114 has failed the programming verification, in step S404, the memory control circuit 120 determines whether the programming verification cycle executed on the target bit group 114 is the first programming verification cycle.

[0032] If the memory control circuit 120 determines that the programming verification cycle currently being executed for the target bit group 114 is the first programming verification cycle, in step S406, the memory control circuit 120 determines whether the first portion G1 of the target bit group 114 has one or more bad bits. If it does, in step S408, the memory control circuit 120 applies a programming voltage Vprg to the bad bits in the first portion G1 for the duration of the first programming time, and then proceeds to S410. If it does not have bad bits, it proceeds directly to S410 after step S406.

[0033] In step S410, the memory control circuit 120 determines whether the second portion G2 of the target bit group 114 has one or more bad bits. If it does, in step S412, the memory control circuit 120 applies a programming voltage Vprg to the bad bits in the second portion G2 for a first programming time, and then proceeds to S414. If it does not have bad bits, it proceeds directly to S414 after step S410.

[0034] Unlike the previous embodiment, after determining whether the second portion G2 of the target bit group 114 has one or more defective bits, in step S414, the memory control circuit 120 simultaneously performs programming on the two portions G1 to G2 of the target bit group 114 during a third programming time. The third programming time in this embodiment is, for example, longer than the first programming time and less than or equal to the second programming time. Specifically, the memory control circuit 120 can simultaneously apply a programming voltage Vprg to all defective bits in the two portions G1 to G2 during the third programming time. Then, the process returns to step S402 and continues the next programming verification cycle.

[0035] In step S404, if the memory control circuit 120 determines that the programming verification cycle to be executed for the current target bit group 114 is a programming verification cycle other than the first (for example, the second, third, etc.), then in step S416, the memory control circuit 120 simultaneously executes programming for the two parts G1 to G2 of the target bit group 114 with a second programming time that is longer than the first programming time.

[0036] On the other hand, in step S402, if the memory control circuit 120 determines that the target bit group 114 has passed the programming verification, in step S418, the memory control circuit 120 determines whether the target bit group 114 is the last bit group among all the bit groups 112 that are subject to programming. If so, the process proceeds to S420 and the programming operation of the memory array 110 is terminated. Otherwise, in step S422, the memory control circuit 120 sets the next bit group among the bit groups 112 as the target bit group 114, and then proceeds to S402 to continue the programming operation.

[0037] In summary, the flash memory device and programming method of the present invention can reduce the programming current generated by the programming operation. Although the total programming time increases slightly, the peak value of the generated programming current is significantly reduced, thus significantly reducing the area occupied by the charge pump circuit and lowering the manufacturing cost of the product. This is beneficial for IoT and battery applications. Therefore, the present invention provides a green, sustainable semiconductor manufacturing technology. [Industrial applicability]

[0038] The flash memory device and programming method of the present invention can be applied to perform memory programming operations. [Explanation of symbols]

[0039] 100: Flash memory device 110: Memory Array 112: Bit group 114: Target bit group 120: Memory control circuit 130: Flag Register CMD: Select Command FT: Time Flag G1, G2, GM: Partial Vprg: Programming Voltage S200~S208, S300~S320, S400~S422: Process

Claims

1. A memory array having multiple sets of bits, The memory array is coupled to a memory control circuit configured to sequentially execute programming operations on the plurality of bit groups, If the target bit group among the plurality of bit groups fails programming verification, the memory control circuit executes one or more programming verification cycles for the target bit group. The aforementioned target bit group is divided into M parts, where M is a positive integer greater than 1. The memory control circuit determines whether the programming verification cycle executed on the target bit group is the first programming verification cycle, and if the first programming verification cycle is executed on the target bit group, the memory control circuit sequentially executes programming on the M parts in the first programming time. When the programming verification cycle other than the first is performed on the target bit group, the memory control circuit performs programming on the M parts simultaneously with a second programming time that is longer than the first programming time. Flash memory device.

2. When the first programming verification cycle is executed for the target bit group, the memory control circuit sets the initial value of K to 1, determines whether the K portion of the target bit group has one or more defective bits, and if it does, applies a programming voltage to the one or more defective bits in the K portion for the duration of the first programming time. The flash memory device according to claim 1.

3. The memory control circuit increments K and continues the determination of the next part, repeating the process of determining whether the part of K has one or more bad bits and incrementing K until K becomes greater than M. The flash memory device according to claim 2.

4. After determining whether M portions of the target bit group have one or more defective bits, the memory control circuit simultaneously performs programming on the M portions for a third programming time, where the third programming time is longer than the first programming time and less than or equal to the second programming time. The flash memory device according to claim 3.

5. The flash memory device further includes a flag register used for storing a time flag, the flag register is coupled to the memory control circuit, and the memory control circuit determines, based on the time flag, whether the programming verification cycle performed on the target bit group is the first programming verification cycle. The flash memory device according to claim 1.

6. If the target bit set passes the programming verification, the memory control circuit determines whether the target bit set is the last bit set. If not, the memory control circuit sets the next bit set as the target bit set and executes the programming operation. The flash memory device according to claim 1.

7. A method for programming a flash memory device, The flash memory device includes a memory array of multiple bit groups, The aforementioned programming method is The process involves sequentially executing programming operations on the aforementioned set of bits, If the target bit group among the aforementioned plurality of bit groups fails programming verification, one or more programming verification cycles are performed on the target bit group, wherein the target bit group is divided into M parts, and M is a positive integer greater than 1. Determining whether the programming verification cycle performed on the target bit group is the first programming verification cycle, When the first programming verification cycle is performed on the target bit group, the programming is performed sequentially on the M parts in the first programming time, When performing the programming verification cycle other than the first for the target bit group, the programming is performed simultaneously for the M parts with a second programming time that is longer than the first programming time. A method for programming a flash memory device, including [specific details omitted].

8. Executing programming sequentially for the M parts in the first programming time means Setting the initial value of K to 1, To determine whether the K portion of the target bit group has one or more defective bits, If there is one or more defective bits, a programming voltage is applied to the one or more defective bits in the K portion during the first programming time. The programming method according to claim 7, including the method described in claim 7.

9. Executing programming sequentially for the M parts in the first programming time means Increment K and continue the evaluation of the next part, The process involves repeatedly determining whether the portion of K has one or more defective bits, and incrementing K, until K becomes greater than M. The programming method according to claim 8, further comprising:

10. After determining whether M portions of the target bit group have one or more defective bits, programming is performed simultaneously on the M portions for a third programming time, wherein the third programming time is longer than the first programming time and less than or equal to the second programming time. The programming method according to claim 9, further comprising:

11. The flash memory device further includes a flag register used to store a time flag, and determines whether the programming verification cycle performed on the target bit group is the first programming verification cycle. This includes determining, based on the time flag, whether the programming verification cycle performed on the target bit group is the first programming verification cycle. The programming method according to claim 7.

12. If the aforementioned target bit group passes programming verification, it is determined whether the aforementioned target bit group is the last bit group, Otherwise, the following set of bits is set as the target set of bits, and the programming operation is executed. The programming method according to claim 7 is further included.

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