Manufacturing method for multilayer electronic components

Abstract

In multilayer electronic components including side margins, this invention mitigates the problem of reduced moisture resistance reliability of the multilayer electronic component due to decreased adhesion force of the side margins, and mitigates the problem of increased size variation of the multilayer electronic component due to pressure applied during the formation of the side margins. [Solution] A method for manufacturing a stacked electronic component according to one embodiment of the present invention includes the steps of: arranging dielectric ceramic sheets, a first internal electrode pattern, and a second internal electrode pattern alternately to form a stacked chip including a side margin attachment surface connected to the first internal electrode pattern and the second internal electrode pattern; forming a side margin on the side margin attachment surface; firing the stacked chip on which the side margin is formed to form a main body; and forming an external electrode on the main body. The step of forming the side margin can be performed by placing a side margin sheet on the side margin attachment surface and applying pressure with a roller.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing stacked electronic components. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] The side margins of multilayer electronic components can serve to prevent damage to internal electrodes due to physical or chemical stress. On the other hand, in order to suppress steps caused by internal electrodes, a method is used in which, after stacking, the internal electrodes are cut so that they are exposed on both ends of the stacked chip, and then a single dielectric layer or two or more dielectric layers (side margin sheets) are stacked on both sides of the capacitance forming portion to form margin portions 114 and 115.

[0004] However, during the high-temperature pressing and punching processes used to attach the side margin sheet to the laminated chip, the spatial distribution increases due to factors such as uneven thermal expansion of the mold. This can reduce the bonding force between the laminated chip and the side margin sheet, potentially lowering the moisture resistance reliability of the laminated electronic component.

[0005] Therefore, there is a need to improve the method for forming the side margin portion in order to improve the adhesion between the side margin sheet and the laminated chip. [Overview of the project] [Problems that the invention aims to solve]

[0006] One of the various objectives of the present invention is to mitigate the problem of reduced moisture resistance reliability of a multilayer electronic component due to a decrease in the adhesion force of the side margin portion in a multilayer electronic component that includes a side margin portion.

[0007] One of the various objectives of the present invention is to mitigate the problem of increased size variation in stacked electronic components, which occurs when pressure is applied during the formation of side margins, in stacked electronic components that include side margins.

[0008] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0009] A method for manufacturing a stacked electronic component according to one embodiment of the present invention includes the steps of: arranging dielectric ceramic sheets, a first internal electrode pattern, and a second internal electrode pattern alternately to form a stacked chip including a side margin attachment surface connected to the first internal electrode pattern and the second internal electrode pattern; forming a side margin on the side margin attachment surface; firing the stacked chip on which the side margin is formed to form a body; and forming an external electrode on the body. The step of forming the side margin can be performed by placing a side margin sheet on the side margin attachment surface and applying pressure with a roller. [Effects of the Invention]

[0010] One of the various effects of the present invention is to improve the moisture resistance reliability of stacked electronic components by placing a side margin sheet on the side margin attachment surface of a stacked chip and forming the side margin portion by applying pressure with a roller.

[0011] One of the various effects of the present invention is to reduce size variations of stacked electronic components by placing a side margin sheet on the side margin attachment surface of a stacked chip and forming the side margin portion by applying pressure with a roller.

[0012] However, the diverse and beneficial advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. [Figure 2] This is a schematic perspective view showing the main body according to one embodiment. [Figure 3] This is a schematic perspective view showing a stacked chip according to one embodiment. [Figure 4] This is a cross-sectional view along the line I-I' in Figure 1. [Figure 5] This is a cross-sectional view along the line II-II' in Figure 1. [Figure 6] This is an exploded perspective view schematicly showing the process of stacking dielectric ceramic sheets and internal electrode patterns to form a laminate. [Figure 7] (a) and (b) are schematic perspective views showing the step of cutting the laminate. [Figure 8] (a) is a schematic perspective view showing the step of widening the spacing between multiple stacked chips, and (b) is a schematic perspective view showing the step of rotating the multiple stacked chips to open the side margin attachment surface. [Figure 9] (a) is a schematic plan view showing the step of pressing a side margin sheet onto a conventional multilayer chip, and (b) is a schematic plan view showing the step of punching a side margin sheet onto a conventional multilayer chip. [Figure 10] This is a schematic diagram illustrating an example of the side margin formation step in a method for manufacturing a stacked electronic component according to one embodiment. [Figure 11] It is a plan view schematically showing the S4 stage of FIG. 10. [Figure 12] It is a plan view schematically showing the S5 stage of FIG. 10. [Figure 13] It is a graph showing the thickness of the multilayer electronic component (chip) after firing according to the comparative example and the example. [Figure 14] (a) is a graph showing the result of the moisture resistance reliability test of the multilayer electronic component according to the comparative example, and (b) is a graph showing the result of the moisture resistance reliability test of the multilayer electronic component according to the example.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more fully explain the present invention to ordinary technicians. Therefore, the shape and size of elements in the drawings may be enlarged, reduced (or emphasized or simplified) for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0015] In addition, parts not related to the explanation are omitted in the drawings for clearly explaining the present invention, and the size and thickness of each illustrated configuration are arbitrarily shown for convenience of explanation. Therefore, the present invention is not necessarily limited by the illustration. In addition, components having the same function within the scope of the same idea can be described using the same reference numerals. Furthermore, throughout the specification, when a part "includes" a certain component, it means that other components can be further included, rather than excluding other components, unless there is a particularly contrary description.

[0016] In the drawings, the first direction can mean the direction in which the dielectric ceramic sheet and the internal electrode pattern are laminated, or the direction in which the dielectric layer and the internal electrode are laminated, or the thickness direction of the multilayer electronic component.

[0017] Furthermore, in the drawings, the second direction may mean a direction perpendicular to the first direction or the length direction, and the third direction may mean a direction perpendicular to both the first and second directions or the width direction.

[0018] Multilayer electronic components In the following, before describing in detail the manufacturing method of a stacked electronic component according to one embodiment, a stacked electronic component 100 according to one embodiment will be described in detail with reference to Figures 1 to 5.

[0019] Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention; Figure 2 is a schematic perspective view of the main body according to one embodiment; Figure 3 is a schematic perspective view of a stacked chip according to one embodiment; Figure 4 is a cross-sectional view along the line I-I' in Figure 1; and Figure 5 is a cross-sectional view along the line II-II' in Figure 1.

[0020] Referring to Figure 1, one embodiment of the stacked electronic component 100 may include external electrodes 131 and 132 arranged on the main body 110.

[0021] Referring to Figure 2, the main body 110 may include the laminated chip 210 and the side margin portions 114 and 115 placed on the laminated chip 210. There are no particular restrictions on the specific shape of the main body 110, but as shown in Figure 2, the main body 110 may have a hexahedral shape or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 may not have a perfectly straight hexahedral shape, but may have a substantially hexahedral shape.

[0022] Referring to Figure 2, the main body 110 may include one and other faces 1 and 2 facing the first direction, one and other faces 3 and 4 facing the second direction, and one and other faces 5 and 6 facing the third direction. In this case, the first direction can be defined as the direction in which the plurality of dielectric layers 111 and the plurality of internal electrodes 121 and 122 are stacked, the second direction can be defined as the direction perpendicular to the first direction, in which the ends of the first internal electrode 121 and the ends of the second internal electrode 122 are alternately exposed on the surface of the main body 110, and the third direction can be defined as the direction perpendicular to the first and second directions.

[0023] The main body 110 may include corners connecting one face and the other face facing the first to third directions. The corners of the main body can be formed by shrinkage behavior during the sintering process. In one embodiment, the corners of the main body 110 may be rounded. This can suppress chipping defects of the stacked electronic component 100.

[0024] Referring to Figure 3, the multilayer chip 210 may include a dielectric layer 111 and internal electrodes 121, 122. The dielectric layer 111 and internal electrodes 121, 122 may be arranged alternately in a first direction, and the multilayer chip 210 may include a capacitance forming region Ac, which is a region where the dielectric layer 111 and internal electrodes 121, 122 overlap in a first direction, and cover portions 112, 113 arranged on one and the other surface of the capacitance forming region Ac in the first direction.

[0025] Referring to Figure 3, the stacked chip 210 may include a first side and a second side ES1, ES2 facing the first direction, a third side and a fourth side ES3, ES4 facing the second direction, and a fifth side and a sixth side ES5, ES6 facing the third direction.

[0026] Each side surface of the stacked chip 210 can form the surface of the main body 110 after firing or can be covered by the side margin portions 114 and 115. Specifically, the first side surface ES1 can form the first surface 1 of the main body 110, the second side surface ES2 can form the second surface 2 of the main body 110, the third side surface ES3 can form the third surface 3 of the main body 110, the fourth side surface ES4 can form the fourth surface 4 of the main body 110, and the fifth side surface ES5 and the sixth side surface ES6 can be covered by the side margin portions 114 and 115 described later. On the other hand, in this specification, for convenience of explanation, the fifth side surface ES5 and the sixth side surface ES6 are defined as side margin portion attachment surfaces.

[0027] The dielectric layer 111 is in a fired state, and the boundary between adjacent dielectric layers can be integrated to such an extent that it is difficult to confirm without using a scanning electron microscope (SEM).

[0028] The raw material for forming the dielectric layer 111 is not particularly limited as long as sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, a strontium titanate-based material, or the like can be used. The barium titanate-based material can contain BaTiO3-based ceramic powder. Examples of the ceramic powder include BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc.

[0029] In addition, various ceramic additives, organic solvents, binders, dispersants, etc. may be added to the raw material for forming the dielectric layer 111 according to the purpose of the present invention to powders such as barium titanate (BaTiO3).

[0030] On the other hand, the average thickness td of the dielectric layer 111 does not need to be particularly limited. However, when the dielectric layer 111 is formed to a thickness of less than 0.6 μm in general, reliability may decrease, especially when the average thickness td of the dielectric layer 111 is 0.35 μm or less.

[0031] According to one embodiment of the present invention, the step of forming the side margin portion is performed by placing a side margin sheet on the side margin portion attachment surface and applying pressure with a roller, so that excellent moisture resistance reliability of the stacked electronic component 100 can be ensured even when the average thickness te of the dielectric layer 111 is 0.35 μm or less.

[0032] Therefore, when the average thickness td of the dielectric layer 111 is 0.35 μm or less, the effects of the present invention become more pronounced, and miniaturization and increased capacitance of the stacked electronic component 100 can be achieved more easily.

[0033] The average thickness td of the dielectric layer 111 can mean the average size in the first direction of the dielectric layer 111 that is placed between the first and second internal electrodes 121 and 122. On the other hand, if the main body 110 includes a plurality of dielectric layers 111, the average thickness td of the dielectric layer 111 can mean the average thickness of at least one of the plurality of dielectric layers 111.

[0034] The average thickness td of the dielectric layer 111 can be measured by scanning an image of the cross-section of the main body 110 in the length and thickness direction (LT) with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, in the scanned image, the thickness of one dielectric layer can be measured at 30 equally spaced locations in the length direction, and the average value can be calculated. These 30 equally spaced locations can be specified by the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 dielectric layers and measuring the average values, the average thickness of the dielectric layer can be further generalized.

[0035] Cover portions 112 and 113 can be arranged on one and the other surface of the capacity forming portion Ac in the first direction.

[0036] The cover portions 112 and 113 can be formed by laminating a single dielectric layer or two or more dielectric layers on one and the other surface in the first direction of the capacitance forming portion Ac, respectively, and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0037] The cover portions 112 and 113 do not include internal electrodes and may contain substantially the same material as the dielectric layer 111.

[0038] The average thickness tc of the cover portions 112 and 113 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the average thickness tc of the cover portions 112 and 113 can be 15 μm or less. Here, the average thickness of the cover portions 112 and 113 can mean the average thickness of the first cover portion 112 and the second cover portion 113, respectively.

[0039] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction, and may be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced locations on the upper or lower part of the volume forming portion Ac.

[0040] The internal electrodes 121 and 122 can be arranged alternately with respect to the dielectric layer 111 in a first direction, and the internal electrodes 121 and 122 can include first and second internal electrodes 121 and 122. Referring to Figures 2 and 3, the first and second internal electrodes 121 and 122 can be arranged alternately facing each other across the dielectric layer 111 and can be connected to one or more of the third to sixth sides ES3, ES4, ES5, and ES6 of the laminated chip 210.

[0041] Specifically, one end of the first internal electrode 121 in the second direction can be connected to the third side surface ES3, and the other end in the second direction can be separated from the fourth side surface ES4. Similarly, one end of the second internal electrode 122 in the second direction can be connected to the fourth side surface ES4, and the other end in the second direction can be separated from the third side surface ES3.

[0042] In other words, the first internal electrode 121 is not connected to the second external electrode 132, but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131, but is connected to the second external electrode 132. In this case, the first and second internal electrodes 121 and 122 can be electrically isolated from each other by the dielectric layer 111 placed in between.

[0043] Referring to Figure 2, both ends of the first internal electrode 121 in the third direction and both ends of the second internal electrode 122 in the third direction can be simultaneously connected to the fifth side surface ES5 and the sixth side surface ES6. This increases the specific gravity of the capacitance forming portion Ac relative to the total components, maximizing the capacitance per unit volume of the stacked electronic component 100, and mitigating the step difference caused by the degree of stacking between the side margin portions 114, 115 and the internal electrodes of the capacitance forming portion Ac.

[0044] The materials used to form the internal electrodes 121 and 122 are not particularly limited, and any material with excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 may include one or more of the following: nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0045] Furthermore, the internal electrodes 121 and 122 can be formed by printing a conductive paste for internal electrodes containing one or more of the following onto a ceramic green sheet: nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. The printing method for the conductive paste for internal electrodes can be screen printing or gravure printing, but the present invention is not limited thereto.

[0046] On the other hand, the average thickness te of the internal electrodes 121 and 122 does not need to be particularly limited.

[0047] However, when the internal electrodes 121 and 122 are formed to a thickness of less than 0.6 μm, reliability may decrease, especially if the average thickness te of the internal electrodes 121 and 122 is 0.35 μm or less.

[0048] According to one embodiment of the present invention, the step of forming the side margin portion is performed by placing a side margin sheet on the side margin portion attachment surface and applying pressure with a roller. Therefore, even when the average thickness te of the internal electrodes 121 and 122 is 0.35 μm or less, excellent moisture resistance reliability of the stacked electronic component 100 can be ensured.

[0049] Therefore, the effects of the present invention become more pronounced when the average thickness te of the internal electrodes 121 and 122 is 0.35 μm or less, making it easier to achieve miniaturization and increased capacitance of the stacked electronic component 100.

[0050] The average thickness te of the internal electrodes 121 and 122 can mean the average size of the internal electrodes 121 and 122 in the first direction. On the other hand, if the main body 110 contains multiple internal electrodes 121 and 122, the average thickness td of the internal electrodes 121 and 122 can mean the average thickness of at least one of the multiple internal electrodes 121 and 122.

[0051] The average thickness te of the internal electrodes 121 and 122 can be measured by scanning an image of the cross-section of the main body 110 in the length and thickness direction (LT) with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, in the scanned image, the thickness of one internal electrode can be measured at 30 equally spaced locations in the length direction, and the average value can be calculated. These 30 equally spaced locations can be specified by the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes and measuring the average value, the average thickness of the internal electrodes can be further generalized.

[0052] Referring to Figures 1, 2, and 5, side margins 114 and 115 can be arranged on the fifth and sixth sides ES5 and ES6 of the stacked chip 210.

[0053] The side margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0054] The material forming the side margins 114 and 115 is not particularly limited and can be formed from the same material as the dielectric layer 111, but is not limited to this, and can have a different composition if it is formed from a different material than the dielectric layer 111.

[0055] On the other hand, the width of the side margins 114 and 115 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the average width of the margins 114 and 115 can be 15 μm or less.

[0056] The average width of the side margins 114 and 115 can represent the average size of the side margins 114 and 115 in the third direction, and may be the average value of the size of the side margins 114 and 115 in the third direction measured at five equally spaced locations on the side surface of the volume forming portion Ac.

[0057] The external electrodes 131 and 132 can be arranged on the third or fourth surface of the main body 110. Specifically, the first external electrode 131 is arranged on one surface 3 in the second direction of the main body 110 and connected to the first internal electrode 121, and the second external electrode 132 is arranged on the other surface 4 in the second direction of the main body 110 and connected to the second internal electrode 122.

[0058] In this embodiment, a structure is described in which the stacked electronic component 100 has two external electrodes 131 and 132. However, the number and shape of the external electrodes 131 and 132 may vary depending on the form of the internal electrodes 121 and 122 and other purposes.

[0059] On the other hand, the external electrodes 131 and 132 can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. Furthermore, they can have a multilayer structure.

[0060] On the other hand, the external electrodes 131 and 132 can be formed on one and the other surface of the main body 110 in the second direction, but they can also be extended and arranged on one and the other surface in the first direction or on a part of one and the other surface in the third direction. In this case, the external electrodes 131 and 132 can be arranged to cover the ends of the side margin portions 114 and 115. In this case, the area of ​​the external electrodes 131 and 132 arranged on the ends of the side margin portions 114 and 115 can be rounded, thereby ensuring coverage of the external electrodes 131 and 132 even on the corners of the main body 110 or on the side margin portions 114 and 115.

[0061] The external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0062] To give more specific examples of electrode layers 131a and 132a, the electrode layers can be fired electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0063] Furthermore, the electrode layers 131a and 132a can be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body 110. Additionally, the electrode layers 131a and 132a can be formed by transferring a sheet containing a conductive metal onto the main body 110, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0064] The conductive metal contained in the electrode layers 131a and 132a can be any material with excellent electrical conductivity, and is not particularly limited. For example, the conductive metal can be one or more of nickel (Ni), copper (Cu), and their alloys.

[0065] The plating layers 131b and 132b can serve to improve the airtightness or mounting characteristics of the multilayer electronic component 100. The types of plating layers 131b and 132b are not particularly limited and can be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and can be formed in multiple layers.

[0066] To give a more specific example of the plating layers 131b and 132b, the plating layers 131b and 132b can be plating layers containing Ni or plating layers containing Sn, and can be configured such that a plating layer containing Ni and a plating layer containing Sn are sequentially formed on the electrode layers 131a and 132a, or can be configured such that a plating layer containing Sn, a plating layer containing Ni, and a plating layer containing Sn are sequentially formed. Furthermore, the plating layers can also include multiple Ni plating layers and / or multiple Sn plating layers.

[0067] Manufacturing method for multilayer electronic components In the following, the method for manufacturing a stacked electronic component will be described in detail with reference to Figures 6 to 12. However, the method for manufacturing a stacked electronic component according to one embodiment of the present invention is not limited to the method for manufacturing the stacked electronic component 100 described above.

[0068] Figures 7(a) and 7(b) are schematic perspective views showing the step of cutting the laminate; Figure 8(a) is a schematic perspective view showing the step of widening the spacing between multiple laminated chips; Figure 8(b) is a schematic perspective view showing the step of rotating multiple laminated chips to open the side margin attachment surface; Figure 9(a) is a schematic plan view showing the step of pressing a side margin sheet onto a conventional laminated chip; Figure 9(b) is a schematic plan view showing the step of punching a side margin sheet onto a conventional laminated chip; Figure 10 is a schematic diagram showing an example of the side margin formation step in a manufacturing method of a laminated electronic component according to one embodiment; Figure 11 is a schematic plan view showing step S4 in Figure 10; and Figure 12 is a schematic plan view showing step S5 in Figure 10.

[0069] A method for manufacturing a stacked electronic component according to one embodiment of the present invention includes the steps of: arranging dielectric ceramic sheets 201, 202, a first internal electrode pattern 221, and a second internal electrode pattern 222 alternately to form a stacked chip 210 including side margin attachment surfaces ES5, ES6 connected to the first internal electrode pattern and the second internal electrode pattern; forming side margins 114, 115 on the side margin attachment surfaces; and firing the stacked chip on which the side margins are formed. The step of forming the side margins can be performed by placing a side margin sheet 13 on the side margin attachment surfaces and applying pressure with rollers 30, 30'.

[0070] Referring to Figure 6, a method for manufacturing a stacked electronic component according to one embodiment of the present invention may include the step of forming a stacked body 200 by alternately arranging dielectric ceramic sheets 201, 202, 203, a first internal electrode pattern 221, and a second internal electrode pattern 222.

[0071] The step of forming the laminate 200 can be carried out by alternately arranging dielectric ceramic sheets 201, 202, a first internal electrode pattern 221, and a second internal electrode pattern 222 on a support film 310, with dielectric ceramic sheets 201 and 202 placed between the first internal electrode pattern 221 and the second internal electrode pattern 222. On the other hand, the uppermost internal electrode pattern and the lowermost internal electrode pattern can be covered with a dielectric ceramic sheet 203, in which case the dielectric ceramic sheet 203 can form cover portions 112 and 113 in the laminated electronic component 100.

[0072] The dielectric ceramic sheets 201, 202, and 203 may be manufactured by creating a slurry in which additives, organic solvents, binders, dispersants, etc. are mixed with the main component powder of a dielectric material such as barium titanate (BaTiO3), and then forming this slurry into a sheet.

[0073] On the other hand, among the dielectric ceramic sheets, the dielectric ceramic sheets 201 and 202, which are placed between the first and second internal electrode patterns 221 and 222, can form the dielectric layer 111 of the stacked electronic component 100 after firing.

[0074] The internal electrode patterns 221 and 222 may be striped. Specifically, the internal electrode patterns can be formed so as to be in contact with both ends of the dielectric ceramic sheets 201 and 202 in the third direction at a constant interval in the second direction.

[0075] The internal electrode patterns 221 and 222 contain conductive metals such as nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, and can be printed on dielectric ceramic sheets 201 and 202. The printing method for the internal electrode patterns 221 and 222 can be screen printing or gravure printing, but the present invention is not limited thereto.

[0076] The step of forming the above-mentioned laminate 200 can be carried out by laminating the internal electrode patterns 221, 222 and the dielectric ceramic sheets 201, 202, 203 onto the support film 310 and pressing them together.

[0077] Referring to Figures 7(a) and 7(b), the laminate 200 can be cut along mutually orthogonal cutting lines C1-C1 and C2-C2. The C1-C1 cutting line is a cutting line parallel to the second direction and is substantially equally spaced in the third direction, and the C2-C2 cutting line is a cutting line parallel to the third direction and is substantially equally spaced in the second direction. The C1-C1 cutting line can form a laminate chip 210 having substantially a constant size in the third direction, and the C2-C2 cutting line can form a laminate chip 210 having substantially a constant size in the second direction.

[0078] The means for cutting the laminate 200 are not particularly limited. For example, the laminate 200 can be cut using a blade cutting method such as a doctor blade or dicing blade, a guillotine cutting method, or a laser cutting method.

[0079] Referring to Figure 8(a), after cutting the laminate 200 to form the laminated chips 210, a step can be taken to widen the spacing between the multiple laminated chips 210. This can be done by stretching the support film 310 in a second and a third direction, but is not limited to this, and may also be done by moving the multiple laminated chips 210 to a separate support film.

[0080] Referring to Figure 8(b), a step can be taken in which the side margin attachment surfaces ES5 and ES6 of the stacked chip 210 are released. This step is a process in which the fifth or sixth side surfaces ES5 and ES6, which are the surfaces on which the side margins of multiple stacked chips 210 are formed, are simultaneously released to facilitate the formation of the side margins. As described in the stacked electronic component 100 according to one embodiment, the side margin attachment surface of the stacked chip 210 can be the surface to which both ends of the first internal electrode pattern 221 and the second internal electrode pattern 222 are connected.

[0081] The method for releasing the side margin adhesion surfaces ES5 and ES6 of the stacked chip 210 is not particularly limited. For example, this may be done by rotating multiple unit chips 210 simultaneously or by moving them to another film without rotation.

[0082] Referring to Figures 9(a) and 9(b), the conventional method for forming the side margin involves placing the side margin sheet 13, elastic plate 12, and pressure plate 11' on one side of the side margin adhesion surfaces ES5 and ES6 of the laminated chip 210, and the metal plate 14 on the opposite side. This is followed by a process of applying pressure to the pressure plates 11, 11' and the metal plate 14, and then pressing and punching. This plate-to-plate method of forming the side margin can increase variations in the adhesion force between the laminated chip 210 and the side margin sheet 13 due to variations in the thermal expansion of the metal plate 14 and the pressure plates 11, 11', and the angle between the metal plate 14 and the pressure plates 11, 11'. This can reduce the moisture resistance reliability of the laminated electronic component.

[0083] Referring to Figures 10 to 12, the side margin formation step of the manufacturing method for stacked electronic components according to one embodiment of the present invention can be performed by placing the side margin sheet 13 on the side margin adhesion surfaces ES5 and ES6 and applying pressure with rollers 30 and 30'.

[0084] As a result, instead of the laminated chip 210 and the side margin sheet 13 being pressurized and punched by the pressure generated when surfaces are in contact, the laminated chip 210 and the side margin sheet 13 are pressurized and punched by the pressure generated when surfaces are in contact. This minimizes and homogenizes the spatial distribution of the components involved in the formation process of the side margin, thereby reducing the degree of deformation of the laminated chip 210 by pressing and punching the side margin sheet 13 together, and improving the adhesion force between the laminated chip 210 and the side margin sheet 13.

[0085] On the other hand, the length of rollers 30 and 30' allows rollers 30 and 30' to apply pressure to multiple stacked chips 210 simultaneously. In other words, the step of forming the side margin portion according to one embodiment can be performed simultaneously on multiple stacked chips 210 arranged in a sequence.

[0086] Referring to Figure 10, in the side margin formation stage according to one embodiment, a carrier film 15 connected to the transfer roll 10 and the recovery roll 10' can be positioned, and the laminated chips 210 can be attached to the carrier film 15.

[0087] In this case, the carrier film 15 can lose or improve its adhesive function by irradiation with ultraviolet light, etc., thereby allowing the same process to be repeated on other side margin attachment surfaces that do not have a side margin sheet attached, after the side margin formation process has been performed once.

[0088] On the other hand, the components of the carrier film 15 are not particularly limited. In one example, the carrier film 350 may contain one or more of the following: PET (Polyethylene terephthalate), PU (Polyurethane), PE (Polyethylene), PO (Polyolefin), PS (Poly Styrene), PVC (Poly Vinyl Chloride), and PVDC (Poly Vinylidene Chloride).

[0089] Referring to Figure 10, in one embodiment, the side margin formation step can be performed with multiple laminated chips 210 arranged on one surface of the carrier film 15, thereby allowing the rollers 30, 30' to apply pressure directly to the surface of the carrier film 15 to which the laminated chips 210 are not attached.

[0090] In one embodiment, the side margin formation step may include a pressurizing step S4 in which the side margin sheet 13 is pressed with a pressure roller 30' to adhere to the side margin adhesion surfaces ES5 and ES6, and a punching step S5 in which the side margin sheet 13 adhered to the side margin adhesion surfaces ES5 and ES6 is punched with a punching roller 30.

[0091] The side margin formation step according to one embodiment may include steps S1 to S7, as shown in Figure 10. For convenience of explanation, the pressurizing step S4 and the punching step S5 will be described in detail below, followed by the remaining steps.

[0092] S4 stage In one embodiment, the pressurizing step S4 can be performed by placing the elastic plate 12 and the metal plate 11' on the side margin sheet 13.

[0093] In one embodiment, the metal plate 11' in the pressurizing step S4 can be heated to a temperature higher than room temperature, specifically to a temperature of 50°C to 150°C. This improves the fluidity of the elastic plate 12 and the side margin sheet 13, and can alleviate warping of the multiple laminated chips 210.

[0094] In one embodiment, the pressure roller 30' used in the pressurizing step S4 may include a high-rigidity portion 31 positioned in the center and a low-rigidity portion 32 positioned on the high-rigidity portion 31. The high-rigidity portion 31 can play a role in maintaining the rigidity of the pressure roller 30', and the low-rigidity portion 32 can play a role in reducing variations in pressure applied to each of the multiple laminated chips 210 in the pressurizing step S4 due to their position.

[0095] The material included in the high-rigidity part 31 is not particularly limited, and any material with high rigidity and durability can be used. On the other hand, the material included in the low-rigidity part 32 is not particularly limited, and can be, for example, polyurethane.

[0096] S5 level In one embodiment, the punching step S5 can be performed by placing the elastic plate 12 and the metal plate 11 on the side margin sheet 13.

[0097] In one embodiment, the metal plate 11 during punching step S5 can be maintained at 50°C or below, or at room temperature or a temperature lower than room temperature, to prevent thermal shock. That is, punching step S5 can be performed without heating the metal plate 11. This reduces the fluidity of the side margin sheet 13, and when pressure is applied, areas of the side margin sheet 13 other than those corresponding to the side margin adhesion surfaces ES5 and ES6 may be separated.

[0098] In one embodiment, the punching roller 30 used in punching stage S5 can be made of a high-rigidity part. This allows the pressure applied in punching stage S5 to be effectively transmitted to the side margin sheet 13.

[0099] In one embodiment, the side margin formation step involves placing the side margin sheet 13 on the side margin adhesion surfaces ES5 and ES6 and applying pressure with rollers 30 and 30'. In addition to this step, further steps S1 to S3, S6 and S7 can be performed before and after this step.

[0100] The following sections will provide a detailed explanation of stages S1-S3, S6, and S7.

[0101] S1 stage To perform the side margin formation step, multiple laminated chips 210 can be moved via an adhesive member 20. The adhesive member 20 may have a configuration in which the adhesive film is fixed by a ring.

[0102] The adhesive member 20 can rotate so that the multiple laminated chips 210 face the carrier film 15, and move so that the multiple laminated chips 210 adhere to the carrier film 15.

[0103] S2 stage After the multiple laminated chips 210 have been attached to the carrier film 15, the adhesive member 20 can be separated from the multiple laminated chips 210. Such separation can be achieved by adjusting the adhesive force between the multiple laminated chips 210 and the carrier film 15 so that it is greater than the adhesive force between the multiple laminated chips 210 and the adhesive member 20.

[0104] The method for adjusting the adhesive strength between the carrier film 15 and the laminated chip 210 is not particularly limited. As an example, a method can be used to increase or decrease the adhesive strength of the carrier film 15 depending on the wavelength of ultraviolet light.

[0105] S3 stage After step S2 described above, a side margin sheet 13 can be placed on the side margin adhesion surface of the laminated chip 210. At this point, since the pressurizing step S4 or punching step S5 has not yet been performed on the side margin sheet 13, the adhesive force between the side margin sheet 13 and the laminated chip 210 may be minimal. On the other hand, in order to further improve the adhesive force between the laminated chip 210 and the side margin sheet 13, an additional adhesive layer may be placed between the laminated chip 210 and the side margin sheet 13.

[0106] S6 stage After the punching step S5 described above, a step can be taken to separate the laminated chip 210' to which the side margin sheet 13 is attached from the carrier film 15. The method for separating the laminated chip 210' to which the side margin sheet 13 is attached from the carrier film 15 is not particularly limited. For example, a method can be used in which an ultraviolet irradiation unit 16 is placed below the carrier film 15 and ultraviolet light is irradiated onto the carrier film 15 to reduce or eliminate the adhesive strength between the laminated chip 210' and the carrier film 15.

[0107] S7 levels After step S6 described above, a step can be performed to separate the laminated chip 210' to which the side margin sheet 13 is attached from the carrier film 15 using the adhesive member 20. Since the laminated chip 210' to which the side margin sheet 13 is attached has reduced or lost its adhesive strength to the carrier film 15 after step S6, it can adhere to the adhesive member 20 and be separated from the carrier film 15.

[0108] On the other hand, in the side margin formation step according to one embodiment shown in Figure 10, the side margin sheet is attached to either the side margin attachment surface ES5 or ES6 of the laminated chip 210. Therefore, after performing steps S1 to S7 on either the side margin attachment surface ES5 or ES6, the same steps S1 to S7 can be performed on other side margin attachment surfaces that do not have the side margin sheet 13 attached, thereby attaching the side margin sheet 13 to all side margin attachment surfaces ES5 and ES6.

[0109] Subsequently, the process may include a body formation step in which the laminated chip 210' with the side margin sheet 13 attached is fired. The firing temperature is not particularly limited, but for example, it can be fired at 1000 to 1300°C. The firing can also be carried out in a reducing atmosphere.

[0110] Subsequently, the stacked electronic component 100 can be manufactured by forming external electrodes 131 and 132 on one and the other surface of the main body 110 in the second direction, respectively. The external electrodes 131 and 132 can be formed by placing a conductive paste containing a metal with excellent electrical conductivity on one and the other surfaces 3 and 4 in the second direction, respectively, and firing them together with the main body 110.

[0111] On the other hand, referring to Figures 11 and 12, the rollers 30 and 30' can move along the X direction, which is the transport direction of the carrier film 15 or laminated chip 210, and along the -X direction, which is the opposite direction. They can also move along the Z direction, which is perpendicular to the X direction and is the direction in which the side margin sheet 13, elastic plate 12, and metal plate 11 are laminated, and along the -Z direction, which is the opposite direction. Meanwhile, pressure during the pressing and punching stages can be applied by the rollers 30 and 30' moving along the Z direction, which is the side margin sheet side.

[0112] In one embodiment, rollers 30 and 30' can be connected to a drive unit in order to drive them. In this case, the drive unit may include a servo motor 40, a vertical movement rod 41 connected to the servo motor 40, and a horizontal movement rod 42.

[0113] In one embodiment, the rollers 30 and 30' can move along one or more axes of the X-axis and Z-axis directions in accordance with the movement of the drive unit. At this time, the Z-axis displacement of the rollers 30 and 30' can be determined by the relative position between the laminated chip 210 and the rollers 30 and 30', and the X-axis movement speed can be determined by the time required for the process.

[0114] In one embodiment, the vertical movement rod 41 and the horizontal movement rod 42 can be formed from pneumatic cylinders, but are not limited to this, and the servo motor 40 can be connected to a support 50 fixed to the drive unit.

[0115] (Experimental Example 1) Table 1 below shows the results of measuring the average value avg, standard deviation std, and coefficient of variation Cv of the thickness T and width W of the main body after firing, for the initial laminated chip state in which the average thickness was 455 μm and the average width was 450 μm, and performing the side margin formation step according to the conventional (comparative example) method and the side margin formation step according to the present invention (Examples 1, 2, and 3).

[0116] On the other hand, Figure 13 is a graph showing the thickness of the main body for the comparative example and the example, and in the case of the example, it is the average value of the values ​​measured in Examples 1 to 3.

[0117] On the other hand, the average values ​​for the thickness and width of the stacked chip and the main body were measured by taking the average values ​​for the maximum thickness and maximum width of the stacked chip and the main body, respectively.

[0118] Approximately 100,000 samples were prepared for each comparative example and each example. The experimental conditions for the comparative example and Examples 1-3 were identical, except that in the comparative example, pressurization and punching were performed using a pressurizing plate and a metal plate, while in Examples 1-3, pressurizing punching was performed using a metal plate and a pressurizing roller.

[0119] [Table 1]

[0120] Referring to Table 1, it can be confirmed that Examples 1, 2, and 3 have smaller T_avg values ​​and larger W_avg values ​​than the comparative example. During the side margin formation stage, pressure is applied in the width direction of the laminated chip, so it can be confirmed that Examples 1, 2, and 3, which have smaller T_avg values ​​and larger W_avg values ​​than the comparative example, exhibit smaller size changes than the comparative example.

[0121] On the other hand, in Examples 1, 2, and 3, the T_std, T_Cv, W_std, and W_Cv values ​​are lower than in the comparative example, confirming that the variation in chip size after firing is less in Examples 1, 2, and 3 than in the comparative example.

[0122] Therefore, in the side margin formation step of the manufacturing method for stacked electronic components according to one embodiment of the present invention, the side margin sheet 13 is placed on the side margin adhesion surfaces ES5 and ES6 and pressure is applied with rollers 30 and 30', thereby providing stacked electronic components with reduced size variation compared to conventional methods.

[0123] (Experimental Example 2) Figures 14(a) and 14(b) are graphs showing the results of the combined reliability evaluation of multilayer electronic components using comparative examples and examples.

[0124] Samples were prepared by performing the side margin formation step according to the conventional method (comparative example) and the side margin formation step according to one embodiment of the present invention (Examples 1, 2, and 3), followed by firing, and then forming external electrodes. The experimental conditions for the comparative example and the examples were identical, except that in the comparative example, pressing and punching were performed using a press plate and a metal plate, while in the examples, pressing and punching were performed using a press plate and rollers.

[0125] The comparative examples and examples were each conducted with 400 samples. The evaluation conditions were 85% relative humidity, 85°C, 4.8vr, and 4hr. Insulation resistance (IR) was measured, and a decrease in insulation resistance value to 10^4 (Ω) or less was considered unreliable.

[0126] Referring to Figure 14(a), it can be confirmed that defects occur in the case of the multilayer electronic component in the comparative example, while referring to Figure 14(b), it can be confirmed that the moisture resistance reliability is excellent because no defects occur.

[0127] Therefore, in the side margin formation step of the method for manufacturing a stacked electronic component according to one embodiment of the present invention, by placing the side margin sheet 13 on the side margin adhesion surfaces ES5 and ES6 and applying pressure with rollers 30 and 30', it can be confirmed that the moisture resistance reliability is improved compared to the conventional method. [Explanation of symbols]

[0128] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 114, 115 Side margin section 121, 122 Internal electrode 131, 132 External electrode 200-layer structure 210 stacked chips 201, 202, 203 Dielectric ceramic sheets 221, 222 Internal electrode patterns 310 Support film 300 Laminated Bar 10 Transfer Rolls 10' Recovery Roll 11, 11' Crimping Plate 12 Elastic plates 13 Side margin sheets 14 Metal Plates 15 Carrier film 16. UV irradiation area 20 Adhesive members 30, 30' Laura 31 High rigidity part 32 Low rigidity part 41 Vertical movement rod 42 Horizontal movement rod 40 Servo motors 50 Support part

Claims

1. The steps include: arranging dielectric ceramic sheets, a first internal electrode pattern, and a second internal electrode pattern alternately to form a laminated chip including a side margin attachment surface connected to the first internal electrode pattern and the second internal electrode pattern; The steps include forming a side margin portion on the side margin portion attachment surface, The steps include firing the laminated chip on which the side margin portion is formed to form the main body, The step includes forming an external electrode on the main body, The step of forming the side margin portion is carried out by placing the side margin sheet on the side margin portion attachment surface and applying pressure with a roller. Manufacturing method for multilayer electronic components.

2. The step of forming the side margin portion includes a pressing step of pressing the side margin sheet with a pressure roller to adhere it to the side margin portion adhesion surface and a punching step of punching the side margin sheet with a punching roller. A method for manufacturing a stacked electronic component according to claim 1.

3. The pressurization step is performed by placing an elastic plate and a metal plate on the side margin sheet. A method for manufacturing a stacked electronic component according to claim 2.

4. The pressurizing step is performed by heating the metal plate. A method for manufacturing a stacked electronic component according to claim 3.

5. The pressurization step is carried out by heating the metal plate to a temperature of 50°C to 150°C. A method for manufacturing a stacked electronic component according to claim 4.

6. The punching step is performed by placing the elastic plate and the metal plate on the side margin sheet. A method for manufacturing a stacked electronic component according to claim 2.

7. The punching step is performed while the metal plate is not heated. A method for manufacturing a stacked electronic component according to claim 6.

8. The pressure roller includes a high-rigidity portion and a low-rigidity portion disposed on the high-rigidity portion. A method for manufacturing a stacked electronic component according to claim 2.

9. The punching roller includes a high-rigidity section. A method for manufacturing a stacked electronic component according to claim 2.

10. The stacked chips form a plurality of arrays, The step of forming the side margin portion is performed simultaneously on the stacked chips which form a plurality of arrays. A method for manufacturing a stacked electronic component according to claim 1.

11. The aforementioned stacked chips form multiple arrays and adhere to the carrier film. The step of forming the side margin portion is performed by applying pressure to the surface of the carrier film to which the roller does not have the laminated chips forming the plurality of arrangements attached. A method for manufacturing a stacked electronic component according to claim 1.

12. The step of forming the side margin portion is performed when the roller is connected to the drive unit and moves toward the side margin sheet. A method for manufacturing a stacked electronic component according to claim 1.

13. The drive unit includes a servo motor, a vertical movement rod and a horizontal movement rod. A method for manufacturing a stacked electronic component according to claim 12.

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