Multilayer ceramic capacitor and method for manufacturing the same

Abstract

The present invention provides a multilayer ceramic capacitor with minimal variation in capacitance characteristics and a method for manufacturing the same. [Solution] A multilayer ceramic capacitor according to one embodiment includes a capacitor body comprising a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, wherein the dielectric layer comprises a barium titanate-based main component and minor components comprising cerium (Ce) and dysprosium (Dy), and the Ce / Dy molar ratio is 1 to 10.

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the same.

Background Art

[0002] As electronic components using ceramic materials, there are capacitors, inductors, piezoelectric elements, varistors, or thermistors. Among such ceramic electronic components, a multilayer ceramic capacitor (MLCC) can be used in various electronic devices due to its advantages of being small in size, having a high capacitance, and being easy to mount.

[0003] For example, a multilayer ceramic capacitor (MLCC) can be used as a chip-shaped capacitor mounted on a substrate of various electronic products such as a liquid crystal display (LCD), a plasma display panel (PDP), a video device such as an organic light-emitting diode (OLED), a computer, a personal mobile terminal, and a smartphone to charge or discharge electricity.

[0004] Currently, as MLCCs become ultra-small and highly integrated, the ratio of the active region that determines the capacitance characteristics has increased compared to the cover region and the margin region. Therefore, it has become important to realize a uniform fine structure in the active region.

Summary of the Invention

Problems to be Solved by the Invention

[0007] One embodiment provides a multilayer ceramic capacitor comprising a capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, wherein the dielectric layer comprises a barium titanate-based main component and minor components including cerium (Ce) and dysprosium (Dy), and the Ce / Dy molar ratio is 1 to 10.

[0008] The dielectric layer may include a plurality of dielectric crystal grains.

[0009] The capacitor body includes an active region in which the dielectric layer and the internal electrode layer are arranged alternately, and a cover region in which the dielectric layer is arranged on the upper and lower surfaces of the active region in the thickness direction (T-axis). The active region includes an active center defined as extending from the middle of the active region to a region in the thickness direction (T-axis) where two dielectric layers are visible both above and below, and an active end defined as extending from the boundary between the active region and the cover region to a region in the direction of the active region where four dielectric layers are visible. When the average size of the plurality of dielectric crystal grains in the active center is denoted as D1, and the average size of the plurality of dielectric crystal grains in the active end is denoted as D2, the dielectric crystal grain size deviation rate obtained from the following formula 1 may be 0 or more and less than 10%.

[0010] [Formula 1] Dielectric crystal grain size deviation rate (%) = (|D1-D2| / D1) × 100 (In the above formula 1, D1 and D2 are the average values ​​of the sizes of multiple dielectric crystal grains, and the size of the dielectric crystal grain is the average value of the major axis length and minor axis length of the dielectric crystal grain.)

[0011] If the size deviation rate of the dielectric crystal grains is greater than 0, then D1 can have a value greater than D2.

[0012] The aforementioned D1 may be in the range of 210 nm to 230 nm.

[0013] The aforementioned D2 may be in the range of 200 nm to 220 nm.

[0014] The cerium (Ce) may be present in an amount of 1 to 2 moles per 100 moles of the main barium titanate component.

[0015] The dysprosium (Dy) may be present in an amount of 0.2 to 1 mole per 100 moles of the main barium titanate component.

[0016] The capacitance variation coefficient of the multilayer ceramic capacitor obtained by the following formula 2 may be greater than 0 and less than 3%.

[0017] [Formula 2] Coefficient of variation (Cp CV) (%) = {Standard deviation of capacity (σ1) / Mean of capacity} × 100 (In formula 2 above, the capacity standard deviation (σ1) is the square root of the mean of the squares of the deviations.)

[0018] The dielectric loss variation coefficient of the multilayer ceramic capacitor obtained by the following formula 3 may be greater than 0 and less than 6%.

[0019] [Formula 3] Dielectric loss variation coefficient (DF CV) (%) = {Standard deviation of dielectric loss (σ²) / Mean dielectric loss} × 100 (In equation 3 above, the dielectric loss standard deviation (σ²) is the square root of the mean of the squares of the deviations.)

[0020] Another embodiment includes the steps of mixing barium titanate-based main component powder and sub-component powder to produce a dielectric slurry; using the dielectric slurry to produce a dielectric green sheet and forming a conductive paste layer on the surface of the dielectric green sheet; laminating the dielectric green sheets with the conductive paste layer formed thereon to produce a dielectric green sheet laminate; firing the dielectric green sheet laminate to produce a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on one surface of the capacitor body. The dielectric layer includes a barium titanate-based main component and a sub-component including cerium (Ce) and dysprosium (Dy). The sub-component powder includes a Ce-containing compound and a Dy-containing compound. The Ce-containing compound and the Dy-containing compound are included in a content such that the Ce / Dy molar ratio is 1 to 10. A method for manufacturing a multilayer ceramic capacitor is provided.

[0021] The Ce-containing compound may be included in a content such that the Ce is 1 to 2 mole parts with respect to 100 mole parts of the barium titanate-based main component.

[0022] The Dy-containing compound may be included in a content such that the Dy is 0.2 to 1 mole parts with respect to 100 mole parts of the barium titanate-based main component.

[0023] Each of the Ce-containing compound and the Dy-containing compound may include an oxide, a nitride, a salt compound, or a sol form dispersed in an organic solvent.

Advantages of the Invention

[0024] A multilayer ceramic capacitor according to an embodiment can reduce the variation in capacitance characteristics by reducing the size deviation of dielectric crystallites (grains) by position in the active region and having a uniform microstructure.

Brief Description of the Drawings

[0025] [Figure 1] It is a perspective view showing a multilayer ceramic capacitor according to an embodiment. [Figure 2] This is a cross-sectional view of a multilayer ceramic capacitor cut along the line I-I' in Figure 1. [Figure 3] This is a cross-sectional view of a multilayer ceramic capacitor cut along the line II-II' in Figure 1. [Figure 4] Figure 1 is a separated perspective view showing the stacked structure of the internal electrode layers in the capacitor body. [Figure 5a] This is a schematic diagram showing the cross-sectional microstructure of one dielectric layer contained in region A of Figure 3. [Figure 5b] This is a schematic diagram showing the cross-sectional microstructure of one dielectric layer contained in region B of Figure 3. [Figure 6] This is an EPMA (Electron Probe Microanalyzer) analysis image of the active center within the active region according to Example 3. [Figure 7] This is an SEM (scanning electron microscope) analysis image of the active region at different locations according to Example 3. [Figure 8] This is an SEM (scanning electron microscope) analysis image of the active region at different locations according to Comparative Example 6. [Figure 9] This graph shows the variation in capacitance (Cp) of multilayer ceramic capacitors in Examples 1-3 and Comparative Examples 1-7. [Figure 10] This graph shows the variation in dielectric loss (dissipation factor, DF) of multilayer ceramic capacitors in Examples 1-3 and Comparative Examples 1-7. [Modes for carrying out the invention]

[0026] Embodiments of the present invention will be described in detail below with reference to the attached drawings so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. In order to clearly illustrate the present invention, unnecessary parts have been omitted from the drawings, and the same or similar components are denoted by the same reference numerals throughout the specification. Furthermore, some components in the attached drawings are exaggerated, omitted, or shown schematically, and the size of each component does not fully reflect its actual size.

[0027] The accompanying drawings are provided solely to facilitate understanding of the embodiments disclosed herein, and it should be understood that the accompanying drawings do not limit the technical ideas disclosed herein and include all modifications, equivalents, or substitutions that fall within the concept and scope of the invention.

[0028] Terms including ordinal numbers, such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. These terms are used solely for the purpose of distinguishing one component from another.

[0029] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on top of" or "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on top of" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on top of" or "above" the opposite side of gravity.

[0030] Throughout the specification, terms such as “includes” or “have” are intended to specify the presence of features, figures, stages, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, stages, operations, components, parts, or combinations thereof. Therefore, when a part “includes” a component, this means that it may include other components rather than excluding them, unless otherwise stated.

[0031] Furthermore, throughout the specification, "on a plane" refers to the view of the subject from above, and "on a cross-section" refers to the view of a cross-section obtained by cutting the subject perpendicularly, viewed from the side.

[0032] Furthermore, throughout the specification, the term "connected" does not only mean that two or more components are directly connected, but can also mean that two or more components are indirectly connected through other components, that they are not only physically connected but also electrically connected, or that they are a single unit despite being referred to by different names depending on their position or function.

[0033] A multilayer ceramic capacitor according to one embodiment will be described below with reference to Figures 1 to 4.

[0034] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to one embodiment; Figure 2 is a cross-sectional view of the multilayer ceramic capacitor cut along the line I-I' in Figure 1; Figure 3 is a cross-sectional view of the multilayer ceramic capacitor cut along the line II-II' in Figure 1; and Figure 4 is a separated perspective view showing the laminated structure of the internal electrode layers in the capacitor body of Figure 1.

[0035] The L-axis, W-axis, and T-axis shown in Figures 1 to 4 represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be perpendicular to the broad surface (main surface) of the sheet-shaped component, and can be used as the same concept as the stacking direction in which the dielectric layer 111 is stacked, for example. The length direction (L-axis direction) extends parallel to the broad surface (main surface) of the sheet-shaped component and may be roughly perpendicular to the thickness direction (T-axis direction), for example, the direction in which the first external electrode 131 and the second external electrode 132 are located on both sides. The width direction (W-axis direction) extends parallel to the broad surface (main surface) of the sheet-shaped component and may be roughly perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction), and the length in the length direction (L-axis direction) of the sheet-shaped component may be even longer than the length in the width direction (W-axis direction).

[0036] Referring to Figures 1 to 4, a multilayer ceramic capacitor 100 according to one embodiment includes a capacitor body 110 and external electrodes 131 and 132 positioned outside the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 positioned at opposite ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0037] The capacitor body 110 may, for example, have a roughly hexahedral shape.

[0038] For the convenience of describing one embodiment, the two surfaces of the capacitor body 110 that face each other in the thickness direction (T-axis direction) are defined as the first and second surfaces, the two surfaces connected to the first and second surfaces that face each other in the length direction (L-axis direction) are defined as the third and fourth surfaces, and the two surfaces connected to the first and second surfaces and connected to the third and fourth surfaces that face each other in the width direction (W-axis direction) are defined as the fifth and sixth surfaces.

[0039] For example, the first surface, which is the bottom surface, may be the surface facing the mounting direction. Also, the first to sixth surfaces may be flat, but this is not the only embodiment. For example, the first to sixth surfaces may be curved surfaces with a convex central portion, and the corners that form the boundaries of each surface may be rounded.

[0040] The shape, dimensions, and number of dielectric layers 111 of the capacitor body 110 are not limited to those shown in the drawings of this embodiment.

[0041] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and first internal electrode layers 121 and second internal electrode layers 122 that are alternately arranged in the thickness direction (T-axis direction) with the dielectric layers 111 in between.

[0042] At this time, the boundaries between adjacent dielectric layers 111 of the capacitor body 110 can become so integrated that they are difficult to confirm without using a scanning electron microscope (SEM).

[0043] The capacitor body 110 may include an active region 120 and cover regions 112, 113.

[0044] The active region 120 is a region in which the dielectric layer 111 and the internal electrode layers 121 and 122 are arranged alternately, and is a part that contributes to the formation of capacitance in the multilayer ceramic capacitor 100. Specifically, the active region 120 may be a region in which the first internal electrode layer 121 or the second internal electrode layer 122, which are stacked along the thickness direction (T-axis direction), overlap.

[0045] The cover regions 112 and 113 are thickness-direction margins and can be arranged on the first and second surfaces of the active region in the thickness direction (T-axis direction), respectively. Such cover regions 112 and 113 may be formed by a single dielectric layer 111 or by two or more dielectric layers 111 being laminated on the upper and lower surfaces of the active region 120, respectively.

[0046] Furthermore, the capacitor body 110 may also include a side margin region.

[0047] The side margin region is a widthwise margin portion and can be located on both opposite ends of the active region 120 in the widthwise direction (W-axis direction), i.e., on the fifth and sixth surfaces, respectively. The side margin region is formed when applying a conductive paste layer for the internal electrode layer to the surface of the dielectric green sheet, by applying the conductive paste layer only to a portion of the surface of the dielectric green sheet, and stacking dielectric green sheets without the conductive paste layer on both sides of the dielectric green sheet surface, and then firing, but the formation method is not limited to this.

[0048] The cover regions 112, 113 and the side margin regions serve to prevent damage to the first internal electrode layer 121 and the second internal electrode layer 122 due to physical or chemical stress.

[0049] The dielectric layer 111 within the active region 120 may contain multiple dielectric crystal grains.

[0050] The dielectric layer 111 may contain a barium titanate-based main component and a secondary component.

[0051] The barium titanate-based main component is a dielectric matrix material that has a high dielectric constant and contributes to the dielectric constant formation of the multilayer ceramic capacitor 100.

[0052] The main component of barium titanate compounds is a compound containing barium (Ba) and titanium (Ti), and may include, for example, BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Ca)O3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, (Ba,Sr)(Ti,Sn)O3, or combinations thereof.

[0053] The minor components may include cerium (Ce) and dysprosium (Dy).

[0054] During the firing process, the matrix particles within the active region undergo densification and grain growth. The dielectric constant and reliability are determined by the size of the grown dielectric crystal grains and the degree of densification. Generally, the degree of grain growth varies depending on the firing conditions and additive composition. However, even with the same firing conditions and additive composition, the degree of grain growth can vary from location to location in the active region, which is the largest region in a multilayer ceramic capacitor. A larger deviation in the size of dielectric crystal grains from location to location in the active region can lead to an increase in capacitance deviation.

[0055] According to one embodiment, cerium (Ce) and dysprosium (Dy) may be included in the dielectric layer 111 in a predetermined range of ratios. Specifically, the molar ratio of Ce to Dy, i.e., the Ce / Dy molar ratio, may be 1 to 10, for example, 2 to 9, 3 to 8, 4 to 7, or 5 to 6. When the Ce / Dy molar ratio is within the above range, the size deviation of the dielectric crystal grains at different positions within the active region 120 can be reduced. That is, by ensuring a uniform microstructure of the dielectric crystal grains throughout the active region 120, it is possible to secure a multilayer ceramic capacitor with less variation in capacitance characteristics, i.e., reduced variation in capacitance characteristics.

[0056] The Ce / Dy molar ratio within the dielectric layer 111 can be determined by electron probe microanalysis (EPMA).

[0057] Specifically, after curing the multilayer ceramic capacitor 100 in an epoxy mixture, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body 110 are polished to half a depth in the L-axis direction. After fixing, the sample is maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample that allows observation of the active region where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect. EPMA analysis is performed on the obtained cross-sectional sample under conditions of an acceleration voltage of 15kV and a residence time of 40ms to confirm the presence of elements in the dielectric layer 111, and the elemental content can be determined from the intensity obtained during EPMA analysis.

[0058] The microstructure of the positional dielectric layers 111 within the active region 120 can be explained through Figures 5a and 5b.

[0059] Figure 5a is a schematic diagram showing the cross-sectional microstructure of one dielectric layer included in region A of Figure 3, and Figure 5b is a schematic diagram showing the cross-sectional microstructure of one dielectric layer included in region B of Figure 3.

[0060] Referring to Figure 3, the active region 120 in one embodiment can include an active central region A, which corresponds to the center, and an active end region B, which corresponds to the end adjacent to the cover regions 112 and 113. Specifically, the active central region A can be defined as the area from the middle of the active region 120 to the area where two dielectric layers are visible both above and below in the thickness direction (T-axis). The active end region B can be defined as the area from the boundary between the active region 120 and the cover regions 112 and 113 to the area where four dielectric layers are visible in the direction of the active region 120. In this case, although only one location of active end region B is shown in Figure 3, this is merely for convenience, and any end of the active region 120 adjacent to the cover regions 112 and 113 can correspond to active end region B.

[0061] Furthermore, referring to Figures 5a and 5b, the dielectric layer 111 within the active region 120 can contain multiple dielectric crystal grains 10.

[0062] According to one embodiment, when the average size of multiple dielectric crystal grains at the active central part A is called D1, and the average size of multiple dielectric crystal grains at the active end B is called D2, the dielectric crystal grain size deviation rate obtained from the following formula 1 may be 0 or more and less than 10%, for example, 0.01% to 9.9% or 0.01% to 9.8%.

[0063] [Formula 1] Dielectric crystal grain size deviation rate (%) = (|D1-D2| / D1) × 100

[0064] When the size deviation rate of the dielectric crystal grains is within the aforementioned range, the overall uniformity of the dielectric crystal grain microstructure in the active region makes it possible to secure a multilayer ceramic capacitor with reduced variation in capacitance characteristics.

[0065] The average sizes D1 and D2 of the dielectric crystal grains can be measured by scanning electron microscopy (SEM) analysis of the active region.

[0066] Specifically, in the cross-sectional sample obtained by the method described above, the active center A is defined as the area from the middle of the active region 120 to the area where two dielectric layers are visible both above and below in the thickness direction (T-axis), and the active end B is defined as the area from the boundary between the active region 120 and the cover regions 112 and 113 to the area where four dielectric layers are visible in the direction of the active region 120. For example, the SEM can be used to measure in an approximately 5 μm × 5 μm area in both the active center A and the active end B, where at least four dielectric layers 111 are visible, under the condition of an acceleration voltage of 2.0 kV. From the SEM image of the measured cross-sectional sample, the average size D1 of multiple dielectric crystal grains present in the active center A and the average size D2 of multiple dielectric crystal grains present in the active end B can be determined.

[0067] The size of a dielectric crystal grain is obtained by the average of the long axis length and short axis length of a single dielectric crystal grain, while the average sizes D1 and D2 of multiple dielectric crystal grains are calculated by the average sizes of multiple dielectric crystal grains located in the active center A and active edge B, respectively. For example, D1 and D2 are obtained by the average size of 100 to 500 dielectric crystal grains, or they may be the average size of 150 to 400 or 200 to 300 dielectric crystal grains.

[0068] Figures 5a and 5b show that the sizes of the dielectric crystal grains 10 differ between the active central region A and the active edge region B, but this is not the only embodiment. In other words, Figures 5a and 5b should be considered merely as aids in understanding the positional size deviation of the dielectric crystal grains in the active region.

[0069] When the size deviation rate of the dielectric crystal grains is greater than 0, D1 can have a value greater than D2, and in this case, the capacitance characteristics of the multilayer ceramic capacitor are excellent.

[0070] The average size D1 of multiple dielectric crystal grains in the active central region A may be 210 nm to 230 nm, for example, 215 nm to 230 nm, or 220 nm to 230 nm. When D1 is within this range, the positional size deviation of dielectric crystal grains within the active region 120 can be reduced, thereby reducing the variation in the capacitance characteristics of the multilayer ceramic capacitor.

[0071] The average size D2 of the multiple dielectric crystal grains at the active end B may be 200 nm to 220 nm, for example, 200 nm to 215 nm or 200 nm to 210 nm. When D2 is within this range, the size deviation of the dielectric crystal grains at different positions within the active region 120 can be reduced, thereby reducing the variation in the capacitance characteristics of the multilayer ceramic capacitor.

[0072] In the dielectric layer 111, cerium (Ce) may be present in an amount of 1 to 2 moles per 100 moles of the barium titanate-based main component, for example, 1.1 to 1.9 moles, 1.2 to 1.8 moles, or 1.3 to 1.7 moles. When cerium (Ce) is present within the above content range, the positional size deviation of the dielectric crystal grains within the active region 120 decreases, and the microstructure of the dielectric crystal grains throughout the active region becomes uniform, thereby ensuring a multilayer ceramic capacitor with reduced variation in capacitance characteristics.

[0073] In the dielectric layer 111, dysprosium (Dy) may be present in an amount of 0.2 to 1 mole per 100 moles of the barium titanate-based main component, for example, 0.3 to 0.9 moles, 0.4 to 0.8 moles, or 0.5 to 0.7 moles. When dysprosium (Dy) is present within the above content range, the positional size deviation of the dielectric crystal grains within the active region 120 decreases, and the microstructure of the dielectric crystal grains throughout the active region becomes uniform, thereby ensuring a multilayer ceramic capacitor with reduced variation in capacitance characteristics.

[0074] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 0.1 μm to 8.0 μm, for example, 0.1 μm to 6.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor is excellent.

[0075] The average thickness of the dielectric layer 111 can be measured by ion milling and scanning electron microscope (SEM) analysis after the multilayer ceramic capacitor 100 has been cured in an epoxy mixture, polished, and then ion milled. For example, a Verios G4 product from Thermofisher Scientific can be used as the scanning electron microscope, with measurement conditions of 10kV and 0.2nA, and the analysis magnification may be 100x. The measurement can be performed so that at least one, three, five, or ten dielectric layers 111 are shown. The scanning electron microscope (SEM) image may also be used to obtain the arithmetic mean of the dielectric layer 111 thickness at 10 points separated by a predetermined interval from the reference point, with the reference point being the center point in the length direction (L-axis direction) or width direction (W-axis direction) of the dielectric layer 111. The spacing between the 10 points can be adjusted by the scale of the scanning electron microscope (SEM) image, for example, between 1 μm and 100 μm, 1 μm and 50 μm, or 1 μm and 10 μm. In this case, all 10 points must be located within the dielectric layer 111. If all 10 points are not located within the dielectric layer 111, the position of the reference point can be changed or the spacing between the 10 points can be adjusted.

[0076] The internal electrode layers 121 and 122, namely the first internal electrode layer 121 and the second internal electrode layer 122, are electrodes having different polarities and are arranged alternately facing each other along the T-axis direction with the dielectric layer 111 in between, with one end of each exposed through the third and fourth surfaces of the capacitor body 110.

[0077] The first internal electrode layer 121 and the second internal electrode layer 122 can be electrically insulated from each other by the dielectric layer 111 placed in between them.

[0078] The ends of the first internal electrode layer 121 and the second internal electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first external electrode 131 and the second external electrode 132, respectively.

[0079] The first internal electrode layer 121 and the second internal electrode layer 122 contain a conductive metal, which may include metals such as Ni, Cu, Ag, Pd, Au, or alloys thereof, such as Ag-Pd alloy.

[0080] Furthermore, the first internal electrode layer 121 and the second internal electrode layer 122 may also contain dielectric particles of the same composition as the ceramic material contained in the dielectric layer 111.

[0081] The first internal electrode layer 121 and the second internal electrode layer 122 can be formed using a conductive paste containing a conductive metal. The conductive paste can be printed using screen printing or gravure printing.

[0082] The average thickness of the first internal electrode layer 121 and the second internal electrode layer 122 may be 0.1 μm to 2 μm. The average thickness of the first internal electrode layer 121 and the second internal electrode layer 122 can be measured by scanning electron microscopy (SEM) analysis. Here, the explanation of scanning electron microscopy (SEM) analysis is the same as the method used to measure the average thickness of the dielectric layer 111 described above, so it will be omitted.

[0083] The capacitor body 110 can be formed by firing a laminate in which multiple dielectric layers 111 and internal electrode layers 121 and 122 are stacked.

[0084] External electrodes 131 and 132, namely the first external electrode 131 and the second external electrode 132, are supplied with voltages of different polarities and can be electrically connected to the exposed portions of the first internal electrode layer 121 and the second internal electrode layer 122, respectively.

[0085] With the above configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge is accumulated between the first internal electrode layer 121 and the second internal electrode layer 122, which are opposite each other. At this time, the capacitance of the multilayer ceramic capacitor 100 becomes proportional to the overlapping area of ​​the first internal electrode layer 121 and the second internal electrode layer 122, which are superimposed on each other along the T-axis in the active region.

[0086] The first external electrode 131 and the second external electrode 132 may each include a first connecting portion and a second connecting portion, which are arranged on the third and fourth surfaces of the capacitor body 110 and connected to the first internal electrode layer 121 and the second internal electrode layer 122, respectively, and a first band portion and a second band portion, which are arranged at the corners where the third and fourth surfaces of the capacitor body 110 meet the first and second surfaces or the fifth and sixth surfaces.

[0087] The first band portion and the second band portion extend from the first and second connection portions to a portion of the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, respectively. The first band portion and the second band portion can serve to improve the adhesion strength of the first external electrode 131 and the second external electrode 132.

[0088] The first external electrode 131 and the second external electrode 132 may each include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer positioned to cover the sintered metal layer, and a plating layer positioned to cover the conductive resin layer.

[0089] The sintered metal layer may contain conductive metals and glass.

[0090] Conductive metals may include copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), alloys thereof, or combinations thereof. For example, copper (Cu) may include copper (Cu) alloys. If the conductive metal contains copper, other metals may be included in amounts of 5 moles or less per 100 moles of copper.

[0091] The glass may contain a composition of mixed oxides, for example, one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni); the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K); and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0092] Selectively, the conductive resin layer can be formed on top of the sintered metal layer, for example, in a form that completely covers the sintered metal layer. On the other hand, the first external electrode 131 and the second external electrode 132 do not have to include a sintered metal layer, in which case the conductive resin layer can be in direct contact with the capacitor body 110.

[0093] The conductive resin layer extends to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, and the length of the region where the conductive resin layer extends to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110 (i.e., the band portion) may be longer than the length of the region where the sintered metal layer extends to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110 (i.e., the band portion). In other words, the conductive resin layer can be formed on top of the sintered metal layer and can be formed in a manner that completely covers the sintered metal layer.

[0094] The conductive resin layer contains a resin and a conductive metal.

[0095] The resin contained in the conductive resin layer is not particularly limited as long as it has bonding and shock-absorbing properties and can be mixed with conductive metal powder to form a paste. Examples include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0096] The conductive metal contained in the conductive resin layer serves to electrically connect with the first internal electrode layer 121 and the second internal electrode layer 122 or the sintered metal layer.

[0097] The conductive metal contained in the conductive resin layer may be spherical, flake-shaped, or a combination thereof. That is, the conductive metal may consist only of flake-shaped elements, only of spherical elements, or a mixture of flake-shaped and spherical elements.

[0098] Here, spherical can include forms that are not perfectly spherical, for example, forms in which the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) is 1.45 or less. Flake powder means powder having a flat and elongated shape, and is not particularly limited, but for example, the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) may be 1.95 or more.

[0099] The first external electrode 131 and the second external electrode 132 may further include a plating layer disposed on the outside of the conductive resin layer.

[0100] The plating layer may include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb), either alone or in alloys thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or it may be a configuration in which nickel (Ni) plating layers and tin (Sn) plating layers are sequentially laminated, or it may be a configuration in which tin (Sn) plating layers, nickel (Ni) plating layers, and tin (Sn) plating layers are sequentially laminated. The plating layer may also include multiple nickel (Ni) plating layers and / or multiple tin (Sn) plating layers.

[0101] The plating layer can improve the mountability of the multilayer capacitor 100 on the substrate, structural reliability, durability against external elements, heat resistance, and equivalent series resistance (ESR).

[0102] A multilayer ceramic capacitor according to one embodiment can reduce variations in capacitance characteristics. Specifically, the capacitance variation coefficient of the multilayer ceramic capacitor obtained by the following formula 2 may be greater than 0 and less than 3%, for example, 0.01% to 2.9%, or 0.01% to 2.8%.

[0103] [Formula 2] Coefficient of variation (Cp CV) (%) = {Standard deviation of capacity (σ1) / Mean of capacity} × 100

[0104] In equation 2 above, the volume standard deviation (σ1) is obtained by squaring the volume deviations, summing them up, dividing by the number of measurements, and finding the square root; that is, it represents the square root of the average of the squares of the volume deviations, as shown in equation 2-1 below.

[0105]

number

[0106] For example, the capacitance of approximately 50 multilayer ceramic capacitors can be measured under 120Hz and 0.5V conditions, and the average capacitance can be calculated by taking the average of these values.

[0107] Furthermore, the dielectric loss variation coefficient of the multilayer ceramic capacitor obtained by the following formula 3 may be greater than 0 and less than 6%, for example, 0.01% to 5.8%, or 0.01% to 5.6%.

[0108] [Formula 3] Dielectric loss variation coefficient (DF CV) (%) = {Standard deviation of dielectric loss (σ²) / Mean dielectric loss} × 100

[0109] In equation 3 above, the dielectric loss standard deviation (σ²) is obtained by squaring the dielectric loss deviations, summing them up, dividing by the number of measurements, and finding the square root; that is, it represents the square root of the average of the squares of the dielectric loss deviations, as shown in equation 3-1 below.

[0110]

number

[0111] For example, the dielectric loss of approximately 50 multilayer ceramic capacitors can be measured under 120Hz and 0.5V conditions, and the average dielectric loss can be calculated by taking the average of these measurements.

[0112] The following describes a method for manufacturing a multilayer ceramic capacitor 100 according to one embodiment.

[0113] A multilayer ceramic capacitor 100 according to one embodiment can be manufactured by the following steps: mixing barium titanate-based main component powder and auxiliary component powder to produce a dielectric slurry; manufacturing a dielectric green sheet using the dielectric slurry and forming a conductive paste layer on the surface of the dielectric green sheet; laminating the dielectric green sheets on which the conductive paste layer is formed to produce a dielectric green sheet laminate; firing the dielectric green sheet laminate to produce a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on one surface of the capacitor body.

[0114] The barium titanate-based main component powder is a compound containing barium (Ba) and titanium (Ti), and may include, for example, BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Ca)O3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, (Ba,Sr)(Ti,Sn)O3, or combinations thereof.

[0115] The auxiliary component powder may contain Ce-containing compounds and Dy-containing compounds.

[0116] The Ce-containing compound and the Dy-containing compound may be included in a content such that the molar ratio of Ce to Dy, i.e., the Ce / Dy molar ratio, is 1 to 10. For example, they may be included in a content such that the Ce / Dy molar ratio is 2 to 9, 3 to 8, 4 to 7, or 5 to 6. When the Ce-containing compound and the Dy-containing compound are included within the above molar ratio range, the size deviation of the dielectric crystal grains at different positions within the active region 120 decreases, thereby ensuring a multilayer ceramic capacitor with reduced variation in capacitance characteristics.

[0117] The Ce-containing compound may be present in a content of 1 to 2 moles of Ce per 100 moles of the barium titanate-based main component, for example, in a content of 1.1 to 1.9 moles, 1.2 to 1.8 moles, or 1.3 to 1.7 moles. When the Ce-containing compound is present within the above content range, the microstructure of the dielectric crystal grains is uniform throughout the active region, thereby reducing variations in the capacitance characteristics of the multilayer ceramic capacitor.

[0118] The Dy-containing compound may contain Dy in an amount of 0.2 to 1 mole per 100 moles of the barium titanate-based main component, for example, 0.3 to 0.9 moles, 0.4 to 0.8 moles, or 0.5 to 0.7 moles. When the Dy-containing compound is included within the above content range, the microstructure of the dielectric crystal grains is uniform throughout the active region, thereby reducing variations in the capacitance characteristics of the multilayer ceramic capacitor.

[0119] The Ce-containing compound and the Dy-containing compound may be oxides, nitrides, or salt compounds, respectively, or they may be used in sol form dispersed in an organic solvent.

[0120] Dielectric slurry can be manufactured by additionally mixing solvents with additives such as dispersants, binders, plasticizers, lubricants, and antistatic agents.

[0121] The dispersant may include, for example, phosphate ester-based dispersants, polycarboxylic acid-based dispersants, or combinations thereof. The dispersant may be mixed in an amount of 0.1 to 5 parts by weight per 100 parts by weight of the barium titanate-based main component powder, or for example, 0.3 to 3 parts by weight. When the dispersant is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0122] The binder may be, for example, an acrylic resin, a polyvinyl butyral resin, a polyvinyl acetal resin, or an ethylcellulose resin. The binder may be added in an amount of 0.1 to 50 parts by weight per 100 parts by weight of the barium titanate-based main component powder, for example, 3 to 30 parts by weight. When the binder is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0123] The plasticizer may be, for example, phthalate compounds such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, and di(2-ethylbutyl) phthalate; adipic acid compounds such as dihexyl adipic acid and di(2-ethylhexyl) adipic acid; glycol compounds such as ethylene glycol, diethylene glycol, and triethylene glycol; or glycol ester compounds such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), and triethylene glycol di(2-ethylhexanoate). The plasticizer may be added in an amount of 0.1 to 20 parts by weight per 100 parts by weight of the barium titanate main component powder, for example, in an amount of 1 to 10 parts by weight. When the plasticizer is mixed within the above content range, the dispersion of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0124] The solvent may be an aqueous solvent such as water; an alcohol solvent such as ethanol, methanol, benzyl alcohol, or methoxyethanol; a glycol solvent such as ethylene glycol or diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate, or butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether, or tetrahydrofuran; or an aromatic solvent such as benzene, toluene, or xylene. For example, an alcohol solvent or an aromatic solvent can be used, taking into consideration the solubility and dispersibility of the various additives contained in the dielectric slurry. The solvent may be mixed in an amount of 50 to 1000 parts by weight per 100 parts by weight of the barium titanate main component powder, or for example, 100 to 500 parts by weight. When the solvent is mixed within the above content range, the dielectric slurry components can be sufficiently mixed, and the solvent can be easily removed thereafter.

[0125] The aforementioned dielectric slurry can be mixed using a wet ball mill or a stirring mill. When using zirconia balls in a wet ball mill, a large number of zirconia balls with diameters from 0.1 mm to 10 mm can be used for wet mixing for 8 to 48 hours, or 10 to 24 hours.

[0126] The manufactured dielectric slurry is formed as a dielectric layer after firing.

[0127] Methods for forming the manufactured dielectric slurry into a sheet shape include tape molding methods such as the doctor blade method and the calender roll method, or, for example, an on-roll molding coater with a head discharge system. A dielectric green sheet can then be obtained by drying the molded body.

[0128] To form a conductive paste layer that will become the internal electrode layer after firing, a conductive paste can be manufactured by mixing conductive powder made of a conductive metal or an alloy thereof, a binder, and a solvent. Barium titanate powder may also be mixed in as a co-material if necessary. The co-material can suppress the sintering of the conductive powder during the firing process. The conductive paste layer is then formed by applying the conductive paste in a predetermined pattern to the surface of a dielectric green sheet using various printing methods such as screen printing or transfer methods.

[0129] The conductive powder may include nickel (Ni) or a nickel (Ni) alloy.

[0130] Next, a dielectric green sheet laminate is manufactured by stacking multiple dielectric green sheets with internal electrode patterns formed on them in layers, and then pressing them in the stacking direction. At this time, the dielectric green sheets and internal electrode layer patterns can be stacked such that dielectric green sheets are positioned on the upper and lower surfaces of the dielectric green sheet laminate in the stacking direction.

[0131] The manufacturing dielectric green sheet laminate can be selectively cut to predetermined dimensions by dicing or other methods.

[0132] Furthermore, the dielectric green sheet laminate can be solidified and dried to remove plasticizers and other substances as needed, and after solidification and drying, it can be barrel polished using a horizontal centrifugal barrel polishing machine or the like. In barrel polishing, the dielectric green sheet laminate is placed in a barrel container along with media and polishing fluid, and rotational motion or vibration is applied to the barrel container to polish away unwanted parts such as burrs generated during cutting. After barrel polishing, the dielectric green sheet laminate is washed with a cleaning solution such as water and then dried.

[0133] Next, the dielectric green sheet laminate can be debindered (plasticized) and fired to manufacture a capacitor body.

[0134] The debinding treatment conditions can be appropriately adjusted depending on the composition of the dielectric layer and the internal electrode layer. For example, the heating rate during debinding may be 5°C / hour to 300°C / hour, the support temperature 180°C to 400°C, and the temperature maintenance time 0.5 hours to 24 hours. The atmosphere during debinding may be air or a reducing atmosphere.

[0135] The firing conditions can be appropriately adjusted depending on the main component composition of the dielectric layer and the internal electrode layer. For example, firing can be carried out at a temperature of 1100°C to 1400°C, for example, 1200°C to 1350°C. Furthermore, firing can be carried out for 0.5 hours to 8 hours, for example, 1 hour to 3 hours. Also, firing can be carried out in a reducing atmosphere, for example, a humidified atmosphere of a mixed gas of nitrogen and hydrogen, for example, under conditions of a hydrogen concentration of 1.0% or less. If the internal electrode layer contains nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the firing atmosphere should be 1.0 × 10⁻⁶. -14 MPa ~ 1.0 × 10 -10 MPa is also acceptable.

[0136] After firing, annealing can be performed as needed. Annealing is a process to re-oxidize the dielectric layer, and can be performed when firing is carried out in a reducing atmosphere. The conditions for the annealing process can also be appropriately adjusted depending on the composition of the dielectric layer. For example, the temperature during annealing may be 950°C to 1150°C, the time may be 0 to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen gas (N2) atmosphere, and the oxygen partial pressure may be 1.0 × 10⁻⁶. -9 MPa ~ 1.0 × 10 -5 MPa is also acceptable.

[0137] For debinding, calcination, or annealing processes, a wetter, for example, can be used to humidify nitrogen gas or a mixed gas, in which case the water temperature may be between 5°C and 75°C. Debinding, calcination, and annealing processes can be performed continuously or independently.

[0138] Selectively, the third and fourth surfaces of the manufactured capacitor body 110 can be subjected to surface treatments such as sandblasting, laser irradiation, and barrel polishing. By performing such surface treatments, the edges of the first and second internal electrode layers are exposed on the outermost surfaces of the third and fourth surfaces, thereby improving the electrical connection between the first and second external electrodes and the first and second internal electrode layers, and potentially facilitating the formation of alloy parts.

[0139] Next, an external electrode is formed on one surface of the manufactured capacitor body 110.

[0140] As an example, a sintered metal layer can be formed by applying a paste for forming a sintered metal layer to an external electrode and then sintering it.

[0141] The paste for forming a sintered metal layer may contain conductive metals and glass. The explanation of conductive metals and glass is the same as described above, so repeated explanations will be omitted. The paste for forming a sintered metal layer may also selectively contain binders, solvents, dispersants, plasticizers, oxide powders, etc. Binders can include, for example, ethyl cellulose, acrylic, butyral, and solvents can include organic solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, and toluene, or aqueous solvents.

[0142] Methods for applying the sintered metal layer-forming paste to the outer surface of the capacitor body 110 include the dip method, various printing methods such as screen printing, application methods using dispensers, and spraying methods using sprays. The sintered metal layer-forming paste is applied to at least the third and fourth surfaces of the capacitor body 110, and can also be applied to parts of the first, second, fifth, or sixth surfaces where the band portions of the first and second external electrodes are selectively formed.

[0143] Subsequently, the capacitor body 110 coated with the paste for forming a sintered metal layer is dried and sintered at a temperature of 700°C to 1000°C for 0.1 to 3 hours to form a sintered metal layer.

[0144] A conductive resin layer can be selectively formed on the outer surface of the obtained capacitor body 110 by applying a conductive resin layer-forming paste and then curing it.

[0145] The paste for forming a conductive resin layer may contain a resin and, selectively, a conductive metal or a non-conductive filler. The descriptions of conductive metals and resins are the same as those given above, so repeated explanations will be omitted. The paste for forming a conductive resin layer may also selectively contain a binder, solvent, dispersant, plasticizer, oxide powder, etc. Binders can be, for example, ethyl cellulose, acrylic, or butyral, and solvents can be organic solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, or toluene, or aqueous solvents.

[0146] As an example, the conductive resin layer can be formed by dipping the capacitor body 110 into a conductive resin layer forming paste and then curing it, or by printing the conductive resin layer forming paste onto the surface of the capacitor body 110 using a screen printing method or gravure printing method, or by applying the conductive resin layer forming paste to the surface of the capacitor body 110 and then curing it.

[0147] Next, a plating layer is formed on the outside of the conductive resin layer.

[0148] For example, the plating layer can be formed by a plating method, and can also be formed by sputtering or electroplating (electric deposition).

[0149] The embodiments described above will be explained in more detail below through the examples provided. However, the following examples are for illustrative purposes only and do not limit the scope of rights.

[0150] [Examples] (Manufacturing of multilayer ceramic capacitors) Examples 1-3 and Comparative Examples 1-7 A dielectric slurry was prepared by mixing BaTiO3 as the main component powder and CeO2 and Dy2O3 as secondary component powders to achieve the Ce and Dy content shown in Table 1 below. In Table 1 below, the Ce and Dy content are shown in molar parts relative to 100 molar parts of BaTiO3.

[0151] During the production of the dielectric slurry, mixing was carried out by using zirconia balls (ZrO2 balls) as the dispersion medium, adding ethanol / toluene, a wetting dispersant, and polyvinyl butyral (PVB) resin as a binder, and then mechanically milling the mixture.

[0152] Dielectric green sheets were manufactured using a head-dispensing type on-roll molding coater with the manufactured dielectric slurry.

[0153] A dielectric green sheet laminate was manufactured by printing a conductive paste layer containing nickel (Ni) onto the surface of a dielectric green sheet, and then laminating and pressing the dielectric green sheets with the conductive paste layer formed on them.

[0154] The dielectric green sheet laminate was subjected to a plasticizing process at a temperature of 400°C or lower and in a nitrogen atmosphere, followed by firing at a firing temperature of 1300°C or lower and a hydrogen concentration of 1.0% H2 or lower.

[0155] Next, the multilayer ceramic capacitor was manufactured through processes such as the addition of external electrodes and plating.

[0156] [Table 1]

[0157] Evaluation 1: EPMA Analysis Electron probe microanalysis (EPMA) was performed on the multilayer ceramic capacitors manufactured in Examples 1-3 and Comparative Examples 1-7, and the results are shown in Figure 6.

[0158] Specifically, the multilayer ceramic capacitors manufactured in Examples 1-3 and Comparative Examples 1-7 were cured in an epoxy mixture. Then, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body were polished to half a depth in the L-axis direction. After fixing, the capacitors were maintained in a vacuum atmosphere chamber to obtain cross-sectional samples that allowed observation of the active region where the dielectric layer and the internal electrode layer intersected. EPMA analysis was performed on the obtained cross-sectional samples under conditions of an acceleration voltage of 15kV and a residence time of 40ms to confirm the elements and their content present in the dielectric layer.

[0159] Figure 6 shows an EPMA (Electron Probe Microanalyzer) analysis image of the active region according to Example 3.

[0160] Referring to Figure 6, it can be confirmed that Ce and Dy are detected in the dielectric layer in the active region according to one embodiment, and that Ce and Dy are present in the Ce / Dy molar ratio shown in Table 1.

[0161] Evaluation 2: SEM analysis SEM (scanning electron microscope) analysis was performed on the multilayer ceramic capacitors manufactured in Examples 1-3 and Comparative Examples 1-7, and the results are shown in Table 2, Figure 7, and Figure 8 below.

[0162] Specifically, for the active region of the cross-sectional sample obtained in Evaluation 1, SEM measurements were performed on the active center A, defined as the area from the middle of the active region to where two dielectric layers are visible both above and below in the thickness direction (T-axis), and on the active end B, defined as the area from the boundary between the active region and the cover region to where four dielectric layers are visible in the direction of the active region. The SEM measurements were performed in an approximately 5 μm × 5 μm area where four dielectric layers 111 were visible in both the active center A and the active end B, under the condition of an acceleration voltage of 2.0 kV. From the SEM images of the measured cross-sectional sample, the average size D1 of multiple dielectric crystal grains present in the active center A and the average size D2 of multiple dielectric crystal grains present in the active end B were determined, and then the size deviation rate (%) of the dielectric crystal grains was calculated.

[0163] The size deviation rate (%) of dielectric crystal grains was obtained from the following formula 1. Here, D1 and D2 were calculated as the average values ​​of the sizes of multiple dielectric crystal grains present in the active center A and active edge B, respectively. In this case, the size of the dielectric crystal grain was obtained as the average value of the long axis length of the dielectric crystal grain measured using the Max fret diameter and the short axis length of the dielectric crystal grain measured using the orthogonal fret diameter.

[0164] [Formula 1] Dielectric crystal grain size deviation rate (%) = (|D1-D2| / D1) × 100

[0165] Figure 7 shows SEM (scanning electron microscope) analysis images of the active regions at different locations according to Example 3, and Figure 8 shows SEM (scanning electron microscope) analysis images of the active regions at different locations according to Comparative Example 6.

[0166] Referring to Table 2 and Figures 7 and 8 below, it can be seen that in Examples 1 to 3, the size deviation rate of the dielectric crystal grains is less than 10%, indicating less size deviation compared to Comparative Examples 1 to 7. This shows that in one embodiment, when the Ce / Dy molar ratio in the dielectric layer is in the range of 1 to 10, the size deviation of the dielectric crystal grains at different positions decreases in the active region, resulting in a uniform microstructure.

[0167] Rating 3: Capacity characteristics Capacitance characteristics were measured for the multilayer ceramic capacitors manufactured in Examples 1-3 and Comparative Examples 1-7, and the results are shown in Table 2, Figure 9, and Figure 10 below.

[0168] Specifically, 50 multilayer ceramic capacitors manufactured in Examples 1-3 and Comparative Examples 1-7 were prepared. Then, their capacitance was measured using a 4268A Capacitance Meter under 120Hz and 0.5V conditions. The average values ​​were calculated to determine the capacitance average, and the capacitance variation coefficient was then calculated.

[0169] In Table 2 below, the coefficient of variation of capacity was obtained by the following formula 2. Here, the standard deviation of capacity (σ1) represents the square root of the mean of the squares of the capacity deviations.

[0170] [Formula 2] Coefficient of variation (Cp CV) (%) = {Standard deviation of capacity (σ1) / Mean of capacity} × 100

[0171] Furthermore, 50 multilayer ceramic capacitors manufactured in Examples 1-3 and Comparative Examples 1-7 were prepared, and their dielectric losses were measured at 120Hz and 0.5V using a 4268A Capacitance Meter. The average values ​​of these measurements were calculated to determine the average dielectric loss, and the dielectric loss variation coefficient was then calculated.

[0172] In Table 2 below, the dielectric loss variation coefficient was obtained by the following formula 3. Here, the dielectric loss standard deviation (σ1) represents the square root of the mean of the squares of the dielectric loss deviations.

[0173] [Formula 3] Dielectric loss variation coefficient (DF CV) (%) = {Standard deviation of dielectric loss (σ²) / Mean dielectric loss} × 100

[0174] Figure 9 is a graph showing the variation in capacitance (Cp) of multilayer ceramic capacitors for Examples 1-3 and Comparative Examples 1-7, and Figure 10 is a graph showing the variation in dielectric loss (dissipation factor, DF) of multilayer ceramic capacitors for Examples 1-3 and Comparative Examples 1-7.

[0175] Referring to Table 2 and Figures 9 and 10 below, it can be confirmed that in Examples 1 to 3, the capacitance variation coefficient is less than 3% and the dielectric loss variation coefficient is less than 6% compared to Comparative Examples 1 to 7. This shows that in one embodiment, when the Ce / Dy molar ratio in the dielectric layer is in the range of 1 to 10, the variation in capacitance characteristics is reduced because the positional size deviation of the dielectric crystal grains decreases in the active region, resulting in a uniform microstructure.

[0176] [Table 2]

[0177] While preferred embodiments of the present invention have been described above, the present invention is not limited thereto. It can be implemented in various ways within the scope of the claims, the detailed description of the invention, and the attached drawings, and these also naturally fall within the scope of the present invention. [Explanation of symbols]

[0178] 10: Dielectric crystal grain 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 121: First internal electrode layer 122: Second internal electrode layer 131: 1st external electrode 132:Second external electrode

Claims

1. A capacitor body including a dielectric layer and an internal electrode layer, The capacitor body includes an external electrode disposed on the outside of the capacitor body, The dielectric layer comprises a barium titanate-based main component and minor components including cerium (Ce) and dysprosium (Dy). A multilayer ceramic capacitor with a Ce / Dy molar ratio of 1 to 10.

2. The multilayer ceramic capacitor according to claim 1, wherein the dielectric layer includes a plurality of dielectric crystal grains.

3. The capacitor body includes an active region in which the dielectric layer and the internal electrode layer are arranged alternately with respect to each other, and a cover region in which the dielectric layer is arranged on the upper and lower surfaces of the active region in the thickness direction (T-axis). The active region includes an active central area defined as extending from the middle of the active region to an area where two dielectric layers are visible both above and below in the thickness direction (T-axis), and an active end area defined as extending from the boundary between the active region and the cover region to an area where four dielectric layers are visible in the direction of the active region. The multilayer ceramic capacitor according to claim 2, wherein the average size of the plurality of dielectric crystal grains at the active center is denoted as D1, and the average size of the plurality of dielectric crystal grains at the active end is denoted as D2, and the dielectric crystal grain size deviation rate obtained from the following formula 1 is 0 or more and less than 10%. [Formula 1] Dielectric crystal grain size deviation rate (%) = (|D1 - D2| / D1) × 100 (In the above formula 1, D1 and D2 are the average values ​​of the sizes of multiple dielectric crystal grains, and the size of the dielectric crystal grain is the average value of the major axis length and minor axis length of the dielectric crystal grain.)

4. The multilayer ceramic capacitor according to claim 3, wherein the size deviation ratio of the dielectric crystal grains is greater than 0, and D1 has a value greater than D2.

5. The multilayer ceramic capacitor according to claim 3, wherein D1 is 210 nm or more and 230 nm or less.

6. The multilayer ceramic capacitor according to claim 3, wherein D2 is 200 nm or more and 220 nm or less.

7. The multilayer ceramic capacitor according to claim 1, wherein the cerium (Ce) is contained in an amount of 1 mole or more and 2 moles or less per 100 moles of the barium titanate-based main component.

8. The multilayer ceramic capacitor according to claim 1, wherein the dysprosium (Dy) is contained in an amount of 0.2 moles or more and 1 mole or less per 100 moles of the barium titanate-based main component.

9. The multilayer ceramic capacitor according to claim 1, wherein the capacitance variation coefficient of the multilayer ceramic capacitor obtained by the following formula 2 is greater than 0 and less than 3%. [Formula 2] Coefficient of variation of capacity (Cp CV) (%) = {Standard deviation of capacity (σ) １ ) / capacity average}×100 (In formula 2 above, the capacity standard deviation (σ １ ) is the square root of the mean of the squares of the deviations.

10. The multilayer ceramic capacitor according to claim 1, wherein the dielectric loss variation coefficient of the multilayer ceramic capacitor obtained by the following formula 3 is greater than 0 and less than 6%. [Formula 3] Dielectric loss variation coefficient (DFCV) (%) = {Dielectric loss standard deviation (σ) ２ ) / average dielectric loss} × 100 (In formula 3 above, the dielectric loss standard deviation (σ ２ ) is the square root of the mean of the squares of the deviations.

11. A step in which a dielectric slurry is manufactured by mixing barium titanate-based main component powder and auxiliary component powder; A step of manufacturing a dielectric green sheet using the dielectric slurry and forming a conductive paste layer on the surface of the dielectric green sheet; A step of manufacturing a dielectric green sheet laminate by stacking dielectric green sheets on which the conductive paste layer is formed; A step of firing the dielectric green sheet laminate to manufacture a capacitor body including a dielectric layer and an internal electrode layer; and The step includes forming an external electrode on one surface of the capacitor body, The dielectric layer comprises a barium titanate-based main component and a secondary component containing cerium (Ce) and dysprosium (Dy). A method for manufacturing a multilayer ceramic capacitor, wherein the auxiliary component powder comprises a Ce-containing compound and a Dy-containing compound, and the Ce-containing compound and the Dy-containing compound are included in a content such that the Ce / Dy molar ratio is 1 or more and 10 or less.

12. The method for manufacturing a multilayer ceramic capacitor according to claim 11, wherein the Ce-containing compound contains Ce in an amount of 1 mole part or more and 2 mole parts or less per 100 mole parts of the barium titanate-based main component.

13. The method for manufacturing a multilayer ceramic capacitor according to claim 11, wherein the Dy-containing compound contains Dy in an amount of 0.2 moles or more and 1 mole or less per 100 moles of the barium titanate-based main component.

14. The method for manufacturing a multilayer ceramic capacitor according to claim 11, wherein the Ce-containing compound and the Dy-containing compound each include an oxide, nitride, salt compound, or a sol dispersed in an organic solvent.

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