Filter device

Abstract

The present invention provides a filter device that can perform filtering using a single filter circuit even when the number of channels increases. [Solution] A filter device 1 that performs filtering on each digital value of multiple channels, comprising: a filter circuit 5 that performs filtering using the Nth digital value and the (N-1)th processed digital value and outputs the Nth processed digital value; a first multiplexer 3 that inputs the digital value of a selected channel from among the digital values ​​of multiple channels as the Nth digital value to the filter circuit 5; a second multiplexer 6 that temporarily stores the Nth processed digital value output by the filter circuit 5 for each channel; and a third multiplexer 8 that inputs the processed digital value of a selected channel from among the temporarily stored processed digital values ​​of multiple channels as the (N-1)th processed digital value to the filter circuit 5.

Description

[Technical Field]

[0001] Embodiments of this disclosure relate to a filtering device that applies filtering to a reference input signal. [Background technology]

[0002] A filtering device has been proposed that applies filtering to a reference input signal, which is a series of digital values ​​(see, for example, Patent Document 1). The filtering device of Patent Document 1 can perform filtering using a single filter circuit even when the number of digital values ​​increases. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 10361681 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, with conventional technology, when there are digital values ​​for multiple channels, a filter circuit is required for each channel, which increases the circuit size. As shown in Figure 4, if the number of channels is A, the number of filter circuits will be the same as the number of channels, A.

[0005] The purpose of this disclosure is to provide a filtering device that can perform filtering using a single filter circuit even when the number of digital value channels increases. [Means for solving the problem]

[0006] The filter device of the present disclosure is a filter device that performs filtering on each digital value of a plurality of channels, and is characterized by comprising a filter circuit that performs filtering on the input digital values, and a multiplexer that inputs the digital values ​​of the selected channels to the filter circuit. [Effects of the Invention]

[0007] The filter device of this disclosure can switch the channels of the digital values ​​input to the filter circuit, so that even if the number of digital value channels increases, filtering can be performed using a single filter circuit. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram shows the configuration of an embodiment of the filter device. [Figure 2] This diagram shows the configuration of the selection unit shown in Figure 1. [Figure 3] Figure 2 shows an example of a group set up in the group management unit. [Figure 4] This figure shows an example of the configuration of a conventional filter device. [Modes for carrying out the invention]

[0009] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0010] Referring to Figure 1, the filter device 1 of this embodiment is a digital filter that uses a predetermined bit (a bit) digital value converted from an analog signal by an A / D converter 2 or the like as a reference input signal, and applies filtering processing to each of the multiple channel (Ach) reference input signals. Part or all of the filter device 1 can be configured as a control IC, which is a semiconductor device integrated on a substrate.

[0011] Filter device 1 is an information processing circuit such as a microcomputer equipped with a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc. The ROM stores a control program for controlling the operation of filter device 1. Filter device 1 controls the entire device by reading the control program stored in the ROM and loading the control program into the RAM.

[0012] As shown in Fig. 1, the filter device 1 includes a first multiplexer 3, a bit addition unit 4, a filter circuit 5, a second multiplexer 6, and registers 71 to 7 A and a third multiplexer 8 and a fourth multiplexer 9.

[0013] The first multiplexer 3 includes an input port to which a reference input signal (A × a bits) for the Ach part is input, and an output port that outputs a reference input signal (a bits) for one channel. Hereinafter, the reference input signal (A × a bits) is referred to as an input digital value. The first multiplexer 3 outputs, to the bit addition unit 4, the input digital value of the channel selected by the channel selection signal from the input digital values for the Ach part that are input.

[0014] The bit addition unit 4 extends the lower side of the input digital value input from the first multiplexer 3 by b bits, and outputs the extended input digital value [(a + b) bits] to the filter circuit 5. Hereinafter, the extended input digital value [(a + b) bits] is referred to as an extended digital value.

[0015] The filter circuit 5 performs a filter process on the extended digital value, and outputs the extended digital value after the filter process to the second multiplexer 6. Hereinafter, the extended digital value after the filter process is referred to as a processed digital value.

[0016] The second multiplexer 6 includes an input port to which a processed digital value for one channel is input, and an output port that outputs a processed digital value for the Ach part. The second multiplexer 6 outputs the processed digital value input from the filter circuit 5 from the output ports of the channels selected by the channel selection signal to the registers 71 to 7 A for output.

[0017] The registers |71 to 7 A correspond to the output ports of the second multiplexer 6, and are storage areas that temporarily store the processed digital values for each channel.

[0018] The third multiplexer 8 includes an input port to which the processed digital value of the Ach component is input, and an output port that outputs the processed digital value for one channel. The first multiplexer 3 outputs the processed digital value of the channel selected by the channel selection signal from the processed digital values of the Ach component temporarily stored in the registers 71 to 7 A to the filter circuit 5.

[0019] The filter circuit 5 includes an addition unit 51, a lower shift unit 52, an upper shift unit 53, and a subtraction unit 54, and performs a moving average filtering process. The filter circuit 5 executes a filtering process based on the extended digital value input from the bit addition unit 4 and the processed digital value input from the third multiplexer 8. When the extended digital value input from the bit addition unit 4 is regarded as the Nth of the consecutive reference input signals, the processed digital value input from the third multiplexer 8 is the result of executing the filtering process on the (N - 1)th reference input signal.

[0020] The upper shift unit 53 amplifies by a factor of 2 by shifting the processed digital value input from the third multiplexer 8 n bits to the upper side. The subtraction unit 54 calculates the processed digital value amplified by a factor of 2 by subtracting the processed digital value input from the third multiplexer 8 from the processed digital value amplified by a factor of 2 in the upper shift unit 53. n The addition unit 51 adds the extended digital value input from the bit addition unit 4 and the processed digital value amplified by a factor of 2 in the subtraction unit 54. Thereby, a digital signal approximately equal to the superposition of the 1st to Nth reference input signals is generated. The lower shift unit 52 shifts the calculation result of the addition unit 51 n bits to the lower side, and this operation corresponds to the division process in the averaging process. Thereby, the processed digital value of the Nth obtained by performing the moving average process (filtering process) on the 1st to Nth reference input signals can be obtained. n The subtraction unit 54 calculates the processed digital value amplified by a factor of 2 by subtracting the processed digital value input from the third multiplexer 8 from the processed digital value amplified by a factor of 2 in the upper shift unit 53. n-1 The subtraction unit 54 calculates the processed digital value amplified by a factor of 2 by subtracting the processed digital value input from the third multiplexer 8 from the processed digital value amplified by a factor of 2 in the upper shift unit 53.

[0021] The addition unit 51 adds the extended digital value input from the bit addition unit 4 and the processed digital value amplified by a factor of 2 in the subtraction unit n-1 54. Thereby, a digital signal approximately equal to the superposition of the 1st to Nth reference input signals is generated. The lower shift unit 52 shifts the calculation result of the addition unit 51 n bits to the lower side, and this operation corresponds to the division process in the averaging process. Thereby, the processed digital value of the Nth obtained by performing the moving average process (filtering process) on the 1st to Nth reference input signals can be obtained.

[0022] The filter device 1 includes a first multiplexer 3, a second multiplexer 6, and a third multiplexer 8, so that filtering processing can be performed on the reference input signals of all channels by a single filter circuit 5.

[0023] In addition, the filter circuit 5 performs filtering processing on the extended digital value whose lower side is extended by b bits by the bit addition unit 4. Therefore, the processed digital value output from the filter circuit 5 includes a fractional value without truncating the fractional value generated by the lower shift unit 52 of the filter circuit 5, so that the calculation error can be reduced.

[0024] Registers 71 to 7 A The processed digital values for Ach (channel) temporarily stored therein are selectively output by the fourth multiplexer 9. The fourth multiplexer 9 includes an input port to which the processed digital value (a bits) for Ach is input, an input port to which the processed digital value [(a + b) bits] for Ach is input, and an output port for outputting the processed digital value for 1ch. The fourth multiplexer 9 outputs the processed digital value of the channel selected by the channel selection signal in the output format selected by the output selection signal, either (a bits) or [(a + b) bits]. Thereby, the filter device 1 can change the output format depending on whether the extended bits are necessary in the subsequent processing.

[0025] The filter device 1 includes a selection unit 10. The selection unit 10 functions as a group and output setting unit, selecting a group of channels for which filtering is to be performed, and also selecting the output format. Here, the channels to be filtered by the filter device 1 are managed as groups, and an example of the correspondence between groups and channels, and their output formats, is shown in Figure 3. This correspondence between groups and channels is registered in the selection unit 10. In Figure 3, the group selection is determined according to the group setting signal input from the outside in Figure 2. In Figure 2, the selection unit 10 outputs a corresponding channel selection signal to the first multiplexer 3, second multiplexer 6, third multiplexer 8, and fourth multiplexer 9 in Figure 1, causing them to perform the processing described above.

[0026] In addition, a separate output setting signal that determines the output format of the filter device 1 is also input to the selection unit 10 from an external source. The selection unit 10 outputs the output selection signal that determines the output format, along with the channel selection signal, to the fourth multiplexer 9, which is the preceding stage of the output in Figure 1, causing it to output in a format that conforms to this setting.

[0027] For example, when the group designation signal receives the designation of groups 0 and 1 as shown in Figure 3, the selection unit 10 sequentially outputs channel selection signals to select channels 0, 2, and 4 of group 0, and then sequentially outputs channel selection signals to select channels 0 and 1 of group 1. As a result, filtering is performed in the order of channels 0, 2, 4, 0, and 1. ru.

[0028] The fourth multiplexer 9 outputs the processed digital value of the channel selected by the channel selection signal input from the selection unit 10 in the output format selected by the output selection signal.

[0029] As described above, this embodiment is a filter device 1 that performs filtering on each digital value of multiple channels, comprising a filter circuit 5 that performs filtering on input digital values, and a multiplexer (first multiplexer 3, second multiplexer 6, third multiplexer 8) that inputs the digital values ​​of the selected channels to the filter circuit 5. With this configuration, the filter device 1 can switch the channels of the digital values ​​input to the filter circuit 5, so that even if the number of digital value channels increases, filtering can be performed using a single filter circuit.

[0030] Furthermore, according to this embodiment, the filter circuit 5 includes a first multiplexer 3 that performs filtering using the Nth digital value and the (N-1)th processed digital value to output the Nth processed digital value and inputs the digital value of a selected channel from among the digital values ​​of multiple channels to the filter circuit 5 as the Nth digital value; a second multiplexer 6 that temporarily stores the Nth processed digital value output by the filter circuit 5 for each channel; and a third multiplexer 8 that inputs the processed digital value of a selected channel from among the temporarily stored processed digital values ​​of multiple channels to the filter circuit 5 as the (N-1)th processed digital value. With this configuration, the filter device 1 can switch between the channels of the Nth digital value input to the filter circuit 5 and the (N-1)th processed digital value, so that filtering can be performed using a single filter circuit even if the number of digital value channels increases.

[0031] Furthermore, this embodiment includes a bit addition unit 4 that adds bits to the lower side of the digital value input from the first multiplexer 3 to the filter circuit 5. With this configuration, the filter device 1 includes the decimal values ​​generated by the filter circuit 5 without truncation, thus reducing calculation errors.

[0032] Furthermore, this embodiment includes a fourth multiplexer 9 that outputs the processed digital value of a selected channel from among the processed digital values ​​of multiple channels temporarily stored, and the fourth multiplexer 9 selects whether or not to output the bits loaded by the bit addition unit 4. With this configuration, the filter device 1 can change the output format depending on whether the extended bits are needed in subsequent processing.

[0033] It is clear that the present invention is not limited to the above embodiments, and that each embodiment can be modified as appropriate within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-mentioned components are not limited to the above embodiments, and can be set to a number, position, shape, etc. that is suitable for carrying out the present invention. In each figure, the same reference numeral is used for the same component. [Explanation of Symbols]

[0034] 1. Filter device 2 A / D converters 3. First Multiplexer 4-bit extension 5. Filter Circuit 6. Second Multiplexer 71-7 A Register 8. Third Multiplexer 9. Fourth Multiplexer 10 Selection Section 51 Addition section 52 Lower shift section 53 Upper Shift Section 54 Subtraction Unit

Claims

1. A filter device that performs filtering on each of the digital values ​​of multiple channels, A filter circuit that performs filtering on the input digital value, A filter device characterized by comprising a multiplexer that inputs the digital value of the selected channel to the filter circuit.

2. The filter circuit performs filtering using the Nth digital value and the (N-1)th processed digital value and outputs the Nth processed digital value. As the aforementioned multiplexer, A first multiplexer inputs the digital value of a channel selected from among the digital values ​​of multiple channels as the Nth digital value to the filter circuit, A second multiplexer that temporarily stores the Nth processed digital value output by the filter circuit for each channel, The filter device according to claim 1, further comprising: a third multiplexer that inputs the processed digital value of a channel selected from among the processed digital values ​​of multiple channels temporarily stored as the (N-1)th processed digital value to the filter circuit.

3. The filter device according to claim 2, further comprising a bit addition unit that adds bits to the lower side of the digital value input from the first multiplexer to the filter circuit.

4. The system includes a fourth multiplexer that outputs the processed digital value of a channel selected from the processed digital values ​​of multiple channels that are temporarily stored, The filter device according to claim 3, characterized in that the fourth multiplexer selects whether or not to output the bits loaded by the bit addition unit.

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