Semiconductor package and method for manufacturing the same

Abstract

The present invention provides a semiconductor package and a method for manufacturing the same that can reduce manufacturing costs and increase yield. [Solution] The semiconductor package of the present invention includes a base substrate, an intermediate substrate placed on the base substrate, a plurality of first conductive blocks sandwiched between the base substrate and the intermediate substrate and electrically connected to the base substrate and the intermediate substrate, a first die placed on the intermediate substrate, and a plurality of second conductive blocks sandwiched between the intermediate substrate and the first die and electrically connected to the intermediate substrate and the first die. The second conductive blocks are electrically connected to the first conductive blocks via the intermediate substrate. The present invention further provides a method for manufacturing the above semiconductor package.

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package including an intermediate substrate and a method for manufacturing the same.

Background Art

[0002] Currently, the manufacturing cost of high-computing semiconductor packages is too high, and it is not easy to control the yield.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In view of this, the present invention provides a semiconductor package and a method for manufacturing the same to solve the above problems.

Means for Solving the Problems

[0004] To achieve the above object, the semiconductor package of the present invention includes a base substrate, an intermediate substrate disposed on the base substrate, a plurality of first conductive blocks sandwiched between the base substrate and the intermediate substrate and electrically connected to the base substrate and the intermediate substrate, a first die disposed on the intermediate substrate, and a plurality of second conductive blocks sandwiched between the intermediate substrate and the first die and electrically connected to the intermediate substrate and the first die. The second conductive blocks are electrically connected to the first conductive blocks through the intermediate substrate.

[0005] The present invention provides a method for manufacturing a semiconductor package, comprising the steps of: forming a plurality of first conductive blocks on an intermediate substrate; placing the intermediate substrate on a base substrate, sandwiching the first conductive blocks between the base substrate and the intermediate substrate, and electrically connecting them to the base substrate and the intermediate substrate; forming a plurality of second conductive blocks on a first die; and placing the first die on the intermediate substrate, sandwiching the second conductive blocks between the intermediate substrate and the first die, and electrically connecting them to the intermediate substrate and the first die. The second conductive blocks are electrically connected to the first conductive blocks via the intermediate substrate. [Effects of the Invention]

[0006] According to the semiconductor package of the present invention, manufacturing costs are reduced and yield is increased. [Brief explanation of the drawing]

[0007] [Figure 1] This is an explanatory diagram of a first embodiment of the semiconductor package of the present invention. [Figure 2] This is an explanatory diagram of a second embodiment of the semiconductor package of the present invention. [Figure 3] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 4] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 5] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 6] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 7] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 8] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 9] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 10] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 11]It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 1. [Figure 12] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 13] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 14] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 15] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 16] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 17] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 18] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 19] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 20] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 21] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 22] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2. [Figure 23] It is an explanatory diagram of a method for manufacturing a semiconductor package shown in FIG. 2.

Embodiments for Carrying Out the Invention

[0008] In order to make the above and other objects, features, and advantages of the present invention more clear, embodiments of the present invention will be given below and described in detail with reference to the drawings.

[0009] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that various members are not drawn to scale according to industry standard practices. In fact, for clarity of explanation, the dimensions of various members can be arbitrarily enlarged or reduced.

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. To simplify the present disclosure, specific examples of members and configurations are described below. Of course, these members and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming the first member above or on the second member can include embodiments in which the first member and the second member are formed in direct contact, and can also include embodiments in which an additional member is formed between the first member and the first member so that the first member and the second member are not in direct contact. Also, in various examples of the present disclosure, reference numerals and / or letters may be repeated. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations being discussed.

[0011] Also, in this text, for ease of explanation, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. are used to describe the relationship between one member or component shown in the figure and another one or more members or components. In addition to the orientation shown in the figure, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this text are to be interpreted accordingly.

[0012] Referring to Figure 1, a first embodiment of the semiconductor package of the present invention includes a base substrate 110, which may be a single-layer or multilayer circuit board, but is not limited thereto. The base substrate 110 has opposing first surfaces 111 and second surfaces 112, the first surface 111 and the second surface 112 located on different planes, for example, the first surface 111 being the top surface and the second surface 112 being the bottom surface, but is not limited thereto. Conductive wires 113 and 114 are formed on the first surface 111 and the second surface 112 of the base substrate 110, respectively, and the conductive wires 113 and 114 are electrically connected via a plurality of conductive plated through-holes 115 that penetrate the first surface 111 and the second surface 112 of the base substrate 110.

[0013] An intermediate substrate 120 made of silicon, glass, or other material is provided on the first surface 111 of the base substrate 110. The intermediate substrate 120 has opposing first surfaces 121 and second surfaces 122, and the first surface 121 and the second surface 122 are located on different planes, for example, the first surface 121 is the top surface and the second surface 122 is the bottom surface.

[0014] Conductive wires are formed on the first surface 121 and the second surface 122 of the intermediate substrate 120, and are electrically connected via conductive plated through-holes (not shown) that penetrate the first surface 121 and the second surface 122 of the intermediate substrate 120. A plurality of first conductive blocks 131 are formed on the second surface 122 of the intermediate substrate 120, and the first conductive blocks 131 are sandwiched between the intermediate substrate 120 and the base substrate 110. The intermediate substrate 120 is electrically connected to the base substrate 110 via the first conductive blocks 131. The gap between the intermediate substrate 120 and the base substrate 110 is filled with underfill 140 that covers the first conductive blocks 131. In addition, a plurality of passive members may be installed on the first surface 111 of the base substrate 110 as needed.

[0015] In one embodiment, the intermediate substrate 120 can be formed by cutting from a silicon wafer, and conductive wires are provided on two opposing surfaces of the silicon wafer, which are used to form conductive wires on the first surface 121 and the second surface 122 of the intermediate substrate 120, respectively. In another embodiment, the first conductive block 131 is a metal bump formed on the second surface 122 of the intermediate substrate 120 using a bumping process. The first conductive block 131 can be formed from a eutectic alloy, lead-free material, high-lead material, or copper pillar. The intermediate substrate 120 is attached to the first surface 111 of the base substrate 110 using flip-chip technology.

[0016] At least one die 150 is installed on the first surface 121 of the intermediate substrate 120, for example, multiple dies 150 are installed in parallel. Each die 150 has an active surface and a back surface opposite to the active surface. Multiple second conductive blocks 132 are provided on the active surface of the die 150, and each is electrically connected to the die 150. The second conductive blocks 132 are sandwiched between the die 150 and the intermediate substrate 120. The second conductive blocks 132 are electrically connected to the first conductive block 131 via conductive wires on the first surface 121 and the second surface 122 of the intermediate substrate 120, thereby enabling the die 150 to be electrically connected to the base substrate 110. The gap between the die 150 and the intermediate substrate 120 is filled with underfill 170 that covers the second conductive blocks 132.

[0017] In one embodiment, the second conductive block 132 is a metal bump formed on the active surface of the die 150 using a bumping process. The second conductive block 132 can be formed from a eutectic alloy, a lead-free material, a high-lead material, or a copper pillar. The die 150 is mounted to the first surface 121 of the intermediate substrate 120 using flip-chip technology.

[0018] A heat dissipation frame 180 is provided on the first surface 111 of the base substrate 110, surrounding the intermediate substrate 120 and the die 150. Furthermore, a plurality of solder balls 190 are provided on the second surface 112 of the base substrate 110, electrically connected to the base substrate 110. The solder balls 190 are electrically connected to the first conductive block 131 via the conductive wires 113, 114 and the conductive plated through-holes 115 on the base substrate 110. This allows the die 150 to be electrically connected to an external circuit using the solder balls 190 via the intermediate substrate 120 and the base substrate 110.

[0019] Referring to Figure 2, a second embodiment of the semiconductor package of the present invention includes a base substrate 210, which may be a single-layer or multilayer circuit board, but is not limited thereto. The base substrate 210 has opposing first surfaces 211 and second surfaces 212, the first surface 211 and the second surface 212 located on different planes, for example, the first surface 211 being the top surface and the second surface 212 being the bottom surface, but is not limited thereto. Conductive wires 213 and 214 are formed on the first surface 211 and the second surface 212 of the base substrate 210, respectively, and the conductive wires 213 and 214 are electrically connected via a plurality of conductive plated through-holes 215 that penetrate the first surface 211 and the second surface 212 of the base substrate 210.

[0020] An intermediate substrate 220 made of silicon, glass, or other material is provided on the first surface 211 of the base substrate 210. The intermediate substrate 220 has opposing first surfaces 221 and second surfaces 222, and the first surface 221 and the second surface 222 are located on different planes, for example, the first surface 221 is the top surface and the second surface 222 is the bottom surface.

[0021] Conductive wires are formed on the first surface 221 and the second surface 222 of the intermediate substrate 220, and are electrically connected via conductive plated through-holes (not shown) that penetrate the first surface 221 and the second surface 222 of the intermediate substrate 220. A plurality of first conductive blocks 231 are formed on the second surface 222 of the intermediate substrate 220, and the first conductive blocks 231 are sandwiched between the intermediate substrate 220 and the base substrate 210. The intermediate substrate 220 is electrically connected to the base substrate 210 via the first conductive blocks 231. The gap between the intermediate substrate 220 and the base substrate 210 is filled with underfill 240 that covers the first conductive blocks 231. In addition, a plurality of passive members 282 may be installed on the first surface 211 of the base substrate 210 as needed.

[0022] In one embodiment, the intermediate substrate 220 can be formed by cutting from a silicon wafer, and conductive wires are provided on two opposing surfaces of the silicon wafer, which are used to form conductive wires on the first surface 221 and the second surface 222 of the intermediate substrate 220, respectively. In another embodiment, the first conductive block 231 is a metal bump formed on the second surface 222 of the intermediate substrate 220 using a bumping process. The first conductive block 231 can be formed from a eutectic alloy, lead-free material, high-lead material, or copper pillar. The intermediate substrate 220 is attached to the first surface 211 of the base substrate 210 using flip-chip technology.

[0023] At least one first die 250 is installed on the first surface 221 of the intermediate substrate 220, and for example, multiple first dies 250 are installed in parallel. Each first die 250 has an active surface and a back surface opposite to the active surface. Multiple second conductive blocks 232 are provided on the active surface of the first die 250, and each is electrically connected to the first die 250. The second conductive blocks 232 are sandwiched between the first die 250 and the intermediate substrate 220. The second conductive blocks 232 are electrically connected to the first conductive blocks 231 via conductive wires on the first surface 221 and the second surface 222 of the intermediate substrate 220, thereby enabling the first die 250 to be electrically connected to the base substrate 210. The gap between the first die 250 and the intermediate substrate 220 is filled with underfill 270 that covers the second conductive blocks 232.

[0024] In one embodiment, the second conductive block 232 is a metal bump formed on the active surface of the first die 250 using a bumping process. The second conductive block 232 can be formed from a eutectic alloy, lead-free material, high-lead material, or copper pillar. The first die 250 is mounted to the first surface 221 of the intermediate substrate 220 using flip-chip technology.

[0025] The first die 250 is fitted with at least one, for example, a plurality of second dies 280. Each of the second dies 280 has an active surface and a back surface opposite to the active surface. The back surfaces of the second dies 280 are attached to the back surfaces of the first die 250, respectively, using a silver adhesive / die attach film (DAF) 272.

[0026] In another embodiment, the second die 280 may be mounted on the first surface 221 of the intermediate substrate 220. The back surface of the second die 280 is attached to the first surface 221 of the intermediate substrate 220 using silver adhesive or a die attach film.

[0027] The second die 280 is electrically connected to the first surface 211 of the base substrate 210 or the first surface 221 of the intermediate substrate 220 using a plurality of bonding wires 284, with each end of the bonding wires 284 connected to the active surface of the second die 280 and the first surface 211 of the base substrate 210 or the first surface 221 of the intermediate substrate 220, respectively. Therefore, the second die 280 is electrically connected to the intermediate substrate 220 or the base substrate 210 via the bonding wires 284. A molded layer 292 is further formed on the first surface 211 of the base substrate 210, covering the intermediate substrate 220, the passive member 282, the first die 250, the second die 280, and the bonding wires 284.

[0028] Furthermore, a plurality of solder balls 290 are provided on the second surface 212 of the base substrate 210, which are electrically connected to the base substrate 210. The solder balls 290 are electrically connected to the first conductive block 231 via the conductive wires 213 and 214 on the base substrate 210, thereby allowing the first die 250 to be electrically connected to an external circuit using the solder balls 290 via the intermediate substrate 220 and the base substrate 210. Similarly, the solder balls 290 are electrically connected to the bonding wires 284 via the conductive wires 213 and 214 on the base substrate 210, thereby allowing the second die 280 to be electrically connected to an external circuit using the solder balls 290 via the bonding wires 284, the intermediate substrate 220, and the base substrate 210.

[0029] Referring to Figures 3 to 11, Figures 3 to 11 illustrate the manufacturing method of the semiconductor package shown in Figure 1. As shown in Figure 3, a base substrate 110 is prepared, which may be a single-layer or multi-layer circuit board, but is not limited thereto. The base substrate 110 has opposing first surfaces 111 and second surfaces 112, and the first surface 111 and the second surface 112 are located on different planes, for example, the first surface 111 is the top surface and the second surface 112 is the bottom surface, but is not limited thereto. Conductive wires 113 and 114 are formed on the first surface 111 and the second surface 112 of the base substrate 110, respectively, and the conductive wires 113 and 114 are electrically connected by a plurality of conductive plated through-holes 115 that penetrate the first surface 111 and the second surface 112 of the base substrate 110. In addition, a plurality of passive members may be installed on the first surface 111 of the base substrate 110 as needed.

[0030] As shown in Figure 4, an intermediate substrate 120 made of silicon, glass, or other material is prepared. The intermediate substrate 120 has opposing first surfaces 121 and second surfaces 122, the first surface 121 and the second surface 122 located on different planes, for example, the first surface 121 being the top surface and the second surface 122 being the bottom surface. Conductive wires are formed on the first surface 121 and the second surface 122 of the intermediate substrate 120 and are electrically connected by conductive plated through-holes (not shown) that penetrate the first surface 121 and the second surface 122 of the intermediate substrate 120. A plurality of first conductive blocks 131 are formed on the second surface 122 of the intermediate substrate 120, and the first conductive blocks 131 are electrically connected to the intermediate substrate 120.

[0031] In one embodiment, the intermediate substrate 120 can be formed by cutting from a silicon wafer, and conductive wires are provided on two opposing surfaces of the silicon wafer, which are used to form conductive wires on the first surface 121 and the second surface 122 of the intermediate substrate 120, respectively. In another embodiment, the first conductive block 131 is a metal bump formed on the second surface 122 of the intermediate substrate 120 using a bumping process. The first conductive block 131 can be formed from a eutectic alloy, lead-free material, high-lead material, or copper pillar.

[0032] As shown in Figure 5, the intermediate substrate 120 is then attached to the first surface 111 of the base substrate 110 using flip-chip technology, and the first conductive block 131 is sandwiched between the intermediate substrate 120 and the base substrate 110. The intermediate substrate 120 is electrically connected to the base substrate 110 via the first conductive block 131.

[0033] As shown in Figure 6, the gap between the intermediate substrate 120 and the base substrate 110 is filled with underfill 140 so as to cover the first conductive block 131.

[0034] As shown in Figure 7, at least one, for example, multiple dies 150 are prepared, each of which has an active surface and a back surface opposite to the active surface. Multiple second conductive blocks 132 are formed on the active surface of the die 150 and each is electrically connected to the die 150. In one embodiment, the second conductive blocks 132 are metal bumps formed on the active surface of the die 150 using a bumping process. The second conductive blocks 132 can be formed from a eutectic alloy, a lead-free material, a high-lead material, or a copper pillar.

[0035] As shown in Figure 8, the die 150 is mounted on the first surface 121 of the intermediate substrate 120 using flip-chip technology, and the second conductive block 132 is sandwiched between the die 150 and the intermediate substrate 120. The second conductive block 132 is electrically connected to the first conductive block 131 via the conductive wires on the first surface 121 and the second surface 122 of the intermediate substrate 120, thereby enabling the die 150 to be electrically connected to the base substrate 110.

[0036] As shown in Figure 9, the gap between the die 150 and the intermediate substrate 120 is then filled with underfill 170 to cover the second conductive block 132.

[0037] As shown in Figure 10, the heat dissipation frame 180 is then placed on the first surface 111 of the base substrate 110 so as to surround the intermediate substrate 120 and the die 150.

[0038] As shown in Figure 11, a plurality of solder balls 190 are then formed on the second surface 112 of the base substrate 110, and the solder balls 190 are electrically connected to the base substrate 110 to form a semiconductor package as shown in Figure 1.

[0039] The solder ball 190 is electrically connected to the first conductive block 131 via conductive wires 113, 114 and conductive plated through-holes 115 on the base substrate 110, and the die 150 can be electrically connected to an external circuit using the solder ball 190 via the intermediate substrate 120 and the base substrate 110.

[0040] Referring to Figures 12 to 23, Figures 12 to 23 illustrate a method for manufacturing the semiconductor package shown in Figure 2. As shown in Figure 12, a base substrate 210 is prepared, which may be a single-layer or multi-layer circuit board, but is not limited thereto. The base substrate 210 has opposing first surfaces 211 and second surfaces 212, the first surface 211 and the second surface 212 located on different planes, for example, the first surface 211 being the top surface and the second surface 212 being the bottom surface, but is not limited thereto. Conductive wires 213 and 214 are formed on the first surface 211 and the second surface 212 of the base substrate 210, respectively, and the conductive wires 213 and 214 are electrically connected via a plurality of conductive plated through-holes 215 that penetrate the first surface 211 and the second surface 212 of the base substrate 210. In addition, if necessary, a plurality of passive members 282 may be placed on the first surface 211 of the base substrate 210.

[0041] As shown in Figure 13, an intermediate substrate 220 made of silicon, glass, or other material is prepared. The intermediate substrate 220 has opposing first surfaces 221 and second surfaces 222, and the first surface 221 and the second surface 222 are located on different planes, for example, the first surface 221 is the top surface and the second surface 222 is the bottom surface. Conductive wires are formed on the first surface 221 and the second surface 222 of the intermediate substrate 220 and are electrically connected via conductive plated through-holes (not shown) that penetrate the first surface 221 and the second surface 222 of the intermediate substrate 220. A plurality of first conductive blocks 231 are formed on the second surface 222 of the intermediate substrate 220, and the first conductive blocks 231 are electrically connected to the intermediate substrate 220.

[0042] In one embodiment, the intermediate substrate 220 can be formed by cutting from a silicon wafer, and conductive wires are provided on two opposing surfaces of the silicon wafer, which are used to form the conductive wires on the first surface 221 and the second surface 222 of the intermediate substrate 220, respectively. In another embodiment, the first conductive block 231 is a metal bump formed on the second surface 222 of the intermediate substrate 220 using a bumping process. The first conductive block 231 can be formed from a eutectic alloy, lead-free material, high-lead material, or copper pillar.

[0043] As shown in Figure 14, the intermediate substrate 220 is attached to the first surface 211 of the base substrate 210 using flip-chip technology, and the first conductive block 231 is sandwiched between the intermediate substrate 220 and the base substrate 210. The intermediate substrate 220 is electrically connected to the base substrate 210 via the first conductive block 231.

[0044] As shown in Figure 15, the gap between the intermediate substrate 220 and the base substrate 210 is then filled with underfill 240 to cover the first conductive block 231.

[0045] As shown in Figure 16, at least one, for example, multiple first dies 250 are prepared, each of which has an active surface and a back surface opposite to the active surface. Multiple second conductive blocks 232 are formed on the active surface of the first die 250 and each is electrically connected to the first die 250. In one embodiment, the second conductive blocks 232 are metal bumps formed on the active surface of the first die 250 using a bumping process. The second conductive blocks 232 can be formed from a eutectic alloy, a lead-free material, a high-lead material, or a copper pillar.

[0046] As shown in Figure 17, the first die 250 is then mounted on the first surface 221 of the intermediate substrate 220 using flip-chip technology, and the second conductive block 232 is sandwiched between the first die 250 and the intermediate substrate 220. The second conductive block 232 is electrically connected to the first conductive block 231 via the conductive wires on the first surface 221 and the second surface 222 of the intermediate substrate 220, thereby enabling the first die 250 to be electrically connected to the base substrate 210.

[0047] As shown in Figure 18, the gap between the first die 250 and the intermediate substrate 220 is then filled with underfill 270 to cover the second conductive block 232.

[0048] As shown in Figure 19, at least one, for example, multiple second dies 280 are prepared. Each of the second dies 280 has an active surface and a back surface opposite to the active surface.

[0049] As shown in Figure 20, the second die 280 is then placed on the first die 250. The back surface of the second die 280 is attached to the back surface of the first die 250 using silver adhesive / die attach film (DAF) 272.

[0050] In other embodiments, the second die 280 may be mounted on the first surface 221 of the intermediate substrate 220. The back surface of the second die 280 is attached to the first surface 221 of the intermediate substrate 220 using silver adhesive or a die attach film.

[0051] As shown in Figure 21, the second die 280 is electrically connected to the first surface 211 of the base substrate 210 or the first surface 221 of the intermediate substrate 220 using a plurality of bonding wires 284. Each end of the bonding wire 284 is connected to the active surface of the second die 280 and the first surface 211 of the base substrate 210 or the first surface 221 of the intermediate substrate 220, respectively. Therefore, the second die 280 is electrically connected to the intermediate substrate 220 or the base substrate 210 via the bonding wires 284.

[0052] As shown in Figure 22, a molded layer 292 is then formed on the first surface 211 of the base substrate 210, covering the intermediate substrate 220, the passive member 282, the first die 250, the second die 280, and the bonding wire 284.

[0053] As shown in Figure 23, a plurality of solder balls 290 are then formed on the second surface 212 of the base substrate 210, and the solder balls 290 are electrically connected to the base substrate 210 to form a semiconductor package as shown in Figure 2.

[0054] The solder ball 290 is electrically connected to the first conductive block 231 via the conductive wires 213 and 214 on the base substrate 210, thereby allowing the first die 250 to be electrically connected to an external circuit using the solder ball 290 via the intermediate substrate 220 and the base substrate 210. Similarly, the solder ball 290 is electrically connected to the bonding wire 284 via the conductive wires 213 and 214 on the base substrate 210, thereby allowing the second die 280 to be electrically connected to an external circuit using the solder ball 290 via the bonding wire 284, the intermediate substrate 220 and the base substrate 210.

[0055] According to the semiconductor package of the present invention, manufacturing costs are reduced and yield is increased.

[0056] Although the present invention is disclosed in the embodiments described above, this does not limit the invention, and those skilled in the art can make various changes and modifications without departing from the spirit of the invention. Accordingly, the scope of protection of the present invention shall be as defined in the claims described below. [Explanation of Symbols]

[0057] 110 Base board 111 Page 1 112 Side 2 113 Conductive wire 114 Conductive wire 115 Conductive plated through-holes 120 Intermediate board 121 Page 1 122 2nd page 131 First conductive block 132 Second conductive block 140 Underfill 150 Dies 170 Underfill 180 Heat Dissipation Frame 190 solder balls 210 base board 211 Page 1 212 2nd page 213 Conductive wire 214 Conductive wire 215 Conductive plated through-holes 220 Intermediate board 221 Page 1 222 2nd page 231 First conductive block 232 Second conductive block 240 Underfill 250 First Die 270 Underfill 272 Silver Adhesive / Dia Attach Film 280 Second Die 282 Passive member 284 Bonding Wire 290 solder balls 292 Molding layer

Claims

1. Base board and An intermediate substrate is installed on the base substrate, A plurality of first conductive blocks are sandwiched between the base substrate and the intermediate substrate and electrically connected to the base substrate and the intermediate substrate, A first die is installed on the aforementioned intermediate substrate, A plurality of second conductive blocks are sandwiched between the intermediate substrate and the first die and are electrically connected to the intermediate substrate and the first die, Includes, The second conductive block is electrically connected to the first conductive block via the intermediate substrate, forming a semiconductor package.

2. The semiconductor package according to claim 1, further comprising a heat dissipation frame mounted on the base substrate and surrounding the intermediate substrate and the first die.

3. A second die attached to the first die or the intermediate substrate, A plurality of bonding wires, each having one end connected to the second die and the other end connected to the base substrate or the intermediate substrate, A mold layer covering the first die, the second die, and the bonding wire, The semiconductor package according to claim 1, further comprising:

4. A step of forming a plurality of first conductive blocks on an intermediate substrate, The steps include: installing the intermediate substrate on the base substrate, sandwiching the first conductive block between the base substrate and the intermediate substrate, and electrically connecting the base substrate and the intermediate substrate; A step of forming a plurality of second conductive blocks on a first die, The process involves placing the first die on the intermediate substrate, sandwiching the second conductive block between the intermediate substrate and the first die, and electrically connecting the intermediate substrate and the first die. Includes, A method for manufacturing a semiconductor package, wherein the second conductive block is electrically connected to the first conductive block via the intermediate substrate.

5. A method for manufacturing a semiconductor package according to claim 4, further comprising the step of installing a heat dissipation frame on the base substrate and surrounding the intermediate substrate and the first die.

6. A step of attaching the second die to the first die or the intermediate substrate, The process involves installing multiple bonding wires, connecting one end of each bonding wire to the second die, and connecting the other end to the base substrate or the intermediate substrate, A step of forming a mold layer that covers the first die, the second die, and the bonding wire, A method for manufacturing a semiconductor package according to claim 4, further comprising:

7. A method for manufacturing a semiconductor package according to claim 4, further comprising the step of filling the gap between the intermediate substrate and the base substrate with underfill and covering the first conductive block.

8. The method for manufacturing a semiconductor package according to claim 4, wherein the intermediate substrate is made of silicon or glass.

9. The method for manufacturing a semiconductor package according to claim 4, wherein the intermediate substrate is attached to the base substrate using flip-chip technology.

10. The method for manufacturing a semiconductor package according to claim 6, wherein the second die is attached to the first die using a silver adhesive or a die attach film.

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