Semiconductor equipment

Abstract

To provide a semiconductor device that suppresses the occurrence of cracks due to thermal stress. [Solution] A semiconductor device 10 according to one embodiment comprises a substrate 11. The substrate has five conductive layers 31-35, five insulating layers 41-45, and a plurality of vias 51, 52. The conductive layers have pads 21, terminals 71, wiring, a first mesh 61, and a second mesh 73. The pads are included in the first conductive layer 31. The terminals are included in the second conductive layer 33 and connected to the pads through at least one of the vias. The wiring is connected to the terminals. The first mesh 73 is included in the second conductive layer and spaced apart from the terminals and wiring. The second mesh 61 is included in the first conductive layer or in a third conductive layer 32 located between the first and second conductive layers, is electrically independent of the pads, terminals and wiring, and covers the terminals, wiring and the first mesh, respectively.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] A semiconductor device may have a substrate provided with pads. The semiconductor device is connected to other devices, for example, by solder provided on the pads. The substrate has, for example, a plurality of conductive layers, insulating layers each interposed between two adjacent layers of the plurality of conductive layers, and vias each connecting at least two layers of the plurality of conductive layers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Inside the substrate, due to the difference in thermal expansion between the conductive layer and the insulating layer, stress (thermal stress) may occur at the connection portion between the edge of the pattern of the conductive layer and the insulating layer. The thermal stress may cause cracks at the connection portion between the edge of the pattern of the conductive layer and the insulating layer.

[0005] One example of the problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the occurrence of cracks due to thermal stress.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment includes a substrate. The substrate has a first outer surface, a second outer surface located opposite the first outer surface, and pads provided on the first outer surface. The substrate has four or five conductive layers, a plurality of insulating layers, each interposed between two adjacent conductive layers, and a plurality of vias, each connecting at least two of the conductive layers. When there are four conductive layers, the distance between the first outer surface and the second outer surface is 50 μm or less, and when there are five conductive layers, the distance between the first outer surface and the second outer surface is 60 μm or less. The conductive layers include the pads, terminals, wiring, a first mesh, and a second mesh. The pads are included in the first conductive layer. The terminals are included in the second conductive layer and connected to the pads through at least one of the vias. The wiring is included in the second conductive layer and connected to the terminals. The first mesh is included in the second conductive layer and spaced apart from the terminals and the wiring. The second mesh is included in the first conductive layer or in a third conductive layer located between the first and second conductive layers, is electrically independent of the pads, the terminals and the wiring, and at least partially covers the terminals, the wiring and the first mesh in a direction perpendicular to the first outer surface. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic and exemplary cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view illustrating a part of the semiconductor device of the first embodiment. [Figure 3] An illustrative plan view schematically showing the three conductive layers of the first embodiment. [Figure 4] A schematic cross-sectional view illustrating a conductive layer deposited on a glass substrate according to the first embodiment. [Figure 5] A schematic cross-sectional view illustrating an insulating layer formed on a conductive layer according to the first embodiment. [Figure 6] A schematic cross-sectional view illustrating a conductive layer deposited on the insulating layer of the first embodiment. [Figure 7] A schematic cross-sectional view illustrating an interposer formed on a glass substrate according to the first embodiment. [Figure 8] A schematic cross-sectional view illustrating an interposer sealed with the sealing resin of the first embodiment. [Figure 9] A schematic cross-sectional view illustrating a semiconductor device cut out according to the first embodiment. [Figure 10] A schematic plan view illustrating three conductive layers according to a first modified example of the first embodiment. [Figure 11] A schematic plan view illustrating three conductive layers according to a second modified example of the first embodiment. [Figure 12] A schematic plan view showing three conductive layers according to a third modified example of the first embodiment. [Figure 13] A schematic cross-sectional view illustrating a part of a semiconductor device according to the second embodiment. [Figure 14] A schematic cross-sectional view illustrating a part of a semiconductor device according to a modified example of the second embodiment. [Figure 15] An illustrative plan view schematically showing three conductive layers according to the third embodiment. [Figure 16] A schematic cross-sectional view illustrating a part of a semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0008] (First Embodiment) The first embodiment will be described below with reference to Figures 1 to 12. Note that in this specification, the components of the embodiment and their descriptions may be described using multiple expressions. The components and their descriptions are examples and are not limited by the expressions used herein. Components may also be identified by names different from those used herein. Furthermore, components may also be described using expressions different from those used herein.

[0009] In the following description, "suppress" is defined as, for example, preventing the occurrence of an event, an action, or an influence, or reducing the degree of an event, an action, or an influence.

[0010] FIG. 1 is an exemplary cross-sectional view schematically showing a semiconductor device 10 according to the first embodiment. An example of the semiconductor device 10 in this embodiment is, for example, a universal flash storage (UFS) or an embedded memory of another standard. The semiconductor device 10 of this embodiment may also be referred to as, for example, a semiconductor memory device, a package, or an electronic component. Note that the semiconductor device may be another memory such as a dynamic random access memory (DRAM), or may be another semiconductor device such as a central processing unit (CPU).

[0011] As shown in each drawing, in this specification, an X direction (+X direction and -X direction), a Y direction (+Y direction and -Y direction), and a Z direction (+Z direction and -Z direction) are defined. The X direction, the Y direction, and the Z direction are orthogonal to each other. The X direction is a direction along the width of the semiconductor device 10, and the +X direction and the -X direction are opposite to each other. The Y direction is a direction along the depth of the semiconductor device 10, and the +Y direction and the -Y direction are opposite to each other. The Z axis is a direction along the thickness of the semiconductor device 10, and the +Z direction and the -Z direction are opposite to each other.

[0012] As shown in FIG. 1, the semiconductor device 10 includes an interposer 11, a memory controller 12, a plurality of flash memories 13, a plurality of spacers 14, a plurality of adhesive films 15, a plurality of bonding wires 16, a sealing resin 17, and a plurality of bumps 18. The interposer 11 is an example of a substrate. Note that the substrate is not limited to an interposer and may be another substrate. The memory controller 12 and the flash memory 13 may each also be referred to as a semiconductor chip.

[0013] The interposer 11 in this embodiment is, for example, an organic substrate manufactured using redistribution layer (RDL) technology. Therefore, the interposer 11 can be formed thinly. Hereinafter, an organic substrate manufactured using RDL technology is referred to as an RDL substrate. Note that the interposer 11 is not limited to an RDL substrate.

[0014] The interposer 11 has two outer surfaces 11a and 11b. The outer surface 11a is an example of a first outer surface. The outer surface 11b is an example of a second outer surface. Each of the two outer surfaces 11a and 11b can also be referred to as a main surface. Each of the two outer surfaces 11a and 11b is formed in a substantially rectangular shape arranged along the X-Y plane. The outer surface 11a faces in the substantially -Z direction. The outer surface 11b is located on the opposite side of the outer surface 11a and faces in the substantially +Z direction.

[0015] The interposer 11 further has a plurality of pads 21 and 22. The plurality of pads 21 are provided on the outer surface 11a. The plurality of pads 21 are arranged, for example, in a grid pattern. The plurality of pads 22 are provided on the outer surface 11b.

[0016] The memory controller 12 is mounted on the outer surface 11b of the interposer 11, for example, by flip-chip mounting. That is, a plurality of bumps of the memory controller 12 are connected to the plurality of pads 22. Note that the memory controller 12 may be mounted on the interposer 11 by other mounting methods.

[0017] The plurality of flash memories 13 are stacked in the Z direction on the memory controller 12. That is, the memory controller 12 is located between the interposer 11 and the stacked plurality of flash memories 13.

[0018] The spacer 14 is, for example, a silicon component coated with an insulating resin such as polyimide on its surface. The spacer 14 may be made of silicon, polyimide, or other materials. The material of the spacer 14 is not limited to this example. Multiple spacers 14 are positioned between the interposer 11 and the stacked flash memories 13.

[0019] Two adjacent flash memory units 13 are bonded to each other by an adhesive film 15. Additionally, the flash memory unit 13 closest to the interposer 11 is bonded to the memory controller 12 and several spacers 14 by the adhesive film 15. Each of the spacers 14 is bonded to the outer surface 11b of the interposer 11 by the adhesive film 15.

[0020] Two adjacent flash memories 13 are offset from each other in a direction perpendicular to the Z direction. The flash memories 13 are connected to the interposer 11 by wire bonding. That is, the electrodes of each flash memory 13 are connected to the electrodes of other flash memories 13 or to the pads 22 of the interposer 11 via bonding wires 16.

[0021] The sealing resin 17 seals the memory controller 12, flash memory 13, spacer 14, adhesive film 15, and bonding wire 16. That is, the sealing resin 17 adheres to the outer surface 11b of the interposer 11, and the memory controller 12, flash memory 13, spacer 14, adhesive film 15, and bonding wire 16 are embedded in the sealing resin 17.

[0022] The bumps 18 are, for example, solder. Each of the multiple bumps 18 is provided on a corresponding one of the multiple pads 21. The multiple pads 21 of the semiconductor device 10 are connected to, for example, pads on another substrate through the bumps 18.

[0023] Figure 2 is a schematic cross-sectional view illustrating a part of the semiconductor device 10 of the first embodiment. As shown in Figure 2, the interposer 11 of this embodiment has five conductive layers 31, 32, 33, 34, 35, five insulating layers 41, 42, 43, 44, 45, and a plurality of vias 51, 52. Conductive layer 31 is an example of a first conductive layer. Conductive layer 32 is an example of a third conductive layer. Conductive layer 33 is an example of a second conductive layer. Via 51 is an example of a first via. Via 52 is an example of a second via.

[0024] The conductive layers 31, 32, 33, 34, and 35 and the vias 51 and 52 are each made of metal. For example, the conductive layers 31, 32, 33, 34, and 35 and the vias 51 and 52 have a titanium (Ti) film and a copper (Cu) film formed on the titanium (Ti) film by electroplating. However, the materials and manufacturing methods of the conductive layers 31, 32, 33, 34, and 35 and the vias 51 and 52 are not limited to this example.

[0025] The insulating layers 41, 42, 43, 44, and 45 are made of insulating organic material (dielectric). For example, insulating layers 41, 42, 43, 44, and 45 are made of polyimide (PI). Note that the materials for insulating layers 41, 42, 43, 44, and 45 are not limited to this example.

[0026] Multiple conductive layers 31, 32, 33, 34, and 35 are stacked with gaps in the Z direction. An insulating layer 41 is interposed between two conductive layers 31 and 32. An insulating layer 42 is interposed between two conductive layers 32 and 33. An insulating layer 43 is interposed between two conductive layers 33 and 34. An insulating layer 44 is interposed between two conductive layers 34 and 35. An insulating layer 45 covers both the conductive layer 35 and the insulating layer 44.

[0027] The conductive layer 31 includes a plurality of pads 21. The conductive layer 31 may also include other patterns. Each of the plurality of pads 21 has two planes 21a and 21b. The planes 21a and 21b are each formed in a substantially circular shape.

[0028] Plane 21a forms part of the outer surface 11a; that is, plane 21a is included in the outer surface 11a. Plane 21a is oriented approximately in the -Z direction. The insulating layers 41, 42, 43, 44, and 45 of the interposer 11 in this embodiment do not cover plane 21a; that is, plane 21a is spaced apart from the insulating layers 41, 42, 43, 44, and 45. Plane 21b is located on the opposite side of plane 21a and is oriented approximately in the +Z direction. Plane 21b is covered by the insulating layer 41.

[0029] The conductive layer 32 includes a mesh 61 and multiple relay patterns 62. That is, the mesh 61 is contained within the conductive layer 32 located between the two conductive layers 31 and 33. Mesh 61 is an example of a second mesh.

[0030] Multiple holes 65 are provided in the mesh 61. Each of the multiple holes 65 penetrates the mesh 61 in the Z direction. The multiple holes 65 are, for example, substantially the same shape and spaced apart from each other. However, the shapes of the multiple holes 65 may differ from each other. The holes 65 are, for example, circular. However, the holes 65 may be formed in other shapes.

[0031] Each of the multiple relay patterns 62 is located within one of the multiple holes 65 of the mesh 61. In this embodiment, four of the multiple relay patterns 62 are located within one of the multiple holes 65. Note that the number of relay patterns 62 located within the holes 65 is not limited to this example.

[0032] Multiple relay patterns 62 are spaced apart from each other and also spaced apart from the mesh 61. The relay patterns 62 are electrically independent from the mesh 61. Within a single hole 65, at least two of the multiple relay patterns 62 may be connected to each other.

[0033] Figure 3 is an exemplary plan view schematically showing three conductive layers 31, 32, and 33 of the first embodiment. In Figure 3, conductive layer 31 is shown by a dashed line, conductive layer 32 by a solid line, and conductive layer 33 by a dashed line. Conductive layer 33 includes a plurality of terminals 71, a plurality of wirings 72, and a plurality of meshes 73. Mesh 73 is an example of a first mesh. Figure 3 shows one of the plurality of terminals 71. The number of plurality of terminals 71 is equal to the number of plurality of pads 21.

[0034] Each of the multiple terminals 71 is formed in a roughly rectangular shape. However, the terminals 71 may also be formed in other shapes, such as circles. Each of the multiple terminals 71 is connected to at least one of the multiple wires 72. For example, the wires 72 are connected to the corners of the terminals 71.

[0035] Each of the multiple meshes 73 is spaced apart from the terminals 71 and wiring 72. Each of the multiple meshes 73 is provided with multiple holes 75. Each of the multiple holes 75 penetrates the mesh 73 in the Z direction. The multiple holes 75 are, for example, substantially the same shape and spaced apart from each other. However, the shapes of the multiple holes 75 may differ from each other. The holes 75 are, for example, rhombic (rectangular or quadrilateral) holes. However, the holes 75 may be formed in other shapes.

[0036] The conductive layers 34 and 35 shown in Figure 2 each include, for example, multiple wirings. Furthermore, the conductive layer 35 includes, for example, multiple pads 22. Thus, the conductive layer 35 forms a part of the outer surface 11b of the interposer 11.

[0037] The insulating layer 41 has a surface 41a. The surface 41a, together with the plane 21a of the pad 21, forms a part of the outer surface 11a. The surface 41a is formed to be substantially flat and oriented substantially in the -Z direction. In this embodiment, the surface 41a of the insulating layer 41 protrudes in the -Z direction from the plane 21a of the pad 21. In other words, the plane 21a of the pad 21 is recessed from the surface 41a of the insulating layer 41.

[0038] The insulating layer 45 has a surface 45a. The surface 45a, together with the pad 22, forms a part of the outer surface 11b. The surface 45a is formed to be substantially flat and oriented substantially in the +Z direction.

[0039] Each of the multiple vias 51 and 52 is, for example, a filled via. However, vias 51 and 52 may also be other types of vias, such as a conformal via.

[0040] Each of the multiple vias 51 penetrates the insulating layer 41 between the two conductive layers 31 and 32, connecting the two conductive layers 31 and 32. In this embodiment, each of the multiple vias 51 connects one of the multiple pads 21 to one of the multiple relay patterns 62. The vias 51 are connected to the plane 21b of the pad 21.

[0041] Each of the multiple vias 52 penetrates the insulating layer 42 between the two conductive layers 32 and 33, connecting the two conductive layers 32 and 33. In this embodiment, each of the multiple vias 52 connects one of the multiple terminals 71 to one of the multiple relay patterns 62.

[0042] One via 51 and one via 52 connected to one relay pattern 62 are positioned approximately identically in the X and Y directions and aligned in the Z direction. That is, vias 51, 52 and relay pattern 62 form a stacked via SV1. The stacked via SV1 may include other patterns. The Z direction is perpendicular to the outer surface 11a.

[0043] Each of the multiple terminals 71 is connected to one of the multiple pads 21 through at least one via. In this embodiment, each of the multiple terminals 71 is connected to one pad 21 through four vias 51, four relay patterns 62, and four vias 52. The number of vias 51, relay patterns 62, and vias 52 connected to one pad is not limited to four; it may be two, three, five, or more. Also, one terminal 71 may be connected to one pad 21 through one via 51, one relay pattern 62, and one via 52.

[0044] Each of the stacked vias SV1 extends through the holes 65 of the mesh 61 between one of the pads 21 and one of the terminals 71. The stacked vias SV1 are spaced apart from the mesh 61.

[0045] The mesh 61 is electrically independent from the multiple pads 21, multiple terminals 71, and multiple wirings 72. In this embodiment, the mesh 61 is electrically floating or connected to ground. The mesh 61 of the conductive layer 32 and the mesh 73 of the conductive layer 33 may be electrically connected to each other. For example, the meshes 61 and 73 may be connected to each other by vias, for example.

[0046] In a projection view taken in the Z direction perpendicular to the outer surface 11a, as shown in Figure 3, each of the multiple holes 65 in the mesh 61 is smaller than each of the multiple terminals 71. For example, the diameter of a circular hole 65 is smaller than the width of a terminal 71. The mesh 61 covers each of the multiple terminals 71, the multiple wirings 72, and the multiple meshes 73 at least partially in the Z direction.

[0047] Specifically, the mesh 61 overlaps, at least partially, in the Z direction with the edges 71a of the terminals 71, the wiring 72, and the edges 73a of the meshes 73. The edges 71a are the ends of the terminals 71 in the direction along the outer surface 11a. The edges 73a are the ends of the meshes 73 in the direction along the outer surface 11a. In addition, the mesh 61 covers the insulating layer 43 between the edges 71a of the terminals 71 and the edges 73a of the meshes 73.

[0048] In the projection view in the Z direction, each of the multiple holes 65 in the mesh 61 in this embodiment is smaller than each of the multiple pads 21. The mesh 61 covers the multiple pads 21 at least partially in the Z direction. Note that the pads 21 do not necessarily have to be covered by the mesh 61.

[0049] The interposer 11 manufactured using RDL technology is thinner than a typical multilayer substrate. In this embodiment, the interposer 11 has five conductive layers 31, 32, 33, 34, and 35, and the thickness of the interposer 11 is 60 μm or less. The thickness of the interposer 11 is the distance between the two outer surfaces 11a and 11b.

[0050] The interposer 11 may also have four conductive layers 31, 32, 33, and 35 and four insulating layers 41, 42, 43, and 45. In other words, the conductive layer 34 and the insulating layer 44 may be omitted. In this case, the thickness of the interposer 11 will be 50 μm or less.

[0051] Interposers 11 manufactured using RDL technology allow for thinner conductive layers 31, 32, 33, 34, and 35. The thickness of each conductive layer 31, 32, 33, 34, and 35 is 10 μm or less. An example of the thickness of each conductive layer 31, 32, 33, 34, and 35 is approximately 5-6 μm. In a typical multilayer substrate, the thickness of the conductive layer is, for example, 20-35 μm.

[0052] Interposers 11 manufactured using RDL technology can have a smaller wiring width 72. The wiring width 72 is less than 10 μm. An example of a wiring width 72 is 5-6 μm. In a typical multilayer substrate, the wiring width is, for example, 20-35 μm.

[0053] The following examples illustrate some methods for manufacturing the semiconductor device 10, with reference to Figures 4 to 9. Note that the manufacturing method of the semiconductor device 10 is not limited to the methods described below, and other methods may be used. Figure 4 is a schematic cross-sectional view illustrating a conductive layer 31 formed on a glass substrate G in the first embodiment.

[0054] The interposer 11 is formed on a glass substrate G as shown in Figure 4. First, a release layer RL is applied to the glass substrate G. Next, a titanium layer TL is deposited on the release layer RL. The titanium layer TL is deposited over the entire upper surface of the release layer RL, as shown by the dashed line in Figure 4.

[0055] Next, a conductive layer 31 as copper foil is formed on the titanium layer TL by electroplating. The conductive layer 31 is deposited over the entire upper surface of the titanium layer TL, as shown by the dashed line in Figure 4. Then, the conductive layer 31 and the titanium layer TL are partially removed by photolithography, and pads 21 of the conductive layer 31 are formed as shown in Figure 4.

[0056] Figure 5 is a schematic cross-sectional view illustrating an insulating layer 41 deposited on the conductive layer 31 in the first embodiment. Next, the insulating layer 41 is deposited on the glass substrate G and the conductive layer 31. The thickness of the insulating layer 41 is greater than the thickness of the conductive layer 31. Therefore, the insulating layer 41 covers the conductive layer 31.

[0057] Next, as shown in Figure 4, multiple through-holes 81 are provided in the insulating layer 41. For example, multiple through-holes 81 are formed in the insulating layer 41 by reactive ion etching (RIE). Each of the multiple through-holes 81 penetrates the insulating layer 41, exposing the flat surface 21b of the pad 21.

[0058] Figure 6 is a schematic cross-sectional view illustrating a conductive layer 32 deposited on the insulating layer 41 of the first embodiment. Next, a titanium layer is deposited on the insulating layer 41 and on the flat surface 21b of the pad 21 exposed by the through hole 81.

[0059] Next, a copper foil film is formed on the titanium layer by electroplating. This forms a conductive layer 32 and a plurality of vias 51. Specifically, the conductive layer 32 includes a titanium layer provided on the insulating layer 41 and a copper foil provided on the titanium layer. Each of the plurality of vias 51 includes a titanium layer provided on the plane 21b and a copper foil provided on the titanium layer. The titanium layer and copper foil fill the through holes 81. Next, the conductive layer 32 is partially removed by photolithography, and a mesh 61 and a plurality of relay patterns 62 of the conductive layer 32 are formed as shown in Figure 6.

[0060] Figure 7 is a schematic cross-sectional view illustrating an interposer 11 formed on a glass substrate G according to the first embodiment. Next, an insulating layer 42 is formed on the conductive layer 32 and the insulating layer 41. The thickness of the insulating layer 42 is greater than the thickness of the conductive layer 32. Therefore, the insulating layer 42 covers the conductive layer 32. Furthermore, the insulating layer 42 fills the multiple holes 65 of the mesh 61.

[0061] Next, as shown in Figure 7, multiple through-holes 82 are provided in the insulating layer 42. For example, multiple through-holes 82 are formed in the insulating layer 42 by RIE. Each of the multiple through-holes 82 penetrates the insulating layer 42, exposing the relay pattern 62.

[0062] Next, a titanium layer is formed on the insulating layer 42 and on the relay pattern 62 exposed by the through holes 82. Then, copper foil is formed on the titanium layer by electroplating. This forms a conductive layer 33 and a plurality of vias 52. Specifically, the conductive layer 33 includes a titanium layer provided on the insulating layer 42 and copper foil provided on the titanium layer. Each of the plurality of vias 52 includes a titanium layer provided on the relay pattern 62 and copper foil provided on the titanium layer. The titanium layer and copper foil fill the through holes 82. Next, the conductive layer 33 is partially removed by photolithography, and a plurality of terminals 71, a plurality of wirings 72, and a plurality of meshes 73 are formed on the conductive layer 33 as shown in Figure 7.

[0063] As shown in Figure 7, after the conductive layer 33 is formed, the insulating layer 43, conductive layer 34, insulating layer 44, conductive layer 35, and insulating layer 45 are formed sequentially. The conductive layers 34 and 35, like the conductive layers 32 and 33, contain a titanium layer and copper foil, and patterns are formed by photolithography. This forms multiple pads 22 on the conductive layer 35. As a result, multiple interposers 11 are integrally formed on the glass substrate G.

[0064] Figure 8 is a schematic cross-sectional view illustrating an interposer 11 sealed with a sealing resin 17 according to the first embodiment. Next, the memory controller 12 and flash memory 13 are mounted on the interposer 11. For example, the memory controller 12 is mounted on the interposer 11 by flip-chip mounting. Furthermore, a plurality of spacers 14 are bonded to the interposer 11, and a plurality of flash memory 13 are bonded to the memory controller 12 and spacers 14. Furthermore, the plurality of flash memory 13 are connected to the interposer 11 by wire bonding.

[0065] Next, as shown in Figure 8, the memory controller 12, flash memory 13, spacer 14, adhesive film 15, and bonding wire 16 are sealed by the sealing resin 17. The sealing resin 17 adheres to the outer surface 11b of the interposer 11.

[0066] Figure 9 is a schematic cross-sectional view illustrating the semiconductor device 10 being cut out according to the first embodiment. Next, the interposer 11 and the release layer RL are removed from the glass substrate G. Next, the release layer RL is removed from the outer surface 11a of the interposer 11.

[0067] Next, the titanium layer TL on the flat surface 21a of the pad 21 is removed, for example, by wet etching. This exposes the flat surface 21a of the pad 21, which is made of copper foil. Then, multiple bumps 18 are provided on the multiple pads 21.

[0068] As a result, multiple semiconductor devices 10 are formed integrally. Next, the multiple semiconductor devices 10 are separated from each other by the blade BL. This completes the manufacturing of each individual semiconductor device 10.

[0069] As described above, the interposer 11 manufactured using RDL technology has thin conductive layers 31, 32, 33, 34, 35 and thin insulating layers 41, 42, 43, 44, 45. The conductive layers 31, 32, 33, 34, 35 and the insulating layers 41, 42, 43, 44, 45 have different coefficients of thermal expansion.

[0070] Due to the difference in thermal expansion between the conductive layers 31, 32, 33, 34, 35 and the insulating layers 41, 42, 43, 44, 45, stress (thermal stress) may occur, for example, at the connection point (boundary) between the edge 71a of the terminal 71 and the insulating layer 43.

[0071] In a typical RDL board, thermal stress at the connection point between the edge of a pattern, such as terminal 71, and the insulating layer can cause cracks at that connection point. Because the wiring on an RDL board is thin and narrow, these cracks can lead to disconnection. On the other hand, cracks are relatively less likely to occur at the connection point between the edge of a metal mesh and the insulating layer, and in the areas where the metal mesh overlaps.

[0072] In the interposer 11 of this embodiment, the mesh 61 covers the edge 71a of the terminal 71, the wiring 72, and the edge 73a of the mesh 73. Therefore, the mesh 61 reinforces the connection between the edge 71a of the terminal 71 and the insulating layer 43, and can suppress the occurrence of cracks in the connection. In addition, the mesh 61 reinforces the thin and narrow wiring 72 formed using RDL technology, and can suppress the disconnection of the wiring 72.

[0073] Figure 10 is an illustrative plan view schematically showing three conductive layers 31, 32, and 33 according to a first modification of the first embodiment. As shown in Figure 10, the mesh 61 may be provided with multiple holes 65A instead of multiple holes 65.

[0074] As shown in Figure 3, two adjacent holes 65 are adjacent in a direction between the X and Y directions (diagonal direction). That is, the multiple holes 65 are arranged in a rhombic lattice or a hexagonal lattice, for example.

[0075] On the other hand, as shown in Figure 10, two adjacent holes 65A are adjacent in either the X or Y direction. That is, the multiple holes 65A are arranged, for example, in a square lattice or a rectangular lattice.

[0076] Figure 11 is a schematic plan view illustrating three conductive layers 31, 32, and 33 according to a second modified example of the first embodiment. Figure 12 is a schematic plan view illustrating three conductive layers 31, 32, and 33 according to a third modified example of the first embodiment.

[0077] As shown in Figure 11, the mesh 61 may have multiple holes 65B instead of multiple holes 65. Also, as shown in Figure 12, the mesh 61 may have multiple holes 65C instead of multiple holes 65.

[0078] As shown in Figure 3, each of the multiple holes 65 is circular. On the other hand, as shown in Figures 11 and 12, each of the multiple holes 65B and 65C is square. The multiple holes 65B are arranged in a rhombic or hexagonal grid. The multiple holes 65C are arranged in a square or rectangular grid.

[0079] As described above, the holes in mesh 61 (holes 65, 65A, 65B, 65C) may be of various shapes. The holes in mesh 61 are not limited to the examples above; they may be other polygons such as hexagons, or other shapes.

[0080] In the semiconductor device 10 according to the first embodiment described above, the interposer 11 has an outer surface 11a, an outer surface 11b located on the opposite side of the outer surface 11a, and a pad 21 provided on the outer surface 11a. The interposer 11 has conductive layers 31, 32, 33, 34, 35, insulating layers 41, 42, 43, 44, 45 interposed between two adjacent conductive layers 31, 32, 33, 34, 35, and a plurality of vias 51, 52 connecting at least two conductive layers 31, 32, 33, 34, 35. When there are four conductive layers 31, 32, 33, 34, 35, the distance between the outer surface 11a and the outer surface 11b is 50 μm or less. When there are five conductive layers 31, 32, 33, 34, and 35, the distance between the outer surface 11a and the outer surface 11b is 60 μm. Such a thin interposer 11 can be manufactured by RDL technology.

[0081] The conductive layers 31, 32, 33, 34, and 35 each contain a pad 21, a terminal 71, wiring 72, a mesh 73, and a mesh 61. The pad 21 is included in conductive layer 31 of the conductive layers 31, 32, 33, 34, and 35. The terminal 71 is included in conductive layer 33 of the conductive layers 31, 32, 33, 34, and 35, and is connected to the pad 21 through at least one of the vias 51 and 52. The wiring 72 is included in conductive layer 33 and is connected to the terminal 71. The mesh 73 is included in conductive layer 33 and is spaced apart from the terminal 71 and the wiring 72. The mesh 61 is included in conductive layer 32, which is located between conductive layer 31 and conductive layer 33 of the conductive layers 31, 32, 33, 34, and 35. The mesh 61 is electrically independent of the pad 21, terminal 71, and wiring 72, and at least partially covers each of the terminal 71, wiring 72, and mesh 73 in the Z direction perpendicular to the outer surface 11a.

[0082] For example, in an interposer 11 manufactured using RDL technology, thermal stress may occur at the connection point between the edge 71a of the terminal 71 and the insulating layer 43 due to the difference in thermal expansion between the conductive layers 31, 32, 33, 34, 35 and the insulating layers 41, 42, 43, 44, 45. However, the mesh 61 reinforces the connection point between the edge 71a of the terminal 71 and the insulating layer 43 by covering the terminal 71, the wiring 72, and the mesh 73. The mesh 61 also reinforces the connection point between the terminal 71 and the wiring 72. As a result, the semiconductor device 10 can suppress the occurrence of cracks between the edge 71a of the terminal 71 and the insulating layer 43 due to thermal stress, and can also suppress the occurrence of cracks between the terminal 71 and the wiring 72 due to thermal stress. In other words, the semiconductor device 10 can suppress the occurrence of disconnections due to thermal stress.

[0083] The mesh 61 covers the pad 21 at least partially in the Z direction perpendicular to the outer surface 11a. This reinforces the connection between the pad 21 and the insulating layer 41. As a result, the semiconductor device 10 can suppress the occurrence of cracks between the pad 21 and the insulating layer 41 due to thermal stress.

[0084] The pad 21 has a plane 21a that is included in the outer surface 11a. The insulating layers 41, 42, 43, 44, and 45 are spaced apart from the plane 21a. In other words, the insulating layers 41, 42, 43, 44, and 45 do not cover the plane 21a of the pad 21. Therefore, the semiconductor device 10 can prevent the thickness of the interposer 11 from increasing due to the insulating layers 41, 42, 43, 44, and 45 covering the plane 21a of the pad 21.

[0085] The mesh 61 is contained within the conductive layer 32. The conductive layer 32 is located within one of the multiple holes 65 of the mesh 61 and includes a relay pattern 62 that is electrically independent from the mesh 61. Via 51 connects the pad 21 to the relay pattern 62. Via 52 connects the terminal 71 to the relay pattern 62. Via 51 and via 52 are aligned in the Z direction perpendicular to the outer surface 11a. That is, the terminal 71 and the pad 21 are connected to each other by a stacked via SV1. By connecting the terminal 71 and the pad 21 to each other by the stacked via SV1, the semiconductor device 10 can reduce the size of the holes 65 in the mesh 61.

[0086] In the projection view taken in the Z direction perpendicular to the outer surface 11a, each of the multiple holes 65 in the mesh 61 is smaller than the terminal 71. This allows the semiconductor device 10 to have smaller terminals 71, and consequently, to have a higher wiring density in the conductive layer 33.

[0087] (Second embodiment) A second embodiment will be described below with reference to Figures 13 and 14. In the following descriptions of multiple embodiments, components having the same function as those already described will be denoted by the same reference numerals as those previously described, and their descriptions may be omitted. Furthermore, multiple components denoted by the same reference numerals do not necessarily share all functions and properties, and may have different functions and properties depending on the embodiment.

[0088] Figure 13 is an exemplary cross-sectional view schematically showing a part of the semiconductor device 10 according to the second embodiment. As shown in Figure 13, the conductive layer 32 of the second embodiment has a plurality of relay patterns 201 instead of a plurality of relay patterns 62. The relay patterns 201 are substantially equivalent to the relay patterns 62, except as described below.

[0089] The relay pattern 201 extends in a direction along the outer surface 11a of the interposer 11. For example, the relay pattern 201 extends in the X direction. The relay pattern 201 may also extend in the Y direction, or in a direction between the X and Y directions (diagonal direction).

[0090] Via 51 is connected to one end of the relay pattern 201 in the X direction. Via 52 is connected to the other end of the relay pattern 201 in the X direction. That is, one via 51 and one via 52 connected to one relay pattern 201 are spaced apart from each other in the X direction. Vias 51, 52 and the relay pattern 201 form a staggered via SV2. The staggered via SV2 may include other patterns.

[0091] Two staggered vias SV2 adjacent to each other in the X direction are formed symmetrically in the X direction. For example, two vias 52 are positioned outside of two vias 51. That is, in the X direction, two vias 51 are located between two vias 52.

[0092] Figure 14 is a schematic cross-sectional view illustrating a part of a semiconductor device 10 according to a modification of the second embodiment. As shown in Figure 14, in the X direction, the two vias 52 may be located between the two vias 51. The multiple staggered vias SV2 may have the same shape as each other, or they may have different shapes as each other.

[0093] In the semiconductor device 10 of the second embodiment described above, vias 51 and 52 are spaced apart from each other in the X direction along the outer surface 11a. That is, terminal 71 and pad 21 are connected to each other by staggered vias SV2. Since terminal 71 and pad 21 are connected to each other by staggered vias SV2, the semiconductor device 10 does not need to use filled vias for vias 51 and 52, and can be easily manufactured.

[0094] (Third embodiment) A third embodiment will be described below with reference to Figure 15. Figure 15 is a schematic plan view illustrating three conductive layers 31, 32, and 33 according to the third embodiment. As shown in Figure 15, the mesh 61 of the third embodiment is provided with multiple holes 301 instead of multiple holes 65. The holes 301 are substantially equivalent to the holes 65, except as described below.

[0095] As shown in Figure 15, in the projection view in the Z direction, each of the multiple holes 301 in the mesh 61 in this embodiment is larger than each of the multiple pads 21. The mesh 61 at least partially covers the multiple pads 21 such that each of the multiple pads 21 overlaps the holes 301 in the Z direction.

[0096] In the semiconductor device 10 of the third embodiment described above, in the projection view in the Z direction, each of the multiple holes 301 of the mesh 61 is larger than the pad 21. The mesh 61 covers the pad 21 at least partially such that the pad 21 overlaps one of the multiple holes 301 in the Z direction. That is, the pad 21 is not covered by the metal portion of the mesh 61. Therefore, the mesh 61 does not easily restrain the pad 21 when the conductive layers 31, 32, 33, 34, 35 and the insulating layers 41, 42, 43, 44, 45 undergo thermal expansion. Consequently, the mesh 61 can suppress the increase in thermal stress at the connection portion between the pad 21 and the insulating layer 41 due to the restraint of the pad 21.

[0097] (Fourth embodiment) A fourth embodiment will be described below with reference to Figure 16. Figure 16 is a schematic cross-sectional view illustrating a part of the semiconductor device 10 according to the fourth embodiment. As shown in Figure 16, the interposer 11 of the fourth embodiment omits the conductive layer 32 and the insulating layer 42. That is, the interposer 11 has four conductive layers 31, 33, 34, and 35, four insulating layers 41, 43, 44, and 45, and a plurality of vias 51. For this reason, the thickness of the interposer 11 is 50 μm or less.

[0098] In the fourth embodiment, the insulating layer 41 is interposed between the two conductive layers 31 and 33. Also, the multiple vias 51 in the fourth embodiment connect the two conductive layers 31 and 33. In the fourth embodiment, each of the multiple vias 51 connects one of the multiple pads 21 to one of the multiple terminals 71.

[0099] In a fourth embodiment, the conductive layer 31 includes a mesh 401, which is an example of a second mesh. Mesh 401 is substantially equivalent to mesh 61, except as described below.

[0100] The mesh 401 is provided with a plurality of holes 301, as in the third embodiment. That is, in the projection view in the Z direction, each of the plurality of holes 301 in the mesh 401 is larger than each of the plurality of pads 21. Each of the plurality of pads 21 is located within one of the plurality of holes 301. The pads 21 are spaced apart from the mesh 401.

[0101] Mesh 401 has a plane 401a. Plane 401a forms part of the outer surface 11a. That is, plane 401a is included in the outer surface 11a. Plane 401a is oriented approximately in the -Z direction.

[0102] In the fourth embodiment, the insulating layers 41, 43, 44, and 45 of the interposer 11 do not cover the plane 401a. That is, the plane 401a is spaced apart from the insulating layers 41, 43, 44, and 45.

[0103] Since the titanium layer TL is removed during the manufacturing process, the surface 41a of the insulating layer 41 in the fourth embodiment protrudes in the -Z direction from the plane 401a of the mesh 401. In other words, the plane 401a of the mesh 401 is recessed from the surface 41a of the insulating layer 41. Note that the plane 401a may be covered by the insulating layer 41 or another insulating layer.

[0104] In the semiconductor device 10 of the fourth embodiment described above, the mesh 401 is included in the conductive layer 31. That is, the interposer 11 does not need to have a conductive layer 32 between the conductive layer 31 and the conductive layer 33. Therefore, the interposer 11 of the semiconductor device 10 can be made thinner.

[0105] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0106] 10... Semiconductor device, 11... Interposer, 11a, 11b... Outer surface, 21... Pad, 21a... Plane, 31, 32, 33, 34, 35... Conductive layer, 41, 42, 43, 44, 45... Insulating layer, 51, 52... Via, 61, 73, 401... Mesh, 62, 201... Relay pattern, 65, 65A, 65B, 65C, 301... Hole, 71... Terminal, 72... Wiring.

Claims

1. A substrate having a first outer surface, a second outer surface located on the opposite side of the first outer surface, and a pad provided on the first outer surface, It is equipped with, The substrate comprises four or five conductive layers, a plurality of insulating layers interposed between two adjacent conductive layers, and a plurality of vias connecting at least two of the conductive layers. When the number of conductive layers is four, the distance between the first outer surface and the second outer surface is 50 μm or less, and when the number of conductive layers is five, the distance between the first outer surface and the second outer surface is 60 μm or less. The conductive layer is The pad included in the first conductive layer among the conductive layers, A terminal included in the second conductive layer of the conductive layer and connected to the pad through at least one of the vias, Wiring included in the second conductive layer and connected to the terminal, The first mesh is included in the second conductive layer and is spaced apart from the terminals and the wiring, A second mesh is included in the conductive layer, which is located between the first conductive layer and the second conductive layer, and is electrically independent of the pad, the terminal, and the wiring, and at least partially covers the terminal, the wiring, and the first mesh in a direction perpendicular to the first outer surface. Having, Semiconductor equipment.

2. The pad has a plane included in the first outer surface, The insulating layer is spaced apart from the plane. The semiconductor device according to claim 1.

3. The second mesh is included in the third conductive layer, The third conductive layer includes a relay pattern located in one of the multiple holes of the second mesh and electrically independent from the second mesh. The via includes a first via connecting the pad and the relay pattern, and a second via connecting the terminal and the relay pattern. The first via and the second via are aligned in a direction perpendicular to the first outer surface, or spaced apart from each other in a direction along the first outer surface. The semiconductor device according to claim 1.

4. In the projection view taken in a direction perpendicular to the first outer surface, each of the multiple holes in the second mesh is smaller than the terminal. The semiconductor device according to claim 1.

5. The second mesh is included in the first conductive layer, The semiconductor device according to claim 1.

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