Semiconductor equipment

Abstract

To provide semiconductor devices and display devices with good electrical characteristics, high reliability, and stable electrical characteristics. [Solution] The semiconductor device has a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. The first insulating layer is in contact with the upper surface of the first conductive layer, the semiconductor layer is in contact with the upper surface of the first insulating layer, the pair of second conductive layers are in contact with the upper surface of the semiconductor layer, and the pair of second conductive layers are separated in the region where they overlap with the first conductive layer. The semiconductor layer has indium and oxygen, and in a triangular diagram showing the atomic ratios of indium, element M, and zinc, the composition is within the range where the first coordinate (1:0:0), the second coordinate (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), the sixth coordinate (2:0:3), and the first coordinate are connected by straight lines in this order. Furthermore, element M is one or more of gallium, aluminum, yttrium, or tin.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Regarding the device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technology field is semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, Electronic equipment, lighting equipment, input devices, input / output devices, methods for driving them, or methods for manufacturing them. One example is semiconductor devices that function by utilizing semiconductor properties. This refers to all types of devices. [Background technology]

[0003] Oxide semiconductors, which use metal oxides, are attracting attention as semiconductor materials applicable to transistors. For example, Patent Document 1 describes stacking multiple oxide semiconductor layers, and the multiple oxide semiconductor layers are stacked. In the material semiconductor layer, the oxide semiconductor layer that forms the channel contains indium and gallium, and By making the proportion of indium greater than the proportion of gallium, the field effect mobility (simply move A semiconductor device with increased mobility (sometimes referred to as μFE) is disclosed.

[0004] Non-patent documents 1 and 2 describe the oxidation of InGaO3(ZnO)m (m: natural number). A semiconductor material is disclosed.

[0005] Metal oxides that can be used in semiconductor layers can be formed using methods such as sputtering. Therefore, it can be used in the semiconductor layer of transistors that make up large display devices. By improving some of the production equipment for transistors using polycrystalline silicon and amorphous silicon, Because it can be used, capital investment can be reduced. Also, a transient using metal oxides Because it has a higher field-effect mobility compared to when amorphous silicon is used, the drive circuit This enables the creation of high-performance display devices. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 2] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Overview of the project] [Problems that the invention aims to solve]

[0008] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. One aspect of the invention aims to provide a highly reliable semiconductor device. One aspect of this invention aims to provide a semiconductor device with stable electrical characteristics. One of the objectives is to provide a highly reliable display device.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title can be extracted from descriptions such as the specification, drawings, and claims. [Means for solving the problem]

[0010] One aspect of the present invention comprises a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. A semiconductor device having layers. The first insulating layer is in contact with the upper surface of the first conductive layer, and the semiconductor The layer is in contact with the upper surface of the first insulating layer, and the pair of second conductive layers are in contact with the upper surface of the semiconductor layer, The second conductive layer is separated in the region where it overlaps with the first conductive layer. The semiconductor layer is made of indium and In a triangular diagram showing the atomic ratios of indium, element M, and zinc, the first The coordinates are (1:0:0), the second coordinates are (2:1:0), and the third coordinates are (14:7:1) , the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), and the sixth coordinate (2:0 :3) and the first coordinate are within the range of the composition that is connected by a straight line in this order. Also, element M is , gallium, aluminum, yttrium, or tin (one or more of these).

[0011] One aspect of the present invention comprises a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. A semiconductor device having layers. The first insulating layer is in contact with the upper surface of the first conductive layer, and the semiconductor The layer is in contact with the upper surface of the first insulating layer, and the pair of second conductive layers are in contact with the upper surface of the semiconductor layer, The second conductive layer is separated in the region where it overlaps with the first conductive layer. The semiconductor layer is made of indium and In a triangular diagram showing the atomic ratios of indium, element M, and zinc, the first The coordinates are (7:1:0), the second coordinates are (2:1:0), and the third coordinates are (14:7:1) , the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), and the sixth coordinate (2:0 Within the range of the lines connecting :3), the 7th coordinate (7:0:1), and the 1st coordinate in that order It has a composition. Also, element M is gallium, aluminum, yttrium or tin. The difference is one or more.

[0012] One aspect of the present invention comprises a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. A semiconductor device having layers. The first insulating layer is in contact with the upper surface of the first conductive layer, and the semiconductor The layer is in contact with the upper surface of the first insulating layer, and the pair of second conductive layers are in contact with the upper surface of the semiconductor layer, The second conductive layer is separated in the region where it overlaps with the first conductive layer. The semiconductor layer is made of indium and It contains zinc and oxygen, and in a triangular diagram showing the atomic ratio of indium, element M and zinc... The first coordinates are (44:11:10), the second coordinates are (4:1:6), and the third coordinates are (2 The range of lines connecting the fourth coordinate (11:0:2) and the first coordinate in this order. It has the composition within the range. Also, element M is gallium, aluminum, yttrium or s It is one or more of the following:

[0013] One aspect of the present invention comprises a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. A semiconductor device having layers. The first insulating layer is in contact with the upper surface of the first conductive layer, and the semiconductor The layer is in contact with the upper surface of the first insulating layer, and the pair of second conductive layers are in contact with the upper surface of the semiconductor layer, The second conductive layer is separated in the region where it overlaps with the first conductive layer. The semiconductor layer is made of indium and It contains zinc and oxygen, and in a triangular diagram showing the atomic ratio of indium, element M and zinc... The first coordinates are (44:11:10), the second coordinates are (4:1:4), and the third coordinates are (1 The range of lines connecting the fourth coordinate (11:0:2) and the first coordinate in this order. It has the composition within the range. Also, element M is gallium, aluminum, yttrium or s It is one or more of the following:

[0014] In the semiconductor device described above, the semiconductor layer comprises a first metal oxide film and a first metal oxide film It has a laminated structure with a second metal oxide film on top, and the first metal oxide film is the second metal oxide film Lower crystallinity than that of a film is preferable.

[0015] In the semiconductor device described above, the second conductive layer comprises the first conductive film and the second conductive layer on the first conductive film. It is preferable to have a laminated structure of a conductive film and a third conductive film on a second conductive film. The second conductive film preferably contains copper, silver, gold, or aluminum. The conductive film and the third conductive film each contain elements different from those of the second conductive film, and the first conductive film The first and third conductive films are, independently, titanium, tungsten, molybdenum, chromium, and It is preferable to include one of the following: nitral, zinc, indium, platinum, and ruthenium. stomach.

[0016] The semiconductor device described above further has a second insulating layer, the second insulating layer being a semiconductor layer It is preferable that the upper surface and the upper and side surfaces of the second conductive layer are in contact. It is preferable that it contains oxygen.

[0017] The aforementioned semiconductor device further has a third insulating layer, the third insulating layer is the second insulating layer It is preferable that the third insulating layer is in contact with the upper surface of the layer. Furthermore, it is preferable that the third insulating layer contains nitrogen.

[0018] In the aforementioned semiconductor device, the second insulating layer contains silicon oxide, and the third insulating layer contains, It is preferable that the material contains silicon nitride. [Effects of the Invention]

[0019] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, reliability We can provide semiconductor devices with high performance, or semiconductor devices with stable electrical characteristics. Alternatively, a highly reliable display device can be provided.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0021] [Figure 1] Figures 1A and 1B illustrate the composition of metal oxides. [Figure 2] Figures 2A and 2B illustrate the composition of metal oxides. [Figure 3] Figures 3A and 3B illustrate the composition of metal oxides. [Figure 4] Figure 4 is a diagram illustrating the composition of metal oxides. [Figure 5]Figure 5A illustrates the classification of IGZO crystal structures. Figure 5B illustrates the XRD spectrum of quartz glass. Figure 5C illustrates the XRD spectrum of crystalline IGZO. [Figure 6] Figures 6A and 6B are cross-sectional views showing examples of transistor configurations. [Figure 7] Figures 7A and 7B are cross-sectional views showing examples of transistor configurations. [Figure 8] Figure 8A is a top view showing an example of a transistor configuration. Figures 8B and 8C are cross-sectional views showing an example of a transistor configuration. [Figure 9] Figures 9A, 9B, and 9C are cross-sectional views showing examples of transistor configurations. [Figure 10] Figure 10A is a top view showing an example of a transistor configuration. Figures 10B and 10C are cross-sectional views showing an example of a transistor configuration. [Figure 11] Figures 11A and 11B are cross-sectional views showing examples of transistor configurations. [Figure 12] Figures 12A and 12B are cross-sectional views showing examples of transistor configurations. [Figure 13] Figures 13A, 13B, and 13C are cross-sectional views illustrating the method for fabricating a transistor. [Figure 14] Figures 14A and 14B are cross-sectional views illustrating the method for fabricating a transistor. [Figure 15] Figures 15A and 15B are cross-sectional views illustrating the method for fabricating a transistor. [Figure 16] Figures 16A and 16B are cross-sectional views illustrating the method for fabricating a transistor. [Figure 17] Figure 17 is a cross-sectional view illustrating the method for fabricating a transistor. [Figure 18] Figures 18A and 18B are cross-sectional views illustrating the method for fabricating a transistor. [Figure 19] Figures 19A and 19B are cross-sectional views illustrating the method for fabricating a transistor. [Figure 20]Figures 20A and 20B are cross-sectional views illustrating the method for fabricating a transistor. [Figure 21] Figures 21A, 21B, 21C, and 21D are cross-sectional views showing examples of transistor configurations. [Figure 22] Figure 22A is a top view showing an example of a transistor configuration. Figures 22B and 22C are cross-sectional views showing an example of a transistor configuration. [Figure 23] Figure 23A is a top view showing an example of a transistor configuration. Figures 23B and 23C are cross-sectional views showing an example of a transistor configuration. [Figure 24] Figure 24A is a top view showing an example of a transistor configuration. Figures 24B and 24C are cross-sectional views showing an example of a transistor configuration. [Figure 25] Figures 25A, 25B, 25C, 25D, and 25E show examples of transistor configurations. [Figure 26] Figures 26A, 26B, and 26C are top views of the display device. [Figure 27] Figure 27 is a cross-sectional view of the display device. [Figure 28] Figure 28 is a cross-sectional view of the display device. [Figure 29] Figure 29 is a cross-sectional view of the display device. [Figure 30] Figure 30 is a cross-sectional view of the display device. [Figure 31] Figure 31 is a cross-sectional view of the display device. [Figure 32] Figure 32A is a block diagram of the display device. Figures 32B and 32C are circuit diagrams of the display device. [Figure 33] Figures 33A, 33C, and 33D are circuit diagrams of the display device. Figure 33B is a timing chart of the display device. [Figure 34] Figures 34A and 34B show examples of the display module configuration. [Figure 35] Figures 35A and 35B show examples of electronic device configurations. [Figure 36]Figures 36A, 36B, 36C, and 36D show examples of electronic device configurations. [Modes for carrying out the invention]

[0022] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different forms, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0023] In each figure described herein, the size, layer thickness, or area of ​​each component is clearly defined. It may be exaggerated for that reason.

[0024] The ordinal numbers "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This was added to avoid the issue of a numerical limitation.

[0025] In this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the constituent elements. The positional relationships are used for convenience in explaining them with reference to the drawings. Also, the positions of the components are shown. The arrangement changes as appropriate depending on the direction in which each component is described. Therefore, the description in the specification is not provided. The vocabulary is not limited to the explicitly stated terms; it can be appropriately rephrased depending on the situation.

[0026] In this specification, the source and drain functions of a transistor are defined as having different polarities. When using transistors, or when the direction of current changes during circuit operation, They can be swapped. Therefore, the terms source and drain can be used interchangeably. It shall be done.

[0027] In this specification and elsewhere, the channel length direction of a transistor refers to the source region and the drain region. It refers to one of the directions parallel to the straight line connecting the two points by the shortest distance. In other words, the channel length direction is This corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. Furthermore, the channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the zista, the channel length and channel width directions may not be uniquely determined. There are cases where this is the case.

[0028] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where they are connected via. Here, "something that has some kind of electrical effect" is There are no particular restrictions as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes, wiring, transistors, etc. Switching elements, resistive elements, inductors, capacitors, and other elements with various functions This includes children, etc.

[0029] In this specification, the terms "membrane" and "layer" are interchangeable. It is possible. For example, the terms "conductive layer" and "insulating layer" are similar to "conductive film" and "insulating layer". In some cases, the term "membrane" can be used interchangeably.

[0030] In this specification, unless otherwise specified, off-current refers to the state in which the transistor is in the off state. This refers to the drain current when the device is in a non-conductive state or interrupted state. The off state is a special state. Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source V gs but Threshold voltage Vth Lower than (in p-channel transistors, V th (Higher than) To describe a state or attitude.

[0031] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0032] In this specification, the substrate of the display panel is, for example, FPC (Flexible Printed Circuit). ed Circuit) or TCP (Tape Carrier Package) Connectors such as those mentioned above are attached, or COG (Chip On Glare) is attached to the circuit board. A display panel module, display module, etc., is a device on which an IC is mounted using the ss) method, etc. Alternatively, it may simply be called a display panel.

[0033] In this specification, a touch panel, which is one form of a display device, displays images, etc. on its display surface. The display function detects when an object such as a finger or stylus touches, presses, or comes near the display surface. It has the function of a touch sensor that detects things like touching. Therefore, touch panel This is one form of an input / output device.

[0034] A touch panel is, for example, a display panel (or display device) with a touch sensor. It can also be called a display panel (or display device) with a touch function. It can also be configured to have a panel and a touch sensor panel. Alternatively, the display panel The configuration can also include a touch sensor functioning either internally or on its surface.

[0035] In this specification, a touch panel circuit board with connectors and ICs mounted on it is referred to as a touch panel. It may be called a touch panel module, display module, or simply a touch panel.

[0036] (Embodiment 1) In this embodiment, a metal that can be suitably used in a semiconductor device according to one aspect of the present invention. Let me explain oxides.

[0037] One aspect of the present invention is a semiconductor device in which a metal acid functioning as a semiconductor is formed in a channel-forming region. It contains oxides (hereinafter also called oxide semiconductors). When metal oxides are used, silicon and others Compared to other semiconductors, transistors have good switching characteristics and extremely low off-current. It is preferable because it is low.

[0038] Here, the composition of the metal oxide significantly affects the electrical characteristics and reliability of the transistor. The metal oxide preferably contains indium. Furthermore, the metal oxide contains indium. A high content is preferable. By increasing the indium content of the metal oxide, the metal acid The carrier mobility (electron mobility) of the ion can be increased. Therefore, indium Transistors using metal oxides with a high content in the channel formation region have a high field-effect mobility. It can conduct high and large currents. Furthermore, semiconductor devices using this transistor... High-speed driving becomes possible. Therefore, a display device having such a semiconductor device has a pixel section The transistors used in the drive circuit and the transistors used in the drive circuit can be formed on the same substrate. It is possible. Furthermore, by using such transistors in the pixel section, high-quality images can be provided. It is possible.

[0039] The metal oxide preferably contains element M in addition to indium. Element M is oxygen and It is preferable that the bond energy is high. In particular, the bond energy of element M with oxygen is It is preferable that the concentration is higher than that of indium. Metal oxides have a higher bonding energy with oxygen than indium. Having element M with high ghee content makes it less likely for oxygen vacancies to form in the metal oxide. Element M includes gallium, aluminum, silicon, boron, yttrium, tin, and copper. Vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum Butene, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or One or more elements of magnesium can be used. In particular, as element M, gallium, aluminum, etc. One or more of um, yttrium, or tin can be used. Also, element M is a metal. It has the function of increasing the energy gap of oxides.

[0040] Gallium can be particularly preferred as element M. The metal oxide is indium. By having gallium with a higher bonding energy with oxygen than the metal oxide, acid Elementary defect formation becomes less likely. Oxygen vacancies are present in the metal oxide used in the channel formation region. If there are too many, it can lead to a decrease in the electrical characteristics and reliability of the transistor. Therefore, indicators By using metal oxides containing um and gallium, high field-effect mobility and reliable This enables the creation of high-performance transistors.

[0041] The metal oxide preferably contains zinc in addition to indium. Alternatively, the metal oxide It is preferable that it contains indium, element M, and zinc. Zinc is a crystalline metal oxide. It has the function of enhancing [something]. Crystalline metal oxides are suitably used in the channel formation region. This is possible. For example, CAAC (c-axis aligned crystal) as described later. Metals having structures such as al(a) structure, polycrystalline structure, and microcrystalline (nc: nanocrystal) structure. Oxides can be used in the channel-forming region. Crystalline metal oxides can be used as channels. By using it in the channel formation region, the defect level density in the channel formation region can be reduced, and reliability This enables the creation of high-performance transistors.

[0042] The higher the crystallinity of the metal oxide, the lower the defect level density in the film. On the other hand, the lower the crystallinity... By using a metal oxide in the channel formation region, a channel capable of carrying a large current can be created. It is possible to realize ZISTA.

[0043] <Composition of metal oxides> The composition of metal oxides will be explained in detail below. This shows the atomic ratios of indium, element M, and zinc.

[0044] The preferred range of the atomic ratios of indium, element M, and zinc in the metal oxide is shown in Figure 1A. This is shown in Figures 1B, 2A, and 2B. Figures 1A, 1B, 2A, and 2B are indium. Using an equilateral triangle with elements M and zinc as vertices, the atomic ratios of indium, element M, and zinc are determined. This is shown and is also called a triangular diagram, triangular coordinate diagram, or triangular figure. (See Figure 1A, Figure 1) B. Figures 2A and 2B do not show the atomic ratio of oxygen.

[0045] First, the atomic ratios of each element will be explained using Figures 3A, 3B, and 4. Figure 3A Figures 3B and 4 show examples of metal oxides containing elements X, Y, and Z, respectively. The triangular diagrams shown in Figures 3A, 3B, and 4 have points X, Y, and Z as vertices. A triangle and the coordinate point W(α:β:γ) are shown as an example of the composition of a metal oxide.

[0046] The coordinate point W(α:β:γ) is such that the atomic ratio of elements X, Y, and Z is X:Y:Z=α: This indicates that the ratio is β:γ. The atomic ratio of each element is higher closer to each vertex. The further away it is, the lower the value. Here, point X has coordinates (1:0:0) and elements X and Y. And the atomic ratio of element Z is X:Y:Z=1:0:0, that is, the metal oxide contains element X, This also indicates that it does not contain either element Y or element Z. Point Y has coordinates (0:1:0 ) and the atomic ratio of elements X, Y, and Z is X:Y:Z=0:1:0, that is, gold This indicates that the group oxide contains element Y, but does not contain either element X or element Z. Point Z has coordinates (0:0:1) and the atomic ratio of elements X, Y, and Z is X:Y:Z =0:0:1, meaning the metal oxide contains element Z, and also contains both element X and element Y. It indicates that they will not.

[0047] In this specification, the atomic ratio of elements X, Y, and Z is denoted as X:Y:Z. In some cases, the ratio of the total number of atoms of elements X and Y to the number of atoms of element Z is (X + Y ): This is sometimes written as Z. Other combinations of each element may be written similarly.

[0048] Figure 3A shows lines LNx, LNy, and LNz. Line LNx is the length of side YZ. The line LNx is the line connecting point Dx (0:β:γ), which divides the element in the ratio γ:β, and point X. It can also be described as the set of points where the atomic ratio of element Y to element Z is Y:Z=β:γ. The line LNy is the same as the edge X. The line LNy is the line connecting point Dy (α:0:γ), which divides the length of Z in the ratio γ:α, and point Y. It can also be described as the set of points where the atomic ratio of element X to element Z is X:Z=α:γ. The line LNz is Line L is the straight line connecting point Dz (α:β:0), which divides the length of side XY in the ratio β:α, and point Z. Nz can also be described as the set of points where the atomic ratio of elements X and Y satisfies X:Y=α:β. Lines LNx, LNy, and LNz all intersect the coordinate point W(α:β:γ).

[0049] In this specification, etc., "the straight line connecting point A and point B" is referred to as "the line segment connecting point A and point B". It can be replaced.

[0050] Here, the coordinate point W(α:β:γ) can also be said to be the intersection of the line LNx and the line LNy. Furthermore, the coordinate point W(α:β:γ) can also be said to be the intersection of line LNy and line LNz. The reference point W(α:β:γ) can also be described as the intersection of line LNx and line LNz.

[0051] Note that the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z is (X + Y ): This is the set of points satisfying Z=1:0. In other words, the edge XY is such that the metal oxide is element X or This indicates that it has one or more elements of Y, and does not have element Z. The edge YZ is element The set of points where the atomic ratio of element X to the sum of elements Y and Z is X:(Y+Z)=0:1. Therefore, the side YZ contains one or more elements Y or Z in the metal oxide. This also indicates that element X is not present. The edge XZ is the sum of elements X and Z, and element Y This is the set of points where the atomic ratio of (X+Z):Y=1:0. In other words, edge XZ is a metal. This indicates that the oxide contains one or more elements X or Z, and does not contain element Y. It is.

[0052] As a concrete example, let's explain the case where the coordinate point W is (5:1:3). Coordinate point W(5:1: In case 3), the ratio of the length of line segment XDz to the length of line segment DzY is 1:5. The ratio of the lengths of line segments Dx and Z is 3:1. The ratio of the length of line segment XDy to the length of line segment DyZ is The ratio becomes 3:5. Also, the line LNx satisfies the atomic ratio of element Y to element Z: Y:Z=1:3. It is a point. The line LNy is the set of points where the atomic ratio of element X to element Z is X:Z=5:3. Yes, the line LNz is the set of points where the atomic ratio of element X to element Y is X:Y=5:1. .

[0053] Figure 3B shows lines PEx, PEy, and PEz. Line PEx is the coordinate point W( It is the perpendicular line drawn from α:β:γ) to side YZ. Line PEy is the coordinate point W(α:β:γ) This is a perpendicular line dropped to edge XZ. Line PEz is a perpendicular line dropped from coordinate point W(α:β:γ) to edge XY. This is the perpendicular line. Here, the ratio of the lengths of line PEx, line Pey, and line Pez is α :β:γ.

[0054] As a concrete example, let's explain the case where the coordinate point W is (5:1:3). Coordinate point W(5:1: In case 3), the ratio of the lengths of lines PEx, PEY, and Pez is 5:1:3. ru.

[0055] Figure 4A shows lines PAx, PAy, and PAz. Line PAx is parallel to side YZ. It is a straight line and intersects the coordinate point W(α:β:γ). Line PAy is a straight line parallel to side XZ. It is a line and intersects the coordinate point W(α:β:γ). Line PAz is a straight line parallel to side XY. Furthermore, the line PAx intersects with element X, element Y, and element It can also be described as the set of points where the ratio of the total number of atoms of prime Z satisfies X:(Y+Z)=α:(β+γ). Line PAy is the ratio of the total number of atoms of element X and element Z to the number of atoms of element Y (X+Z): It can also be described as the set of points satisfying Y=(α+γ):β. The line PAz represents the sum of elements X and Y. The set of points where the ratio of the number of atoms of element X to the number of atoms of element Z is (X+Y):Z=(α+β):γ That's also true.

[0056] As a concrete example, let's explain the case where the coordinate point W is (5:1:3). Coordinate point W(5:1: In case 3), the line PAx is the ratio of the number of atoms of element X to the total number of atoms of elements Y and Z. This is the set of points satisfying (Y+Z)=5:4. The line PAy is the sum of the elements X and Z. This is the set of points where the ratio of the number of atoms to the number of atoms of element Y is (X+Z):Y=8:1. (Line P) Az is the ratio of the total number of atoms of elements X and Y to the number of atoms of element Z, where (X+Y):Z=2 This is the set of points that satisfy :1.

[0057] The following describes metal oxides that can be suitably used in the channel formation region of a transistor. I will now explain the composition in detail.

[0058] [Composition of metal oxides 1] The metal oxide preferably contains indium and oxygen. It may contain one or more of element M or zinc. The composition of metal oxides that can be suitably used is shown in Figure 1A. Indium metal oxide The atomic ratio of element M and zinc falls within range 11 in the triangular diagram shown in Figure 1A. This is preferable. Range 11 is coordinate point A(1:0:0), coordinate point B(2:1:0), and coordinate Point C (14:7:1), coordinate point D (7:2:2), coordinate point E (14:4:21), The interior of the polygon formed by connecting coordinate point F(2:0:3) and the aforementioned coordinate point A with straight lines in that order. Note that range 11 also includes each coordinate point and each edge. Metals having compositions included in range 11. By using oxides in the channel formation region, high reliability and high field effect mobility are achieved. It can be made into a transistor.

[0059] Furthermore, if element M has multiple elements, the ratio of the total number of atoms of those elements is used. It is used as the atomic ratio of element M. For example, when element M is gallium and tin. The ratio of the total number of atoms of gallium and tin is used as the atomic ratio of element M.

[0060] Here, the coordinate point B(2:1:0) is the set of points satisfying (In+M):Zn=1:0. The intersection point C is the point where line L1 intersects with line L2, which is the set of points satisfying In:M=2:1. (14:7:1) is the set of points that satisfy the aforementioned line L2 and In:(M+Zn)=7:4. It is the intersection point of a certain line L3. Also, the coordinate point C is the same as the aforementioned line L2, with In:Zn=14:1. It is also an intersection point of line L4, which is the set of points that satisfy the condition. Coordinate point D(7:2:2) is the same as the aforementioned line L3 And it is the intersection point of line L5, which is the set of points satisfying In:Zn=7:2. Also, coordinate point D is It is also the intersection point of the aforementioned line L3 and line L6, which is the set of points satisfying In:M=7:2. The reference point E(14:4:21) is the set of points that satisfy the aforementioned line L6 and In:Zn=2:3. It is the intersection point of a certain line L7. The coordinate point F(2:0:3) is the intersection point of the aforementioned line L7 and (In+Zn) These are the intersection points of line L8, which is the set of points satisfying :M=1:0.

[0061] In this specification, the ratio of the number of atoms of indium, element M, and zinc is referred to as In:M:Z. It is sometimes denoted as n. Also, the ratio of the total number of atoms of indium and element M to the number of atoms of zinc. This is sometimes written as (In+M):Zn. The same applies to other combinations of each element. .

[0062] Side AB lies on the aforementioned line L1, side BC lies on the aforementioned line L2, and side CD lies on the aforementioned line L 3 is on the line L6, edge DE is on the aforementioned line L6, edge EF is on the aforementioned line L7, and edge FA is It lies on line L8 as mentioned above. In other words, range 11 is on lines L1, L2, L3, L6, and L7. It can also be said that it is the interior of a polygon enclosed by line L8.

[0063] The composition of the metal oxide satisfies line L2, In:M=2:1, as shown in range 11. It is preferable that the indium content is higher than In:M = 2:1. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of other atoms, In / M, is 2 or greater. Metal oxides with a high zinc content have high carrier mobility (electron mobility), and indium content Transistors using metal oxides with a high efficiency in the channel formation region have high field-effect mobility. It can conduct a large current.

[0064] However, a high content of element M increases the number of defect levels, which alters the threshold voltage in reliability tests. The dynamic range can sometimes become large. This is one of the indicators used to evaluate the reliability of transistors. And, the gate is held in a state where an electric field is applied to it, GBT (Gate Bias Tempo There is a stress test (ratio). In particular, the source potential and drain potential A test in which a positive potential is applied to the gate and held at a high temperature is called PBTS (Positive Potential Test). (e Bias Temperature Stress) test, applying a negative potential to the gate. In this state, a test is conducted in which the condition is maintained at a high temperature (NBTS - Negative Bias Tempe This is called a stress test. It also involves irradiating the body with light such as white LED light. The PBTS and NBTS tests conducted at the following locations are referred to as PBTIS (Positive Biological Inspection System). (as a test of NB) TIS(Negative Bias Temperature Illuminati) This is called an "on-stress" test.

[0065] In particular, in n-type transistors using metal oxides, when the transistor is in the ON state ( When current is flowing, a positive potential is applied to the gate. Therefore, PBTS test The amount of variation in the threshold voltage is an important factor to consider as an indicator of transistor reliability. It will be one of them.

[0066] Here, by using a metal oxide that does not contain element M, or has a low content of element M, This can reduce the variation in threshold voltage during PBTS testing. Furthermore, it contains element M. In some cases, the composition of the metal oxide is such that the content of element M is smaller than the indium content. It is preferable to do so. Furthermore, the ratio of the number of indium atoms to the number of atoms of element M, In / M, is Preferably, it is 2 or more. This makes it possible to realize a highly reliable transistor. It is possible.

[0067] One factor causing the threshold voltage fluctuation in PBTS testing is the relationship between the semiconductor layer and the gate insulating layer. Examples include defect levels at or near the interface. The higher the defect level density, the higher the PB Degradation becomes significant in TS tests. However, in the part of the semiconductor layer that is in contact with the gate insulating layer. By reducing the content of element M, the formation of the defect level can be suppressed. .

[0068] By not including element M, or by reducing the content of element M, PBTS degradation can be suppressed. Possible reasons for this include the following: The element M contained in the semiconductor layer is also Compared to other metallic elements (such as indium and zinc), it has a property that makes it more likely to attract oxygen. Therefore, at the interface between the metal oxide film containing a large amount of element M and the insulating layer containing oxide, Element M combines with excess oxygen in the insulating layer, creating a carrier (electron) trap site. It is presumed that this makes it easier to cause this. Therefore, when a positive potential is applied to the gate... In this case, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, thus creating a threshold. The voltage value may fluctuate.

[0069] Therefore, metal acids in which the ratio of the number of indium atoms to the number of atoms of element M (In / M) is 2 or greater By using the ion in the channel formation region, the generation of defect levels can be suppressed, resulting in high reliability. Furthermore, it is possible to create a transistor with high field-effect mobility.

[0070] The composition of the metal oxide is as shown in range 11, line L3: In:(M+Zn)=7: It is preferable that the condition satisfies 4, or that the indium content is higher than In:(M+Zn)=7:4. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc is In / (M+ It is preferable that the indium content is 7 / 4 or more. Metal oxides with a high indium content are... Metal oxides with high rear mobility (electron mobility) and high indium content form channel-forming regions. The transistor used in this region has high field-effect mobility and can conduct large currents. Therefore, metal oxides having the atomic ratio within the aforementioned range are used in the channel-forming region. This allows for the creation of transistors with higher field-effect mobility.

[0071] The composition of the metal oxide satisfies line L6, In:M=7:2, as shown in range 11. Alternatively, it is preferable that the indium content is higher than In:M = 7:2. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of atoms of , In / M, is 7 / 2 or greater. By using a metal oxide having the atomic ratio within the aforementioned range in the channel formation region, defect conditions To create a transistor that can suppress the generation of fault zones, is highly reliable, and has high field-effect mobility. It is possible.

[0072] The composition of the metal oxide satisfies line L7, In:Zn=2:3, as shown in range 11. It is preferable that the indium content is higher than In:Zn = 2:3. It is preferable that the ratio of indium atoms to lead atoms (In / Zn) is 2 / 3 or greater. High zinc content can result in polycrystalline metal oxides. These become defect levels and act as carrier traps and carrier sources, thus polycrystalline metallic acids Transistors using synthetic materials often exhibit large fluctuations in electrical characteristics, resulting in low reliability. Therefore, by setting the atomic ratio to the aforementioned range, the metal oxide becomes polycrystalline. It can be suppressed. Furthermore, by using the metal oxide in the channel formation region, reliability can be increased. It can be made into a transistor.

[0073] As the metal oxide, an In-M-Zn oxide having a composition within range 11 is used. This can be done. As an In-M-Zn oxide, for example, In:M:Zn = 5:1:1, In :M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1 :1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn =10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In :M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1 :10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or this These vicinity can be suitably used. In addition, indium oxide can be used as the metal oxide. It is possible to use it. Furthermore, In-M oxide can be used as the metal oxide. For nM oxides, for example, In:M=2:1, In:M=7:2, In:M=5:1 In:M=7:1, In:M=10:1, or a range near these values ​​can be preferably used. In addition, In-Zn oxide can be used as the metal oxide. As examples of chromosomes, for instance, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, In:Zn=14: 1, or a vicinity thereof, can be preferably used.

[0074] For example, energy-dispersive X-ray spectroscopy (EDX) is used as an analytical technique for the composition of metal oxides. Energy Dispersive X-ray spectroscopy), X-ray Photoelectron spectroscopy (XPS:X-ray Photoelectron Spectrosc) Opy), Inductively Coupled Plasma Mass Spectrometry (ICP-MS) (inductively coupled plasma-mass spectrometry), Emission spectroscopy (ICP-AES: Inductively Coupled Plasma Emission Spectroscopy) - Atomic Emission Spectroscopy (ATOM) and other methods can be used. It is possible. However, for elements with low content, the actual content may differ from the analysis result due to the influence of analytical accuracy. The obtained content may differ. For example, if the content of element M is low, the analysis may show The resulting element M content may be lower than the actual content.

[0075] Furthermore, when forming metal oxides by sputtering, the atomic ratio of the target and the The atomic ratio of metal oxides can vary. In particular, zinc may have a different atomic ratio than the target. The atomic ratio of metal oxides may decrease. Specifically, the zinc contained in the target The atomic ratio may be between 40% and 90%. The target used here is Polycrystalline is preferable.

[0076] [Composition of metal oxides 2] Metal oxides contain one or more of the elements M or zinc, indium, and oxygen. Preferably, a metal oxide suitable for use in the channel formation region of a transistor. The composition of the substance is shown in Figure 1B. The atomic ratios of indium, element M, and zinc in the metal oxide are shown in Figure In the triangular diagram shown in 1B, it is preferable that it is included in range 13. Range 13 is coordinate point G (7:1:0), coordinate point B(2:1:0), coordinate point C(14:7:1), and coordinate point D (7:2:2), coordinate point E(14:4:21), coordinate point F(2:0:3), and coordinate point This is the interior of the polygon formed by connecting H(7:0:1) and the aforementioned coordinate point G with straight lines in that order. Range 13 also includes each coordinate point and each edge. Metal oxides having compositions included in Range 13. By using this in the channel formation region, a highly reliable and high field-effect mobility transistor is produced. It can be used as a generator.

[0077] Here, the coordinate point G(7:1:0) is the set of points satisfying (In+M):Zn=1:0. It is the intersection of a line L1 and a line L9 which is the set of points satisfying In:(M+Zn)=7:1. The coordinate point H(7:0:1) is the point that satisfies (In+Zn):M=1:0 with the aforementioned line L9. These are the intersection points of line L8, which is the set of points. For coordinate points B through F, please refer to the description above. Since it is possible, a detailed explanation will be omitted.

[0078] Edge GB lies on the aforementioned line L1, edge BC lies on the aforementioned line L2, and edge CD lies on the aforementioned line L 3 is on the line L6 mentioned above, edge DE is on the line L7 mentioned above, edge EF is on the line L7 mentioned above, edge FH is It lies on the aforementioned line L8, and edge HG lies on the aforementioned line L9. In other words, range 13 is on line L1, It is also the interior of the polygon enclosed by lines L2, L3, L6, L7, L8, and L9. Yes, I can.

[0079] The composition of the metal oxide is as shown in range 13, line L9, In:(M+Zn)=7: It is preferable that the formula satisfies 1, or that the In content is lower than In:(M+Zn)=7:1. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc is In / (M+Zn). However, it is preferable that it be 7 or less. If the indium content is high, the metal oxide will be bixba In some cases, a lithotype crystal structure may be formed. Alternatively, the metal oxide may have a bixbite-type crystal structure. In some cases, a crystalline structure may exist in which layered crystalline structures coexist. Grain boundaries can form between different crystal structures. Grain boundaries are defect levels and As such, metal oxides with grain boundaries become carrier traps and carrier sources. Transistors using this technology can exhibit large fluctuations in electrical characteristics, resulting in low reliability. Therefore, by setting the atomic ratio within the aforementioned range, the metal oxide becomes a bixbite type crystal. The formation of a structure is suppressed, and it becomes easier to have a layered crystalline structure. By using this in the channel formation region, a highly reliable transistor can be created. .

[0080] The composition of the metal oxide satisfies line L2, In:M=2:1, as shown in range 13. It is preferable that the indium content is higher than In:M = 2:1. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of atoms of the other substance (In / M) is 2 or greater. By using a metal oxide with an atomic ratio within this range in the channel formation region, defect levels can be formed. This allows for the suppression of generation, resulting in a highly reliable transistor with high field-effect mobility. Cut.

[0081] The composition of the metal oxide is as shown in range 13, line L3: In:(M+Zn)=7: It is preferable that the condition satisfies 4, or that the indium content is higher than In:(M+Zn)=7:4. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc is In / (M+ Preferably, Zn is 7 / 4 or more. By using this in the channel formation region, a transistor with high field-effect mobility can be created. can.

[0082] The composition of the metal oxide satisfies line L6, In:M=7:2, as shown in range 13. Alternatively, it is preferable that the indium content is higher than In:M = 7:2. In other words, element M It is preferable that the ratio of the number of indium atoms to the number of atoms of , In / M, is 7 / 2 or greater. By using a metal oxide having the atomic ratio within the aforementioned range in the channel formation region, defect conditions To create a transistor that can suppress the generation of fault zones, is highly reliable, and has high field-effect mobility. It is possible.

[0083] The composition of the metal oxide satisfies line L7, In:Zn=2:3, as shown in range 13. It is preferable that the indium content is higher than In:Zn = 2:3. It is preferable that the ratio of indium atoms to lead atoms (In / Zn) is 2 / 3 or greater. By setting the atomic ratio within the aforementioned range, the formation of polycrystalline metal oxides can be suppressed. By using the metal oxide in the channel formation region, a highly reliable transistor can be produced. It is possible.

[0084] As the metal oxide, an In-M-Zn oxide having a composition included in range 13 is used. This can be done. As an In-M-Zn oxide, for example, In:M:Zn = 5:1:1, In :M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1 :1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn =10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In :M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1 :10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or this These vicinity can be suitably used. In addition, In-M oxide can be used as the metal oxide. It can exist. As an In-M oxide, for example, In:M=2:1, In:M=7: 2. In:M=5:1, In:M=7:1, or a range close to these can be preferably used. In addition, In-Zn oxide can be used as the metal oxide. As examples of chromosomes, for instance, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or neighborhoods of these. This can be used suitably.

[0085] [Composition of metal oxides 3] The metal oxide preferably contains indium, zinc, and oxygen. It may also contain element M. It is suitable for use in the channel formation region of a transistor. The composition of the resulting metal oxide is shown in Figure 2A. The metal oxides are indium, element M, and zinc. The atomic ratio is preferably included within range 15 in the triangular diagram shown in Figure 2A. 5 is coordinate point I (44:11:10), coordinate point J (4:1:6), and coordinate point F (2:0 A polygon formed by connecting point 3), coordinate point K(11:0:2), and the aforementioned coordinate point I with straight lines in this order. This is the interior of [the region]. Note that range 15 also includes each coordinate point and each edge. Composition included in range 15 By using a metal oxide having the properties of the field effect in the channel formation region, a highly reliable and field-effect-resistant material is obtained. This allows for the creation of transistors with high reproductive mobility.

[0086] Here, the coordinate point I(44:11:10) is the set of points satisfying In:M=4:1. The intersection of line L10 and line L11, which is the set of points satisfying (In+M):Zn=11:2 The coordinate point J(4:1:6) is the intersection of the aforementioned line L7 and the aforementioned line L10. K(11:0:2) is the intersection of the aforementioned line L11 and the aforementioned line L8. Regarding coordinate point F... Therefore, since the above information can be found, a detailed explanation will be omitted.

[0087] Edge IJ lies on the aforementioned line L10, edge JF lies on the aforementioned line L7, and edge FK lies on the aforementioned line It lies on line L8, and edge KI lies on the aforementioned line L11. In other words, range 15 is on line L10, line L 7. It can also be said that it is the interior of the polygon enclosed by lines L8 and L11.

[0088] The composition of the metal oxide satisfies line L10, In:M=4:1, as shown in range 15. It is preferable that the In content is higher than In:M = 4:1. In other words, the original content of element M The ratio of the number of indium atoms to the number of electrons, In / M, is preferably 4 or greater. Defect levels are generated by using a metal oxide with a specific atomic ratio in the channel formation region. This allows for the suppression of certain behaviors, resulting in a highly reliable transistor with high field-effect mobility. .

[0089] The composition of the metal oxide satisfies line L7, In:Zn=2:3, as shown in range 15. It is preferable that the indium content is higher than In:Zn = 2:3. It is preferable that the ratio of indium atoms to lead atoms (In / Zn) is 2 / 3 or greater. By setting the atomic ratio within the aforementioned range, the formation of polycrystalline metal oxides can be suppressed. By using the metal oxide in the channel formation region, a highly reliable transistor can be fabricated.

[0090] As shown in Range 15, the composition of the metal oxide is the line L11 where (In + M):Zn = 1 satisfies 1:2 or preferably has a higher zinc content than (In + M):Zn = 11:2. That is, the ratio of the total number of atoms of indium and element M to the number of zinc atoms (In + M) / Zn is preferably 11 / 2 or less. By having zinc in the metal oxide, it tends to have a layered crystal structure. Also, the higher the zinc content, the higher the crystallinity of the metal oxide becomes. An In-M-Zn oxide having a composition included in Range 15 can be used as the metal oxide.

[0091] As the In-M-Zn oxide, for example, In:M:Zn = 5:1:2, In :M:Zn = 5:1:3, In:M:Zn = 5:1:4, In:M:Zn = 5:1:5, In:M:Zn = 5:1:6, In:M:Zn = 10:1:2, In:M:Zn = 10: 1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:5, In:M:Z n = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, I n:M:Zn = 10:1:10, In:M:Zn = 10:1:12, In:M:Zn = 1 0:1:15, or those in the vicinity thereof can be preferably used. Also, as the metal oxide an In-Zn oxide can be used. As the In-Zn oxide, for example, In: Zn = 2:3, In:Zn = 3:2, In:Zn = 7:2, In:Zn = 4:1, In: Zn = 11:2, In:Zn = 7:1, or those in the vicinity thereof can be preferably used. <​​。

[0092] The metal oxide has a composition within the aforementioned range and is preferably CAAC-OS (c-axis Aligned Crystalline Oxide Semiconductor), nc- OS (nanocrystalline oxide semiconductor), or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). Hereinafter, CAC-OS, which is a metal oxide that can be used for a transistor, and CA

[0093] AC-OS will be described.

[0094] 〔Structure of Metal Oxide〕 CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-m<00上記の翻訳では、原文の内容を正確に反映するために、一部の技術用語は原文のまま残してあります。これは、特許文献の翻訳においては一般的な手法で、読み手が正確な技術的意味を理解できるようにするためです。etal oxide is used for the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) that become carriers, and the insulating function is the function of not flowing electrons that become carriers. By causing the conductive function and the insulating function to act complementarily with each other, a switching function (On / Off function) can be imparted to CAC-OS or CAC -metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

[0095] CAC-OS or CAC-metal oxide has a conductive region and an insulating region The conductive region has the conductive function described above, and the insulating region has the insulating function described above. It has the following properties. Furthermore, within the material, the conductive region and the insulating region are separated at the nanoparticle level. They may be separated. Also, conductive regions and insulating regions are unevenly distributed within the material. In some cases, the conductive region may appear as a cloud-like, connected area with a blurred periphery. There is.

[0096] In CAC-OS or CAC-metal oxide, there is a conductive region and an insulating region. The range refers to a range of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The particles may be dispersed within the material depending on their size.

[0097] CAC-OS or CAC-metal oxides have different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxide is Components with a wide gap due to the insulating region and components with a narrow gap due to the conductive region It is composed of a component having a hop and a hop. In this configuration, when the carrier is flowed, narrow In components with gaps, carriers primarily flow. Also, in components with narrow gaps. The component acts complementaryly with the component having a wide gap, and with the component having a narrow gap. In conjunction with this, carriers also flow to components with a wide gap. Therefore, the above CAC-O When using S or CAC-metal oxide in the channel formation region of a transistor. , high current driving force in the on state of the transistor, i.e., large on current, and high electric current You can obtain the field effect mobility.

[0098] In other words, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or a metal matrix composite (metal m atrix composite) can also be referred to as such.

[0099] 〔Structure of Metal Oxide〕 Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-li ke oxide semiconductor), and amorphous oxide semiconductors.

[0100] When focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure in oxide semiconductors will be explained using FIG. 5A. FIG. 5A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn). As shown in FIG. 5A, IGZO is roughly classified into Amorphous, Crysta

[0101] lline, and Crystal. Also, among Amorphous, completely amorphous is included. Also, among Crystalline CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Co mposite) are included. Note that the classification of Crystalline excludes single crystal and poly crystal, which will be described later. Also, Crys In addition, Crystalline excludes single crystal and poly crystal, which will be described later. Also, Crys ngle crystal, and poly crystal are excluded from the classification of Crystalline. Also, Crys Tal contains single crystals and polycrystals. It can be done.

[0102] Note that the structure within the thick frame shown in Figure 5A is the New crystalline phase. It is a structure to which it belongs. This structure is the boundary area between Amorphous and Crystal. It is in the region. That is, the energetically unstable Amorphous and Crystal This can be rephrased as having a completely different structure from ine.

[0103] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using an ion pattern. Here, quartz glass and Cryst X of IGZO (also called crystalline IGZO) which has a crystalline structure classified as alline The RD spectra are shown in Figures 5B and 5C. Figure 5B shows the quartz glass, and Figure 5C shows the crystal. This is the XRD spectrum of crystalline IGZO. Note that the composition of crystalline IGZO shown in Figure 5C is I n:Ga:Zn = 4:2:3 [atomic ratio]. Also, the crystalline IGZO shown in Figure 5C The thickness is 500 nm.

[0104] As shown by the arrow in Figure 5B, the peaks in the XRD spectrum of quartz glass are nearly symmetrical. On the other hand, as shown by the arrow in Figure 5C, crystalline IGZO has a pinpoint XRD spectrum. The peaks are asymmetrical. The asymmetrical peaks in the XRD spectrum indicate that the crystal is Its presence is clearly indicated. In other words, if the peaks in the XRD spectrum are not symmetrical, Am It cannot be said that it is orphosal. Note that Figure 5C shows 2θ = 31° or its vicinity. It is clearly stated that it is a nanocrystal. The peaks in the XRD spectrum are Therefore, it is presumed that the asymmetry is due to the microcrystals in question.

[0105] Specifically, as shown in Figure 5C, crystalline IGZO has a 2θ spectrum in its XRD spectrum. It has a peak at 2θ=34° or near it. Also, the microcrystals have a peak at 2θ=31° or near it. It has a peak nearby. When evaluating oxide semiconductor films using X-ray diffraction patterns, see Figure 5C. As shown, the spectral width at angles lower than the peak at 2θ=34° or nearby is It widens. This is because the oxide semiconductor film has a peak at or near 2θ = 31°. This suggests the presence of microcrystals.

[0106] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, the grid arrangement This refers to the point where the orientation has changed.

[0107] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Furthermore, the distortion may have a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bounds) are present. It is not possible to confirm the grain boundaries (also known as dally). In other words, due to the distortion of the lattice arrangement, the grain boundaries It can be seen that the formation is suppressed. This is because CAAC-OS is in the ab plane direction The arrangement of oxygen atoms is not dense, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by processes such as transformation.

[0108] Furthermore, crystal structures in which clear grain boundaries can be observed are known as multi-grain structures. It is called a polycrystal. The grain boundaries become recombination centers, and carriers A is trapped, causing a decrease in the transistor's on-current or a decrease in its field-effect mobility. It is highly likely. Therefore, CAAC-OS, in which no clear grain boundaries can be identified, is a transistor It is one of the crystalline oxides having a crystal structure suitable for semiconductor layers. A configuration containing Zn is preferred for S. For example, In-Zn oxide and In -Ga-Zn oxide is preferred because it can suppress the generation of grain boundaries more effectively than In oxide.

[0109] CAAC-OS consists of a layer containing indium and oxygen (hereinafter referred to as the In layer), and the element M, sub A layered crystalline structure in which layers containing lead and oxygen (hereinafter referred to as (M,Zn) layers) are stacked (layered It tends to have a structure (also called a structure). Furthermore, indium and element M are mutually substitutable. Furthermore, when the element M in the (M,Zn) layer is replaced with indium, it is represented as the (In,M,Zn) layer. It is also possible that if the indium in the In layer is replaced by element M, the (In,M) layer and the surface It is possible.

[0110] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has a clear Since grain boundaries cannot be identified, a decrease in electron mobility caused by grain boundaries occurs. It can be said that it is difficult. Also, the crystallinity of oxide semiconductors is affected by the inclusion of impurities and the formation of defects. Because it may decrease, CAAC-OS is an oxidation product with fewer impurities and defects (such as oxygen deficiencies). It can also be called a material semiconductor. Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is designed to withstand high temperatures (so-called thermal budgets) in the manufacturing process. It is also stable. Therefore, when using CAAC-OS in OS transistors, the manufacturing process This will allow for greater flexibility.

[0111] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. Also, nc-OS has different na No regularity is observed in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body.

[0112] a-like OS is an oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a semiconductor. an a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0113] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and n It may have two or more types of c-OS and CAAC-OS.

[0114] [Transistors containing oxide semiconductors] Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0115] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility is obtained. This can be achieved. Furthermore, highly reliable transistors can be realized.

[0116] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. When lowering the carrier concentration of a semiconductor film, the impurity concentration in the oxide semiconductor film is reduced. Therefore, it is sufficient to lower the defect level density. In this specification, the impurity concentration is low and the defect level A low particle density is referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0117] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density. In some cases, the trap level density may also be low.

[0118] Charges trapped in the trap levels of oxide semiconductors take a long time to disappear. It can sometimes behave as if it were a fixed charge. Therefore, oxidation with a high trap level density In transistors where a channel formation region is formed in a semiconductor material, the electrical characteristics become unstable. There is.

[0119] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is Reducing it is effective. Furthermore, in order to reduce the impurity concentration in oxide semiconductors, It is also preferable to reduce the concentration of impurities in the adjacent membrane. Examples of impurities include hydrogen, nitrogen, and aluminum. Examples include potash metals, alkaline earth metals, iron, nickel, and silicon.

[0120] 〔impurities〕 Here, we will explain the effects of various impurities in oxide semiconductors.

[0121] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, oxidation occurs. Defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 atoms / cm or less, preferably 2×10 atoms / cm or less. The concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 atoms / cm or less, preferably 2×10 atoms / cm or less. (SIMS:Secondary Ion Mass Spectrometry) The concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 atoms / cm or less, preferably 2×10 atoms / cm or less. 18 atoms / cm 3 The concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 atoms / cm or less, preferably 2×10 atoms / cm or less. 17 a toms / cm 3 The concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 atoms / cm or less, preferably 2×10 atoms / cm or less.

[0122] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 atoms / cm or less, preferably 2×10 atoms / cm or less. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 atoms / cm or less, preferably 2×10 atoms / cm or less. 18 atoms / cm 3 Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 atoms / cm or less, preferably 2×10 atoms / cm or less. 16 atoms / cm 3 Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 atoms / cm or less, preferably 2×10 atoms / cm or less.

[0123] When nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 atoms / cm in SIMS, preferably 5×10 atoms / cm or less. When nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 atoms / cm in SIMS, preferably 5×10 atoms / cm or less. When nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 atoms / cm in SIMS, preferably 5×10 atoms / cm or less. When nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 atoms / cm in SIMS, preferably 5×10 atoms / cm or less. When nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 atoms / cm in SIMS, preferably 5×10 atoms / cm or less. 19 atoms / cm 3 When nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 atoms / cm in SIMS, preferably 5×10 atoms / cm or less.18 a toms / cm 3 More preferably 1 × 10 18 atoms / cm 3 Below, further better Mashikuha 5 x 10 17 atoms / cm 3 The following applies:

[0124] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, so acid In some cases, an elementary defect may form. When hydrogen enters this oxygen defect, an electron, which acts as a carrier, is produced. This can occur. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, forming a carrier. It can generate electrons. Therefore, using an oxide semiconductor containing hydrogen... Lampistors tend to exhibit normally-on characteristics. Therefore, hydrogen in oxide semiconductors is formed. It is preferable that it be reduced as much as possible. Specifically, in oxide semiconductors, SIMS The hydrogen concentration obtained is 1 × 10 20 atoms / cm 3 Less than 1 × 10 1 9 atoms / cm 3 Less than 5x10 18 atoms / cm 3 less than, further Preferably 1 × 10 18 atoms / cm 3 Less than.

[0125] Using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor. This allows for the provision of stable electrical characteristics.

[0126] [Composition of metal oxides 4] The metal oxide preferably contains indium, zinc, and oxygen. It may also contain element M. It is suitable for use in the channel formation region of a transistor. The composition of the resulting metal oxide is shown in Figure 2B. The metal oxides are indium, element M, and zinc. The atomic ratio is preferably included in range 17 in the triangular diagram shown in Figure 2B. 7 is coordinate point I (44:11:10), coordinate point L (4:1:4), and coordinate point M (1:0 A polygon formed by connecting point 1), coordinate point K(11:0:2), and the aforementioned coordinate point I with straight lines in this order. This is the interior of [the region]. Note that range 17 also includes each coordinate point and each edge. Composition included in range 17 By using a metal oxide having the properties of the field effect in the channel formation region, a highly reliable and field-effect-resistant material is obtained. This allows for the creation of transistors with high reproductive mobility.

[0127] Here, the coordinate point L(4:1:4) satisfies the ratio In:Zn=1:1 with the aforementioned line L10. It is the intersection point of line L12, which is a set of points. The coordinate point M(1:0:1) is the same as the aforementioned line L12, This is the intersection point of the aforementioned line L8. For coordinate points I and K, please refer to the previously mentioned description. Therefore, a detailed explanation will be omitted.

[0128] Edge IL lies on the aforementioned line L10, edge LM lies on the aforementioned line L12, and edge MK lies on the aforementioned line It lies on line L8, and edge KI lies on the aforementioned line L11. In other words, range 17 is on line L10, line It can also be said that it is the interior of a polygon enclosed by lines L12, L8, and L11.

[0129] The composition of the metal oxide satisfies line L10, In:M=4:1, as shown in range 17. It is preferable that the In content is higher than In:M = 4:1. In other words, the original content of element M The ratio of the number of indium atoms to the number of electrons, In / M, is preferably 4 or greater. Defect levels are generated by using a metal oxide with a specific atomic ratio in the channel formation region. This allows for the suppression of certain behaviors, resulting in a highly reliable transistor with high field-effect mobility. .

[0130] The composition of the metal oxide satisfies line L12, In:Zn=1:1, as shown in range 17. It is preferable that the indium content is higher than In:Zn = 1:1. It is preferable that the ratio of indium atoms to zinc atoms (In / Zn) is 1 or greater. By setting the atomic ratio within the aforementioned range, the formation of polycrystalline metal oxides can be suppressed. Since the oxides are less likely to form polycrystalline structures, the margin for the conditions required for metal oxide formation can be widened. Furthermore, by using the metal oxide in the channel formation region, a highly reliable tunnel can be formed. It can be used as a generator.

[0131] The composition of the metal oxide is as shown in range 17, line L11 (In+M):Zn=1 It is preferable that the ratio satisfies 1:2, or that the zinc content is higher than (In+M):Zn=11:2. In other words, the ratio of the total number of atoms of indium and element M to the number of zinc atoms (In+M) It is preferable that the Zn content is 1 1 / 2 or less. It has high crystallinity. Furthermore, by using this metal oxide in the channel-forming region, This allows for the creation of highly reliable transistors.

[0132] As the metal oxide, an In-M-Zn oxide having a composition within range 17 is used. This can be done. As an In-M-Zn oxide, for example, In:M:Zn=5:1:2, In :M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10 :1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M: Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10 , or their vicinity can be suitably used as metal oxides. n oxides can be used. For example, as an in-Zn oxide, In:Zn = 2:3 , In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11: 2. In:Zn = 7:1, or a ratio close to these, can be preferably used.

[0133] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0134] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0135] (Embodiment 2) In this embodiment, the configuration example of a semiconductor device to which the metal oxide shown in Embodiment 1 is applied is as follows: I will explain this further. Below, I will use a transistor as an example.

[0136] <Configuration Example 1> [Configuration Example 1-1] Figure 6A shows a schematic cross-sectional view of a transistor 10 in the channel length direction, which is one embodiment of the present invention. vinegar.

[0137] The transistor 10 consists of a conductive layer 104, an insulating layer 106, a semiconductor layer 108, and a conductive layer 1 It has 12a and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. A portion of the margin layer 106 functions as a gate insulating layer. The conductive layer 112a is also the source electrode. One of the semiconductor layers functions as one drain electrode, and the conductive layer 112b functions as the other. The region of 08 that overlaps with the conductive layer 104 functions as a channel formation region. Transistor 1 0 is a so-called bottom-gate type transistor, having the gate electrode below the semiconductor layer 108. He is a genista.

[0138] The conductive layer 112a, the conductive layer 112b, and the semiconductor layer 108 are covered by the insulating layer 114, insulating layer 1 16 and insulating layer 118 are provided. insulating layer 114, insulating layer 116 and insulating layer 118 Each of these functions as a protective layer.

[0139] If a conductive film containing a metal or alloy is used as the conductive layer 104, electrical resistance can be suppressed. Therefore, it is preferable. In particular, it is preferable to use a conductive material containing copper as the conductive layer 104. An oxide film may also be used for the conductive layer 104.

[0140] It is preferable to use an oxide film as the insulating layer 106. In particular, the film that is in contact with the semiconductor layer 108 It is preferable to use an oxide film in the relevant portion.

[0141] The insulating layer 106 preferably has a high dielectric strength. This allows for the creation of highly reliable transistors.

[0142] It is preferable that the insulating layer 106 has low stress. This suppresses the occurrence of problems during the manufacturing process caused by stress, such as warping of the substrate.

[0143] The insulating layer 106 contains impurities such as water, hydrogen, and sodium on the surface of the insulating layer 106. As a barrier film that suppresses diffusion from a component (such as a substrate) to the transistor 10 It is preferable that it functions. Also, the insulating layer 106 has components of the conductive layer 104 that are transistor 1 It is preferable that it functions as a barrier film that suppresses diffusion to 0. By functioning as a barrier film that suppresses the diffusion of pure substances, it exhibits good electrical properties. Furthermore, it can be made into a highly reliable transistor.

[0144] Furthermore, it is preferable that the insulating layer 106 releases little impurities such as water and hydrogen from itself. It is good. Due to the low release of impurities from the insulating layer 106, the impurities are less likely to be released from the transistor 10 Diffusion to the side is suppressed, exhibiting good electrical characteristics and resulting in a highly reliable transistor. It is possible.

[0145] Furthermore, the insulating layer 106 functions as a barrier film that suppresses the diffusion of oxygen. This is preferable. The insulating layer 106 has the function of suppressing the diffusion of oxygen, so that oxygen is insulating Diffusion from above layer 106 to conductive layer 104 is suppressed, and the conductive layer 104 is oxidized. This can suppress the process. As a result, it produces transistors that exhibit good electrical characteristics and are highly reliable. It can be done this way.

[0146] Figure 6A shows that the insulating layer 106 is connected to the insulating layer 106a and the insulating layer 106b on top of the insulating layer 106a. This shows a layered structure. For example, an insulating layer located on the side of the insulating layer 106 that is to be formed. A nitride film is used for 106a, and an oxide film is used for the insulating layer 106b that is in contact with the semiconductor layer 108. It is possible.

[0147] The insulating layer 106a preferably has a high dielectric strength. This makes it possible to create a highly reliable transistor.

[0148] It is preferable that the insulating layer 106a has low stress. This makes it possible to suppress the occurrence of problems during the manufacturing process caused by stress, such as warping of the substrate.

[0149] Insulating layer 106a contains impurities such as water, hydrogen, and sodium on the surface side of insulating layer 106. A barrier film that suppresses diffusion from the component (e.g., a substrate) to the transistor 10. It is preferable that it functions in this way. Also, the insulating layer 106 has components of the conductive layer 104 that are transistor It is preferable that the insulating layer 106 functions as a barrier film that suppresses diffusion to 10. By having the function of suppressing the diffusion of impurities, it exhibits good electrical characteristics and reliability. It can be made into a high-performance transistor.

[0150] Furthermore, it is preferable that the insulating layer 106a releases little impurities such as water and hydrogen from itself. It seems that the release of impurities from the insulating layer 106a is small, and the impurities are less likely to be released into the transistor. Diffusion to the 10 side is suppressed, exhibiting good electrical characteristics and reliable transistors. It can be written as "ta".

[0151] Furthermore, the insulating layer 106a functions as a barrier film that suppresses the diffusion of oxygen. This is preferable. The insulating layer 106a has the function of suppressing the diffusion of oxygen, so that oxygen Diffusion from above the insulating layer 106a to the conductive layer 104 is suppressed, and the conductive layer 104 is acidic. This suppresses the process of transformation. As a result, it exhibits good electrical characteristics and is a highly reliable transistor. It can be made into a zista.

[0152] For example, the insulating layer 106a can be aluminum oxide, aluminum oxide nitride, or HA5 oxide. nium, hafnium oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, acid Oxide films such as yttrium nitride, silicon nitride, silicon oxide nitride, aluminum nitride A nitride film such as aluminum oxide nitride can be used. The insulating layer 106a is Therefore, silicon nitride can be used particularly suitably.

[0153] The insulating layer 106b has a region that is in contact with the channel formation region of the semiconductor layer 108. 106b preferably has a low defect density. Furthermore, the insulating layer 106b is protected from water, It is preferable that the release of hydrogen-containing impurities such as hydrogen is kept to a minimum. As the insulating layer 106b, Oxide films such as silicon oxide and silicon oxide nitride can be suitably used.

[0154] As shown in Figure 6A, by making the insulating layer 106 a laminated structure, good electrical characteristics are exhibited. Furthermore, it can be made into a highly reliable transistor.

[0155] A nitride film is formed as the insulating layer 106a, and then oxygen is added to the top of the insulating layer 106a. This may form an oxygen-containing region, and this oxygen-containing region may be used as the insulating layer 106b. As a process of adding oxygen, for example, heat treatment or plasma in an oxygen-containing atmosphere These include treatments such as ion doping and other similar processes.

[0156] In this specification, an oxidized nitride is defined as a compound in which the oxygen content is greater than the nitrogen content. It refers to substances that are abundant in oxygen, and oxidized nitrides are included in oxides. Nitrided oxides are substances whose composition is such that oxygen is abundant in them. This refers to substances with a high nitrogen content, and nitride oxides are included in nitrides.

[0157] Note that Figure 6A shows a two-layer structure of insulating layer 106, consisting of insulating layer 106a and insulating layer 106b. As shown, the present invention is not limited to this embodiment. The insulating layer 106 may have a single-layer structure. Furthermore, it may have a laminated structure of three or more layers. Also, the insulating layer 106a and insulating layer 106b Each may have a laminated structure of two or more layers.

[0158] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. It is composed of the following. The semiconductor layer 108 uses a metal oxide having the composition shown in Embodiment 1. It is preferable to use the metal oxide in the channel-forming region, which improves reliability. Furthermore, it is possible to create a transistor with high field-effect mobility.

[0159] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, CAAC (c-axis aligned crystal) structure, polycrystalline structure, which will be described later. Metal oxide films having a microcrystalline (nc) structure, etc., can be used. By using a gen oxide film in the semiconductor layer 108, the defect level density in the semiconductor layer 108 is reduced. This reduces the amount of material used, enabling the creation of highly reliable semiconductor devices.

[0160] The higher the crystallinity of the semiconductor layer 108, the lower the defect level density in the film. On the other hand, By using a metal oxide film with low crystallinity, transistors can conduct large currents. This can be achieved.

[0161] When forming a metal oxide film by sputtering, the substrate temperature (stage temperature) during formation is important. The higher the degree, the more crystalline the metal oxide film that can be formed. Also, the more... The higher the ratio of the oxygen gas flow rate to the total film-forming gas (also called the oxygen flow rate ratio), the better the film formation. It is possible to form a metal oxide film with high crystallinity.

[0162] The semiconductor layer 108 consists of semiconductor layer 108a and semiconductor layer 108b on top of semiconductor layer 108a. It is preferable to have a layered structure. The semiconductor layer 108a and the semiconductor layer 108b are each made of metal It is preferable that it contains an oxide. ) may not be clearly visible. Therefore, in the drawings illustrating one embodiment of the present invention, The boundary between them is shown by a dashed line. Semiconductor layer 108a and semiconductor layer 108b are respectively implemented It is preferable to use the metal oxide film shown in Form 1.

[0163] The semiconductor layer 108b located on the back channel side is the semiconductor layer located on the conductive layer 104 side. It is preferable that the semiconductor layer 108b has a region with higher crystallinity than 108a. By having a high region, when forming conductive layer 112a and conductive layer 112b, semiconductor This prevents a portion of layer 108 from being etched and disappearing. Furthermore, the semiconductor layer When cleaning the surface of 108, damage to the semiconductor layer 108 can be suppressed. .

[0164] Semiconductor layer 108a and semiconductor layer 108b can be fabricated, for example, by using different formation conditions. It can be separated. For example, semiconductor layer 108a and semiconductor layer 108b in the deposition gas The flow rate of oxygen gas can be varied.

[0165] At this time, the formation conditions for the semiconductor layer 108a are as follows: The ratio (also called the oxygen flow rate ratio or oxygen partial pressure) is preferably 0% or more and less than 50%, and more preferably 5 A concentration of % or more and 30% or less is preferred, and more preferably 5% or more and 20% or less. The aforementioned oxygen flow rate By using this ratio, the crystallinity of the semiconductor layer 108a can be reduced.

[0166] On the other hand, for the formation conditions of the semiconductor layer 108b, an oxygen flow rate ratio of 50% to 100% is preferable. Preferably between 60% and 100%, and even more preferably between 70% and 100%. Preferably, the oxygen flow rate ratio is 80% or more and 100% or less. This allows for increased crystallinity of the semiconductor layer 108b.

[0167] When the semiconductor layer 108 has a stacked structure, the same sputtering target is used and the same process It is preferable to continuously form the layers in the laboratory because it allows for a good interface. In particular, each The conditions for forming the metal oxide film may vary, including the pressure, temperature, and power during formation. However, by keeping all conditions except the oxygen flow rate ratio the same, the time required for the formation process can be shortened. Preferably, a laminated structure of metal oxide films with different compositions can be used as the semiconductor layer 108. It is also possible to laminate metal oxide films of different compositions without exposure to the atmosphere. It is preferable to form them in succession.

[0168] The substrate temperature during the formation of the semiconductor layer 108 is preferably between room temperature (25°C) and 200°C. A temperature between room temperature and 130°C is more preferable. By keeping the substrate temperature within the aforementioned range, large-area gas can be processed. When using a lath substrate, the bending or distortion of the substrate can be suppressed. The semiconductor layer 108 is stacked in a laminated structure. If the semiconductor layer 108a and semiconductor layer 108b are constructed at the same substrate temperature, This can increase productivity. Also, the substrate temperature between semiconductor layer 108a and semiconductor layer 108b If the temperature is different, the temperature at which semiconductor layer 108b is formed should be higher than the substrate temperature at which semiconductor layer 108a is formed. It is preferable to increase the substrate temperature. Therefore, the crystallinity of semiconductor layer 108b can be increased compared to the crystallinity of semiconductor layer 108a. In this specification, room temperature includes the temperature when the substrate is not heated.

[0169] For example, the semiconductor layer 108a contains CAC-OS (Cloud-Aligned Compo A site oxide semiconductor film is used, and C is placed in the semiconductor layer 108b. AAC-OS(c-axis-aligned crystalline oxide It is preferable to use a semiconductor film.

[0170] The crystallinity of semiconductor layer 108a and semiconductor layer 108b is determined, for example, by X-ray diffraction (XRD:X- Ray Diffraction, Transmission Electron Microscope (TEM) (on Electron Microscope), electron diffraction (ED: Electro This can be analyzed using methods such as n-diffraction.

[0171] The thickness of the semiconductor layer 108a is preferably 1 nm to 50 nm, and more preferably 5 nm or more. A wavelength of 30 nm or less is preferred, and more preferably 5 nm to 20 nm. The thickness of 108b is preferably 1 nm to 50 nm, and more preferably 5 nm to 30 nm. The lower value is preferable, and more preferably 5 nm to 20 nm.

[0172] Here, we will explain the oxygen vacancies that may be formed in the semiconductor layer 108.

[0173] When semiconductor layer 108 contains an oxide semiconductor, in particular, the hydrogen contained in the oxide semiconductor is metallic It reacts with oxygen that bonds to atoms to form water, creating oxygen vacancies (V) in the oxide semiconductor. O :Oxyge In some cases, a vacancy may form. Furthermore, a defect in which hydrogen enters the oxygen vacancy may form. Bottom, V O H acts as a donor, and can generate electrons, which are carriers. Furthermore, some of the hydrogen combines with oxygen, which is bonded to a metal atom, to generate electrons, which are carriers. This can happen. Therefore, transistors using oxide semiconductors that contain a lot of hydrogen are It tends to exhibit normally-on characteristics. Also, hydrogen in oxide semiconductors is susceptible to heat, electric fields, etc. Because it is more flexible due to the presence of hydrogen, when oxide semiconductors contain a lot of hydrogen, the transistor This could also lead to a decline in reliability.

[0174] V O H can function as a donor in oxide semiconductors. However, quantitatively determining the defect is difficult. It is difficult to evaluate this. Therefore, in oxide semiconductors, instead of donor concentration, In some cases, it is evaluated by carrier concentration. Therefore, in this specification, the parameters of oxide semiconductors are used. As the data, we use the carrier concentration assuming a state where no electric field is applied, rather than the donor concentration. In some cases, the "carrier concentration" described in this specification, etc., is equivalent to the "donor concentration." It may be possible to replace it.

[0175] Based on the above, when an oxide semiconductor is used for the semiconductor layer 108, V in the semiconductor layer 108 O H It is preferable to reduce it as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. sea ​​urchin, V OTo obtain an oxide semiconductor with sufficiently reduced H content, water, hydrogen, etc. in the oxide semiconductor are needed. The removal of impurities (sometimes referred to as dehydration and dehydrogenation treatment) and oxide semiconductors The process of supplying oxygen to the body to compensate for oxygen deficiency (sometimes referred to as oxygenation treatment) It is important. V O Oxide semiconductors with sufficiently reduced impurities such as H are used in transistors. By using it in the flannel formation region, stable electrical properties can be imparted.

[0176] When an oxide semiconductor is used for semiconductor layer 108, the region that functions as a channel formation region The carrier concentration of an oxide semiconductor is 1 × 10⁻⁶ 18 cm -3 The following is preferable, 1× 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 Less than More preferably, 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 1 2 cm -3 It is even more preferable that it be less than [a certain value]. Furthermore, the region that functions as a channel-forming region... There are no particular limitations on the lower limit of the carrier concentration of oxide semiconductors in the region, but for example, 1× 10 -9 cm -3 It can be done this way.

[0177] The insulating layer 114 and the insulating layer 116 function as protective films for the transistor 10. Furthermore, the insulating layer 114 and the insulating layer 116 have the function of supplying oxygen to the semiconductor layer 108. .

[0178] Backcharging from insulating layer 114 and insulating layer 116 to semiconductor layer 108, particularly semiconductor layer 108 By supplying oxygen to the Nell side, V in semiconductor layer 108 O and V O H can be reduced This makes it possible to realize highly reliable transistors. By supplying oxygen to the semiconductor layer 108 Other treatments include heat treatment in an oxygen-containing atmosphere, or under an oxygen-containing atmosphere. This includes plasma treatment, among other things.

[0179] When conductive layers 112a and 112b use a conductive film containing a metal or alloy, electrical This is preferable because it suppresses resistance. In particular, it contains copper as the conductive layer 112a and conductive layer 112b. It is preferable to use an oxidizing conductive material. A physical film may also be used.

[0180] In Figure 6A, conductive layers 112a and 112b are arranged in order from the side of the surface to be formed, An example having a laminated structure in which an electrical layer 113a, a conductive layer 113b, and a conductive layer 113c are laminated. It is showing.

[0181] It is preferable to use a low-resistance conductive material for the conductive layer 113b. Each conductive layer 113c can independently use a different conductive material than conductive layer 113b. Yes, it is possible. By sandwiching conductive layer 113b between conductive layer 113a and conductive layer 113c, conductive The surface of layer 113b is oxidized, and the components of the conductive layer 113b diffuse into the surrounding layers. This can be suppressed. With this configuration, conductive layer 112a and conductive layer 112b It can be made to have extremely low resistance.

[0182] In conductive layers 112a and 112b, the uppermost conductive layer 113c is Materials that are less likely to bond with oxygen than conductive films containing copper or aluminum, or even when oxidized. It is preferable to include a material that is less likely to lose its conductivity. Also, the conductive material in contact with the semiconductor layer 108 is preferable. It is preferable to use a material for layer 113a that does not easily allow oxygen in the semiconductor layer 108 to diffuse. The uppermost conductive layer 113c and the conductive layer 113a in contact with the semiconductor layer are, for example, Titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, Alternatively, conductive materials containing ruthenium, etc., can be used. Conductive layer 113a and conductive layer 113c can use the same conductive material. Also, conductive layer 113a and conductive layer 1 13c may be made of a different conductive material.

[0183] It is preferable to perform a cleaning process before forming the insulating layer 114 on the semiconductor layer 108. By performing the purification process, water, hydrogen, organic components, etc. adsorbed on the surface of the semiconductor layer 108 are removed. It is possible to do so. As a cleaning method, wet cleaning using a cleaning solution, heat treatment, or p This includes cleaning using plasma treatment with a rasma. Furthermore, the aforementioned cleaning methods can be combined as appropriate. You can go.

[0184] The heat treatment is preferably carried out in an atmosphere containing an oxidizing gas or in a reduced-pressure atmosphere. Oxidizing gases are gases that possess oxidizing power. Examples of oxidizing gases include oxygen (O2). Ozone (O3), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2) Gases containing oxygen, such as ), can be used. Heat treatment can be performed, for example, in an oxygen gas atmosphere. Therefore, it can be carried out at a temperature between 70°C and 200°C.

[0185] Plasma treatment is preferably carried out in an atmosphere containing an oxidizing gas. By performing plasma treatment in a suitable atmosphere, organic matter on the surface of the semiconductor layer 108 can be effectively removed. Furthermore, after the plasma treatment, the surface of the semiconductor layer 108 is continuously treated without being exposed to the atmosphere. It is preferable to form the insulating layer 114 in a manner that is continuous with the plasma treatment. This prevents impurities from adhering to the interface between the semiconductor layer 108 and the insulating layer 114. can.

[0186] Furthermore, the aforementioned cleaning process oxidizes conductive layers 112a and 112b, resulting in increased resistance. This can negatively affect the electrical characteristics and reliability of the transistor. Therefore, as a cleaning treatment, a plasma is used with a mixed gas containing an oxidizing gas and a reducing gas. It is particularly preferable to perform the treatment. The aforementioned gases can be used as the oxidizing gas. A reducing gas refers to a gas that has reducing power. Examples of reducing gases include ammonia (NH3). ), hydrogen-containing gases such as hydrogen (H2), or carbon monoxide (CO) can be used. For example, a mixture containing nitrous oxide, which is an oxidizing gas, and ammonia, which is a reducing gas. By performing plasma treatment in a mixed gas atmosphere, conductive layers 112a and 112b In addition to suppressing oxidation, it effectively removes water and hydrogen adsorbed on the surface of the semiconductor layer 108. It can remove organic components, etc.

[0187] In plasma processing, the flow rate of reducing gas should be 0.005 times or less compared to the flow rate of oxidizing gas. Preferably, it is 1x or less, more preferably 0.01x or more and 0.9x or less, and even more preferably 0. A ratio of 0.2 times or more and 0.8 times or less is preferable, and even more preferably 0.03 times or more and 0.6 times or less. Furthermore, a ratio of 0.03 times or more and 0.5 times or less is preferable.

[0188] As a mixed gas used in plasma treatment, in addition to oxidizing gases and reducing gases, argon is also used. Any mixed gas containing any noble gas may be used.

[0189] The insulating layer 114 in contact with the semiconductor layer 108 is subjected to nitrogen oxides (NOx) when heat is applied. x , It is preferable that the emission of nitrogen oxides (where x is greater than 0 and less than or equal to 2) is small. Nitrogen oxides are, for example, N Examples include O2 or NO.

[0190] Nitrogen oxides form energy levels in the insulating layer 114, etc. These energy levels are located in the semiconductor layer 108. It is located within the energy gap. Therefore, nitrogen oxides are located between the insulating layer 114 and the semiconductor layer 10 When it diffuses to the interface of 8, the energy level may trap electrons on the insulating layer 114 side. As a result, the trapped electrons remain near the interface between the insulating layer 114 and the semiconductor layer 108. Therefore, the transistor's threshold voltage fluctuates in the positive direction.

[0191] Here, it is preferable that the insulating layer 114 releases a large amount of ammonia. Nitrogen oxides are heat When added, it reacts with ammonia and oxygen and decomposes. Nitrogen contained in the insulating layer 114 When heat is applied, the ammonia contained in insulating layers 114 and 116 is released from the oxide. Because it reacts with the insulating layer 114, the nitrogen oxides contained in the insulating layer 114 are reduced. Electrons are less likely to be trapped at the interface between layer 14 and semiconductor layer 108.

[0192] As the insulating layer 114, a film that releases a lot of ammonia and little nitrogen oxides is used. This suppresses fluctuations in the transistor's threshold voltage, thus improving the transistor's electrical characteristics. This can reduce fluctuations.

[0193] The insulating layer 114 is an oxide film such as a silicon oxide film or a silicon oxide nitride film. This is called a plasma chemical vapor deposition (PECVD) apparatus, or simply a plasma CVD apparatus. It is preferable to form it using a silicon depositing gas. In this case, the raw material gas is a silicon depositing gas. It is preferable to use a mixed gas containing gas, an oxidizing gas, and ammonia gas. By forming the insulating layer 114 using a mixed gas containing agas, the release of ammonia is achieved. A large insulating layer 114 can be made. As a silicon-containing depositing gas, for example, silamine Disilane, trisilane, and silane fluoride can be used as oxidizing gases. The following gases can be used.

[0194] The proportion of each gas in the mixed gas is supplied to the processing chamber of the plasma chemical vapor deposition apparatus. It can be controlled by controlling the gas flow rate. The ratio of each gas in the gas mixture is For example, it can be expressed as a volume ratio, partial pressure ratio, or weight ratio. Here, in the processing chamber The flow rate ratio of the supplied gases roughly corresponds to the volume ratio and partial pressure ratio of the gases.

[0195] When plasma treatment is performed as a cleaning treatment before the formation of the aforementioned insulating layer 114, It is possible to use the same gas for both the processing and the formation of the insulating layer 114. In plasma treatment, a mixed gas containing a first oxidizing gas and a reducing gas is used. In forming the insulating layer 114, a second oxidizing gas, ammonia gas, and silicon are included. A first sedimentation gas mixture is used. Here, the first oxidizing gas and the second oxidizing gas Using the same type of gas, and using ammonia gas as the reducing gas, plasma processing Furthermore, in the formation of the insulating layer 114, the use of both an oxidizing gas and ammonia gas is permitted. Yes, it's possible. By using a common gas, the number of gases used in transistor fabrication can be reduced. It is possible.

[0196] When performing plasma processing and forming the insulating layer 114 using a plasma chemical vapor deposition apparatus. Let's use this as an example to explain. Here, the insulating layer 114 is silicon oxidnitride.

[0197] In plasma processing, nitrous oxide (N2O), an oxidizing gas, and a reducing gas are used. Using a mixed gas containing a certain ammonia, in the formation of the insulating layer 114, the depositing gas is A mixed gas containing monosilane, the oxidizing gas nitrous oxide (N2O), and ammonia. A solution can be used. Here, in the plasma treatment and the formation of the insulating layer 114, dinitrate monoxide can be used. Nitrous oxide (N2O) and ammonia can be used in common. That is, dinitrogen monoxide (N2O) Plasma treatment is performed using 2O) and ammonia, followed by the flow of monosilane gas. This allows for the formation of an insulating layer 114. In this way, plasma processing and Because the insulating layer 114 can be formed, the interface between the semiconductor layer 108 and the insulating layer 114 This reduces the amount of pure substances and allows for a good interface.

[0198] In the formation of the insulating layer 114, the flow rate of the oxidizing gas is 20 times that of the depositing gas. Preferably, the ratio is 200 times or less, and more preferably 30 times or more and 150 times or less, and further A dilution ratio of 40 times or more and 100 times or less is preferable, and more preferably 40 times or more and 80 times or less.

[0199] In the formation of the insulating layer 114, the flow rate of ammonia gas is less than or equal to the flow rate of the oxidizing gas. Preferably, the flow rate of ammonia gas should be 0.01 times or more and 1 time compared to the flow rate of oxidizing gas. The following are preferred, more preferably 0.02 times or more and 0.9 times or less, and more preferably 0.03 times Preferably, it is 0.8 times or less, more preferably 0.04 times or more and 0.6 times or less, and further It is preferable that the ratio is 0.05 times or more and 0.5 times or less. By using the gas flow rate described above, the ammonia This allows for an insulating layer 114 with high emission rates, and reduces the emission of nitrogen oxides from the insulating layer 114. This allows for a transistor with smaller threshold voltage fluctuations. By using the gas flow rate described above, even when the pressure inside the processing chamber is relatively high, fewer defects can be produced. An insulating layer 114 can be formed. Note that the conditions under which the insulating layer 114 is formed, for example, pressure Alternatively, the preferred flow rate of ammonia gas relative to the flow rate of oxidizing gas may differ depending on the power. There are cases where this happens.

[0200] The pressure inside the processing chamber during the formation of the insulating layer 114 is preferably 200 Pa or less, and more preferably 150 Pa. Preferably Pa or less, more preferably 120 Pa or less, and even more preferably 100 Pa or less. It seems that by keeping the pressure within the aforementioned range, the emission of nitrogen oxides will be reduced, and the amount of defects will be reduced. An insulating layer 114 can be formed.

[0201] Furthermore, insulating layers that release a lot of ammonia and little nitrogen oxides are subject to temperature-induced desorption gas Thermal Desorption Spectroscopy (TDS) In this context, a membrane that releases more ammonia than nitrogen oxides is a typical example. The amount of munonia released is 1 × 10 18 / cm3 The above 5 x 10 19 / cm 3 The following applies. The amount of ammonia released depends on the film surface temperature being between 50°C and 650°C, preferably above 50°C. The emission amount is defined as the amount emitted at temperatures below 550°C.

[0202] The insulating layer 114 preferably has a low defect density. If the value is high, oxygen will bind to the defect, reducing the oxygen permeability in the insulating layer 114. By using an insulating layer 114 with a low defect density, the fluctuation of the threshold voltage is small. This allows for the creation of a transistor with excellent electrical characteristics. For example, the insulating layer 114 is used. When using an insulating film containing silicon, in ESR measurement, the dangling bore of silicon The spin density of the signal appearing at g=2.001 originating from the r is 3 × 10 17 spins / c m 3 The following is preferable:

[0203] Since the insulating layer 114 is formed on the semiconductor layer 108, damage to the semiconductor layer 108 is minimal. It is preferable that the film is formed under conditions that do not involve certain factors. For example, the deposition rate (also called the deposition rate) ) can be formed under sufficiently slow conditions. For example, by plasma CVD, an insulating layer 1 When forming 14, forming it under low power conditions will reduce the damage to the semiconductor layer 108. The size can be made extremely small.

[0204] The insulating layer 116 preferably uses an oxide film, and contains an excess of oxygen in the stoichiometric composition. It is more preferable to have a region containing [the substance]. In other words, the insulating layer 116 releases oxygen. It has an insulating film that allows for the following: For example, forming the insulating layer 116 in an oxygen atmosphere. The formed insulating layer 116 is subjected to heat treatment or plasma treatment in an oxygen atmosphere. Alternatively, by forming an oxide film on the insulating layer 116 in an oxygen atmosphere, It can also supply oxygen. Furthermore, the insulating layer 116 releases oxygen molecules in TDS. Discharge volume 1.0 × 10 19 molecular / cm² 3 Preferably 3.0 × 10 20 molecular / cm² 3 It has the above range. Furthermore, the amount of oxygen released as described above is TDS The heat treatment temperature in the process is between 50°C and 650°C, or within the range of 50°C and 550°C. This is the total amount within the enclosure.

[0205] The insulating layer 116 preferably has a low defect density, and typically, ESR measurement can be used to determine this. The spin density of the signal appearing at g=2.001, which originates from the dangling bond of Ricon, is 1. 5 x 10 18 spins / cm 3 Less than, and even 1 × 10 18 spins / cm 3 Below It is preferable that there be an insulating layer 116 compared to the insulating layer 114 and the semiconductor layer 108. Because they are far apart, the defect density can be higher than that of the insulating layer 114.

[0206] For example, the insulating layer 114 and insulating layer 116 may be a silicon oxide film or a silicon oxide-nitride film. silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, Zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, ranyl oxide An insulating layer containing one or more of the following can be used: a tan film, a cerium oxide film, and a neodymium oxide film. ru.

[0207] Since insulating layers 114 and 116 can use insulating films of the same material, In some cases, the interface between the margin layer 114 and the insulating layer 116 cannot be clearly identified. Therefore, in this implementation... In this configuration, the boundary (interface) between the insulating layer 114 and the insulating layer 116 cannot be clearly identified. There is a correspondence. Therefore, in the drawings illustrating one embodiment of the present invention, these boundaries are shown with dashed lines. In this embodiment, the two-layer structure of insulating layer 114 and insulating layer 116 will be described. As stated above, the present invention is not limited to this. For example, a single-layer structure of the insulating layer 114, It may also be a laminated structure of three or more layers.

[0208] After forming the insulating layer 114, the surface of the insulating layer 114 is continuously exposed to the atmosphere. It is preferable to form an insulating layer 116. By forming this layer, the adhesion of impurities to the interface between insulating layer 114 and insulating layer 116 is suppressed. can.

[0209] The gas used to form the insulating layer 114 and the gas used to form the insulating layer 116 are common. A gas can be used.

[0210] In forming the insulating layer 114, a second oxidizing gas, ammonia gas, and silicon are included. Using a mixed gas containing a first depositing gas, in the formation of the insulating layer 116, a third oxidizing gas A mixed gas containing a gas and a second depositing gas containing silicon is used. Here, the second acid The same type of gas is used for the oxidizing gas and the third oxidizing gas, and the first depositing gas contains silicon. By using the same type of gas for the second depositing gas containing silicon, the shape of the insulating layer 114 is changed. In forming the insulating layer 116, an oxidizing gas and a silicon-containing depositing gas are used in common. It can be used. By using a common gas, the gas used in the fabrication of the transistor can be The number of types can be reduced.

[0211] When forming insulating layers 114 and 116 using a plasma chemical vapor deposition apparatus: I will explain using an example.

[0212] Here, both insulating layer 114 and insulating layer 116 are made of silicon oxynitride. In formation, monosilane, a sedimentary gas, and nitrous oxide (N2O), an oxidizing gas, are involved. Using a mixed gas containing ammonia, in forming the insulating layer 116, the depositing gas is By using a mixed gas containing monosilane and nitrous oxide (N2O), which is an oxidizing gas, This can be done. Here, in the formation of insulating layer 114 and insulating layer 116, monosilane and dioxide Nitrogen (N2O) can be used in common. That is, monosilane, nitrous oxide (N2O) An insulating layer 114 is formed using 2O) and ammonia, and then ammonia gas is supplied. By stopping the process, the insulating layer 116 can be formed. In this way, insulation can be continuously formed in the same processing chamber. Since layer 114 and insulating layer 116 can be formed, insulating layer 114 and insulating layer 116 This reduces impurities at the interface, resulting in a good interface.

[0213] Furthermore, when plasma treatment is performed as a cleaning treatment before the formation of the aforementioned insulating layer 114, the The gas used for the lath treatment, the gas used for forming the insulating layer 114, and the gas used for forming the insulating layer 116 It is preferable to use a common gas for the gases used. By using a common gas, This allows for a reduction in the number of gases used in the production of the inverter.

[0214] Plasma treatment using a plasma chemical vapor deposition apparatus, formation of insulating layer 114, and insulating layer 1 Let us explain using the case of forming 16 as an example. Here, insulating layer 114 and insulating layer 116 Let it be silicon oxide nitride.

[0215] In plasma processing, nitrous oxide (N2O), an oxidizing gas, and a reducing gas are used. A mixed gas containing a certain ammonia is used. Furthermore, in the formation of the insulating layer 114, deposition It contains monosilane, a gas, nitrous oxide (N2O), an oxidizing gas, and ammonia. A mixed gas is used. Furthermore, in the formation of the insulating layer 116, a monosylamine gas is used. A mixed gas containing nitrate and nitrous oxide (N2O), an oxidizing gas, is used. In the lazma treatment, formation of insulating layer 114, and formation of insulating layer 116, an oxidizing gas is used. Dinitrogen oxide (N2O) can be used in common. Also, plasma treatment and insulating layer 1 In the formation of 14, ammonia can be used in common. Furthermore, the formation of the insulating layer 114 Furthermore, in the formation of the insulating layer 116, monosilane, which is a depositing gas, is commonly used. Yes, it is possible. In other words, plasma treatment is performed using nitrous oxide (N2O) and ammonia. Subsequently, an insulating layer 114 can be formed by flowing monosilane gas through it. Next, an ammonia The insulating layer 116 can be formed by stopping the supply of agas. In this way, the same processing room This allows for continuous plasma processing, formation of the insulating layer 114, and formation of the insulating layer 116. Therefore, the interface between semiconductor layer 108 and insulating layer 114, and the interface between insulating layer 114 and insulating layer 116 This reduces impurities and creates a good interface.

[0216] After forming the insulating layer 116, plasma treatment may be performed on the surface of the insulating layer 116. This plasma treatment reduces impurities such as water adsorbed on the surface of the insulating layer 116. This can be done. If impurities such as water are adsorbed on the surface of the insulating layer 116, the impurities will be absorbed into the semiconductor layer. Reaching 108, V is present in semiconductor layer 108. O , V O In some cases, H and other atoms may be formed. Plasma treatment is performed on the surface of the edge layer 116 to remove impurities such as water from the surface of the insulating layer 116. By suppressing adsorption, a highly reliable transistor can be created. Furthermore, between the formation of insulating layer 116 and the formation of insulating layer 118, the surface of insulating layer 116 is exposed to the air. It is suitable when exposed to the following. Plasma treatments include, for example, oxygen, ozone, nitrogen, monoacid. This can be carried out in an atmosphere of nitrous oxide, argon, etc. In particular, nitrogen can be preferably used. Yes, it is possible. Furthermore, the formation of the insulating layer 116 and the plasma treatment can be carried out continuously without exposure to the atmosphere. It is preferable that it be broken.

[0217] The insulating layer 118 functions as a protective film for the transistor 10. The insulating layer 118 is Impurities such as water and hydrogen diffuse into transistor 10 from outside transistor 10. This suppresses the following: In other words, the reliability and moisture resistance of transistor 10 can be improved. This can result in a semiconductor device with improved reliability.

[0218] The insulating layer 118 prevents impurities such as water and hydrogen from entering the transistor 10 from the outside. It is preferable that it functions as a barrier film that suppresses diffusion to 10. Also, insulating layer 1 It is preferable that component 18 releases little hydrogen-containing impurities such as water and hydrogen from itself. Furthermore, the insulating layer 118 functions as a barrier film that suppresses the diffusion of oxygen. Preferred. As the insulating layer 118, for example, aluminum oxide, aluminum oxide nitride, acid Hafnium oxide, hafnium oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide Oxide films such as yttrium oxide nitride, silicon nitride, silicon oxide nitride, aluminium nitride A nitride film such as luminium or aluminum nitride can be used. Insulating layer 118 Silicon nitride can be used particularly favorably.

[0219] Here, when heat is applied while the insulating layer 116 is exposed, the insulating layer 114 and the insulating layer 116 In some cases, the oxygen contained in the insulating layer 114 and insulating layer 116 may be released outwards. When oxygen is released outward, the amount of oxygen in insulating layer 114 and insulating layer 116 decreases, and half The amount of oxygen supplied to the conductive layer 108 may decrease. Therefore, at least The temperature at which the insulating layer 118 begins to form is such that the oxygen present in insulating layers 114 and 116 is It is preferable that the temperature does not cause desorption to the outside. The insulating layer 118 has a function to suppress the diffusion of oxygen. It has, and furthermore, at a temperature in which the oxygen contained in the insulating layer 114 and insulating layer 116 does not desorb to the outside. By forming the insulating layer 118, oxygen can be supplied to the semiconductor layer 108, and in the semiconductor layer 108 It can efficiently compensate for oxygen deficiency.

[0220] It has the function of suppressing the diffusion of impurities such as water and hydrogen, and also suppressing the diffusion of oxygen. The insulating layer 118 having the function of being dense is preferably a dense film. For example, insulating layer 11 8. By increasing the substrate temperature during formation, a dense film can be created.

[0221] The substrate temperature during the formation of the insulating layer 118 is preferably 180°C to 400°C, and further The temperature is preferably between 200°C and 380°C, and more preferably between 220°C and 360°C. Furthermore, a temperature of 240°C to 350°C is preferable. By setting the substrate temperature as described above, The oxygen contained in the insulating layer 114 and insulating layer 116 can be suppressed from escaping outwards, and insulation Layer 118 can be made into a dense film.

[0222] This configuration provides a transistor with excellent electrical characteristics and extremely high reliability. It is possible to achieve this.

[0223] The above is an explanation of Configuration Example 1-1.

[0224] The following describes a transistor configuration example that differs in some aspects from the previously mentioned Configuration Example 1-1. To clarify, please note that in the following, explanations may be omitted for parts that overlap with the aforementioned configuration example 1-1. Furthermore, in the drawings shown below, the parts having the same function as the above-mentioned example configuration 1-1 are... In some cases, the hatching pattern is the same, and a sign is not assigned.

[0225] [Configuration Example 1-2] Figure 6B shows a schematic cross-sectional view in the channel length direction of transistor 10A, which is one embodiment of the present invention. As shown, transistor 10A differs from the aforementioned transistor in that the configuration of the insulating layer 106a is different. It differs mainly from 10. In transistor 10A, the insulating layer 106a is the insulating layer 106a1 And, insulating layer 106a2 on insulating layer 106a1, and insulating layer 106a3 on insulating layer 106a2 It has a laminated structure.

[0226] Figure 6B shows that the insulating layer 106 is, from the conductive layer 104 side, insulating layer 106a1, insulating layer 106 An example is shown in which a2, insulating layer 106a3, and insulating layer 106b are laminated in this order. The insulating layer 106a1 is in contact with the conductive layer 104. The insulating layer 106b is a semiconductor layer. It is adjacent to 108.

[0227] The insulating layer 106a suppresses the diffusion of impurities such as water, hydrogen, and sodium, and the conductive layer The properties of 104 include suppression of diffusion of components, low stress, high dielectric strength, water, and hydrogen. It is preferable that one or more of the following conditions are met: low release of impurities such as, and all of these conditions It is most preferable to satisfy the following conditions.

[0228] Insulating layer 106a1, insulating layer 106a2, and insulating layer 106a located on the conductive layer 104 side As a third option, an insulating film that can be used for the aforementioned insulating layer 106a can be used. Each of the four insulating films of the marginal layer 106 is exposed to the air using a plasma CVD apparatus. It is preferable to form them continuously without interruption.

[0229] The insulating layer 106a1 contains impurities such as water, hydrogen, and sodium, which affect the shape of the insulating layer 106a1. A barrier that suppresses diffusion from the surface-forming material (e.g., substrate) to the transistor 10. It is preferable that it functions as a film. Also, the insulating layer 106a1 has components of the conductive layer 104. It is preferable that it functions as a barrier film that suppresses diffusion into the transistor 10. Layer 106a2 is preferably low stress and has high dielectric strength. Insulating layer 106a3 is Furthermore, it is preferable that the release of impurities such as water and hydrogen from itself is minimal. Also, insulating layer 106 a3 indicates that impurities such as water and hydrogen from below the insulating layer 106a2 enter the transistor 10. It is preferable that it functions as a barrier film that suppresses diffusion.

[0230] The insulating layers 106a1 and 106a3 prevent the diffusion of impurities from below them. It is preferable that the film is dense and can be formed. The insulating layer 106a1 and insulating layer 106a3 are An insulating film formed under conditions with a slower deposition rate than that of the insulating layer 106a2 can be applied. On the other hand, the insulating layer 106a2 uses an insulating film formed under conditions of low stress and a high deposition rate. It is preferable that the insulating layer 106a2 is made of insulating layer 106a1 and insulating layer 106a A film thickness greater than 3 is preferable.

[0231] The same film type is used for each of the insulating layers 106a1, 106a2, and 106a3. For example, even when using a silicon nitride film formed by plasma CVD, the insulating layer 10 6a2 is a film with a lower film density than insulating layers 106a1 and 106a3. In transmission electron microscope (TEM) images of the cross-section of the insulating layer 106, the control This can sometimes be observed as a difference in the last. Note that insulating layer 106a1 and insulating layer The boundary of 106a2, and the boundary (interface) between insulating layer 106a2 and insulating layer 106a3, are clearly defined. There may be cases where this cannot be recognized. Therefore, in the drawings illustrating one embodiment of the present invention, these boundaries are not broken. It is shown by a line.

[0232] This configuration provides a transistor with excellent electrical characteristics and extremely high reliability. It is possible to achieve this.

[0233] [Configuration Examples 1-3] Figure 7A shows a schematic cross-sectional view in the channel length direction of transistor 10B, which is one embodiment of the present invention. As shown, transistor 10B has a conductive layer 120 on an insulating layer 118, which is the same as the aforementioned transistor. It differs primarily from the 'njista 10'.

[0234] The semiconductor layer 108 is located between the conductive layer 104 and the conductive layer 120. The body layer 108 and the conductive layer 120 have overlapping regions. Transistor 10B is a semiconductor Above and below the body layer 108 are a conductive layer 104 that functions as a gate electrode, and a back gate electrode. It is a dual-gate type transistor having a conductive layer 120 that functions as a transistor. In the inverter 10B, a portion of the insulating layer 106 functions as the first gate insulating layer, providing insulation. Layer 114, insulating layer 116, and a portion of insulating layer 118 function as a second gate insulating layer.

[0235] For example, transistor 10B applies the same potential to conductive layer 104 and conductive layer 120. This allows for a larger current to flow when the device is in the ON state. The transistor 10B controls the threshold voltage on one of the conductive layers 104 and 120. One potential is applied to control the on and off states of transistor 10B. You can also give.

[0236] This configuration provides a transistor with excellent electrical characteristics and extremely high reliability. It is possible to achieve this.

[0237] [Configuration Examples 1-4] Figure 7B shows a schematic cross-sectional view in the channel length direction of transistor 10C, which is one embodiment of the present invention. The transistor 10C differs in the configuration of the insulating layer 106 and has a conductive layer 120. In this respect, it differs mainly from the aforementioned transistor 10. Transistor 10C is the same as in the aforementioned configuration example 1. -2 The transistor 10A exemplified in the above configuration example 1-3 is connected to the transistor 10 This is an example of applying the conductive layer 120 exemplified in B.

[0238] This configuration provides a transistor with excellent electrical characteristics and extremely high reliability. It is possible to achieve this.

[0239] <Configuration Example 2> The following section will describe more specific examples of transistor configurations.

[0240] [Configuration Example 2-1] Figure 8A is a top view of transistor 100, and Figure 8B shows the dashed line A1 shown in Figure 8A. -This corresponds to a cross-sectional view of the cross-section in A2, and Figure 8C corresponds to the dashed line B1-B2 shown in Figure 8A. This corresponds to a cross-sectional view of the cut surface. The direction of the dashed line A1-A2 is the channel length direction. The B1-B2 direction corresponds to the channel width direction. Note that in Figure 8A, transistor 10 Some of the components of 0 (such as the gate insulating layer) are omitted in the diagram. Also, the transistor Regarding the top view, in subsequent drawings, as with Figure 8A, some of the components will be omitted. This is shown. Furthermore, Figure 9A shows an enlarged cross-sectional view of the region P enclosed by the dashed line in Figure 8B. Yes, they are.

[0241] The transistor 100 is provided on the substrate 102, and consists of a conductive layer 104, an insulating layer 106, and a semiconductor It has layers 108, conductive layer 112a, and conductive layer 112b, etc. The insulating layer 106 is conductive layer 10 It is provided covering 4. The semiconductor layer 108 has an island-like shape and is provided on the insulating layer 106. The conductive layer 112a and conductive layer 112b are in contact with the upper surface of the semiconductor layer 108. Furthermore, they are spaced apart on the semiconductor layer 108. Also, the insulating layer 106 and the conductive layer 1 An insulating layer 114 is provided covering 12a, the conductive layer 112b, and the semiconductor layer 108, and the insulating layer An insulating layer 116 is provided on 114.

[0242] The conductive layer 104 functions as a gate electrode. A portion of the insulating layer 106 is a gate insulating layer. It functions as follows. The conductive layer 112a functions as either the source electrode or the drain electrode. The conductive layer 112b functions as the other. The region of the semiconductor layer 108 that overlaps with the conductive layer 104 is It functions as a channel formation region. Transistor 100 is formed more than semiconductor layer 108. This is a so-called bottom-gate type transistor, where the gate electrode is located on the face side. The side of the semiconductor layer 108 opposite to the conductive layer 104 is called the back channel side. Yes. Transistor 100 is located on the back channel side of semiconductor layer 108, and the source electrode and This is a transistor with a so-called channel etch structure, which does not have a protective layer between the rain electrode and the transistor. ru.

[0243] The semiconductor layer 108 consists of, in order from the side to be formed (substrate 102 side), semiconductor layer 108a and semiconductor It has a laminated structure in which layer 108a and semiconductor layer 108b are stacked. Each preferably contains a metal oxide. Also, the semiconductor located on the back channel side. Layer 108b is a film with higher crystallinity than semiconductor layer 108a, which is located on the conductive layer 104 side. This is preferable. This allows the semiconductor layer to be processed during the processing of conductive layer 112a and conductive layer 112b. This can prevent part of 108 from being etched away and disappearing.

[0244] For example, the semiconductor layer 108 is a metal acid having the composition shown in Embodiment 1. It is preferable to use an oxide. By using the metal oxide in the channel-forming region, This allows for the creation of a transistor with high reliability and high field-effect mobility.

[0245] Semiconductor layer 108a and semiconductor layer 108b are metal oxide films as shown in Embodiment 1, respectively. It is preferable to use [this].

[0246] The semiconductor layer 108a and semiconductor layer 108b may have the same or approximately the same composition. By making the compositions of semiconductor layer 108a and semiconductor layer 108b the same or approximately the same, Using the same sputtering target, semiconductor layer 108a and semiconductor layer 108b can be formed. Therefore, manufacturing costs can be reduced.

[0247] Semiconductor layer 108a and semiconductor layer 108b are layers with different compositions and different crystallinity. Alternatively, layers with different impurity concentrations may be used. Furthermore, a laminated structure of three or more layers may be used. .

[0248] The conductive layer 112a and the conductive layer 112b are, in order from the side to be formed, the conductive layer 113a It has a laminated structure in which conductive layer 113b and conductive layer 113c are laminated.

[0249] The conductive layer 113b is made of a low-resistance conductive material, such as copper, silver, gold, or aluminum. It is preferable to use it. In particular, it is preferable that the conductive layer 113b contains copper or aluminum. The conductive layer 113b is a conductive material with lower resistance than conductive layers 113a and 113c. It is preferable to use this. This makes the conductive layer 112a and conductive layer 112b extremely low resistance It can be made to resist.

[0250] Conductive layer 113a and conductive layer 113c are each independently conductive, different from conductive layer 113b. Electrical materials can be used. For example, conductive layer 113a and conductive layer 113c are each These are titanium, tungsten, molybdenum, chromium, tantalum, zinc, and indium, independently. It is preferable to use a conductive material containing platinum or ruthenium.

[0251] Thus, the conductive layer 113b containing copper, aluminum, etc., is connected to the conductive layer 113a and the conductive layer 1 By sandwiching it between 13c, the surface of the conductive layer 113b is oxidized, and the conductive layer 113b This can suppress the diffusion of the elements into the surrounding layers. In particular, the semiconductor layer 108 and the conductive layer 113b By providing a conductive layer 113a between them, the metal elements contained in the conductive layer 113b become semiconductor layer 1 This prevents diffusion during 08, enabling the realization of a highly reliable transistor 100. .

[0252] Here, an insulating layer 114 is provided in contact with the edge of the conductive layer 113b. (More details will follow.) According to one aspect of the present invention, a conductive material that is easily oxidized is used for the conductive layer 113b, Even if an insulating layer 114 containing an oxide film is formed on top, the surface of the conductive layer 113b is acid This suppresses oxidation. Therefore, oxidation occurs at the interface between the conductive layer 113b and the insulating layer 114. One of the features of this invention, in one aspect, is that no extraneous layers containing material are observed.

[0253] Furthermore, the structure of conductive layers 112a and 112b is not limited to a three-layer structure, and can also be made of copper, silver, gold, Alternatively, it may be a two-layer structure or a four-layer structure including a conductive layer containing aluminum. As conductive layers 112a and 112b, conductive layers 113a and 113b are laminated. It may be a two-layer structure, or a two-layer structure in which conductive layer 113b and conductive layer 113c are laminated. You may do so.

[0254] During the formation of conductive layers 112a and 112b, the surface of the semiconductor layer 108 is damaged. In some cases, V may be present in the damaged semiconductor layer 108. O A semiconductor layer 1 is formed, and further semiconductor layer 1 Hydrogen in 08 is V O Enter V O Because H may be formed, damage can be taken. It is preferable to remove the dent layer. By removing the damaged layer, good electrical performance can be achieved. It is possible to create a transistor that exhibits good air characteristics and is highly reliable. Damaged layer An example of a configuration with the element removed is shown in Figure 9B. Figure 9B shows the region P enclosed by the dashed line in Figure 8B. This is an enlarged cross-sectional view. In Figure 9B, the semiconductor layer 108b is connected to the conductive layer 112a and the conductive layer 1 The film thickness of the region that does not overlap with any of 12b is the thickness of either conductive layer 112a or conductive layer 112b This shows an example where the film thickness is thinner than the overlapping region.

[0255] Figures 9A and 9B show the edges of conductive layer 113a, conductive layer 113b, and conductive layer 113c. While all examples shown are identical or substantially identical, one aspect of the present invention is not limited thereto. i. The edges of any of the conductive layers 113a, 113b, and 113c do not coincide. Or, they do not need to be roughly identical.

[0256] As shown in Figure 9C, the edges of conductive layer 113b and conductive layer 113c are the same as those of conductive layer 113a. It is preferable that it be located inside the edge. Furthermore, the edge of the conductive layer 113c is located inside the conductive layer 11 It is preferable that the end of 3b coincides with, or roughly coincides with, the end of 3b. By having such a configuration, Layers formed on the electrode layer 113a, conductive layer 113b, conductive layer 113c and semiconductor layer 108 ( For example, the step coverage of the insulating layer 114) is improved, and defects such as step breaks or porosity occur in the layer. This can suppress the action.

[0257] The edge of conductive layer 113b is located inside the conductive layer 113a, and the edge of conductive layer 113c An example where this coincides with the edge of the conductive layer 113b is shown in Figure 9C. Figure 9C is the dashed line in Figure 8B. This is an enlarged cross-sectional view of the region P enclosed by the box. By using the configuration shown in Figure 9C, the conductive layer 1 The step difference between 12a and conductive layer 112b is reduced, and conductive layer 112a, conductive layer 112b and semi The step coverage of the layer (for example, the insulating layer 118) formed on the conductive layer 108a is improved, and the layer This can suppress defects such as cracking or porosity.

[0258] In Figure 9C, the edges of conductive layer 113b and conductive layer 113c coincide or roughly coincide. An example is shown, but the present invention is not limited thereto. Conductive layer 113b and conductive layer The edges of 113c do not need to coincide or to coincide approximately. Note that the conductive layer 113b If the end is located inside the end of conductive layer 113c, conductive layer 112a, conductive layer 112 b and the stepped coverage of the layer formed on the semiconductor layer 108a (e.g., insulating layer 118) is poor. As a result, defects such as stepped breaks and porosity may occur in the conductive layer 11 It is preferable that the end of 3c is located inside the end of the conductive layer 113b.

[0259] The conductive layer 104 is the conductive material described above, which can be used in conductive layers 113a and 113b. Materials can be used as appropriate. In particular, it is preferable to use a conductive material containing copper.

[0260] The insulating layer 106 and insulating layer 114 that are in contact with the semiconductor layer 108 contain an insulating material containing an oxide. It is preferable to use [this]. Also, when the insulating layer 106 and insulating layer 114 are made into a laminated structure Furthermore, an insulating material containing an oxide is used for the layer in contact with the semiconductor layer 108.

[0261] The insulating layer 106 may also be made of a nitride film such as silicon nitride or aluminum nitride. When using an insulating material that does not contain nitrites, the insulating layer 106 is subjected to a treatment in which oxygen is added to the upper part of the insulating layer 106. It is preferable to perform this process to form an oxygen-containing region. As a treatment for adding oxygen, for example Heat treatment or plasma treatment in an oxygen-containing atmosphere, or ion doping treatment, etc. There is.

[0262] The insulating layer 116 functions as a protective layer to protect the transistor 100. These include silicon nitride, silicon oxide nitride, silicon oxide, silicon oxide nitride, and aluminum oxide. Inorganic insulating materials such as aluminum nitride can be used. In particular, insulating layer 116 By using materials that do not easily diffuse oxygen, such as silicon nitride and aluminum oxide, During the manufacturing process, heat applied causes the semiconductor layer 108 and insulating layer 114 to separate from the insulating layer 116. This is preferable because it prevents oxygen from escaping to the outside.

[0263] An organic insulating material that functions as a planarization film may be used as the insulating layer 116. Alternatively, Even if a laminated film containing an inorganic insulating material and an organic insulating material is used as the insulating layer 116, good.

[0264] The semiconductor layer 108 has portions that are in contact with the conductive layer 112a and the conductive layer 112b and in the vicinity thereof. Even if a pair of low-resistance regions are formed that function as a source region and a drain region, Good. This region is part of the semiconductor layer 108 and has lower resistance than the channel formation region. Furthermore, the low-resistance region is also referred to as the region with high carrier concentration, or the n-type region. It can be replaced. Also, in the semiconductor layer 108, it is sandwiched between a pair of low-resistance regions, The region overlapping with the conductive layer 104 functions as a channel-forming region.

[0265] The above is an explanation of Configuration Example 2-1.

[0266] [Configuration Example 2-2] The following describes a transistor configuration example that differs in some aspects from the previously mentioned Configuration Example 2-1. To clarify, please note that in the following, explanations may be omitted for parts that overlap with the aforementioned configuration example 2-1. Furthermore, in the drawings shown below, the parts having the same function as the aforementioned Configuration Example 2-1 are... In some cases, the hatching pattern is the same, and a sign is not assigned.

[0267] Figure 10A is a top view of transistor 100A, and Figure 10B is a top view of transistor 100 Figure 10C is a cross-sectional view of channel B in the length direction, and Figure 10C is a cross-sectional view in the width direction of the channel.

[0268] Transistor 100A has a conductive layer 120a and a conductive layer 120b on an insulating layer 116. In this respect, it differs primarily from the transistor 100 shown in Configuration Example 2-1.

[0269] The conductive layer 120a is superimposed on the semiconductor layer 108 via the insulating layers 116 and 114. It has a domain.

[0270] In transistor 100A, the conductive layer 104 is the first gate electrode (bottom gate electrode) The conductive layer 120a functions as a second gate electrode (also called a pole), and the conductive layer 120a is the second gate electrode (top gate). It has the function of an electrode. Also, parts of the insulating layer 116 and insulating layer 114 It functions as a second gate insulating layer.

[0271] As shown in Figure 10C, the conductive layer 120a consists of insulating layer 116, insulating layer 114, and insulating layer Even though it is electrically connected to the conductive layer 104 through the opening 142b provided in 106 Good. This allows the conductive layer 120a and the conductive layer 104 to be given the same potential, This makes it possible to create transistors with high current.

[0272] As shown in Figures 10A and 10C, in the channel width direction, the conductive layer 104 and the conductive layer It is preferable that the electrode layer 120a protrudes outward from the edge of the semiconductor layer 108. As shown in Figure 10C, the entire channel width direction of the semiconductor layer 108 is connected to the conductive layer 104. The structure is covered with a conductive layer 120a.

[0273] With this configuration, the semiconductor layer 108 is protected from the electric field generated by the pair of gate electrodes. And it can be electrically surrounded. In particular, the conductive layer 104 and the conductive layer 120a are the same It is preferable to apply a potential. This induces a channel in the semiconductor layer 108. Because the electric field can be applied effectively, the on-current of the 100A transistor can be increased. This makes it possible to miniaturize the 100A transistor.

[0274] Furthermore, the conductive layer 104 and the conductive layer 120a may be configured not to be connected. A constant potential is applied to one of the pair's gate electrodes, and the other is used to drive transistor 100A. A signal may be applied. At this time, the potential applied to one electrode determines the transistor 100A The threshold voltage when driving the other electrode can be controlled.

[0275] The conductive layer 120b is transmitted through the openings 142a provided in the insulating layer 116 and the insulating layer 114. It is electrically connected to the conductive layer 112b. The conductive layer 120b is used as wiring or an electrode. It is possible. For example, when applied to a display device, the conductive layer 120b can be used as a pixel electrode, or It can function as wiring for connecting to pixel electrodes.

[0276] The above is an explanation of configuration example 2-2.

[0277] [Configuration Example 2-3] The transistor 100B shown in Figures 11A and 11B is, in cross-sectional view in the channel length direction Therefore, the edge of the insulating layer 106b is roughly the same as the edge of the conductive layer 112a, or the edge of the conductive layer 112b. In terms of similarities, it differs primarily from transistor 100A shown in the aforementioned configuration example 2-2. Furthermore, in a cross-sectional view in the channel width direction, transistor 100B is at the edge of the insulating layer 106b. The portion roughly coincides with the edge of the semiconductor layer 108.

[0278] The insulating layer 106a overlaps with the semiconductor layer 108, the conductive layer 112a, or the conductive layer 112b. In this region, it has a region in contact with the insulating layer 106b. Furthermore, the insulating layer 106a is a semiconductor layer 108, In a region that does not overlap with either conductive layer 112a or conductive layer 112b, It has a region in contact with layer 114.

[0279] The insulating layer 106a is etched during the formation of the conductive layer 112a and the conductive layer 112b. It is preferable that it functions as an amper. For example, silicon oxide and nitrogen oxide in the insulating layer 106b. When an oxide film such as silicon dioxide is used, aluminum oxide and nitrogen oxide are used in the insulating layer 106a. Aluminum oxide, hafnium oxide, hafnium oxide nitride, gallium oxide, gallium oxide nitride Oxide films such as yttrium oxide, yttrium oxide nitride, silicon nitride, and nitriding acids. Preferably using nitride films such as silicon dioxide, aluminum nitride, and aluminum nitride oxide. It is possible.

[0280] The insulating layer 106a functions as an etching stopper, thereby preventing the conductive layer 112a and The step at the edge of the conductive layer 112b becomes smaller, and a shape is formed on the conductive layer 112a and conductive layer 112b. The step coverage of the resulting layer (for example, the insulating layer 114) is improved, and the layer is free from step breaks and porosity. This can help prevent malfunctions from occurring.

[0281] Note that in Figures 11A and 11B, semiconductor layer 108, conductive layer 112a and conductive layer 112 The thickness of the insulating layer 106a in the region that does not overlap with any of the semiconductor layer 108 and the conductive layer 11 An example is shown where the film thickness of the insulating layer 106a in the region overlapping with 2a or the conductive layer 112b is approximately equal. However, the present invention is not limited to this. Semiconductor layer 108, conductive layer 112a and conductive The thickness of the insulating layer 106a in the region that does not overlap with any of the layers 112b is such that the semiconductor layer 108 and the conductive layer It is acceptable for the thickness of the insulating layer 106a in the region overlapping with the electrical layer 112a or the conductive layer 112b to be less than the thickness of the insulating layer 106a. stomach.

[0282] The above is an explanation of configuration example 2-3.

[0283] [Configuration Example 2-4] The transistor 100C shown in Figures 12A and 12B is, in cross-sectional view in the channel length direction Therefore, the edge of the insulating layer 106b roughly coincides with the edge of the semiconductor layer 108, as in the aforementioned configuration example 2. It differs mainly from transistor 100A shown in -2. Also, transistor 100B is In a cross-sectional view in the channel width direction, the edge of the insulating layer 106b is approximately the same as the edge of the semiconductor layer 108. They are almost identical.

[0284] In the region where the insulating layer 106a overlaps with the semiconductor layer 108, the region in contact with the insulating layer 106b It has a region. In addition, the insulating layer 106a has semiconductor layer 108, conductive layer 112a and conductive layer 11 In a region that does not overlap with any of 2b, there is a region that is in contact with the insulating layer 114.

[0285] The insulating layer 106a functions as an etching stopper during the formation of the semiconductor layer 108. It is preferable that the insulating layer 106a functions as an etching stopper, The step difference at the edge of the semiconductor layer 108 becomes smaller, and the layer formed on the semiconductor layer 108 (for example, The step coverage of conductive layers 112a and 112b) is improved, and the layers are free from step breaks and porosity. This can help prevent malfunctions from occurring.

[0286] Note that in Figures 12A and 12B, the insulating layer 106a in the region that does not overlap with the semiconductor layer 108. This example shows that the film thickness is approximately equal to the film thickness of the insulating layer 106a in the region overlapping with the semiconductor layer 108. However, the present invention is not limited to this. Insulating layer in a region that does not overlap with semiconductor layer 108 Even if the film thickness of 106a is thinner than the film thickness of the insulating layer 106a in the region overlapping with the semiconductor layer 108, stomach.

[0287] The above is an explanation of configuration example 2-4.

[0288] <Example of manufacturing method 1> The following describes a method for manufacturing a semiconductor device according to one aspect of the present invention, with reference to the drawings. Here, we will explain using transistor 100A, as shown in the aforementioned configuration example 2-2, as an example. .

[0289] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Chemical vapor deposition (CVD) method Vacuum deposition, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method It can be formed using methods such as the CVD method. These include the VD (Plasma Enhanced CVD) method and the thermal CVD method. One of the thermal CVD methods is metal-organic chemical vapor deposition (MOCVD). There is the CVD method.

[0290] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are coated using spin coating, DIT coating, etc. Printing methods: spray coating, inkjet, dispensing, screen printing, offset printing. Doctor's knife, slit coat, roll coat, curtain coat, knife coat, etc. It can be formed by doing so.

[0291] When processing thin films that make up semiconductor devices, methods such as photolithography are used. It is possible to do this using other methods such as nanoimprint lithography, sandblasting, and lift-off lithography. The thin film may be processed by any method. Alternatively, a film deposition method using a shielding mask such as a metal mask may be used. This may be used to directly form island-like thin films.

[0292] There are two main methods of photolithography. One is to process the image A resist mask is formed on a thin film, and the thin film is processed by etching or the like, and the resist This is a method for removing the mask. Another method involves forming a photosensitive thin film and then exposing it to light. This method involves developing the film and then processing it into a desired shape.

[0293] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm). Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these light This can be done by using ultraviolet light, KrF laser light, or ArF laser light, etc. It is also possible to perform exposure using immersion lithography. Furthermore, the light used for exposure and Using extreme ultraviolet (EUV) light and X-rays... It is also possible to use an electron beam instead of light for exposure. Extreme ultraviolet Using light, X-rays, or electron beams is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is unnecessary.

[0294] Thin film etching methods include dry etching, wet etching, and sandblasting. Laws and other regulations can be used.

[0295] Figures 13 to 17 illustrate the method for manufacturing transistor 100A. In each figure, the left side shows a cross-section in the channel length direction, and the right side shows a cross-section in the channel width direction. They are shown side by side.

[0296] [Formation of conductive layer 104] A conductive film is formed on the substrate 102, and a resist mass is formed on the conductive film by a lithography process. After forming the groove, the conductive film is etched to create a conductive layer that functions as a gate electrode. Forms 104.

[0297] [Formation of insulating layer 106] Next, an insulating layer 106 is formed to cover the conductive layer 104 and the substrate 102 (Figure 13A). The marginal layer 106 can be formed, for example, by the PECVD method.

[0298] After forming the insulating layer 106, a heat treatment may be performed. By performing the heat treatment, the insulating layer is formed. Water and hydrogen can be removed from the surface and within the film of layer 106.

[0299] The heat treatment temperature is preferably 150°C or higher but below the strain point of the substrate, and more preferably 250°C or higher. A temperature of 450°C or lower is preferred, and more preferably 300°C to 450°C. The heat treatment is as follows: This can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Alternatively, use a dry air (CDA: Clean Dry Air) as the atmosphere containing oxygen. This is also acceptable. Furthermore, it is preferable that the atmosphere contains as little hydrogen, water, etc. as possible. As an atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is used. This is preferable. By using an atmosphere with the lowest possible content of hydrogen, water, etc., the insulating layer 106 This prevents hydrogen, water, etc. from being absorbed as much as possible. Heat treatment is performed by Ob Using, for example, a rapid thermal annealing (RTA) device. It is possible to do so. By using an RTA device, the heat treatment time can be shortened.

[0300] Next, a process of supplying oxygen to the insulating layer 106 may be performed. Then, the insulating layer 106 is subjected to ion doping, ion implantation, plasma treatment, etc. It supplies oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, etc. It also provides insulation. After forming a film on layer 106 that suppresses oxygen desorption, oxygen is transferred to the insulating layer 106 through the film. It may be added. The film is preferably removed after the addition of oxygen. Indium, zinc, gallium, tin, aluminum, chromium, and tan are used as films to suppress separation. It contains one or more of the following: tul, titanium, molybdenum, nickel, iron, cobalt, or tungsten. A conductive film or semiconductor film can be used.

[0301] [Formation of semiconductor layer 108] Next, metal oxide films 108af and 108bf are laminated on the insulating layer 106. This is how it is formed (Figure 13B).

[0302] Metal oxide film 108af and metal oxide film 108bf are metal oxide target It is preferable to form it using a sputtering method with a t

[0303] When forming the metal oxide films 108af and 108bf, in addition to oxygen gas, by mixing in an inert gas (for example, helium gas, argon gas, xenon gas, etc.) This is also acceptable. Furthermore, the proportion of oxygen gas in the total film-forming gas when forming a metal oxide film (hereinafter) The oxygen flow rate ratio (also called the oxygen flow rate ratio) can be in the range of 0% to 100%.

[0304] By lowering the oxygen flow rate ratio and creating a metal oxide film with relatively low crystallinity, highly conductive gold A metal oxide film can be obtained by increasing the oxygen flow rate ratio and using a metal acid with relatively high crystallinity. By forming an oxide film, a metal oxide film with high etching resistance and electrical stability can be obtained. It is possible.

[0305] Here, the metal oxide film 108a is located on the conductive layer 104 side, which functions as the gate electrode. f is a film with low crystallinity, and the metal oxide film 108bf located on the back channel side is crystalline By creating a film with high density, it is possible to realize transistors that are highly reliable and have high field-effect mobility. Cut.

[0306] For example, the formation conditions for metal oxide films 108af and 108bf are the substrate temperature The temperature should be between room temperature and 200°C, preferably the substrate temperature should be between room temperature and 140°C. If the substrate temperature during the formation of the oxide film is set to, for example, room temperature or higher but less than 140°C, productivity will be high. It's much more desirable.

[0307] More specifically, the oxygen flow rate during the formation of the metal oxide film 108af is between 0% and less than 50%. Preferably, 5% to 30% is preferable, and even more preferably 5% to 20% is preferable. Typically, we will use 10%. Also, the oxygen flow rate ratio during the formation of the metal oxide film 108bf. Preferably, it is 50% to 100%, and more preferably 60% to 100%. Furthermore, a ratio of 70% to 100% is preferable, and even more preferably, a ratio of 80% to 100% is preferable. For example, let's consider it to be 100%.

[0308] Metal oxide film 108af and metal oxide film 108bf are films with the same or approximately the same composition. This can be done. The metal oxide film 108af and the metal oxide film 108bf are placed on the same spat Because it can be formed using a taping target, manufacturing costs can be reduced. Also, the same spa When using a dermating target, metal oxide films can be continuously deposited in a vacuum using the same deposition apparatus. Since 08af and the metal oxide film 108bf can be formed, the semiconductor layer 108a and This can suppress the incorporation of impurities at the interface of the semiconductor layer 108b. If the conditions such as pressure, temperature, and power during formation are different for 108af and the metal oxide film 108bf... While it is possible to do so, keeping all conditions except the oxygen flow rate the same will shorten the time required for the formation process. This is preferable because it allows for this.

[0309] Furthermore, metal oxide film 108af and metal oxide film 108bf have different compositions. It may be a film. In this case, both the metal oxide film 108af and the metal oxide film 108bf In the case of using In-Ga-Zn oxide, the metal oxide film 108bf is formed. It is preferable to use an oxide target with a higher In content than 108af.

[0310] After the formation of metal oxide film 108af and metal oxide film 108bf, metal oxide film 108bf A resist mask is formed on top, and metal oxide films 108af and 108bf are applied. After processing by cutting, the resist mask is removed, and the semiconductor layer 108a and semiconductor A layer 108 can be formed in the shape of an island semiconductor layer 108, which is stacked with a body layer 108b (Figure 13C). ).

[0311] The metal oxide films 108af and 108bf are processed using wet etching. Either the method or the dry etching method, or both, may be used.

[0312] Furthermore, when forming the semiconductor layer 108, the insulating layer 106 in the region overlapping with the semiconductor layer 108 In some cases, the thickness of the insulating layer 106 in areas that do not overlap with the semiconductor layer 108 may be thinner than the overall thickness.

[0313] After forming the metal oxide film 108af and the metal oxide film 108bf, or the semiconductor layer 1 After processing to 08, heat treatment may be performed. By performing heat treatment, the metal oxide film Hydrogen in the surface and film of 108af and the metal oxide film 108bf, or the semiconductor layer 108 Water can be removed. Also, by heat treatment, the metal oxide film 108af and metal acid The etching rate of the oxide film 108bf or the semiconductor layer 108 slows down, which can hinder subsequent processes (for example) (This suppresses the disappearance of the semiconductor layer 108 during the formation of conductive layers 112a and 112b.) can.

[0314] The heat treatment temperature is preferably 150°C or higher but below the strain point of the substrate, and more preferably 250°C or higher. A temperature of 450°C or lower is preferred, and more preferably 300°C to 450°C. The heat treatment is as follows: This can be carried out in an atmosphere containing one or more noble gases or nitrogen. Alternatively, heating can be performed in such an atmosphere. Afterward, it may be further heated in an atmosphere containing oxygen. A nitrogen atmosphere, or an oxygen atmosphere. As for the atmosphere, dry air (CDA: Clean Dry Air) may be used. It is preferable that the atmosphere contains as little hydrogen, water, etc. as possible. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. By using an atmosphere with the lowest possible content of hydrogen, water, etc., the semiconductor layer 108 can be protected from hydrogen and water. This prevents as much as possible from being absorbed. Heat treatment can be done by oven or rapid heating. (RTA: Rapid Thermal Annealing) equipment can be used. It is possible. By using an RTA device, the heat treatment time can be shortened.

[0315] [Formation of conductive layer 112a and conductive layer 112b] Next, the insulating layer 106 and the semiconductor layer 108 are covered with conductive film 113af and conductive film 113 bf and the conductive film 113cf are laminated to form the structure.

[0316] The conductive film 113bf is a film that later becomes the conductive layer 113b, and is made of copper, silver, gold, or aluminum. It is preferable that it contains nium. Also, conductive film 113af and conductive film 113cf are respectively These are films that will later become conductive layer 113a and conductive layer 113b, and are independently titanium and tungsten. Stainless steel, molybdenum, chromium, tantalum, zinc, indium, platinum, and ruthenium, etc. It is preferable to include it.

[0317] The conductive films 113af, 113bf, and 113cf are produced by sputtering. It is preferable to form them using a formation method such as vapor deposition or plating.

[0318] Next, a resist mask 140 is formed on the conductive film 113cf (Figure 14A).

[0319] Next, using the resist mask 140 as a mask, conductive film 113cf, conductive film 113bf , and by etching the conductive film 113af, conductive layer 113a, conductive layer 113b, and Conductive layers 112a and 112b are formed, having a structure in which conductive layer 113c is laminated. This is possible (Figure 14B).

[0320] As shown in Figure 14B, conductive layers 112a and 112b are connected to the semiconductor layer 108. It is preferable that the conductive layer 11 be processed to be spaced apart on the flannel formation region. In other words, conductive layer 11 The opposing ends of 2a and the conductive layer 112b overlap with both the conductive layer 104 and the semiconductor layer 108. It is preferable that it be processed to resemble a tatami mat. This increases the on-current of the transistor. It is possible.

[0321] Furthermore, when forming conductive layer 112a and conductive layer 112b, conductive layer 112a and conductive layer 1 From the thickness of the semiconductor layer 108 in the region overlapping with 12b, conductive layer 112a and conductive layer 112b In some cases, the thickness of the semiconductor layer 108 in non-overlapping regions may become thinner.

[0322] When forming conductive layer 112a and conductive layer 112b, conductive layer 112a and conductive layer 112b The thickness of the insulating layer 106 in the overlapping region is greater than the thickness of the conductive layer 112a and conductive layer 112b. The thickness of the insulating layer 106 in the affected area may become thinner.

[0323] The conductive film 113cf, conductive film 113bf, and conductive film 113af are each wetted It can be etched by scratching or dry etching, etc. You can etch all three layers at once, or you can etch each layer sequentially using different processes. good.

[0324] [Cleaning process 1] Next, a cleaning process is preferable. As a cleaning process, a wet cleaning process using a cleaning solution is performed. This includes cleaning, plasma treatment using plasma, or cleaning by heat treatment, as mentioned above. These may be combined as appropriate. As a cleaning treatment, wet cleaning using phosphoric acid is particularly recommended. It can be used suitably.

[0325] During the formation of conductive film 113cf, conductive film 113bf, and conductive film 113af, and the conductive layer When forming 112a and the conductive layer 112b, the surface of the semiconductor layer 108 may be damaged. There is a match. V is present in the damaged semiconductor layer 108. O A formation is formed, and further in the semiconductor layer 108 The hydrogen of V O Enter V O H may be formed. Conductive layer 112a and conductive layer 1 By performing a washing treatment after the formation of 12b, the damaged layer can be removed. .

[0326] By performing the cleaning process, the semiconductor layer 10 is formed when conductive layer 112a and conductive layer 112b are formed. It can remove metal, organic matter, etc., that are attached to the surface of 8.

[0327] As shown in Figure 14B, the upper surfaces of conductive layer 112a and conductive layer 112b are resist mask 1 It is preferable to perform the cleaning process while covered with 40. Conductive layer 112a and conductive layer 112 By performing a cleaning process with the upper surface of b covered by the resist mask 140, for example, This can prevent the conductive layer 113c from disappearing. Also, conductive layer 112a and conductive layer 1 By performing the cleaning process with the top surface of 12b covered by the resist mask 140, the cleaning is performed. Because the area of ​​the conductive layer 112a and conductive layer 112b exposed during processing can be reduced, This suppresses the adhesion of components of the electrolytic layer 112a and the conductive layer 112b to the semiconductor layer 108. Cut.

[0328] Next, remove the resist mask 140 (Figure 15A).

[0329] The aforementioned cleaning process may be performed after removing the resist mask 140.

[0330] [Cleaning process 2] Next, a cleaning process is preferable. As a cleaning process, a wet cleaning process using a cleaning solution is performed. This includes cleaning, plasma treatment using plasma, or cleaning by heat treatment, as mentioned above. These may be combined as appropriate. Plasma treatment is preferably used as a cleaning treatment. Yes, it is possible. In Figure 15B, the semiconductor layer 108, conductive layer 112a, conductive layer 112b, and insulating layer This diagram schematically shows the surface of 106 being exposed to plasma 130.

[0331] Plasma treatment is preferably performed using a mixed gas containing an oxidizing gas and a reducing gas. It is possible to use oxidizing and reducing gases in plasma treatment, and the conductive layer 112a and This suppresses oxidation of the conductive layer 112b and effectively prevents oxidation of the semiconductor layer 108 surface It can remove water, hydrogen, organic components, etc., adsorbed on it. The aforementioned gas is used as the oxidizing gas. This is possible. The aforementioned gases can be used as reducing gases.

[0332] The ratio of flow rates of oxidizing gas and reducing gas in plasma processing is determined by the conductive layer 113a and the conductive layer. This can be set according to the ease with which layer 113b and conductive layer 113c oxidize, however At the very least, it is preferable to keep the flow rate of the reducing gas below the flow rate of the oxidizing gas. Oxidizing gas If the flow rate of the reducing gas is too low relative to the flow rate of the conductive layer, the oxidation reaction on the surface of the conductive layer 113b will occur. This becomes advantageous, and oxides are more likely to form on the surface. On the other hand, the reduction in relation to the flow rate of the oxidizing gas... If the flow rate of the chemical gas is too high, the surface of the semiconductor layer 108 will be reduced, and the semiconductor There is a risk that reducing gas components (e.g., hydrogen) may be supplied into layer 108.

[0333] In plasma processing, the flow rate of the reducing gas relative to the flow rate of the oxidizing gas is within the range described above. It is preferable to do so. During plasma treatment, conductive layer 113c, conductive layer 113b, and conductive layer 1 The surface of 13a is also exposed to plasma 130, but the gas used for plasma treatment is a reducing gas. Because it is present, even if the surface is oxidized, it is immediately reduced, resulting in the formation of an oxide. This suppresses the occurrence of copper, aluminum, etc. in the conductive layer 113b. Even when using materials that are easily oxidized, the oxidation of the conductive layer 113b is suppressed. Furthermore, it effectively removes water, hydrogen, organic components, etc., adsorbed on the surface of the semiconductor layer 108. Cut.

[0334] Here, we will explain the case where the gas used for plasma treatment does not contain a reducing gas. If a reducing gas is not present, when the conductive layer 113b is exposed to plasma, the conductive layer 113b Oxide may form in some areas. Oxidation may also occur in conductive layer 113a and conductive layer 113c. When pyramidal material is used, oxides will also be formed on its surface. Conductive layer 113 a. When one or more of the conductive layers 113b or 113c are oxidized, the resistance increases. This can negatively affect the electrical characteristics and reliability of the transistor. Also, conductive layer 113 a. The oxide formed on the surface of conductive layer 113b or conductive layer 113c is subjected to plasma treatment. During the process, or after the formation of the insulating layer 114, some of the material is scattered, contaminating the surface of the semiconductor layer 108b. In some cases, oxides adhering to semiconductor layer 108b act as either donors or acceptors. Because it can function in this way, it may negatively affect the electrical characteristics and reliability of the transistor. For example If copper elements diffuse into semiconductor layer 108, the copper elements will function as carrier traps. Electrical characteristics and reliability may be compromised.

[0335] On the other hand, when the gas used for plasma processing contains a reducing gas, conductive layer 113c, conductive layer 1 Even if the surfaces of 13b and the conductive layer 113a, particularly the side surface of the conductive layer 113b, are exposed, This suppresses oxidation of the surface. Therefore, conductive layers 112a and 112b are acidic. It suppresses the transformation of water and hydrogen adsorbed on the surface of the semiconductor layer 108, This allows for the removal of organic components and other substances, resulting in a highly reliable transistor.

[0336] Furthermore, it is preferable to adjust the plasma treatment time. If the plasma treatment time is long, acid The oxidation reaction by the oxidizing gas proceeds, affecting conductive layer 113a, conductive layer 113b, and conductive layer 113c In some cases, it may oxidize. Also, if the plasma treatment time is long, the second gas The reduction reaction proceeds, and in some cases the surface of the semiconductor layer 108 may be reduced. The Zuma treatment time is adjusted so that conductive layers 113a, 113b, and 113c are oxidized. It is preferable to suppress the reduction of the surface of the semiconductor layer 108. The rasma processing time is preferably, for example, 5 seconds to 180 seconds, and more preferably 10 A duration of 120 seconds or more is preferred, and more preferably 15 seconds or more and 60 seconds or less. It is desirable. By using the aforementioned processing time, it exhibits good electrical characteristics and reliable transients. It can be set to start.

[0337] [Formation of insulating layer 114] Next, the conductive layer 112a, conductive layer 112b, semiconductor layer 108, and insulating layer 106 are covered Thus, an insulating layer 114 is formed.

[0338] The insulating layer 114 is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to use an atmosphere containing oxygen. It is preferable to form it by plasma CVD in a controlled atmosphere. This results in fewer defects. It can be an insulating layer 114. Also, the insulating layer 114 releases a lot of ammonia, It is preferable that the release of nitrogen oxides is low. It is preferable that the release of ammonia is high and nitrogen oxides are low. By using an insulating layer 114 that emits less fumes, fluctuations in the transistor's threshold voltage are suppressed. This makes it possible to reduce variations in the electrical characteristics of the transistor.

[0339] The insulating layer 114 is an oxide film such as a silicon oxide film or a silicon oxide nitride film. This is called a plasma chemical vapor deposition (PECVD) apparatus, or simply a plasma CVD apparatus. It is preferable to form it using a silicon depositing gas. In this case, the raw material gas is a silicon depositing gas. It is preferable to use a mixed gas containing gas and an oxidizing gas. Furthermore, if the source gas is an It is preferable to include ammonia. The insulating layer 114 is formed using a mixed gas containing ammonia. This makes it possible to create an insulating layer 114 that releases a large amount of ammonia. The aforementioned gases can be used as the accumulating gas. The aforementioned gases can be used as the oxidizing gas. It is possible to be there.

[0340] For example, when silicon oxynitride is used as the insulating layer 114, for example, monosilane, An insulating layer 114 can be formed using a mixed gas containing nitrous oxide and ammonia.

[0341] In the formation of the insulating layer 114, the flow rate of the oxidizing gas relative to the flow rate of the depositing gas is within the range described above. It is preferable to keep it enclosed. Also, the flow rate of ammonia gas relative to the flow rate of oxidizing gas is as described above. It is preferable to set the flow rate within the aforementioned range. This allows for the use of an insulating layer 114, which reduces the emission of nitrogen oxides from the insulating layer 114. This allows for a transistor with small threshold voltage fluctuations. Also, the aforementioned gas flow By making it a quantity, even when the pressure inside the processing chamber is relatively high, the insulating layer 11 has few defects. It is possible to form 4.

[0342] The pressure inside the processing chamber during the formation of the insulating layer 114 is preferably within the range described above. By setting the force range, an insulating layer 114 with low nitrogen oxide emission and low defect rate is obtained. It can be formed.

[0343] The insulating layer 114 may be formed using a PECVD method with microwaves. A wave refers to a frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature. Furthermore, the electron energy is low. Also, the fraction used to accelerate electrons in the supplied power It has a low concentration and can be used for the dissociation and ionization of a larger number of molecules, and has a high density. It can excite plasma (high-density plasma). Therefore, to the surface to be formed and the deposits This allows for the formation of an insulating layer 114 with minimal plasma damage and fewer defects.

[0344] The insulating layer 114 is connected to the substrate 102 without exposing it to the atmosphere after the aforementioned plasma treatment. It is preferable to continue the formation process. For example, plasma treatment is performed using a film deposition apparatus for the insulating layer 114. It is preferable to do so. In this case, the plasma treatment is performed in the treatment chamber where the insulating layer 114 is formed. This is preferable. Alternatively, a processing chamber connected to the processing chamber via a gate valve or the like may be used. After the Zuma treatment, the material is transported to the processing chamber for the insulating layer 114 under reduced pressure without being exposed to the atmosphere. It may also be configured as such. Furthermore, the plasma treatment and the formation of the insulating layer 114 may be performed in the same apparatus and under the same treatment. When performing the process continuously in a room, it is preferable to perform the plasma treatment and the formation of the insulating layer 114 at the same temperature. It seems so.

[0345] When performing plasma processing and forming the insulating layer 114 using a plasma chemical vapor deposition apparatus. Let's use this as an example to explain. Here, the insulating layer 114 is silicon oxidnitride.

[0346] In plasma processing, nitrous oxide (N2O), which is an oxidizing gas, and a reducing gas are used. Using a mixed gas containing ammonia, in the formation of the insulating layer 114, the depositing gas is ammonia. A mixed gas containing nosilane, the oxidizing gas nitrous oxide (N2O), and ammonia. It can be used. Here, in plasma treatment and formation of the insulating layer 114, nitrous oxide ( Nitrous oxide (N2O) and ammonia can be used in common. Plasma treatment is performed using ) and ammonia, and then monosilane gas is flowed through. This allows for the formation of a more insulating layer 114. In this way, plasma processing and insulating can be performed continuously in the same processing chamber. Because the edge layer 114 can be formed, impurities at the interface between the semiconductor layer 108 and the insulating layer 114 can be eliminated. This allows for a reduction in the amount of material present and creates a good interface.

[0347] After the formation of the insulating layer 114, a process of supplying oxygen to the insulating layer 114 may be performed. The supply process can be carried out using the same method as described above for the insulating layer 106.

[0348] [Formation of insulating layer 116] Next, an insulating layer 116 is formed to cover the insulating layer 114 (Figure 16A).

[0349] The insulating layer 116 uses an insulating film that is less permeable to the diffusion of oxygen, hydrogen, water, etc., than the insulating layer 114. This is preferable. Because the insulating layer 116 does not easily diffuse oxygen, the oxygen in the semiconductor layer 108 It is possible to prevent detachment to the outside via the insulating layer 114. Also, the insulating layer 116 is water By making it difficult for elements to diffuse, it prevents hydrogen, water, etc. from diffusing into the semiconductor layer 108 from the outside. It is possible.

[0350] It is preferable to perform a heat treatment after the formation of the insulating layer 116. By performing the heat treatment, the insulating layer Oxygen present in the margin layer 114 and the insulating layer 116 diffuses into the semiconductor layer 108, and this oxygen causes semiconducting Oxygen vacancies (V) in the conductive layer 108 O ) and V O H can be reduced (oxygenation). In terms of physical properties, oxygen diffused into semiconductor layer 108 creates an oxygen vacancy (V O ) to compensate for. Also, semiconductor The oxygen diffused into body layer 108 is V O It removes hydrogen from H and is eliminated as a water molecule (H2O), V O H is oxygen-deficient (V O ) And furthermore, V O Hydrogen was taken away from H. Oxygen deficiency (V) generated by O ) is filled by another oxygen that reaches semiconductor layer 108. Oxygen vacancies (V) in semiconductor layer 108 O ) and V O By reducing H, a highly reliable It can be configured as a lunger.

[0351] Oxygen diffused into semiconductor layer 108 reacts with hydrogen remaining in semiconductor layer 108 to form water molecules. It is eliminated as (H2O). In other words, hydrogen can be removed from semiconductor layer 108. Dehydration, dehydrogenation). This removes the hydrogen remaining in the semiconductor layer 108 from the oxygen vacancy (V O ) Combined with V OThis can suppress the generation of H.

[0352] By performing a heat treatment, hydrogen and water contained in the insulating layer 116 and insulating layer 114 can be removed. Furthermore, the heat treatment can reduce defects contained in the insulating layer 116 and the insulating layer 114. .

[0353] Furthermore, by heat treatment, the nitrogen oxides contained in insulating layer 114 and insulating layer 116 are removed. However, it reacts with the ammonia contained in the insulating layer 114, and is contained in the insulating layer 114 and insulating layer 116. The amount of nitrogen oxides produced is reduced. By reducing nitrogen oxides, the threshold of the transistor is reduced. It is possible to suppress voltage fluctuations and reduce variations in the electrical characteristics of the transistor. It is possible.

[0354] The heat treatment temperature is preferably 150°C or higher but below the strain point of the substrate, and more preferably 250°C or higher. A temperature of 450°C or lower is preferred, and more preferably 300°C to 450°C. The heat treatment is as follows: This can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Alternatively, an oxygen-containing atmosphere such as ultra-dry air (CDA: Clean Dry Air) can be used. It is acceptable to have them present. Furthermore, it is preferable that the atmosphere contains as little hydrogen, water, etc. as possible. As the atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is used. This is preferable. By using an atmosphere with the lowest possible content of hydrogen, water, etc., the insulating layer 11 It is possible to prevent hydrogen, water, etc. from being incorporated into the 6th grade as much as possible. Heat treatment is O oven, rapid thermal annealing (RTA) equipment, etc. It can be used. By using an RTA device, the heat treatment time can be shortened.

[0355] [Formation of insulating layer 118] Next, an insulating layer 118 is formed to cover the insulating layer 116 (Figure 16B).

[0356] The insulating layer 118 is less permeable to the diffusion of oxygen, hydrogen, water, etc. than the insulating layers 114 and 116. It is preferable to use an insulating film. Because the insulating layer 118 does not easily allow oxygen to diffuse, the insulating layer 1 16. This suppresses the detachment of oxygen from the insulating layer 114 and the semiconductor layer 108 to the outside. Furthermore, because the insulating layer 118 does not easily diffuse hydrogen, hydrogen, water, etc. from the outside can enter the semiconductor layer 108. This can suppress diffusion to other areas. Silicon nitride is particularly preferred as the insulating layer 118. It is possible.

[0357] [Formation of conductive layer 120a and conductive layer 120b] Next, by etching a portion of the insulating layer 118, insulating layer 116, and insulating layer 114 , opening 142a reaching the conductive layer 112b, and opening 142b reaching the conductive layer 104 To form.

[0358] Next, after forming a conductive film to cover the openings 142a and 142b, By processing the conductive film, conductive layers 120a and 120b can be formed. (Figure 17A).

[0359] By following the above steps, transistor 100A can be manufactured.

[0360] <Example of manufacturing method 2> The manufacturing method for transistor 100A is different from the manufacturing method shown in <Example Manufacturing Method 1> above. I will explain this. Note that I will omit explanations for parts that overlap with what was previously mentioned, and will only explain the parts that differ. I will explain about this.

[0361] First, the insulating layer 116 is formed in the same manner as in <Example of Manufacturing Method 1>. Since you can refer to the explanations in Figures 13A to 16A, a detailed explanation will be omitted. It is preferable to perform a heat treatment after the formation of the insulating layer 116. Regarding this heat treatment, see the above. Since you can refer to the description in <Example of Manufacturing Method 1>, a detailed explanation will be omitted.

[0362] Next, a metal oxide layer 150 is formed to cover the insulating layer 116 (Figure 18A).

[0363] The metal oxide layer 150 is formed from a material that is impermeable to oxygen and hydrogen. 150 indicates that the oxygen contained in insulating layers 114 and 116 is on the opposite side from semiconductor layer 108. It has the function of suppressing diffusion. In addition, the metal oxide layer 150 is protected from hydrogen and It has the function of suppressing the diffusion of water to the insulating layer 114 and insulating layer 116. The material layer 150 is less permeable to oxygen and hydrogen than at least the insulating layer 114 and the insulating layer 116. It is preferable to use pile material.

[0364] The metal oxide layer 150 may be an insulating layer or a conductive layer.

[0365] As the metal oxide layer 150, an insulating material with a higher dielectric constant than silicon oxide is used. This is preferable. For example, an aluminum oxide film, a hafnium oxide film, or hafnium aluminum. A nate film or the like can be used.

[0366] For example, the metal oxide layer 150 can be indium oxide, indium tin oxide (IT Conductive oxides such as 0), or silicon-containing indium tin oxide (ITSO), Objects can also be used.

[0367] As the metal oxide layer 150, an oxide material containing one or more of the same elements as the semiconductor layer 108 is used. It is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. The sputtering target used to form the metal oxide layer 150 is It is preferable that the atomic ratio of In is greater than or equal to the atomic ratio of M. As for the atomic ratio of metal elements in the GET, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M :Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1: 8. Examples include In:M:Zn=6:1:6 and In:M:Zn=5:2:5.

[0368] In particular, In-Ga-Zn oxide (IGZO) is preferably used as the metal oxide layer 150. This is possible. If the semiconductor layer 108 is an In-Ga-Zn oxide, then In-Ga-Zn oxide The sputtering target used to form the material has an atomic ratio of In to M. The above is preferable. The atomic ratio of metal elements in such a sputtering target. For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:G a:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3 , In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Z n=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In Examples include Ga:Zn=6:1:6 and In:Ga:Zn=5:2:5.

[0369] As the metal oxide layer 150, a sputtering target with the same composition as the semiconductor layer 108 is used. A metal oxide film formed using this method can be applied. By using a set, the manufacturing equipment and sputtering target can be standardized, which is preferable. It's nice.

[0370] Both the semiconductor layer 108 and the metal oxide layer 150 contain metal acids including indium and gallium. When using a gallium material, use a material with a higher gallium composition (content) than semiconductor layer 108. It can be used in the metal oxide layer 150. Materials with a high gallium composition (content) are used in gold By using it in the oxide layer 150, the blocking properties against oxygen can be further enhanced. This is preferable because it allows for this. At this time, the semiconductor layer 108 has more in than the metal oxide layer 150. By using a material with a high zinc composition, the field-effect mobility of transistor 100 can be increased. It is possible.

[0371] The metal oxide layer 150 is preferably formed using a sputtering apparatus. For example, When forming an oxide film using a puttering device, the film is formed in an atmosphere containing oxygen gas. This allows for the appropriate supply of oxygen to the insulating layer 116, the insulating layer 114, or the semiconductor layer 108. It is possible.

[0372] The metal oxide layer 150 is preferably formed in an atmosphere containing oxygen, for example. In particular, It is preferable to form it by sputtering in an oxygen-containing atmosphere. When the oxide layer 150 is formed, oxygen is supplied to the insulating layer 116, insulating layer 114, or semiconductor layer 108. They can provide it.

[0373] The metal oxide layer 150 is an oxide target containing a metal oxide, similar to the case of the semiconductor layer 108. The above can be applied when forming by sputtering using a tweezers.

[0374] For example, by using oxygen as the deposition gas and a metal target in a reactive sputtering method... A metal oxide layer 150 may be formed. For example, aluminum may be used as the metal target. When used, an aluminum oxide film can be formed.

[0375] When forming the metal oxide layer 150, the total flow rate of the film deposition gas introduced into the processing chamber of the film deposition apparatus is controlled by The higher the oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure inside the treatment chamber, the more the insulating layer 116 The amount of oxygen supplied can be increased. The oxygen flow ratio or oxygen partial pressure can be, for example, 50%. More than 100%, preferably 65% ​​to 100%, more preferably 80% to 10% The oxygen flow rate ratio should be 0% or less, more preferably 90% to 100%. In particular, the oxygen flow rate ratio should be 100%. It is preferable to bring the oxygen partial pressure as close to 100% as possible.

[0376] In this way, a metal oxide layer 150 is formed by sputtering in an oxygen-containing atmosphere. By doing so, oxygen is supplied to the insulating layer 116 when the metal oxide layer 150 is formed, and This prevents oxygen from detaching from the insulating layer 116. As a result, the insulating layer 116 It can trap an extremely large amount of oxygen. And, through subsequent heat treatment, the semiconductor layer This allows for a large supply of oxygen to 108. As a result, oxygen vacancies in semiconductor layer 108 can be eliminated. This allows for reduced costs and the creation of highly reliable transistors.

[0377] Next, by performing a heat treatment, oxygen is supplied from the insulating layer 116 to the semiconductor layer 108. This is preferable. The heat treatment is carried out in an atmosphere containing one or more of nitrogen, oxygen, and noble gases, at 200°C. This can be done at temperatures between ℃ and 400℃.

[0378] After forming the metal oxide layer 150, a heat treatment is performed before forming the insulating layer 118. This allows for effective oxygen supply from the insulating layer 116 to the semiconductor layer 108.

[0379] Next, the metal oxide layer 150 is removed (Figure 18B). The subsequent steps are preferably carried out at a temperature lower than or equal to the temperature of the heat treatment described above. This suppresses the desorption of oxygen from the semiconductor layer 108, resulting in an oxygen deficiency in the semiconductor layer 108. This can suppress the formation of losses. Therefore, the reliability of the transistor can be improved. Cut.

[0380] There are no particular limitations on the method for removing the metal oxide layer 150, but wet etching is preferably used. It is possible to do this. By using wet etching, the metal oxide layer 150 and the anodized layer can be etched simultaneously. Etching of the edge layer 116 can be suppressed. As a result, the thickness of the insulating layer 116 can be reduced. This can suppress the deterioration and make the film thickness of the insulating layer 116 uniform.

[0381] Next, an insulating layer 118 is formed. After the formation of the insulating layer 118, the process is carried out as described in <Example of Manufacturing Method 1>. Since the information can be found in the linked document, a detailed explanation will be omitted.

[0382] By following the above steps, transistor 100A can be manufactured.

[0383] <Example of manufacturing method 3> The following describes the method for fabricating transistor 100B as shown in the above-mentioned example configuration 2-3. I will clarify this. Note that I will omit explanations for parts that overlap with what was previously stated, and will only explain the parts that differ. do.

[0384] First, form the resist mask up to 140, similar to <Example of Fabrication Method 1>. For details on the formation of part 140, please refer to the explanations in Figures 13A to 14A. (This part is omitted.)

[0385] Next, using the resist mask 140 as a mask, conductive film 113cf, conductive film 113bf , and the conductive film 113af is etched. During this etching, the resist mask 140 Furthermore, the insulating layer 106b in the region that does not overlap with any of the semiconductor layers 108 is also removed (Figure 19A). ).

[0386] Next, a cleaning process is preferable. After the cleaning process, the process described in <Example of Manufacturing Method 1> above is followed. Detailed explanations will be omitted as they can be found in the documentation.

[0387] By following the above steps, transistor 100B can be fabricated (Figure 19B).

[0388] <Example of manufacturing method 4> The following describes the method for fabricating transistor 100C as shown in the above-mentioned example configuration 2-4. I will clarify this. Note that I will omit explanations for parts that overlap with what was previously stated, and will only explain the parts that differ. do.

[0389] First, similar to <Example of fabrication method 1>, metal oxide film 108af and metal oxide film 108b Formation continues up to f. The formation of metal oxide films 108af and 108bf is shown in Figure Detailed explanations are omitted as they can be found in the explanations for 13A and Figure 13B.

[0390] Next, after the formation of metal oxide films 108af and 108bf, the metal oxide film A resist mask is formed on 108bf, and the resist mask is used as a mask for metal oxide The film 108af and the metal oxide film 108bf are etched to form the semiconductor layer 108. During this etching process, the insulating layer 106b in areas that do not overlap with the resist mask is also removed. (Figure 20A). Then, the resist mask is removed.

[0391] After forming the metal oxide film 108af and the metal oxide film 108bf, or the semiconductor layer 1 After processing in step 08, heat treatment may be performed. After heat treatment, follow the above-mentioned <Example of Manufacturing Method 1>. Since you can refer to the information provided, a detailed explanation will be omitted.

[0392] By following the above steps, transistor 100C can be fabricated (Figure 20B).

[0393] According to the transistor fabrication method illustrated here, the insulating layer 11 in contact with the semiconductor layer 108 As for point 4, by using a membrane that releases a lot of ammonia and little nitrogen oxides, This suppresses fluctuations in the transistor's threshold voltage, resulting in good electrical characteristics and high reliability. It is possible to fabricate transistors that achieve this property.

[0394] The above is an explanation of an example of a transistor manufacturing method.

[0395] <Example configuration variations> The following describes variations of the transistor configuration example shown above.

[0396] [Variation 1] The transistor 100D shown in Figures 21A and 21B consists of conductive layer 112a and conductive layer 11 In that 2b does not have a layered structure and has a single-layer structure, the transition shown in the above-mentioned configuration example 2-1 It differs primarily from the Ta100.

[0397] By making the conductive layer 112a and conductive layer 112b a single-layer structure, the manufacturing process is simplified. This can be done and productivity can be improved. Conductive layer 112a and conductive layer 112b are It is preferable to use a conductive material containing copper, silver, gold, or aluminum.

[0398] [Variation 2] The transistor 100E shown in Figures 21C and 21D consists of conductive layer 112a and conductive layer 11 In addition to 2b, the semiconductor layer 108 does not have a stacked structure but a single-layer structure, as described above. It differs primarily from transistor 100 illustrated in Example 2-1.

[0399] In addition to conductive layers 112a and 112b, the semiconductor layer 108 is made into a single layer structure. Productivity can be further increased. In this case, the semiconductor layer 108 has crystalline properties. It is preferable to use a metal oxide film.

[0400] [Example 3] The transistor 100F shown in Figures 22A, 22B, and 22C has a conductive layer 120a and The position of the conductive layer 120b is different from the transistor 100 exemplified in the above-mentioned configuration example 2-2. It differs primarily from A.

[0401] The conductive layer 120a and the conductive layer 120b are located between the insulating layer 116 and the insulating layer 118. The conductive layer 120b has openings 142a provided in the insulating layer 114 and the insulating layer 116. It is electrically connected to the conductive layer 112b via this.

[0402] This configuration reduces the distance between the conductive layer 120a and the semiconductor layer 108. This allows for an improvement in the electrical characteristics of transistor 100F.

[0403] [Variation 4] The transistor 100G shown in Figures 23A, 23B, and 23C has an insulating layer 114. This is the main difference between this transistor and the transistor 100 exemplified in the aforementioned configuration example 2-1.

[0404] The insulating layer 114 is processed into an island-like shape that covers the channel formation region of the semiconductor layer 108. Furthermore, the edges of conductive layer 112a and conductive layer 112b located on the semiconductor layer 108 are insulating. It is located on layer 114. Therefore, the insulating layer 114 is a so-called channel protection layer. It functions, and during etching of conductive layer 112a and conductive layer 112b, the semiconductor layer 108 The channel side can be protected.

[0405] At this time, after etching the conductive layer 112a and conductive layer 112b, the above method is used. Further plasma treatment causes oxidation of conductive layer 112a and conductive layer 112b. This suppresses acid in the insulating layer 114 and through the insulating layer 114 into the semiconductor layer 108. It is possible to supply the raw materials. In addition, by performing heat treatment after plasma treatment, Alternatively, oxygen in the insulating layer 114 may be supplied to the semiconductor layer 108.

[0406] [Variation 5] The transistor 100H shown in Figures 24A, 24B, and 24C is composed of an insulating layer 114. This differs from the transistor 100G exemplified in the above modification 4, mainly in the way that it differs from the transistor 100G.

[0407] The insulating layer 114 is provided covering the semiconductor layer 108 and the insulating layer 106, etc. The edge layer 114 is the portion where the semiconductor layer 108 connects to the conductive layer 112a or the conductive layer 112b. An opening 142c is provided therein.

[0408] This configuration allows for finer transients than processing the insulating layer 114 into island shapes. It is possible to achieve this.

[0409] According to a method for manufacturing according to one aspect of the present invention, the insulating layer 114 in contact with the semiconductor layer 108 is A By using a film that emits a lot of nitrogen dioxide and a little nitrogen oxides, transistors This suppresses fluctuations in the threshold voltage, resulting in good electrical characteristics and high reliability. It is possible to fabricate transistors.

[0410] The above is an explanation of the variations.

[0411] <Application Examples> The following describes an example of applying the above transistor to the pixels of a display device.

[0412] Each figure in Figure 25 is a schematic top view showing a portion of the subpixels of the display device. One subpixel is , at least one transistor and a conductive layer (here, conductive layer 1) that functions as a pixel electrode 20b) has the following. For the sake of simplicity, here we will show an example of the configuration of some subpixels. However, depending on the type of display element applied to the sub-pixel, the function added to the pixel, etc., other Transistors, capacitive elements, etc., can be provided as appropriate.

[0413] In Figure 25A, a portion of the conductive layer 104 functions as a gate line (also called a scanning line), A portion of the conductive layer 112a functions as a source line (also called a video signal line), and the conductive layer 112 A portion of b functions as wiring that electrically connects the transistor and the conductive layer 120b.

[0414] In Figure 25A, the conductive layer 104 has an upper surface shape with a portion protruding, and the upper part of this protruding portion A semiconductor layer 108 is provided on top of this, forming a transistor.

[0415] Figures 25B and 25C show an example where the conductive layer 104 does not have any protruding portions. Figure 25B shows that the channel length direction of the semiconductor layer 108 and the stretching direction of the conductive layer 104 are parallel. This is just an example, and Figure 25C shows an example where these are orthogonal.

[0416] Figures 25D and 25E show that the conductive layer 112b has an arc-shaped or roughly arc-shaped portion. It has a U-shaped top surface. Also, conductive layer 112a and conductive layer 112b are connected to semiconductor layer 10 On 8, the two elements are arranged such that they are always equidistant. This makes it possible to increase the channel width of the transistor, allowing for larger currents. It can be flushed away.

[0417] Furthermore, a transistor according to one aspect of the present invention is suitable not only for display devices but also for various circuits and devices. It can be used in, for example, arithmetic circuits, memory circuits, drive circuits, and interface circuits. Circuits within IC chips mounted in electronic devices such as roads, or liquid crystal elements and organic EL displays. Display devices to which elements are applied, as well as touch sensors, optical sensors, and biosensors. It can be suitably used in drive circuits and other components of various sensor devices.

[0418] The above is an explanation of the application examples.

[0419] <Components of a semiconductor device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0420] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, a single crystal made of silicon or silicon carbide. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI groups Plates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used as substrate 102. It is also acceptable to have semiconductor elements mounted on these substrates as substrate 102. You may use it.

[0421] A flexible substrate is used as the substrate 102, and transistors 100, etc. are directly mounted on the flexible substrate. Alternatively, a release layer may be formed between the substrate 102 and the transistor 100, etc. The delamination layer is separated from the substrate 102 after the semiconductor device has been partially or completely completed on it. It can be separated and transferred to another substrate. In this case, transistor 100, etc., will withstand It can be transferred to substrates with poor thermal resistance or flexible substrates.

[0422] [Insulating layer 106] As the insulating layer 106, for example, an oxide insulating film or a nitride insulating film may be used as a single layer or in a multi-layer configuration. It can be formed. Furthermore, in order to improve the interface characteristics with the semiconductor layer 108, the insulating layer 1 In 06, it is preferable that at least the region in contact with the semiconductor layer 108 be formed of an oxide insulating film. Furthermore, it is preferable to use a film that releases oxygen when heated for the insulating layer 106. .

[0423] For example, the insulating layer 106 can be silicon oxide, silicon oxide nitride, silicon oxide nitride, or nitrile Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide These can be used, and the structure can be provided in a single layer or in multiple layers.

[0424] A film other than an oxide film, such as a silicon nitride film, is applied to the side of the insulating layer 106 that is in contact with the semiconductor layer 108. If used, the surface in contact with the semiconductor layer 108 is subjected to pretreatment such as oxygen plasma treatment. It is preferable to oxidize the surface or the vicinity of the surface.

[0425] [Conductive film] Conductive layers 104 and 120a function as gate electrodes, and 12 function as wiring. 0b, conductive layer 112a which functions as either a source electrode or a drain electrode, and source A conductive layer 112b, which functions as either an electrode or the other of a drain electrode, constitutes a semiconductor device. The conductive films include chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, and Metallic elements selected from tan, tungsten, manganese, nickel, iron, and cobalt, or Using an alloy containing the above-mentioned metal elements, or an alloy combining the above-mentioned metal elements, Each can be formed.

[0426] In particular, the conductive layer 112a, which functions as either the source electrode or the drain electrode, and the saw The conductive layer 112b, which functions as the other of the drain electrode or the other electrode, is made of copper, silver, gold, or It is preferable to use a low-resistance conductive material, such as aluminum. In particular, copper, Aluminum is preferred because it is excellent for mass production.

[0427] The conductive film constituting the semiconductor device is In-Sn oxide, In-W oxide, In- W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In - Suitable for oxide conductors or metal oxide films such as Sn-Si oxide and In-Ga-Zn oxide. It can also be used.

[0428] Here, we will explain oxide conductors (OC). For example, an oxygen vacancy is formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancy. Then, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. It becomes conductive. A metal oxide that has been made conductive can be called an oxide conductor.

[0429] The conductive film constituting the semiconductor device includes the above-mentioned oxide conductor (metal oxide). A laminated structure of a film and a conductive film containing a metal or alloy may also be used. By using a film, wiring resistance can be reduced. In this case, as the gate insulating layer It is preferable to apply a conductive film containing an oxide conductor to the side that is in contact with the functional insulating layer.

[0430] Conductive layer 104, conductive layer 112a, and conductive layer 112b contain a Cu-X alloy film (where X is Mn). Ni, Cr, Fe, Co, Mo, Ta, or Ti may be applied. Cu-X alloy film By using this method, processing can be done using a wet etching process, thus reducing manufacturing costs. This becomes possible.

[0431] [Insulating layer 114, insulating layer 116] As an insulating layer 114 provided on the semiconductor layer 108, PECVD method, sputtering method Silicon oxide film, silicon oxide nitride film, aluminum oxide film formed by ALD method, etc. 3mm film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film , tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and ne An insulating layer containing one or more osiminal films can be used. In particular, by plasma CVD It is preferable to use the formed silicon oxide film or silicon oxide-nitride film. The margin layer 114 may be a laminated structure of two or more layers.

[0432] The insulating layer 116, which functions as a protective layer, is produced by PECVD, sputtering, and ALD. Silicon nitride film, silicon nitride film, aluminum nitride film, nitrogen An insulating layer containing one or more types of aluminum oxide films can be used. 6 may be a laminated structure of two or more layers.

[0433] [Semiconductor layer] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... For the sputtering target used, the atomic ratio of metal elements can be, for example, In:M:Z n=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M :Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In :M:Zn=10:1:1, In:M:Zn=10:1:2, In:M:Zn=10:1 :3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn =10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In :M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10 :1:15, or a range near these values, can be preferably used.

[0434] When the semiconductor layer 108 is indium oxide, spars used to deposit the indium oxide film Indium oxide can be used as the tarring target.

[0435] If the semiconductor layer 108 is an In-M oxide, the spars used to deposit the In-M oxide film For example, the atomic ratio of metal elements in the tarring target is In:M=2:1, In: M=7:2, In:M=5:1, In:M=7:1, In:M=10:1, or these The vicinity of can be suitably used.

[0436] When the semiconductor layer 108 is an In-Zn oxide, the In-Zn oxide is used to form the film. For example, the atomic ratio of metal elements in a sputtering target is In:Zn = 2:3. In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2 Preferably, In:Zn = 7:1, In:Zn = 14:1, or near these ratios are used. It is possible.

[0437] When a target containing a polycrystalline oxide is used as a sputtering target, the crystal This is preferable because it facilitates the formation of a semiconductor layer 108 having properties. The atomic ratio of 10⁸ is the atomic ratio of the metal elements contained in the above sputtering target. Includes a variation of plus or minus 40%. For example, the sputtering process used for semiconductor layer 108 When the composition of the film is In:Ga:Zn=5:1:3 (atomic ratio), the resulting semiconductor film is formed. The composition of layer 108 is close to In:Ga:Zn = 5:1:2.4 (atomic ratio). be.

[0438] Using the above target, sputtering is performed with the substrate temperature set to between 100°C and 130°C. The metal oxides formed by the ng process have an nc (nano crystal) structure and CAAC. It tends to adopt one of the crystal structures of the structure, or a structure in which both are present. On the other hand, the substrate At room temperature, the metal oxide formed by sputtering has a nc crystal structure. It's easy to understand.

[0439] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using metal oxides with a wider energy gap than silicon, This can reduce the transistor's off-current.

[0440] The above is an explanation of the constituent elements.

[0441] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0442] (Embodiment 3) In this embodiment, an example of a display device having a transistor as illustrated in the previous embodiment is provided. I will explain about this.

[0443] <Example Configuration> Figure 26A shows a top view of the display device 700. The display device 700 is sealed by a sealing material 712 It has a first substrate 701 and a second substrate 705 that are bonded together. In the region sealed by the second substrate 705 and the sealing material 712, the first substrate 701 A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided above. It can be displayed. Furthermore, the pixel section 702 is provided with multiple display elements.

[0444] In the portion of the first substrate 701 that does not overlap with the second substrate 705, FPC716 (FPC:F The FPC terminal section 708 to which the lexible printed circuit is connected It is provided. FPC716 is provided via FPC terminal section 708 and signal line 710 , the same as the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 Various signals are supplied to each of them.

[0445] Multiple gate driver circuits 706 may be provided. The path section 706 and the source driver circuit section 704 are each formed separately on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is on the first substrate 70 It can be implemented on 1 or on FPC716.

[0446] The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 have A transistor, which is a semiconductor device according to one aspect of the present invention, can be applied to the transistor. ru.

[0447] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. It is possible to use LEDs (Light Emitting Diodes) as light-emitting elements. de), OLED (Organic LED), QLED (Quantum-dot L Examples include self-luminous light-emitting elements such as EDs and semiconductor lasers. Also, shutter-type or optical interferometry MEMS (Micro Electro Mechanical Systems) (Systems) elements, microcapsule method, electrophoresis method, electrowetting Display elements using methods such as the GL method or the electronic powder fluid (registered trademark) method can also be used. Cut.

[0448] The display device 700A shown in Figure 26B uses a flexible resin instead of the first substrate 701. An example of a display device to which layer 743 is applied and which can be used as a flexible display. That is the case.

[0449] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. Furthermore, as shown in region P1 in Figure 26B, the pixel portion 702 and a part of the resin layer 743 It has a notched portion. The pair of gate driver circuit sections 706 are located in the pixel section 702 It is provided on both sides of the . The gate driver circuit section 706 is located at the corner of the pixel section 702. It is provided along an arc-shaped contour.

[0450] The resin layer 743 has a shape in which the portion where the FPC terminal portion 708 is provided protrudes. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, is folded to the back side in area P2 in Figure 26B. It can be folded back. By folding back a part of the resin layer 743, the FPC 716 can be folded back into the pixel section 70 With the display device 700A placed on top of the back of 2, it can be mounted on the electronic device. This allows for space-saving in electronic devices.

[0451] The FPC716 connected to the display device 700A has the IC717 mounted on it. 717 has a function, for example, as a source driver circuit. At this time, the display device 700 The source driver circuit section 704 in B includes a protection circuit, a buffer circuit, and a demultiplexer. The configuration may include at least one circuit or the like.

[0452] The display device 700B shown in Figure 26C is suitable for use in electronic devices having a large screen. It is a display device capable of doing so. For example, television equipment, monitor equipment, personal computers Tablet devices (including notebook and desktop models), digital signage, etc. It can be suitably used for the following purposes.

[0453] The display device 700B consists of multiple source driver ICs 721 and a pair of gate driver circuits. It has part 722.

[0454] Multiple source driver IC721s are each attached to the FPC723. Furthermore, multiple FPC723s have one terminal connected to the first substrate 701 and the other terminal connected to the printed circuit board Each is connected to board 724. By bending FPC723, the printed circuit board 7 By placing 24 on the back side of the pixel unit 702, it can be mounted on electronic devices, reducing the size of the electronic device. This allows for a more controlled pace.

[0455] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to create electronic devices with even narrower bezels.

[0456] This configuration makes it possible to realize a large and high-resolution display device. For example, Surface size is 30 inches or more diagonally, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. Furthermore, resolutions such as 4K2K or 8K4K are also supported. This makes it possible to realize extremely high-resolution display devices.

[0457] <Example of cross-sectional configuration> In the following, Figures 27 to 27 show configurations using liquid crystal elements and electroluminescent elements as display elements. This will be explained using 31. Figures 27 to 30 are shown by the dashed line Q shown in Figure 26A, respectively. -This is a cross-sectional view at R. Also, Figure 31 shows one point in the display device 700A shown in Figure 26B. This is a cross-sectional view along the dashed line ST. Figures 27 to 29 show a display using a liquid crystal element. The configuration is as shown, and Figures 30 and 31 illustrate a configuration using an EL element.

[0458] [Explanation of common parts of display devices] The display device shown in Figures 27 to 31 comprises a wiring section 711, a pixel section 702, and a saw It has a screwdriver circuit section 704 and an FPC terminal section 708. The routing wiring section 711 is , has a signal line 710. The pixel section 702 has a transistor 750 and a capacitive element 790. The source driver circuit section 704 has a transistor 752. In Figure 28, the capacitance This shows the case where element 790 is absent.

[0459] Transistors 750 and 752 are the transistors exemplified in Embodiment 2. It can be applied.

[0460] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can reduce the off-current. Therefore, it can handle electrical signals such as image signals. The retention time for the signal can be extended, and the writing interval for the image signal can also be set to be longer. Therefore, This reduces the frequency of reshuffling, resulting in lower power consumption.

[0461] The transistor used in this embodiment can obtain relatively high field-effect mobility, High-speed driving is possible. For example, if such a high-speed driving transistor is used in a display device... This allows for the switching transistors in the pixel section and the driver transistors used in the drive circuit section. The inverter can be formed on the same substrate, that is, formed on a silicon wafer or the like. A configuration that does not apply the specified drive circuit is also possible, which reduces the number of components in the display device. It is possible. Furthermore, by using transistors capable of high-speed driving in the pixel section, high image quality can be achieved. We can provide images.

[0462] The capacitive element 790 shown in Figures 27, 30, and 31 is a gate of the transistor 750. A lower electrode formed by processing the same film as the source electrode, and a source electrode or drain electrode. It has an upper electrode formed by processing the same conductive film. It also has a lower electrode and an upper electrode. Between them, a portion of the insulating film, which functions as the gate insulating layer of transistor 750, is provided. In other words, the capacitive element 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. It has a layered structure.

[0463] A planarizing insulating film 7 is applied to transistors 750, 752, and capacitive element 790. 70 is provided.

[0464] The transistor 750 in the pixel section 702 and the source driver circuit section 704 Transistors with different structures than the 752 transistor may be used. For example, any one of them A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. A configuration using the above gate driver circuit section 706 may also be used. This is the same as the IBA circuit section 704.

[0465] Signal line 710 is the same as the source and drain electrodes of transistors 750 and 752. It is formed of a conductive film. In this case, if a low-resistance material such as a material containing copper elements is used, This is preferable because it minimizes signal delays caused by line resistance, allowing for display on a large screen.

[0466] The FPC terminal section 708 includes a connecting electrode 760, an anisotropic conductive film 780, and an FPC 716. The connecting electrode 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780. They are connected. Here, the connecting electrode 760 is the source electrode of transistors 750 and 752. It is formed from the same conductive film as the electrodes and drain electrodes.

[0467] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. Flexible substrates such as acrylic substrates can be used. When using a substrate, water or hydrogen is placed between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer that has barrier properties against [the element].

[0468] On the second substrate 705 side, there is a light-shielding layer 738, a coloring layer 736, and an insulating layer 7 in contact with them. 34 and are provided.

[0469] [Example configuration of a display device using liquid crystal elements] The display device 700 shown in Figure 27 has a liquid crystal element 775 and a spacer 778. The subunit 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The electrode layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planar insulating film 770 and functions as a pixel electrode. ru.

[0470] The conductive layer 772 may be made of a material that is transparent to visible light or a material that is reflective to visible light. Yes, it is possible. For example, an oxide material containing indium, zinc, tin, etc., can be used as a translucent material. It would be good to have one. For example, using a reflective material containing aluminum, silver, etc. would be beneficial. stomach.

[0471] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, if a translucent material is used for the conductive layer 772, a transmissive liquid crystal display device is obtained. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device... A pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0472] The display device 700 shown in Figure 28 uses a transverse electric field method (for example, FFS mode) liquid crystal element 77 An example using 5 is shown. A common electrode is formed on the conductive layer 772 via an insulating layer 773. A conductive layer 774 is provided. Due to the electric field generated between the conductive layer 772 and the conductive layer 774, The orientation state of the liquid crystal layer 776 can be controlled.

[0473] In Figure 28, the laminated structure of conductive layer 774, insulating layer 773, and conductive layer 772 provides retention capacity. It can be configured in terms of quantity. Therefore, there is no need to provide a separate capacitive element, and the aperture ratio can be increased. It is possible.

[0474] Although not shown in Figures 27 and 28, the configuration includes an alignment film in contact with the liquid crystal layer 776. This is also fine. In addition, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, and Light sources such as backlights and sidelights can be provided as needed.

[0475] The liquid crystal layer 776 contains thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersion liquid. Crystal (PDLC: Polymer Dispersed Liquid Crystal) Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0476] The modes of liquid crystal elements include TN (Twisted Nematic) mode and VA (V (Certical Alignment) mode, IPS (In-Plane-Switc Fing mode, FFS (Fringe Field Switching) mode, ASM(Axially Symmetric aligned Micro-cell ) Mode, OCB (Optically Compensated Birefringence) ence) mode, ECB (Electrically Controlled Bir You can use modes such as efringence mode and guest host mode.

[0477] A scattering type liquid crystal layer 776 using polymer dispersed liquid crystal or polymer network liquid crystal It is also possible to use a liquid crystal. In this case, a configuration that displays in black and white without providing a colored layer 736 is also possible. Alternatively, a configuration may be used in which a colored layer 736 is used to display color.

[0478] As a method for driving liquid crystal elements, color display is performed based on the time-division table, which uses a time-division table. A display method (also called a field sequential drive method) may be applied. In that case, A configuration without color layer 736 is possible. When using a time-division display method, for example, There is no need to provide subpixels that exhibit the respective colors R (red), G (green), and B (blue). Therefore, it offers advantages such as improving the aperture ratio of pixels and increasing the resolution.

[0479] Unlike the display device 700 shown in Figure 28, this liquid crystal element uses a transverse electric field method (for example, FFS mode). An example using child 775 is shown in Figure 29.

[0480] The display device 700 shown in Figure 29 has a trap between the first substrate 701 and the second substrate 705. It has an array 750, a transistor 752, a liquid crystal element 775, etc. The first substrate 701 and The second substrate 705 is bonded to the first substrate by a sealing layer 732.

[0481] The liquid crystal element 775 has a conductive layer 714, a liquid crystal layer 776, and a conductive layer 713. Layer 713 is provided on the first substrate 701. One or more insulating layers are provided on the conductive layer 713. A conductive layer 714 is provided on the insulating layer. Furthermore, the liquid crystal layer 776 is connected to the conductive layer 714. It is located between the second substrate 705. The conductive layer 713 is electrically connected to the wiring 728 and It functions as a conductive electrode. The conductive layer 714 is electrically connected to the transistor 750 and the pixel It functions as an electrode. A common potential is applied to wiring 728.

[0482] The conductive layer 714 has a comb-like or slit-like upper surface shape. Liquid crystal element 775 The orientation state of the liquid crystal layer 776 is affected by the electric field generated between the conductive layer 714 and the conductive layer 713. It is controlled.

[0483] The laminated structure consists of a conductive layer 714, a conductive layer 713, and one or more insulating layers sandwiched between them. Therefore, a capacitive element 790 that functions as a holding capacitance is formed. This eliminates the need to install a shim and allows for a higher opening ratio.

[0484] The conductive layer 714 and the conductive layer 713 are made of a material that is transparent to visible light, or a material that is transparent to visible light. Translucent materials can be used. Examples of translucent materials include indium, zinc, and s It is preferable to use oxide materials containing ions, etc. Examples of reflective materials include aluminum and silver. It is recommended to use materials containing the following:

[0485] A reflective material is used in either the conductive layer 714 or the conductive layer 713, or in both. Thus, the display device 700 becomes a reflective liquid crystal display device. On the other hand, the conductive layer 714 or conductive layer 7 If light-transmitting materials are used for both of the 13 components, the display device 700 becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device... In this case, a pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0486] Figure 29 shows an example of a transmissive liquid crystal display device. Outside the first substrate 701 A polarizing plate 755 and a light source 757 are provided, and the polarizing plate 755 is located outside the second substrate 705. A 6 is provided. The light source 757 functions as a backlight.

[0487] On the side of the second substrate 705 facing the first substrate 701, there is a light-shielding layer 738 and a coloring layer 736. It is provided. It also covers the light-shielding layer 738 and the colored layer 736 and functions as a planarizing layer. An insulating layer 734 is provided. On the surface of the insulating layer 734 facing the first substrate 701, a spacer is provided. 727 is provided.

[0488] The liquid crystal layer 776 consists of an alignment film 725 covering the conductive layer 714 and an alignment film 72 covering the insulating layer 734. It is located between 6. Note that the alignment film 725 and alignment film 726 may be omitted if they are not needed. It's fine.

[0489] Although not shown in Figure 29, a phase difference film and an anti-reflective film are located outside the second substrate 705. Appropriately provide optical components such as films (optical films), protective films, anti-fouling films, etc. It is possible. As an anti-reflective film, AG (Anti Glare) film, AR (Anti-reflective) films are available, among others.

[0490] The display device 700 shown in Figure 29 includes a conductive layer 714 that functions as a pixel electrode, and a common electrode. An organic insulating film, which functions as a planarizing layer, is provided on the side of the conductive layer 713 that is formed. It has a configuration. In addition, the transistor 750 and the like of the display device 700 are manufactured in the manufacturing process. A bottom-gate transistor is used, which allows for a relatively short length. This reduces manufacturing costs and increases manufacturing yield, and improves reliability. This makes it possible to provide high-quality display devices at a low cost.

[0491] [Example of a display device configuration using light-emitting elements] The display device 700 shown in Figure 30 has a light-emitting element 782. The light-emitting element 782 is a conductive layer It has 772, an EL layer 786, and a conductive film 788. The EL layer 786 is an organic compound, and It contains inorganic compounds such as quantum dots.

[0492] Examples of materials that can be used with organic compounds include fluorescent materials or phosphorescent materials. Furthermore, colloidal quantum dot materials can be used as materials for quantum dots. alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc. These are some examples.

[0493] The display device 700 shown in Figure 30 has a conductive layer 772 covering a portion of the planar insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788, This is a top-emission type light-emitting element. The light-emitting element 782 emits light towards the conductive layer 772. The bottom emission structure that is ejected emits light, and light is emitted to both the conductive layer 772 side and the conductive film 788 side. It may also be a dual-emission structure.

[0494] The colored layer 736 is provided in a position that overlaps with the light-emitting element 782, and the light-shielding layer 738 is an insulating film 730 It is located in a position that overlaps with the above, and is provided in the routing wiring section 711 and the source driver circuit section 704. Furthermore, the colored layer 736 and the light-shielding layer 738 are covered with an insulating layer 734. The space between element 782 and insulating layer 734 is filled with sealing layer 732. Furthermore, the EL layer 786 is When forming island-like structures for each pixel or striped structures for each row of pixels, that is, when forming them by color separation: In this case, a configuration without a colored layer 736 is also possible.

[0495] Figure 31 shows a display device configuration that is suitably applicable to a flexible display. Figure 31 is a cross-sectional view of the display device 700A shown in Figure 26B along the dashed line ST. be.

[0496] The display device 700A shown in Figure 31 replaces the first substrate 701 shown in Figure 30 with a support base The structure has a laminated configuration consisting of a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744. The transistor 750 and the capacitive element 790 are located on the insulating layer 744 provided on the resin layer 743. It is located at [location].

[0497] The support substrate 745 is a substrate containing organic resin, glass, etc., and is thin enough to be flexible. The resin layer 743 is a layer containing organic resins such as polyimide and acrylic. Insulating layer 744 This includes an inorganic insulating film such as silicon oxide, silicon oxide nitride, and silicon nitride. Resin layer 74 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferable that the substrate is thinner than the support substrate 745.

[0498] The display device 700A shown in Figure 31 replaces the second substrate 705 shown in Figure 30 with a protective layer 7 It has 40. The protective layer 740 is bonded to the sealing layer 732. Furthermore, glass substrates and resin films can be used. Also, as the protective layer 740, Optical components such as polarizing plates and scattering plates, input devices such as touch sensor panels, or these A configuration with two or more layers stacked on top of each other may also be applied.

[0499] The EL layer 786 of the light-emitting element 782 is provided in an island-like manner on the insulating film 730 and the conductive layer 772. It is made that the EL layer 786 is made so that each sub-pixel emits a different color of light. Color display can be achieved without using the color layer 736. Also, the light-emitting element 782 is covered. A protective layer 741 is provided. The protective layer 741 protects the light-emitting element 782 from impurities such as water. It has the function of preventing diffusion. It is preferable that the protective layer 741 be an inorganic insulating film. Furthermore, a laminated structure containing one or more inorganic insulating films and one or more organic insulating films is more preferable. stomach.

[0500] Figure 31 shows the foldable region P2. In region P2, the support substrate 745, In addition to the adhesive layer 742, there are portions where no inorganic insulating film such as an insulating layer 744 is provided. Furthermore, in region P2, a resin layer 746 is provided covering the connecting electrode 760. In the region P2 where it is possible to do so, no inorganic insulating film is provided, and a conductive layer containing a metal or alloy and an organic material are provided. By constructing a structure in which only layers containing the material are laminated, cracks are prevented from occurring when the material is bent. This is possible. Furthermore, by not providing a support substrate 745 in region P2, an extremely small radius of curvature can be achieved. Therefore, a part of the display device 700A can be bent.

[0501] [Example of a configuration in which an input device is provided to the display device] Input to the display device 700 shown in Figures 27 to 30, or the display device 700A shown in Figure 31. A device may be provided. Examples of such input devices include touch sensors.

[0502] For example, sensor types include capacitive, resistive, surface acoustic wave, and infrared. Various methods can be used, such as optical and pressure-sensitive methods. Or, two or more of these can be used. They may be used in combination.

[0503] Furthermore, the touch panel configuration involves forming the input device inside a pair of circuit boards, a so-called in-cell design. A type of touch panel, an input device formed on the display device 700, a so-called on-cell type touch panel A so-called out-cell type touch panel that is attached to a panel or display device 700. There is.

[0504] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0505] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0506] (Embodiment 4) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figure 32A. Further explanation will be provided using Figure 32C.

[0507] The display device shown in Figure 32A comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0508] Transistors in the pixel section 502 and the drive circuit section 504 are configured according to one aspect of the present invention. A transistor can be applied. Also, a transistor according to one aspect of the present invention can be applied to the protection circuit 506. You may apply this.

[0509] The pixel section 502 is arranged in X rows and Y columns (where X and Y are independent natural numbers greater than or equal to 2). It has several pixel circuits 501. Each pixel circuit 501 is a circuit that drives a display element. To possess.

[0510] The drive circuit section 504 outputs a scanning signal to the gate lines GL_1 to GL_X. Source driver 504a, which supplies data signals to data lines DL_1 to DL_Y. It has a drive circuit such as 04b. The gate driver 504a has at least a shift register The configuration should include, for example, multiple analog switches. It is constructed using switches, etc. Furthermore, it uses shift registers, etc., to configure the source driver 504 You may also construct b.

[0511] The terminal section 507 inputs power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0512] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires. The protection circuit 506 shown in Figure 32A is, for example, The gate lines GL_1 to G are the wiring between the gate driver 504a and the pixel circuit 501. L_X, or data line DL, is the wiring between source driver 504b and pixel circuit 501. It is connected to various wirings such as _1 to DL_Y. Note that in Figure 32A, the protection circuit 506 and Hatching is applied to the protection circuit 506 to distinguish it from the basic circuit 501.

[0513] The gate driver 504a and the source driver 504b are based on the same base as the pixel unit 502. It may be provided on the board, or the gate driver circuit or source driver circuit may be provided separately. The completed substrate (for example, a drive circuit substrate formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) Mounted on the circuit board using COG or TAB (Tape Automated Bonding). This configuration is also acceptable.

[0514] The multiple pixel circuits 501 shown in Figure 32A have, for example, the configurations shown in Figures 32B and 32C. It is possible.

[0515] The pixel circuit 501 shown in Figure 32B consists of a liquid crystal element 570, a transistor 550, and a capacitive element. It has a sub-unit 560 and a gate line GL_m. The pixel circuit 501 also has a data line DL_n and a gate line GL_m The potential supply line VL and other connections are connected.

[0516] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 in each row One of the electrodes may be given a different potential.

[0517] The pixel circuit 501 shown in Figure 32C consists of transistors 552 and 554, and a capacitive element 562. The pixel circuit 501 also has a data line DL_n and a gate line. GL_m, potential supply line VL_a, potential supply line VL_b, etc. are connected.

[0518] Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied to the gate of transistor 554. Depending on the potential, the current flowing through the light-emitting element 572 is controlled, thereby controlling the light-emitting element 5 The luminescence is controlled from 72 onwards.

[0519] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0520] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0521] (Embodiment 5) Below, we have a pixel circuit equipped with memory for correcting the gradation displayed in the pixel, and this The display device will be described below. The transistor exemplified in Embodiment 2 is exemplified below. This can be applied to transistors used in pixel circuits.

[0522] <Circuit Configuration> Figure 33A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 consists of transistor M1, It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 also has wiring S1, wiring S2, wiring G1, and wiring G2 are connected.

[0523] Transistor M1 has its gate connected to wiring G1, and one of its sources or drains connected to wiring S1. The other end is connected to one electrode of capacitance C1. Transistor M2 has a gate that is wired G2, one of the source and drain is connected to wiring S2, the other electrode is connected to capacitance C1, and rotation It connects to Route 401, respectively.

[0524] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While various types can be used, typically light-emitting elements such as organic EL elements and LED elements, and liquid crystal elements are used. Child, or MEMS (Micro Electro Mechanical System) ms) elements and the like can be applied.

[0525] The node connecting transistor M1 and capacitor C1 is N1, and transistor M2 and circuit 40 Let N2 be the node connecting to node 1.

[0526] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. It can be maintained. Also, by turning off transistor M2, the power of node N2 can be controlled. It can maintain its position. Also, with transistor M2 in the OFF state, By writing a predetermined potential to node N1 via station M1, capacitive coupling via capacitor C1 is achieved. This allows the potential of node N2 to be changed in accordance with the potential displacement of node N1.

[0527] Here, in the embodiment, one or both of transistors M1 and M2 are The transistor using oxide semiconductors, as exemplified in 2, can be applied. Therefore, the extremely low off-current maintains the potential of nodes N1 and N2 for a long period of time. This is possible. However, if the period for which the potential of each node is maintained is short (specifically, the frame When the frequency is 30Hz or higher, a transistor using a semiconductor such as silicon is used. You may also use "ta".

[0528] <Example of driving method> Next, an example of how the pixel circuit 400 operates will be explained using Figure 33B. This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and transistors The effects of the threshold voltage of the staccato are not considered.

[0529] In the operation shown in Figure 33B, one frame period is divided into period T1 and period T2. Period T1 Period T2 is the period during which the potential is written to node N2, and period N1 is the period during which the potential is written to node N1. That is the case.

[0530] [Period T1] During period T1, a potential is applied to both wire G1 and wire G2 that turns the transistor ON. Also, the wiring S1 has a fixed potential V ref It supplies the first day to wiring S2. Potential V w To supply.

[0531] The node N1 is supplied with the potential V from the wiring S1 via the transistor M1. ref is applied. Also, the node N2 is supplied with the first data potential V via the transistor M2. w is applied. Thus the potential difference V w -V ref is held in the capacitor C1.

[0532] 〔Period T2〕 Subsequently, in period T2, a potential for turning on the transistor M1 is applied to the wiring G1, and a potential for turning off the transistor M2 is applied to the wiring G2. Also, the second data potential V is supplied to the wiring S1. A predetermined fixed potential is applied to the wiring S2, or it may be floating. -V data is supplied. A predetermined fixed potential is applied to the wiring S2, or it may be floating. is acceptable.

[0533] The node N1 is supplied with the second data potential V via the transistor M1. data is applied. At this time, due to the capacitive coupling by the capacitor C1, the potential of the node N data 2 changes by the potential dV according to the second data potential V. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Although dV is shown as a positive value in FIG. 33B, it may be a negative value. That is, the second data potential V may be lower than the potential V data is. V ref is also acceptable.

[0534] Here, the potential dV is generally determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes a potential close to the second data potential V. is determined. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes a potential close to the second data potential V. -V data is close to a potential.

[0535] Thus, since the pixel circuit 400 can generate a potential for supplying two types of data signals to the circuit 401 including the display element, it is possible to perform gradation correction within the pixel circuit 400. 路401に供給する電位を生成することができるため、画素回路400内で階調の補正を 行うことが可能となる。

[0536] The pixel circuit 400 can also generate a potential exceeding the maximum potential that can be supplied to the wiring S1 and the wiring S2. For example, in the case of using a light-emitting element, high dynamic range (HDR) display or the like can be performed. Also, in the case of using a liquid crystal element, overdrive driving or the like can be realized. ることも可能となる。例えば発光素子を用いた場合では、ハイダイナミックレンジ(HD R)表示等を行うことができる。また、液晶素子を用いた場合では、オーバードライブ駆 動等を実現できる。

[0537] <Application Example> [Example Using a Liquid Crystal Element] The pixel circuit 400LC shown in FIG. 33C has a circuit 401LC. The circuit 401LC has a liquid crystal element LC and a capacitor C2. 液晶素子LCと、容量C2とを有する。

[0538] One electrode of the liquid crystal element LC is connected to the node N2 and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which a potential V 電位V com2 が与えられる配線と接続する。容量C2は、他方の電極が電位V com1 が与えられる配線と接続する。

[0539] The capacitor C2 functions as a holding capacitor. If the capacitor C2 is not necessary, it can be omitted. きる。

[0540] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example, high-speed display can be realized by overdrive driving, and a liquid crystal material with a high driving voltage can be applied. Also, by supplying a correction signal to the wiring S1 or the wiring S2, gradation can be corrected according to the use temperature, the deterioration state of the liquid crystal element LC, etc. オーバードライブ駆動により高速な表示を実現すること、駆動電圧の高い液晶材料を適用 することなどができる。また、配線S1または配線S2に補正信号を供給することで、使 用温度や液晶素子LCの劣化状態等に応じて階調を補正することもできる。

[0541] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 33D has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0542] Transistor M3 has a gate that connects to one electrode of node N2 and capacitance C2, and a source and a dot. One end of the wire is a wire to which a potential VH is applied, and the other end is one electrode of the light-emitting element EL, and They are connected. Capacitor C2 is connected when the other electrode is at potential V com Connect to the provided wiring. In the light-emitting element (EL), the other electrode is at potential V L Connect to the provided wiring.

[0543] Transistor M3 has the function of controlling the current supplied to the light-emitting element EL. Capacitor C2 This functions as a holding capacity. Capacity C2 can be omitted if it is not needed.

[0544] Note that this configuration shows the anode side of the light-emitting element EL connected to transistor M3. However, transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0545] The pixel circuit 400EL generates light by applying a high potential to the gate of transistor M3. Because it can supply a large current to the sub-EL, it can enable features such as HDR display. It can be done. Also, by supplying a correction signal to wiring S1 or wiring S2, the transistor It can also correct for variations in the electrical characteristics of M3 and light-emitting elements (EL).

[0546] Note that the circuits are not limited to those illustrated in Figures 33C and 33D, and may also include transistors, capacitors, etc. A configuration with the addition of this element is also acceptable.

[0547] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0548] (Embodiment 6) In this embodiment, a display module that can be manufactured using one aspect of the present invention is provided. I will explain.

[0549] The display module 6000 shown in Figure 34A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006, frame 6009, and print, with the FPC6005 connected. It has a circuit board 6010 and a battery 6011.

[0550] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of an extremely low-power display module. It is possible.

[0551] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as needed.

[0552] The display device 6006 may also have the functionality of a touch panel.

[0553] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0554] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It has a power processing circuit, a battery control circuit, etc. Even if the power supply is battery 6011. good.

[0555] Figure 34B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. ru.

[0556] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0557] The display device 6006 connects to the printed circuit board 6010 and the battery via the frame 6009. - It is installed overlapping with 6011. The display device 6006 and frame 6009 are connected to the light guide section 6 017a is fixed to the light guide section 6017b.

[0558] Light 6018 emitted from the light-emitting unit 6015 is directed to the display device 600 by the light guide unit 6017a. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or a stand Touch operation is detected when light 6018 is blocked by an object to be detected, such as an illustration. It is possible.

[0559] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0560] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0561] The light-emitting section 6015 and the light-emitting section 6015 are separated by the light-transmitting light-emitting section 6017a and light-transmitting section 6017b. The light receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light receiving unit 601 Reaching 6 can suppress the malfunction of the touch sensor. In particular, it absorbs visible light and infrared light. Using a resin that allows light to pass through can more effectively suppress malfunctions in touch sensors.

[0562] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0563] (Embodiment 7) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0564] The electronic device 6500 shown in Figure 35A is a portable device that can be used as a smartphone. It is a news terminal device.

[0565] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0566] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0567] Figure 35B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0568] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0569] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0570] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is there. Also, the FPC6515 is connected to the folded portion. FPC651 IC6516 is mounted on board 5. FPC6515 is mounted on printed circuit board 6517. It is connected to a terminal provided there.

[0571] A flexible display panel according to one aspect of the present invention is applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 651 Because it is extremely thin, it allows for a reduction in the thickness of electronic devices while incorporating a large-capacity 6518 battery. It is also possible to fold back a portion of the display panel 6511 and place an FPC on the back of the pixel area. By positioning the connection point with 6515, it is possible to realize electronic devices with narrow bezels.

[0572] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0573] (Embodiment 8) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0574] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0575] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0576] Examples of electronic devices include television equipment, notebook personal computers, and more. Features include relatively large screens such as those found on NITA devices, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and mobile phones Examples include telephones, portable game consoles, personal digital assistants, and audio playback devices.

[0577] An electronic device to which one aspect of the present invention is applied includes the interior or exterior walls of houses and buildings, the interior of automobiles, etc. It can be incorporated along the flat or curved surfaces of the fittings or exterior.

[0578] Figure 36A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0579] The television device 7100 shown in Figure 36A is operated by the operation switches provided on the housing 7101. This can be done by using the remote control unit 7111 or by using the display unit 7500. A touch panel can be applied to it, allowing the television device 7100 to be operated by touching it. The remote control unit 7111 may have a display unit in addition to the operation buttons.

[0580] The television equipment 7100 is a television broadcast receiver and for network connectivity. It may have a communication device.

[0581] Figure 36B shows the notebook personal computer 7200. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0582] Figures 36C and 36D show digital signage. An example of a small sign is shown.

[0583] The digital signage 7300 shown in Figure 36C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0584] Figure 36D shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7500 that is installed along the curved surface of the column 7401. To possess.

[0585] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0586] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows for use not only in advertising but also in route information, traffic information, and commercial facility information. It can also be used to provide information that users are seeking.

[0587] As shown in Figures 36C and 36D, the digital signage 7300 or digital signage The Neige 7400 communicates wirelessly with information terminals 7311 such as smartphones owned by the user. It is preferable that the information displayed on the display unit 7500 is linked. To display this on the screen of the information terminal 7311, or by operating the information terminal 7311 The display on the 7500 display unit can be switched.

[0588] Digital signage 7300 or digital signage 7400, information terminal 731 It is also possible to run a game using 1 as the control device (controller). A large number of users can participate in and enjoy the game simultaneously.

[0589] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 36A to 36D. It is possible.

[0590] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied.

[0591] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination. [Explanation of symbols]

[0592] 10, 10A, 10B, 10C: Transistors, 11, 13, 15, 17: Ranges, 100 , 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H :transistor, 102:substrate, 104:conductive layer, 106, 106a, 106a1, 10 6a2, 106a3, 106b: insulating layer, 108, 108a, 108b: semiconductor layer, 10 8af, 108bf: metal oxide film, 112: gate electrode, 112a, 112b, 113 , 113a, 113b, 113c: conductive layer, 113af, 113bf, 113cf: conductive Film, 114, 116, 118: insulating layer, 120, 120a, 120b: conductive layer, 130: Plasma, 140: Resist mask, 142a, 142b, 142c: Aperture, 150: Metal oxide layer

Claims

1. A first conductive layer having the function of a transistor gate electrode, A first insulating layer having a region in contact with the upper surface of the first conductive layer, A semiconductor layer having a region located above the first conductive layer via the first insulating layer and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the semiconductor layer and functioning as either the source electrode or the drain electrode of the transistor, The present invention comprises a second insulating layer having a region located above the second conductive layer, The semiconductor layer comprises at least indium and oxygen. The second conductive layer has a laminated structure comprising a first conductive film, a second conductive film having a region located above the first conductive film, and a third conductive film having a region located above the second conductive film. A semiconductor device wherein the second insulating layer has a region in contact with the upper surface of the semiconductor layer, a region in contact with the upper surface of the first conductive film, a region in contact with the side surface of the first conductive film, a region in contact with the side surface of the second conductive film, a region in contact with the side surface of the third conductive film, and a region in contact with the upper surface of the third conductive film.

2. A first conductive layer having the function of a transistor gate electrode, A first insulating layer having a region in contact with the upper surface of the first conductive layer, A semiconductor layer having a region located above the first conductive layer via the first insulating layer and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the semiconductor layer and functioning as either the source electrode or the drain electrode of the transistor, The present invention comprises a second insulating layer having a region located above the second conductive layer, The semiconductor layer comprises at least indium and oxygen. The second conductive layer has a laminated structure comprising a first conductive film, a second conductive film having a region located above the first conductive film, and a third conductive film having a region located above the second conductive film. The second conductive film comprises copper, silver, gold, or aluminum. The first conductive film and the third conductive film each independently contain one of titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, and ruthenium. A semiconductor device wherein the second insulating layer has a region in contact with the upper surface of the semiconductor layer, a region in contact with the upper surface of the first conductive film, a region in contact with the side surface of the first conductive film, a region in contact with the side surface of the second conductive film, a region in contact with the side surface of the third conductive film, and a region in contact with the upper surface of the third conductive film.

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