Semiconductor equipment

Abstract

In a semiconductor device having an oxide semiconductor film, a transistor with excellent electrical characteristics is To provide a semiconductor device. [Solution] A semiconductor device having a transistor. The transistor has a gate electrode and A first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film, The source electrode and drain electrode each have a first conductive film and a first conductive film on the first conductive film. It has a second conductive film in contact with the second conductive film, and a third conductive film in contact with the second conductive film. The film contains copper, and the first conductive film and the third conductive film contain a material that suppresses the diffusion of copper. The edges of the conductive film 2 have regions containing copper and silicon.

Description

[Technical Field]

[0001] One aspect of the present invention is a semiconductor device having an oxide semiconductor film, and a semiconductor device having the said semiconductor device Regarding display devices.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Or, one aspect of the present invention. This refers to a process, machine, manufacture, or composition. Regarding the ter. Therefore, the technical aspects of one aspect of the present invention disclosed more specifically herein Examples include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, and memory devices. Examples include apparatus, imaging apparatus, their driving methods, or their manufacturing methods. It is possible.

[0003] In this specification, a semiconductor device is defined as a device that can function by utilizing semiconductor properties. This refers to all types of devices, including semiconductor elements such as transistors, semiconductor circuits, computing devices, and memory devices. The device is a form of semiconductor device. Examples include imaging devices, display devices, liquid crystal display devices, light-emitting devices, and electric devices. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic equipment are subject to the following regulations: It may have a semiconductor device. [Background technology]

[0004] A semiconductor film formed on a substrate is used to create a transistor (thin-film transistor (TFT) or The technology for constructing field-effect transistors (also known as FETs) is attracting attention. Indicators are widely used in electronic devices such as integrated circuits (ICs) and image devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor films applicable to transistors. While these materials are currently being used, oxide semiconductors are attracting attention as another material option.

[0005] For example, transistors were fabricated using an In-Ga-Zn oxide as an oxide semiconductor. A technology for doing so has been disclosed (see, for example, Patent Document 1).

[0006] Furthermore, aluminum has traditionally been widely used as a material for wiring and signal lines. However, there is a lot of development going on to use copper (Cu) to further reduce resistance. However, copper (Cu) has poor adhesion to the film used as the base material, and is also a semiconductor material for transistors. It has the disadvantage of easily diffusing into body membranes and degrading transistor characteristics.

[0007] Furthermore, as a material for ohmic electrodes formed on an oxide semiconductor film containing indium, A Cu-Mn alloy has been disclosed (see, for example, Patent Document 2). [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2007-96055 [Patent Document 2] International Publication No. 2012 / 002573 [Overview of the project] [Problems that the invention aims to solve]

[0009] According to the configuration described in Patent Document 2, a Cu-Mn alloy film is deposited on an oxide semiconductor film. Next, the Cu-Mn alloy film is heat-treated to bond the oxide semiconductor film and the Cu-Mn alloy film. A Mn oxide is formed at the interface. This Mn oxide is formed when Mn in the Cu-Mn alloy film becomes an oxide semi-oxide. It diffuses toward the conductive film and is formed by preferentially bonding with the oxygen that constitutes the oxide semiconductor film. Furthermore, the region in the oxide semiconductor film reduced by Mn becomes an oxygen vacancy, and carrier The concentration of A increases, resulting in high conductivity. Also, Mn diffuses toward the oxide semiconductor film, and Cu- By replacing the Mn alloy with pure Cu, an ohmic electrode with low electrical resistance is obtained.

[0010] However, in the above configuration, after forming the ohmic electrode, The effect of Cu diffusion from other sources is not considered. For example, Cu-Mn compound on an oxide semiconductor film. After forming electrodes containing a gold film, heat treatment is performed to combine the oxide semiconductor film with the Cu-Mn compound. Mn oxide is formed at the bonding interface with the gold film. The formation of this Mn oxide causes acid Cu that can diffuse from the Cu-Mn alloy film in contact with the oxide semiconductor film into the oxide semiconductor film can be suppressed. Even if this happens, the Mn on the sides of the Cu-Mn alloy film, as well as the Mn within the Cu-Mn alloy film, will be removed and pure Cu is reattached to the surface of the oxide semiconductor film from the sides or surface of the film that has become a Cu film. .

[0011] When using an oxide semiconductor film as a transistor, for example, when using a bottom gate structure... A portion of the surface of the oxide semiconductor film becomes the so-called back channel side, and on this back channel side If Cu is reattached, the electrical properties of the transistor (e.g., on-current, field-effect mobility) will be affected. Problems such as degradation of frequency characteristics, etc., and gates, which are one of the reliability tests for transistors. In BT stress testing, there were problems such as degradation of transistor characteristics.

[0012] In view of the above-mentioned problems, in one aspect of the present invention, copper is added to a transistor using an oxide semiconductor film. One of the objectives is to provide a novel semiconductor device that uses the conductive film it possesses. In one aspect of the invention, a conductive film containing copper is used in a transistor using an oxide semiconductor film. , transistors with excellent electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) One of the objectives is to provide a semiconductor device having . Alternatively, in one aspect of the present invention, In transistors using oxide semiconductor films, the use of a conductive film containing copper reduces fluctuations in electrical properties. One of the objectives is to provide a semiconductor device having suppressed transistors. In one aspect of the present invention, a conductive film having copper is used in a transistor using an oxide semiconductor film. Therefore, one of the objectives is to provide a semiconductor device with highly reliable transistors. Alternatively, in one aspect of the present invention, a transistor using an oxide semiconductor film is provided with a copper conductive element. One of the challenges is to provide semiconductor devices with reduced manufacturing costs by using electrolytic films. Alternatively, in one aspect of the present invention, a transistor using an oxide semiconductor film is provided with a conductive material having copper. One of the challenges is to provide a highly productive semiconductor device using a film. In one aspect of the present invention, one of the objectives is to provide a novel semiconductor device. In one embodiment, one of the objectives is to provide a novel method for manufacturing semiconductor devices.

[0013] Furthermore, the description of the above problems does not preclude the existence of other problems. Also, one aspect of the present invention is not necessarily However, it is not necessary to solve all of these problems. Other issues not mentioned above should be described in the specification, etc. This is self-evident, and it is possible to extract issues other than those mentioned above from the description in the specification, etc. ru. [Means for solving the problem]

[0014] One aspect of the present invention is a semiconductor device having a transistor, wherein the transistor is a gate A gate electrode, a first insulating film on the gate electrode, and a first insulating film sandwiched between the gate electrode and the other An oxide semiconductor film having a region, and a source electrode electrically connected to the oxide semiconductor film, An oxide semiconductor film and an electrically connected drain electrode, and on the oxide semiconductor film, on the source electrode The source electrode and the drain electrode have a second insulating film on the drain electrode, and the source electrode and the drain electrode are Each has copper, and the ends of the source electrode and the drain electrode are made of copper and silicon, respectively. It is a semiconductor device having a region that includes [a specific area].

[0015] Another aspect of the present invention is a semiconductor device having a transistor, wherein the transistor The gate electrode, the first insulating film on the gate electrode, and the gate with the first insulating film in between. An oxide semiconductor film having a region that overlaps with the electrode, and a socket electrically connected to the oxide semiconductor film. A drain electrode electrically connected to the oxide semiconductor film, and on the oxide semiconductor film, The source electrode and the drain electrode have a second insulating film on the source electrode and the drain electrode. Each electrode has copper, and the ends of the source electrode and the drain electrode are made of copper and copper, respectively. This is a semiconductor device having a region containing a compound including lycon.

[0016] In each of the above configurations, the end of the source electrode and the end of the drain electrode are each connected to a second insulating It is preferable to have a region that is in contact with the edge film.

[0017] Another aspect of the present invention is a semiconductor device having a transistor, wherein the transistor The gate electrode, the first insulating film on the gate electrode, and the gate with the first insulating film in between. An oxide semiconductor film having a region that overlaps with the electrode, and a socket electrically connected to the oxide semiconductor film. A drain electrode electrically connected to the oxide semiconductor film, and on the oxide semiconductor film, The source electrode and the drain electrode have a second insulating film on the source electrode and the drain electrode. Each electrode consists of a first conductive film, a second conductive film in contact with the first conductive film, and the second conductive film It has a third conductive film in contact with the first conductive film and the third conductive film, the second conductive film having copper, and the first conductive film and the third conductive film. The conductive film has a material that suppresses copper diffusion, and the edges of the second conductive film are copper and silicon. It is a semiconductor device having a region that includes [a specific area].

[0018] Another aspect of the present invention is a semiconductor device having a transistor, wherein the transistor The gate electrode, the first insulating film on the gate electrode, and the gate with the first insulating film in between. An oxide semiconductor film having a region that overlaps with the electrode, and a socket electrically connected to the oxide semiconductor film. A drain electrode electrically connected to the oxide semiconductor film, and on the oxide semiconductor film, The source electrode and the drain electrode have a second insulating film on the source electrode and the drain electrode. Each electrode consists of a first conductive film, a second conductive film in contact with the first conductive film, and the second conductive film It has a third conductive film in contact with the first conductive film and the third conductive film, the second conductive film having copper, and the first conductive film and the third conductive film. The conductive film has a material that suppresses copper diffusion, and the edges of the second conductive film are copper and silicon. This is a semiconductor device having a region containing a compound.

[0019] In each of the above configurations, it is preferable that the edge of the second conductive film has a region in contact with the second insulating film. It seems so.

[0020] Furthermore, in each of the above configurations, the first conductive film and the third conductive film are titanium and tungsten. Preferably, the first conductive film and The third conductive film has an oxide, and the oxide has at least one of In or Zn. It would be preferable if that were the case.

[0021] Furthermore, in each of the above configurations, the oxide semiconductor film is made of In, Zn, and M (where M is Al, G It is preferable that the oxide semiconductor film has a (representing a, Y, or Sn) and a crystalline portion. It is preferable that the crystalline portion has c-axis orientation.

[0022] Furthermore, another aspect of the present invention is a display device having the semiconductor device of each of the above aspects and a display element. This is the arrangement. Another aspect of the present invention is the arrangement of the display device of the above aspect and a touch sensor. It is a display module. Another aspect of the present invention is a semiconductor device according to each of the above aspects, A display device, or a display module in the above-described manner, and at least an operation key or battery. It is an electronic device that also has one. [Effects of the Invention]

[0023] According to one aspect of the present invention, a conductive film having copper is provided in a transistor using an oxide semiconductor film. A novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, oxidation In a transistor using a semiconductor film, a conductive film containing copper is used to improve the electrical properties (for example, O We offer semiconductor devices that have transistors with excellent characteristics (such as current, field-effect mobility, and frequency characteristics). It can be provided. Alternatively, according to one aspect of the present invention, a transient using an oxide semiconductor film The transistor has a conductive film containing copper, which suppresses fluctuations in its electrical properties. A semiconductor device can be provided. Alternatively, according to one aspect of the present invention, an oxide semiconductor film can be provided. The transistor used has a conductive film containing copper, resulting in a highly reliable transistor. A semiconductor device can be provided. Alternatively, according to one aspect of the present invention, an oxide semiconductor film can be provided. A semiconductor device that uses a conductive film containing copper in the transistors, thereby reducing manufacturing costs. This can provide a traction device using an oxide semiconductor film. Alternatively, according to one aspect of the present invention, By using a conductive film containing copper in the inverter, it is possible to provide a semiconductor device with high productivity. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. According to one aspect of the present invention, a novel method for manufacturing a semiconductor device can be provided.

[0024] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention is: It is not necessarily required to have all of these effects. Other effects are described in the specification. This is obvious from the descriptions in the specifications, drawings, and claims, and the descriptions in the specifications, drawings, and claims Therefore, it is possible to extract effects other than those mentioned above. [Brief explanation of the drawing]

[0025] [Figure 1] A top view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 2] A top view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 3] A cross-sectional view showing one aspect of a semiconductor device. [Figure 4] A top view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 5] A cross-sectional view showing one aspect of a semiconductor device. [Figure 6] A top view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 7]A cross-sectional view showing one aspect of a semiconductor device. [Figure 8] A cross-sectional view showing one aspect of a semiconductor device. [Figure 9] A cross-sectional view showing one aspect of a semiconductor device. [Figure 10] A cross-sectional view showing one aspect of a semiconductor device. [Figure 11] A cross-sectional view showing one aspect of a semiconductor device. [Figure 12] A top view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 13] A top view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 14] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 15] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 16] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 17] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 18] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 19] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 20] A cross-sectional view showing an example of the manufacturing process for a semiconductor device. [Figure 21] A diagram illustrating the range of atomic ratios for oxide semiconductors according to one aspect of the present invention. [Figure 22] A diagram illustrating the crystal structure of InMZnO4. [Figure 23] Band diagram of a stacked oxide semiconductor structure. [Figure 24] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 25] Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 26] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 27]Cross-sectional TEM image of an a-like OS. [Figure 28] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 29] A top view showing one embodiment of a display device. [Figure 30] A cross-sectional view showing one embodiment of a display device. [Figure 31] A cross-sectional view showing one embodiment of a display device. [Figure 32] A cross-sectional view showing one embodiment of a display device. [Figure 33] A cross-sectional view showing one embodiment of a display device. [Figure 34] A cross-sectional view showing one embodiment of a display device. [Figure 35] A cross-sectional view showing one embodiment of a display device. [Figure 36] Block diagrams and circuit diagrams illustrating the display device. [Figure 37] A circuit diagram and timing chart illustrating one aspect of the present invention. [Figure 38] A graph and a circuit diagram illustrating one aspect of the present invention. [Figure 39] A circuit diagram and timing chart illustrating one aspect of the present invention. [Figure 40] A circuit diagram and timing chart illustrating one aspect of the present invention. [Figure 41] A block diagram, a circuit diagram, and a waveform diagram illustrating one aspect of the present invention. [Figure 42] A circuit diagram and timing chart illustrating one aspect of the present invention. [Figure 43] A circuit diagram illustrating one aspect of the present invention. [Figure 44] A circuit diagram illustrating one aspect of the present invention. [Figure 45] A diagram illustrating the display module. [Figure 46] A diagram illustrating electronic devices. [Figure 47] A diagram illustrating electronic devices. [Figure 48] A perspective view illustrating the display device. [Figure 49] A cross-sectional view and a circuit diagram illustrating the configuration of a semiconductor device according to one aspect of the present invention. [Figure 50] A block diagram illustrating the configuration of a CPU according to one aspect of the present invention. [Figure 51] A circuit diagram illustrating the configuration of a memory element according to one aspect of the present invention. [Figure 52] A circuit diagram showing an example of an imaging device. [Figure 53] A diagram showing an example configuration of an imaging device. [Figure 54] A diagram illustrating a STEM image of a sample related to an example. [Figure 55] A diagram illustrating the XPS analysis results of the sample in the example. [Figure 56] A diagram illustrating the XPS analysis results of the sample in the example. [Figure 57] Id-Vg characteristics of a transistor according to an embodiment. [Figure 58] Id-Vg characteristics of a transistor according to an embodiment. [Figure 59] A diagram illustrating a STEM image of a sample related to an example. [Figure 60] A diagram illustrating the EDX analysis results of the sample in the example. [Modes for carrying out the invention]

[0026] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and the form and details may not depart from the spirit and scope of the present invention. It is possible to change this in various ways. Therefore, the present invention can be described in the embodiments shown below. It is not interpreted as being limited to volume.

[0027] For the sake of ease of understanding, the position, size, and scope of each component shown in the drawings, etc., are as follows: The actual location, size, and range may not be represented. Therefore, the disclosed invention may not reflect the actual location, size, or range. It is not necessarily limited to the location, size, or scope disclosed in drawings, etc.

[0028] Furthermore, in this specification, the ordinal numbers used as "1st," "2nd," etc., are used for convenience. The order of processes or stacking may not be indicated. For example, "the first" may be written as "the second" or This can be replaced with "third," etc., as appropriate in the explanation. The ordinal numbers used to specify one aspect of this invention may not be the same. be.

[0029] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The relationships are used for convenience in explaining them with reference to the diagrams. Also, the positional relationships between the components are shown. This changes appropriately depending on the direction in which each configuration is described. Therefore, it is not limited to the terms described in the specification. It is not limited to a single word, and can be appropriately rephrased depending on the situation.

[0030] Furthermore, in this specification and other documents, when describing the structure of the invention using drawings, the same thing is used The symbols used are consistent across different drawings.

[0031] Furthermore, even when the term "semiconductor" is used in this specification, for example, if the conductivity is If the value is sufficiently low, it may have the properties of an "insulator". Also, "semiconductor" and " The term "insulator" has an ambiguous boundary and may not be strictly distinguishable in some cases. Therefore, this specification... The term "semiconductor" as used in this document may sometimes be replaced with "insulator." Similarly, this In some cases, the term "insulator" as used in specifications, etc., can be replaced with "semiconductor." In some cases, the term "insulator" as used in this specification may be replaced with "semi-insulator." .

[0032] Furthermore, even when the term "semiconductor" is used in this specification, for example, if the conductivity is If the value is sufficiently high, it may possess the properties of a "conductor." Also, "semiconductor" and " The term "conductor" has an ambiguous boundary and may not be strictly distinguishable in some cases. Therefore, this specification... The term "semiconductor" as used in this document may sometimes be replaced with "conductor." Similarly, this In some cases, the term "conductor" as used in specifications, etc., can be replaced with "semiconductor."

[0033] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain Between the drain region (or drain electrode) and the source (source terminal, source region, or source electrode) It has a channel region, and current flows through the drain, the channel region and the source. This is possible. In this specification, the channel region is the region in which current flows most of the time. It refers to.

[0034] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents and other materials, the terms "source" and "drain" can be used interchangeably.

[0035] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. When the inverter is ON, the part of the semiconductor through which current flows and the gate electrode overlap each other. In the region where a channel is formed, the source (source region or source) This refers to the distance between the electrode and the drain (drain region or drain electrode). In a transistor, the channel length is not necessarily the same across all regions. That is, The channel length of a single transistor may not be fixed to a single value. Therefore, In detailed documents, the channel length is defined as any one value in the region where the channel is formed, maximum This can be the value, minimum value, or mean value.

[0036] Channel width refers to, for example, the width of a semiconductor (or transistor) when it is in the ON state. A region or channel is formed where the part through which current flows and the gate electrode overlap. This refers to the length of the portion of a region where the source and drain are facing each other. In transistors, the channel width is not necessarily the same across all regions. That is, The channel width of a single transistor may not be fixed to a single value. Therefore, In detailed documents, the channel width is defined as any one value in the region where the channel is formed, the maximum This can be the value, minimum value, or mean value.

[0037] Furthermore, in this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "has some electrical effect The term "of" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. Switching elements such as resistors, inductors, capacitors, and other various functional elements are available. This includes elements such as [specific components].

[0038] Furthermore, voltage is defined by a certain potential and a reference potential (e.g., ground potential (GND) or source potential). It often refers to the potential difference between the voltage and the electric potential. Therefore, it is possible to rephrase voltage as electric potential. be.

[0039] In this specification, a silicon oxidizride film is defined as having a composition that is more acidic than nitrogen. This refers to a membrane with a high element content, preferably containing 55 atomic% or more and 65 atomic% or less of oxygen, and 1 atomic% of nitrogen. Atomic percent to 20 atomic percent, silicon 25 atomic percent to 35 atomic percent, hydrogen 0.1 atomic percent This refers to a film containing 10% to 10 atomic percent. A silicon nitride film is defined as having the following composition This refers to a membrane with a higher nitrogen content than oxygen, preferably containing 55 atomic percent or more of nitrogen. Less than 1 atom, oxygen between 1 atom and 20 atoms, silicon between 25 and 35 atoms Hereinafter, this refers to a membrane containing hydrogen in a concentration range of 0.1 atomic% to 10 atomic%.

[0040] Furthermore, in this specification, the terms "membrane" and "layer" are interchangeable. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". In some cases, it may be possible to change the terminology to this.

[0041] Furthermore, in this specification, "parallel" means that two straight lines have an angle of -10° or more and 10° or less. This refers to a state where objects are arranged in degrees. Therefore, it also includes cases where the angle is between -5° and 5°. Furthermore, "approximately parallel" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. This refers to a situation where two lines are positioned at an angle of 80° to 100°. This refers to a state where something is perpendicular. Therefore, it also includes cases where the angle is between 85° and 95°. "A straight line" refers to a state in which two straight lines are positioned at an angle between 60° and 120°.

[0042] Furthermore, in this specification, etc., when the crystal is trigonal or rhombohedral, it is referred to as a hexagonal system. represent.

[0043] (Embodiment 1) In this embodiment, a semiconductor device and a method for manufacturing a semiconductor device according to one aspect of the present invention are described. The following explanation will be given using Figures 1 through 20.

[0044] <1-1. Example of Semiconductor Device Configuration 1> Figure 1(A) is a top view of a transistor 100, which is a semiconductor device according to one aspect of the present invention. Furthermore, Figure 1(B) is a cross-sectional view of the section between the dashed-dotted line X1 and X2 shown in Figure 1(A). This corresponds to Figure 1(C), which shows the cross-section of the section plane between the dashed line Y1-Y2 shown in Figure 1(A). This corresponds to the diagram. Note that in Figure 1(A), for clarity, the configuration of transistor 100 is shown. Some of the components (substrate 102 and insulating film, etc.) are omitted from the illustration.

[0045] Furthermore, the direction of the dashed line X1-X2 in Figure 1(A) is the channel length of transistor 100. The direction indicated by the dashed line Y1-Y2 is sometimes referred to as the channel width direction of transistor 100. be.

[0046] The transistor 100 has a conductive film 104 on the substrate 102 that functions as a gate electrode, and The insulating film 106 on the plate 102 and the conductive film 104, the insulating film 107 on the insulating film 106, and insulation An oxide semiconductor film 108 on film 107, and a pair electrically connected to the oxide semiconductor film 108. Conductive films 112a and 112b that function as electrodes, and on the oxide semiconductor film 108 and conductive film Insulating films 114 and 116 on 112a and 112b, and insulating film 11 on insulating film 116 It has 8 and .

[0047] The oxide semiconductor film 108 is composed of indium (In), zinc (Zn), and M (where M is aluminum). (Represents nium (Al), gallium (Ga), yttrium (Y), or tin (Sn)) It is preferable to have the following:

[0048] Furthermore, in transistor 100, insulating films 106 and 107 are of transistor 100 It functions as a gate insulating film. Also, in transistor 100, a pair of electrodes and The conductive films 112a and 112b, which function as such, have one functioning as a source electrode and the other as such. It functions as a drain electrode.

[0049] Furthermore, the conductive film 112a consists of conductive film 112a_1 and a conductive film in contact with conductive film 112a_1. It has a film 112a_2 and a conductive film 112a_3 in contact with the conductive film 112a_2, and is conductive The film 112b consists of a conductive film 112b_1 and a conductive film 112b_ in contact with the conductive film 112b_1. It has 2 and a conductive film 112b_3 in contact with the conductive film 112b_2. 12a_2 has region 112a_2a and region 112a_2b. Also, conductive film 11 2b_2 has region 112b_2a and region 112b_2b.

[0050] The conductive film 112a_2 and the conductive film 112b_2 each contain copper, and region 112a_2 Regions b and 112b_2b each contain copper and silicon, respectively, and the conductive film 112a_1, The electrical film 112a_3, the conductive film 112b_1, and the conductive film 112b_3 each exhibit copper diffusion. It includes a material that suppresses [something]. Also, region 112a_2b is located at the edge of the conductive film 112a_2. It has a region in contact with the insulating film 114, and region 112b_2b is at the edge of the conductive film 112b_2. It is located in the part and has a region that is in contact with the insulating film 114. Also, the edge of the conductive film 112a_1 is It has a region located outside the edge of the conductive film 112a_2, and the edge of the conductive film 112b_1 is , has a region located outside the edge of the conductive film 112b_2. Also, conductive film 112a_ 3 covers the upper surface of conductive film 112a_2, and conductive film 112b_3 covers conductive film 112b_2 It covers the top surface. Therefore, conductive film 112a_2a is conductive film 112a_1, region 112a It has a structure covered with _2b and conductive film 112a_3, and the conductive film 112b_2a is conductive The structure is covered by film 112b_1, region 112b_2b, and conductive film 112b_3. .

[0051] Furthermore, regions 112a_2b and 112b_2b are copper silicides. It is preferable to form a copper silicide. Because copper silicide has a bond between copper and silicon, compared to copper. It is stable and has the function of suppressing the diffusion of copper to the outside. Also, insulating film 114 If silicon is present, then regions 112a_2b and 112b_2b have copper and silicon. This enhances the adhesion between the conductive films 112a_2 and 112b_2 and the insulating film 114. It plays.

[0052] Furthermore, even if regions 112a_2b and 112b_2b contain copper, silicon, and nitrogen Often, copper silicide nitride may be formed. Region 112a_ 2b and 112b_2b contain copper silicide nitride, which allows copper to diffuse to the outside. This can suppress that.

[0053] Conductive film 112a and conductive film 112b are conductive film 112a_2 and conductive film 112b, respectively, containing copper. The presence of film 112b_2 makes it possible to lower the resistance of conductive films 112a and 112b. This is how it works. Also, by having the conductive films 112a and 112b in the above configuration, the copper element is incorporated into the conductive film 11 Diffusion to the outside of 2a and 112b, particularly diffusion into the oxide semiconductor film 108, is suppressed. Therefore, it is possible to propose a semiconductor device having a transistor with excellent electrical characteristics. It can be provided.

[0054] <1-2. Example of Semiconductor Device Configuration 2> Next, regarding a configuration example different from the transistor 100 shown in Figures 1(A), 1(B), and 1(C), This will be explained using Figures 2 through 11. Note that in Figures 2 through 11 below, transistor 1 If it has the same function as 00, the hatch pattern is the same and no special designation is given. There is a match.

[0055] Figure 2(A) is a top view of transistor 100A, which is a semiconductor device according to one embodiment of the present invention. Figure 2(B) is a cross-sectional view of the section between the dashed-dotted line X1-X2 shown in Figure 2(A). Figure 2(C) is a cross-sectional view of the section between the dashed line Y1 and Y2 shown in Figure 2(A). It corresponds to.

[0056] The transistor 100A functions as the first gate electrode on the substrate 102, via a conductive film 10 4, the insulating film 106 on the substrate 102 and conductive film 104, and the insulating film 107 on the insulating film 106 The oxide semiconductor film 108 on the insulating film 107 and the oxide semiconductor film 108 are electrically connected Conductive films 112a and 112b function as a pair of electrodes, and on the oxide semiconductor film 108 And insulating films 114 and 116 on conductive films 112a and 112b, and on insulating film 116 The conductive film 112a is punctured and has an opening 152c provided in the insulating films 114 and 116. , a conductive film electrically connected to one of 112b (conductive film 112b in Figure 2(B)) 120a and a conductive film 120 provided on the insulating film 116, which functions as a second gate electrode. b has an insulating film 116 and an insulating film 118 on conductive films 120a and 120b.

[0057] In transistor 100A, insulating films 106 and 107 are the first of transistor 100A. The insulating films 114 and 116 function as gate insulating films, and transistor 100A The insulating film 118 functions as a second gate insulating film, and the insulating film 118 maintains the transistor 100A It functions as a protective insulating film. In this specification, insulating films 106 and 107 are referred to as The gate insulating film 1 and insulating films 114 and 116 are sometimes referred to as the second gate insulating film. Furthermore, in transistor 100A, the conductive film 112a, which functions as a pair of electrodes, 112b has one side functioning as a source electrode and the other side functioning as a drain electrode. It possesses the function of a pixel electrode used in a display device.

[0058] ≪s-channel structure≫ The oxide semiconductor film 108 in transistor 100A shown in Figure 2 is the first gate insulator. The conductive film 104 and the conductive film 120b are sandwiched between the film and the second gate insulating film. The length of the conductive film 104 in the channel length direction and the length in the channel width direction are such that the oxide semiconductor It is longer than the length in the channel length direction and the length in the channel width direction of membrane 108. The length of the conductive film 120b in the channel length direction and the length in the channel width direction are the same as that of the oxide semiconductor film 1 It is longer than the channel length and channel width of 08. Therefore, The entire oxide semiconductor film 108 has a first gate insulating film and a second gate insulating film sandwiched in between. It is covered with conductive film 104 and conductive film 120b.

[0059] In other words, in the channel width direction of transistor 100A, the conductive film 104 and the conductive The film 120b is an oxide semiconductor film with a first gate insulating film and a second gate insulating film sandwiched between them. It is a configuration that surrounds 108.

[0060] With this configuration, the oxide semiconductor film 108 of the transistor 100A This can be electrically surrounded by the electric fields of conductive film 104 and conductive film 120b. Like ZISTA 100A, the electric field of conductive film 104 and conductive film 120b causes the channel region The device structure of a transistor that electrically surrounds the oxide semiconductor film in which the region is formed is called a surro This can be called an unded channel (s-channel) structure.

[0061] Since transistor 100A has an s-channel structure, the conductive film 104 and the conductive The electric field for inducing a channel by the film 120b effectively generates an electric field in the oxide semiconductor film 108 It can be applied to it. Therefore, the current driving capability of transistor 100A is improved. This makes it possible to obtain high on-current characteristics. Furthermore, it is possible to increase the on-current. Therefore, it becomes possible to miniaturize transistor 100A. Also, transistor 100 A has a structure in which the oxide semiconductor film 108 is surrounded by conductive films 104 and 120b. Therefore, the mechanical strength of transistor 100A can be increased.

[0062] Furthermore, by adopting the above configuration, carriers flow in the oxide semiconductor film 108 The region includes the first gate insulating film side of the oxide semiconductor film 108 and the second gate insulating film side of the oxide semiconductor film 108, and also a wide range in the film of the oxide semiconductor film 108. Therefore, the carrier mobility of the transistor 100A increases. As a result, the on-current of the transistor 100A increases, and the field-effect mobility increases. Specifically, the field-effect mobility is 10 cm , , , , ,

[0064] , , , / V·s or more. Here, the field-effect mobility is not an approximate value of the mobility as a physical property value of the oxide semiconductor film, but an index of the current driving force in the saturation region of the transistor, and is the apparent field-effect mobility.

[0063] Also, like the transistor 100B shown in FIGS. 3(A) and (B), the conductive films 120a and 12 0b may be provided on the insulating film 118. In this case, at the opening 152c provided in the insulating films 114, 116, and 118 , one of the conductive film 120a and the conductive films 112a and 112b is electrically connected. The top view of the transistor 100B is the same as that of the transistor 100A shown in FIG. 2(A). FIG. 3(A) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line X1- X2 shown in FIG. 2(A), and FIG. 3(B) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line Y1 -Y2 shown in FIG. 2(A). Also, for other configurations of the transistor 100B, since it is the same as that of the transistor 100A, the configuration of the transistor 100A may be referred to.

[0064] Also, like the transistor 100C shown in FIG. 3(C), in the conductive films 112a and 112b , there is a region where the ends of the conductive film 112a_1 and the ends of the conductive film 112a_2 are aligned. ​​​​​​There may also be a region where the end of the conductive film 112b_1 and the end of the conductive film 112b_2 are aligned. This is also acceptable.

[0065] Also, like the transistor 100D shown in FIGS. 4(A), (B), and (C), a conductive film 120b that functions as a second gate electrode may be configured to be connected to a conductive film 104 that functions as a first gate electrode in openings 152a and 152b provided in the first gate insulating film (insulating films 106 and

[107] ) and the second gate insulating film (insulating films 114 and 116). Note that FIG. 4(A) is a top view of the transistor 100D, which is a semiconductor device according to an aspect of the present invention. FIG. |4(B)| corresponds to a cross-sectional view of a cut surface between the dashed-dotted line X1-X2 shown in FIG. 4(A), and FIG. 4(C) corresponds to a cross-sectional view of a cut surface between the dashed-dotted line Y1-Y2 shown in FIG. 4(A). As another configuration of the transistor 100D, since it is the same as that of the transistor 100A, the configuration of the transistor 100A may be referred to. In the transistor 100D, the conductive film 104 and the conductive film 120b are connected in the openings 152a and 152b provided in the first gate insulating film and the second gate insulating film. Therefore, the side surface in the channel width direction of the oxide semiconductor film 108 faces the conductive film 120b with the first gate insulating film and the second gate insulating film interposed therebetween. Also, the conductive film 104 and the conductive film 120b are given the same potential. Therefore, the oxide semiconductor film 108 included in the transistor 100D can be effectively electrically surrounded by the electric fields of the conductive film 104 and the conductive film 120b. Note that either only one of the openings 152a and 152b may be provided.

[0066] ​​​​​​​​

[0067] Also, as shown in Figures 5(A) and 5(B), the conductive films 120a and 12 0b may be provided on the insulating film 118. In this case, insulating films 114, 116, 118 In the opening 152c provided therein, conductive film 120a and conductive films 112a and 112b One side is electrically connected and is provided in insulating films 106, 107, 114, 116, and 118. In the openings 152a and 152b, a conductive film 120b functions as a second gate electrode. This is electrically connected to the conductive film 104, which functions as the first gate electrode. The top view of transistor 100E is the same as that of transistor 100D shown in Figure 4(A). 5(A) corresponds to a cross-sectional view of the section between the dashed line X1 and X2 shown in Figure 4(A), Figure 5(B) corresponds to a cross-sectional view of the section between the dashed-dotted line Y1 and Y2 shown in Figure 4(A). Furthermore, other configurations of transistor 100E are the same as those of transistor 100D. Therefore, you should refer to the configuration of transistor 100D.

[0068] Furthermore, as shown in Figures 6(A), (B), and (C), the transistor 100F has a second gate voltage. The conductive film 120b, which functions as an electrode, is connected via the conductive film 112c, The configuration may also involve connecting to a conductive film 104 that functions as the first gate electrode. (See Figure 6) (A) is a top view of transistor 100F, which is a semiconductor device according to one aspect of the present invention. Furthermore, Figure 6(B) is a cross-sectional view of the section between the dashed line X1 and X2 shown in Figure 6(A). Figure 6(C) is a cross-sectional view of the section between the dashed line Y1 and Y2 shown in Figure 6(A). It corresponds to.

[0069] The transistor 100F shown in FIGS. 6(A), (B), and (C) is provided on the insulating film 107, and has a conductive film 112c that is electrically connected to the conductive film 104 at the opening 151 provided in the first gate insulating film (insulating films 106 and 107). The conductive film 120b is provided on the insulating film 116 and is electrically connected to the conductive film 112c at the opening 152d provided in the second gate insulating film (insulating films 114 and 116). This is different from the transistor 100A.

[0070] In the transistor 100F, the conductive film 104 and the conductive film 120b are electrically connected via the conductive film 112c. One side of the side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112c with the first gate insulating film and the second gate insulating film interposed therebetween. Also, the conductive film 104 and the conductive film 120b are given the same potential. Therefore, the oxide semiconductor film 108 of the transistor 100F can be effectively electrically surrounded by the electric fields of the conductive film 104 and the conductive film 120b. [[ID=二十一]] [[ID=二十二]][[ID=二十三]] [[ID=二十四]][[ID=二十五]] [[ID=二十六]]

[0071] [[ID=二十七]] [[ID=二十八]]On the other hand, for example, in the case of a configuration in which the conductive film 104 and the conductive film 120b are not connected, as in the transistor 100A or the transistor 100B, different potentials can be applied to the conductive film 104 and the conductive film 120b, respectively. [[ID=二十九]] [[ID=三十]] [[ID=三十一]] [[ID=三十二]][[ID=三十三]] [[ID=三十四]]

[0072] [[ID=三十五]] [[ID=三十六]]Also, one or both of the length of the conductive film 120b in the channel length direction and the length in the channel width direction may not be longer than the length of the oxide semiconductor film 108 in the channel length direction and the length in the channel width direction, respectively. [[ID=三十七]] [[ID=三十八]][[ID=三十九]] [[ID=四十]][[ID=四十一]] [[ID=四十二]]

[0073] [[ID=四十三]] [[ID=四十四]]The conductive film 112c can be formed by the same process as the conductive films 112a and 112b. [[ID=四十五]] ​​​​In this case, the conductive film 112c is in contact with the conductive film 112c_1. A conductive film 112c_2 and a conductive film 112c_3 in contact with the conductive film 112c_2 are provided. Furthermore, the conductive film 112c_2 has region 112c_2a and region 112c_2b. do.

[0074] The conductive film 112c_2 contains copper, and region 112c_2b contains copper and silicon. The electrical film 112c_1 and the conductive film 112c_3 each contain a material that suppresses copper diffusion. Furthermore, region 112c_2b is located at the edge of the conductive film 112c_2 and is in contact with the insulating film 114. It has a region. Also, the edge of conductive film 112c_1 is further out than the edge of conductive film 112c_2. It has a region located on the side. Also, the conductive film 112c_3 has an upper surface of the conductive film 112c_2 It covers. Therefore, conductive film 112c_2a covers conductive film 112c_1 and region 112c_2b , and has a structure covered with a conductive film 112c_3.

[0075] Furthermore, region 112c_2b is made of the same material as regions 112a_2b and 112b_2b, and It can be formed by a process.

[0076] The above configuration makes it possible to lower the resistance of the conductive film 112c. Diffusing the element to the outside of the conductive film 112c, particularly into the oxide semiconductor film 108. It can be suppressed.

[0077] The other configurations of transistor 100F are the same as those of transistor 100A. Therefore, you should refer to the configuration of transistor 100A.

[0078] <1-3. Semiconductor device configuration example 3> Figures 7(A) and 7(B) show a cross-section of transistor 100G, which is a semiconductor device according to one embodiment of the present invention. This is a diagram, and the top view of transistor 100G is the same as that of transistor 100 shown in Figure 1(A). As shown in Figure 7(A), the cross-section of the cross-section plane between the dashed line X1-X2 shown in Figure 1(A) is shown. This corresponds to the figure, and Figure 7(B) shows the cross section of the cross-section between the dashed line Y1-Y2 shown in Figure 1(A). This corresponds to a surface drawing.

[0079] In transistor 100G, the oxide semiconductor film 108 is on the conductive film 104 side of the oxide semiconductor film 108a, oxide semiconductor film 108b on oxide semiconductor film 108a, and oxide semiconductor film 1 It differs from transistor 100 in that it has an oxide semiconductor film 108c on 08b. The oxide semiconductor film 108 has a three-layer structure. Regarding the other components, the transistor It is the same as transistor 100 and produces the same effect. Below, the structure differs from transistor 100. Let me explain about the formation.

[0080] The oxide semiconductor films 108a, 108b, and 108c are composed of In, Zn, and M(M), respectively. It has Al, Ga, Y, or Sn.

[0081] For example, in the oxide semiconductor film 108b, the atomic ratio of In is greater than the atomic ratio of M. It is preferable that it has a region. Furthermore, as oxide semiconductor films 108a and 108c, It is preferable that the region has fewer In atoms than the body membrane 108b.

[0082] The oxide semiconductor film 108b has a region in which the atomic ratio of In is greater than the atomic ratio of M. This allows us to increase the field-effect mobility of the 100G transistor. Specifically, The field effect mobility of the 100G radiator is 10 cm. 2 / Vs exceeds, more preferably tra The field effect mobility of the 100G radiator is 30 cm. 2 It becomes possible to exceed / Vs.

[0083] For example, a transistor with high field-effect mobility as described above can be used to generate a gate signal. Driver (especially the demulence connected to the output terminal of the shift register of the gate driver) By using it in a ticplexer, it can be used in semiconductor devices or displays with narrow bezels (also called narrow bezels). We can provide a place for you.

[0084] On the other hand, the oxide semiconductor film 108b has a region in which the atomic ratio of In is greater than the atomic ratio of M. In this case, the electrical characteristics of the 100G transistor are more likely to fluctuate when irradiated with light. However, Furthermore, in a semiconductor device according to one aspect of the present invention, an oxide semiconductor is placed on the oxide semiconductor film 108b. A film 108c is formed. The oxide semiconductor film 108c is more oxide semiconductor film than the oxide semiconductor film 108b. Because it also has a region with a low atomic ratio of In, Eg is larger than that of oxide semiconductor film 108b. Therefore, the stacked structure of oxide semiconductor film 108b and oxide semiconductor film 108c The oxide semiconductor film 108 can be made more resistant to photo-negative bias stress testing. It becomes Noh.

[0085] Furthermore, the oxide semiconductor film 108, particularly the channel region of the oxide semiconductor film 108b, is mixed in. Impurities such as hydrogen or water are problematic because they affect transistor characteristics. Therefore, in the channel region of the oxide semiconductor film 108b, hydrogen or water and other substances The fewer impurities, the better. Also, the channel region formed in the oxide semiconductor film 108b Oxygen deficiencies are problematic because they affect transistor characteristics. For example, oxide semiconductors When an oxygen deficiency is formed in the channel region of the body membrane 108b, hydrogen binds to the oxygen deficiency, It becomes a carrier source. A carrier source is generated in the channel region of the oxide semiconductor film 108b. When this is achieved, the electrical characteristics of the transistor 100G having the oxide semiconductor film 108b change, Typically, a threshold voltage shift occurs. Therefore, the oxide semiconductor film 108b In the Nell region, a smaller oxygen deficiency is preferable.

[0086] Therefore, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film 108, specifically The insulating films 114 and 116 formed on top of the oxide semiconductor film 108 contain excess oxygen. The structure is such that oxygen or excess oxygen is transferred from the insulating films 114 and 116 to the oxide semiconductor film 108. By moving these molecules, it becomes possible to reduce oxygen vacancies in oxide semiconductor films.

[0087] Furthermore, as shown in Figure 8(A)(B), the oxide semiconductor film 108 However, it has a two-layer structure having an oxide semiconductor film 108b and an oxide semiconductor film 108c. This is also acceptable. Note that the top view of transistor 100H is the same as the transistor shown in Figure 1(A). Similar to 100, Figure 8(A) shows the cross-section between the dashed line X1-X2 shown in Figure 1(A). This corresponds to a cross-sectional view of the cross-section, and Figure 8(B) shows the section between the dashed line Y1-Y2 shown in Figure 1(A). This corresponds to a cross-sectional view of the cut surface. Also, other configurations of transistor 100H include... Since it is similar to the 100G transistor, you can refer to the configuration of the 100G transistor.

[0088] Furthermore, as shown in the transistor 100J in Figures 9(A) and 9(B), the second gate electrode is... It has a conductive film 120b that functions as an oxide semiconductor film 108, and the oxide semiconductor film 108b and A configuration having a silicon oxide semiconductor film 108c is also possible. The top view is the same as that of transistor 100A shown in Figure 2(A), and Figure 9(A) is the same as that of Figure 2(A) Figure 9(B) corresponds to a cross-sectional view of the section between the dashed line X1-X2 shown in Figure 2( This corresponds to the cross-sectional view of the section between Y1 and Y2 shown by the dashed line A). Also, the transition Other configurations of the TA100J are the same as those of the transistor 100A, therefore, You should refer to the configuration of 100A.

[0089] Furthermore, as shown in Figure 9(C) for transistor 100K, conductive films 112a and 112b are also used. In this region, there is a region where the edge of conductive film 112a_1 and the edge of conductive film 112a_2 are aligned. Also, there is a region where the edge of conductive film 112b_1 and the edge of conductive film 112b_2 are aligned. That's good too.

[0090] Also, as shown in Figure 10(A)(B), the conductive film 120a, 1 20b may be provided on the insulating film 118. Also, the transistor shown in Figure 10(C) As in 100M, in conductive films 112a and 112b, the edge of conductive film 112a_1 and There may be regions where the edge of conductive film 112a_2 is aligned with the edge of conductive film 112b_1, There may be regions where the edges of the conductive film 112b_2 are aligned.

[0091] Transistors like 100J, 100K, 100L, 100M, s-channel By having this structure, the region in the oxide semiconductor film 108 where carriers flow is acid The first gate insulating film side of the oxide semiconductor film 108b, and the second side of the oxide semiconductor film 108b Because this includes the gate insulating film side and a wide area within the oxide semiconductor film 108, these The amount of carrier movement in the transistor increases. As a result, the on-current of the transistor increases. As the intensity decreases, the field effect mobility increases.

[0092] Furthermore, the oxide semiconductor film 108 of the transistor 100 is shown in the drawing as a conductive film 11 The oxide semiconductor film in the region exposed from 2a and 112b becomes thinner; in other words, the oxide semiconductor An example is given of a shape in which a part of the membrane has a recess. However, one aspect of the present invention is not limited thereto. It is not fixed, and the oxide semiconductor film in the region exposed from the conductive films 112a and 112b does not become thinner. It is not necessary to have a recess. An example of this case is shown in Figure 11(A)(B). Figure 11(A)( Figure B) is a cross-sectional view showing an example of a semiconductor device. Figures 11(A) and (B) are shown above. A transistor having a structure in which the oxide semiconductor film 108 of transistor 100 does not have a recess. This is a cross-sectional view of 100N.

[0093] <1-4. Semiconductor Equipment Configuration Example 4> Figure 12(A) is a top view of transistor 100P, and Figure 12(B) is a top view of transistor 100P. Figure 12(C) corresponds to a cross-sectional view of the section between the dashed line X1 and X2 shown in Figure 1. This corresponds to the cross-sectional view of the section between the dashed line Y1 and Y2 shown in 2(A).

[0094] The transistor 100P shown in Figure 12 has a conductive film 104 on the substrate 102 and the substrate 102 and And insulating film 106 on conductive film 104, insulating film 107 on insulating film 106, and insulating film 107 an oxide semiconductor film 108, an insulating film 114 on the oxide semiconductor film 108, and on the insulating film 114 The insulating film 116 and the opening 151a provided in the insulating film 114 and the insulating film 116 A conductive film 112a electrically connected to the oxide semiconductor film 108, an insulating film 114, and an insulating film. The oxide semiconductor film 108 is electrically connected through the opening 151b provided in 116. It has a conductive film 112b. Also, on transistor 100P, more specifically, conductive film 11 An insulating film 118 is provided on 2a, 112b, and insulating film 116.

[0095] Furthermore, in transistor 100P, insulating films 106 and 107 are in transistor 100 It functions as a gate insulating film for P, and the insulating films 114 and 116 are oxide semiconductor films 108 The insulating film 118 functions as a protective insulating film for transistor 100P. It has the function of a gate. Also, in transistor 100P, the conductive film 104 is the gate The conductive film 112a has the function of an electrode, and the conductive film 1 12b functions as a drain electrode.

[0096] In the transistor 100 shown in Figure 1, the structure was channel etch type, whereas The transistor 100P shown in Figures 12(A), (B), and (C) has a channel-protected structure. In one embodiment of the present invention, a channel-protected transistor is also suitably used in the semiconductor device. This is possible. Note that other configurations of transistor 100P include the same configuration as transistor 100. Therefore, we should refer to the configuration of transistor 100.

[0097] Furthermore, Figure 13(A) is a top view of transistor 100Q, and Figure 13(B) is a top view of Figure 1 Figure 13(C) corresponds to a cross-sectional view of the section between the dashed line X1 and X2 shown in 3(A), and This corresponds to the cross-sectional view of the section between the dashed line Y1 and Y2 shown in Figure 13(A).

[0098] The transistor 100Q shown in Figure 13 is the same as the transistor shown in Figure 12(A),(B),(C). The shapes of 100P and insulating films 114 and 116 are different. Specifically, transistor 100Q The insulating films 114 and 116 are provided in an island-like manner on the channel region of the oxide semiconductor film 108. The other configurations are the same as those of the 100P transistor.

[0099] Furthermore, the transistor according to this embodiment can be freely combined with each of the above structures. It is possible to do so.

[0100] <1-5. Components of a semiconductor device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0101] Circuit board There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, glass substrates, ceramic substrates, quartz substrates, etc. A fire substrate or the like may be used as the substrate 102. Alternatively, silicon or silicon carbide may be used as the material. Single-crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductors such as silicon germanium are used as materials. It is also possible to apply substrates, SOI substrates, etc., and semiconductor elements are provided on these substrates. The resulting material may be used as the substrate 102.

[0102] Furthermore, when using a glass substrate as substrate 102, the 6th generation (1500mm x 185 0mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 240 0mm), 9th generation (2400mm x 2800mm), 10th generation (2950mm x 34 By using large-area substrates such as 00mm, large-scale display devices can be manufactured.

[0103] Furthermore, a flexible substrate is used as the substrate 102, and the transistor 10 is directly mounted on the flexible substrate. A 0 may be formed. Alternatively, a release layer may be provided between the substrate 102 and the transistor 100. Good. The delamination layer is applied to the substrate 102 after the semiconductor device has been partially or completely completed on it. It can be separated and transferred to another substrate. In this case, transistor 100 has a low resistance It can be transferred to substrates with poor thermal resistance or flexible substrates.

[0104] <<Conductive film>> Conductive film 104 functions as the first gate electrode, conductive film 11 functions as the source electrode 2a, conductive film 11 functioning as a drain electrode, 2b, conductive film 11 functioning as a connecting electrode 2c, conductive film 120b which functions as a second gate electrode, and conductive film which functions as a pixel electrode The film 120a consists of chromium (Cr), copper (Cu), aluminum (Al), and gold (Au). ), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti ), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt A metal element selected from (Co), or an alloy containing the above-mentioned metal elements, or the above-mentioned These can be formed using alloys or other combinations of metallic elements.

[0105] Furthermore, the conductive films 104, 112a, 112b, 112c, 120a, and 120b contain Cu It is preferable to use a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co Mo, Ta, or Ti may be applied. By using a Cu-X alloy film, wet Because it can be processed using an etching process, manufacturing costs can be reduced.

[0106] Furthermore, conductive film 112a_2 is present in conductive film 112a, and conductive film 1 is present in conductive film 112b. 12b_2 and the conductive film 112c_2 of the conductive film 112c contain Cu or the above-mentioned C A uX alloy film can be suitably used. As a Cu-X alloy film, a Cu-Mn alloy film can be used. This is particularly preferable. However, in one embodiment of the present invention, the conductive film 112a is not limited thereto. _2, 112b_2, and the conductive film 112c_2 only need to contain at least copper.

[0107] Furthermore, regions 112a_2b, 112b_2b, and 112c_2b contain Cu and Si. It is preferable that the material has copper silicide. Regions 112a_2b, 112b _2b and 112c_2b have copper silicide nitride, which allows copper to diffuse to the outside. This can suppress the formation of copper silicide after forming a film of Cu or an alloy containing Cu. For example, it is formed by reacting it with silane gas. Also, after the reaction with silane gas, for example By reacting it with a nitrogen-containing plasma, copper silicide containing Cu, Si, and N is produced. A lide may be formed. Note that the surface of copper or a copper-containing alloy may be covered with an oxide film. If present, a reduction treatment using hydrogen or ammonia, etc., to remove the oxide film before the above reaction may be necessary. It is preferable to perform the necessary procedures.

[0108] Furthermore, conductive films 112a_1, 112a_3, and conductive film 112b are present in conductive film 112a. The conductive films 112b_1, 112b_3, and conductive film 112c have conductive film 112c _1, 112c_3 contains, among the above-mentioned metallic elements, titanium, tungsten, and tantalum. Preferably, the product contains one or more selected from ru and molybdenum. Electric film 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, 112 c_3 is selected from titanium, tungsten, tantalum, and molybdenum. If there are one or more, the copper contained in the conductive films 112a_2, 112b_2, and 112c_2 This can suppress the diffusion of the substance to the outside. That is, conductive films 112a_1, 112a_3 , 112b_1, 112b_3, 112c_1, and 112c_3 are so-called barrier metals. It has the function of being functional.

[0109] Also, conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_ 1. For 112c3, it is preferable to use a so-called tantalum nitride film containing nitrogen and tantalum. The tantalum nitride film is electrically conductive and has high barrier properties against copper or hydrogen. Furthermore, tantalum nitride films release less hydrogen from themselves, thus possessing the properties of oxides. It can be most preferably used as a conductive film in contact with the semiconductor film 108.

[0110] Also, conductive films 104, 112a_1, 112a_3, 112b_1, 112b_3, 1 12c_1, 112c_3, 120a, and 120b are oxides containing indium and tin. an oxide having tungsten and indium, and an oxide having tungsten, indium and zinc. Oxides that have titanium and indium, oxides having titanium, indium and tin Oxides, oxides having indium and zinc, oxides having silicon, indium and tin It is also possible to apply oxide conductors such as oxides containing indium, gallium, and zinc. Can be used. Conductive films 112a_1, 112a_3, 112b_1, 112b_3, 112c_1 , and 112c_3 have an oxide containing at least one of In or Zn. The conductive films 112a_2, 112b_2, and 112c_2 suppress the diffusion of copper to the outside. It is possible.

[0111] In particular, the above-mentioned oxide conductor can be suitably used for the conductive film 120a. Conductive film 120a and oxide semiconductor film 108 (oxide semiconductor film 108b and oxide semiconductor film It is preferable that 10⁸c) and have the same metallic element. This makes it possible to reduce manufacturing costs.

[0112] Here, we will explain oxide conductors. In this specification and elsewhere, oxide conductors are referred to as OC. It may also be called an Oxide Conductor. Examples of oxide conductors include When an oxygen vacancy is formed in an oxide semiconductor and hydrogen is added to the oxygen vacancy, a donor is formed near the conduction band. - A level is formed. As a result, the oxide semiconductor becomes highly conductive and turns into a conductor. An integrated oxide semiconductor can be called an oxide conductor. Generally, oxide semiconductors are Due to its large energy gap, it is transparent to visible light. On the other hand, oxide conductive The material is an oxide semiconductor having a donor level near the conduction band. Therefore, it is an oxide conductor. The absorption effect due to the donor level is small, and the light transmission for visible light is similar to that of oxide semiconductors. It has a sexual nature.

[0113] ≪An insulating film that functions as the first gate insulating film≫ Insulating films 106 and 107 function as the first gate insulating film of transistor 100. Plasma Enhanced Chemical Vapor Deposition (PECVD) By methods such as the ical vapor deposition method and sputtering method, oxidation Silicon film, silicon oxide nitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide 3mm film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film , tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and ne Each insulating layer can contain one or more odium films. Instead of a 107-layer structure, a single insulating film selected from the above materials, or three or more layers, can be used. An insulating film may also be used.

[0114] Furthermore, the insulating film 106 functions as a blocking film that suppresses oxygen permeation. For example, excess acid in insulating films 107, 114, 116 and / or oxide semiconductor film 108 When a component is supplied, the insulating film 106 can suppress the permeation of oxygen.

[0115] Furthermore, the oxide semiconductor film 108, which functions as the channel region of transistor 100, is in contact with the The insulating film 107 is preferably an oxide insulating film, and is preferably composed of an excess of acid in a stoichiometric composition. It is more preferable to have a region containing elements (oxygen-rich region). In other words, insulating film 1 07 is an insulating film capable of releasing oxygen. Note that the insulating film 107 has an oxygen-rich region. To provide this, for example, an insulating film 107 can be formed in an oxygen atmosphere. Alternatively, a film can be formed. The subsequent insulating film 107 can be heat-treated in an oxygen atmosphere.

[0116] Furthermore, when hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium has a higher dielectric constant than silicon oxide or silicon oxide / nitride. Therefore, Compared to the case using silicon oxide, the thickness of the insulating film 107 can be increased, thus tunnel This can reduce leakage current caused by current. In other words, a transistor with a small off-current It is possible to achieve this. Furthermore, hafnium oxide having a crystalline structure has an amorphous structure It has a higher dielectric constant compared to hafnium oxide, which has a low off-current. For use as a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of crystal structures include monoclinic and cubic systems. However, one aspect of the present invention is... The term "sama" is not limited to these examples.

[0117] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 It forms a silicon oxide film. Compared to the silicon oxide film, the silicon nitride film has a relative dielectric constant. Because the rate is high and the thickness required to obtain capacitance equivalent to that of a silicon oxide film is large, By including a silicon nitride film as the gate insulating film of ZISTA 100, the insulating film can be made thicker. This is possible. Therefore, the decrease in the dielectric strength of transistor 100 is suppressed, and furthermore, the dielectric strength is By improving this, electrostatic discharge damage to transistor 100 can be suppressed.

[0118] ≪Oxide Semiconductor Films≫ The materials shown above can be used as the oxide semiconductor film 108.

[0119] If the oxide semiconductor film 108b is In-M-Zn oxide, then the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used to achieve this satisfies In > M. Preferably, the atomic ratio of metal elements in such a sputtering target is I n:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4 .1 is one example.

[0120] Furthermore, if the oxide semiconductor films 108a and 108c are In-M-Zn oxide, In-M- The atomic ratio of metal elements in the sputtering target used to deposit Zn oxide films is: It is preferable that In ≤ M is satisfied. As for the ratio of offspring, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In: M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, etc. These are some examples.

[0121] Furthermore, the oxide semiconductor film 108 (108a, 108b, and 108c) is composed of In -In the case of M-Zn oxide, the sputtering target is polycrystalline In-M-Zn It is preferable to use a target containing an oxide. A target containing polycrystalline In-M-Zn oxide is preferable. By using GET, crystalline oxide semiconductor films 108a, 108b, and 108 c becomes easier to form. Note that the oxide semiconductor films 108a, 108b, and 10 The atomic ratios of 8c are, respectively, the number of atoms of the metal elements contained in the sputtering target described above. This includes variations of plus or minus 40% in the numerical ratio. For example, sputtering of an oxide semiconductor film 108b. When using a ring target with an atomic ratio of In:Ga:Zn=4:2:4.1, The atomic ratio of the oxide semiconductor film 108b to be deposited is approximately In:Ga:Zn=4:2:3. It can happen.

[0122] Furthermore, the oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV. Above eV, more preferably 3 eV or more. Thus, by using an oxide semiconductor with a wide energy gap, the off-current of the transistor 100 can be reduced. In particular, for the oxide semiconductor film 108b, an oxide semiconductor film with an energy gap of 2 eV or more, preferably 2 eV or more and 3.0 eV or less is used, and for the oxide semiconductor films 108a and 108c, using an oxide semiconductor film with an energy gap of 2.5 eV or more and 3.5 eV or less is preferable. Also, it is preferable that the energy gap of the oxide semiconductor films 108a and 108c is larger than that of the oxide semiconductor film 108b.

[0123] In addition, the thicknesses of the oxide semiconductor films 108a, 108b, and 108c are each 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0124] Also, as the oxide semiconductor films 108a and 108c, an oxide semiconductor film with a low carrier density is used. For example, the oxide semiconductor films 108a and 108c have a carrier density of 1 × 10 1 7 cm -3 or less, preferably 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 or less, and even more preferably 1 × 10 11 cm <00000​​​​​​​​​To obtain the semiconductor characteristics of the transistor, the carrier density and impurities of the oxide semiconductor film 108 are important. The concentration of the material, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc., should be appropriate. It is preferable.

[0126] Furthermore, the oxide semiconductor film 108 is an oxide with a low impurity concentration and a low defect level density. By using semiconductor films, it is possible to fabricate transistors with even better electrical characteristics. This is preferable. Here, the impurity concentration is low and the defect level density is low (few oxygen vacancies). This is called high-purity genuine or substantially high-purity genuine. Oxide semiconductor films, being a material, have few carrier sources, so it is necessary to lower the carrier density. This is possible. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film is It rarely exhibits an electrical characteristic where the voltage is negative (also known as normally-on). Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density. Therefore, the trap level density may also be low. The highly intrinsic oxide semiconductor film has a remarkably low off-current and a channel width of 1 × 10⁻⁶. 6 μm Even with an element with a channel length L of 10 μm, the voltage between the source electrode and the drain electrode (drain In the range of 1V to 10V, the off-current is measured by a semiconductor parameter analyzer. Below the measurement limit, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less.

[0127] Therefore, channels can be channeled into the above-mentioned high-purity intrinsic, or substantially high-purity intrinsic oxide semiconductor film. Transistors in which a region is formed exhibit small fluctuations in electrical characteristics and are highly reliable transistors. This can be done. Furthermore, the charge trapped in the trap levels of the oxide semiconductor film disappears. The time required to do so is long, and it can sometimes behave as if it were a fixed charge. Therefore, A transistor in which a channel region is formed in an oxide semiconductor film with a high trap level density is an electric transistor. The gas properties may become unstable. Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals are among them.

[0128] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atoms to form water. This forms an oxygen vacancy in the lattice (or the part from which oxygen has been removed). When hydrogen enters, electrons, which act as carriers, are sometimes generated. Also, some of the hydrogen It can combine with oxygen atoms that bond with metal atoms to generate electrons, which act as carriers. Transistors using oxide semiconductor films containing hydrogen exhibit normally-on characteristics. It is inexpensive. For this reason, it is preferable that the oxide semiconductor film 108 has as little hydrogen as possible. Specifically, in the oxide semiconductor film 108, the hydrogen concentration obtained by SIMS analysis is Degrees, 2 × 10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 The following is preferably 1 × 10 18 atoms / cm 3 The following is more convenient: 5x1 0 17 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 below Let's assume that.

[0129] Furthermore, the oxide semiconductor film 108b has a lower hydrogen concentration than the oxide semiconductor film 108c. It is preferable that it has a region. The oxide semiconductor film 108b is better than the oxide semiconductor film 108c. Having a region with low hydrogen concentration allows for the creation of a highly reliable semiconductor device.

[0130] Furthermore, in the oxide semiconductor film 108b, silicon and carbon, which are among the Group 14 elements, When included, the oxygen vacancies in the oxide semiconductor film 108b increase, leading to n-type conversion. Therefore, the concentration of silicon and carbon in the oxide semiconductor film 108b and the oxide semiconductor film 10 The concentrations of silicon and carbon near the interface with 8b (concentrations obtained by SIMS analysis) are 2× 10 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following ru.

[0131] Furthermore, in the oxide semiconductor film 108b, alkali metals obtained by SIMS analysis... Alternatively, the concentration of alkaline earth metals is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2× 10 16 atoms / cm 3 The following applies: Alkali metals and alkaline earth metals are oxides. When coupled with a semiconductor, it can generate carriers, increasing the transistor's off-current. This can happen. For this reason, alkali metal or alkaline earth It is preferable to reduce the concentration of metal-like substances.

[0132] Furthermore, if nitrogen is present in the oxide semiconductor film 108b, electrons, which act as carriers, are generated. The carrier density increases, making it easier to convert to n-type. As a result, the oxide semiconductor film containing nitrogen... Transistors using this material tend to exhibit normally-on characteristics. Therefore, when the oxide semiconductor film is used... In this context, it is preferable that nitrogen is reduced as much as possible, for example, by SIMS analysis. The nitrogen concentration obtained is 5 × 10 18 atoms / cm 3 The following is preferable:

[0133] Furthermore, the oxide semiconductor film 108b and the oxide semiconductor film 108c each have a non-single crystal structure. It can also be a single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS (C Axis Ali), which will be discussed later. gned Crystalline Oxide Semiconductor), polyconductor This includes crystalline structures, microcrystalline structures, or amorphous structures. In non-single-crystal structures, amorphous structures are the most common. While the defect level density is high, CAAC-OS has the lowest defect level density.

[0134] ≪An insulating film that functions as a second gate insulating film≫ The insulating films 114 and 116 function as second gate insulating films of transistor 100. Furthermore, the insulating films 114 and 116 have the function of supplying oxygen to the oxide semiconductor film 108. In other words, insulating films 114 and 116 contain oxygen. Also, insulating film 114 is permeable to oxygen. It is an insulating film that can do this. Note that the insulating film 114 forms the insulating film 116 that will be formed later. It also functions as a damage mitigation film for the oxide semiconductor film 108 during the manufacturing process.

[0135] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxide, silicon nitride, etc., with a size of nm or smaller can be used.

[0136] Furthermore, the insulating film 114 preferably has a low defect count, and typically, ESR measurement is used to determine its defect count. Furthermore, the spin density of the signal appearing at g=2.001 originates from the dangling bond of silicon. 3 x 10 17 spins / cm 3 The following is preferable. This is because the insulating film 114 If the defect density is high, oxygen will bond to the defects, and oxygen in the insulating film 114 will be lost. The amount of light transmitted will decrease.

[0137] Furthermore, in the insulating film 114, all of the oxygen that enters the insulating film 114 from the outside is absorbed by the insulating film 11 Some oxygen does not move to the outside of 4 and remains in the insulating film 114. Also, oxygen in the insulating film 114 As it enters, the oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, thus insulating Oxygen migration may occur in the film 114. The insulating film 114 is permeable to oxygen. When an oxide insulating film is formed that can be made, the insulating film 116 provided on the insulating film 114 The desorbed oxygen can be transferred to the oxide semiconductor film 108 via the insulating film 114. .

[0138] Furthermore, the insulating film 114 is formed using an oxide insulating film with a low energy level density due to nitrogen oxides. This can be achieved. Furthermore, the level density caused by the nitrogen oxide is the value of the oxide semiconductor film. The energy at the top of the electron band (Ev_os) and the energy at the bottom of the conduction band of an oxide semiconductor film. It may be formed between (Ec_os) Silicon oxide nitride film with low emission levels, or aluminum oxide nitride with low nitrogen oxide emission levels. A nium film or the like can be used.

[0139] Furthermore, silicon oxidnitride films with low nitrogen oxide emissions are analyzed by the temperature-controlled desorption gas analysis method. In other words, it is a membrane that releases more ammonia than nitrogen oxides, and typically ammonia The amount released is 1 × 10 18 pieces / cm 3 The above 5 x 10 19 pieces / cm 3 The following applies. The amount of Monia released is when the film surface temperature is between 50°C and 650°C, preferably between 50°C and 55°C. This refers to the amount released by heat treatment at temperatures below 0°C.

[0140] Nitrogen oxides (NO x (where x is greater than 0 and less than or equal to 2, preferably between 1 and 2), typically NO2 or NO forms energy levels in the insulating film 114, etc. These energy levels form in the oxide semiconductor film. It is located within an energy gap of 10⁸. Therefore, nitrogen oxides are in the insulating film 114 and When diffused into the interface of the oxide semiconductor film 108, the energy level causes electrons to be drawn to the insulating film 114 side. Wrapping may occur. As a result, trapped electrons may be trapped in the insulating film 114 and the oxide semiconductor. Because it remains near the membrane 108 interface, it shifts the transistor's threshold voltage in the positive direction. It will cause it to happen.

[0141] Furthermore, nitrogen oxides react with ammonia and oxygen during heat treatment. Insulating film 114 The nitrogen oxides contained in react with the ammonia contained in the insulating film 116 during the heat treatment. Therefore, nitrogen oxides contained in the insulating film 114 are reduced. At the interface of the oxide semiconductor film 108, electrons are less likely to be trapped.

[0142] By using the above oxide insulating film as the insulating film 114, the threshold voltage of the transistor can be adjusted. This makes it possible to reduce the shift and reduce fluctuations in the electrical characteristics of the transistor. can.

[0143] Furthermore, the heat treatment in the transistor manufacturing process typically involves heating to temperatures between 300°C and 350°C. Due to the heat treatment, the insulating film 114 has a spectrum obtained by measuring at an ESR of 100K or less. In this case, the first signal is when the g value is 2.037 or higher and 2.039 or lower, and the second signal is when the g value is 2.001 or higher. A second signal of 0.003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less. Null is observed. Note that the split width of the first signal and the second signal, and the The split width of the second signal and the third signal is approximately 5 in the X-band ESR measurement. It is mT. Also, the first signal is when the g value is between 2.037 and 2.039, and the g value is 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966. The sum of the spin densities of the third signal is 1 × 10 18 spins / cm 3 Less than For example, 1 x 10 17 spins / cm 3 The above 1 x 10 18 spins / cm 3 Not yet It is full.

[0144] Furthermore, in ESR spectra below 100K, the g value is between 2.037 and 2.039. Below are the first signal, the second signal with a g value between 2.001 and 2.003, and the g value The sum of the spin densities of the third signal, where is between 1.964 and 1.966, is nitrogen acid Monster (NO x (where x is greater than 0 and less than or equal to 2, preferably between 1 and 2) the signal is caused by It is correct. Typical examples of nitrogen oxides include nitric oxide and nitrogen dioxide. That is, the g value The first signal is between 2.037 and 2.039, and the g value is between 2.001 and 2.003. The second signal and the third signal where the g value is between 1.964 and 1.966 The lower the total density of pins, the lower the nitrogen oxide content in the oxide insulating film. Yes, I can.

[0145] Furthermore, the above oxide insulating film has a nitrogen concentration of 6 × 10 as measured by SIMS. 20 atoms / cm 3 The following applies:

[0146] The substrate temperature is between 220°C and 350°C, and PEC is performed using silane and nitrous oxide. By forming the above oxide insulating film using the VD method, a dense and hard film is obtained. It can be formed.

[0147] The insulating film 116 is an oxide insulating film containing more oxygen than satisfactorily satisfying the stoichiometric composition. It is formed using. An oxide insulating film containing more oxygen than satisfies the stoichiometric composition is Heating causes some of the oxygen to be removed. It contains more oxygen than the oxygen required to satisfy the stoichiometric composition. In the oxide insulating film, TDS analysis showed that the amount of oxygen desorption, converted to oxygen atoms, was 1.0 × 10⁻¹⁶. 1 9 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 That's all. It is an oxide insulating film. Note that the surface temperature of the film in the above TDS is 100°C or higher. A temperature of 0°C or lower, or a range of 100°C to 500°C, is preferred.

[0148] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxide nitride, etc., with a wavelength of 400 nm or less can be used.

[0149] Furthermore, it is preferable that the insulating film 116 has a low defect count, and typically, ESR measurement is used to determine this. Furthermore, the spin density of the signal appearing at g=2.001 originates from the dangling bond of silicon. is 1.5 × 10 18 spins / cm 3 Less than, and even 1 × 10 18 spins / cm 3 The following is preferable. Note that the insulating film 116 is an oxide semiconductor compared to the insulating film 114. Because it is separated from the body film 108, it can have a higher defect density than the insulating film 114.

[0150] Furthermore, insulating films 114 and 116 can be made of the same type of insulating material, thus providing insulation. In some cases, the interface between film 114 and insulating film 116 cannot be clearly identified. Therefore, in this implementation... In the diagram, the interface between insulating film 114 and insulating film 116 is shown with a dashed line. In the embodiment, a two-layer structure of insulating film 114 and insulating film 116 was described, but It is not limited to this, but for example, a single-layer structure of the insulating film 114, or a stacked structure of three or more layers That's good too.

[0151] <An insulating film that functions as a protective insulating film> The insulating film 118 functions as a protective insulating film for the transistor 100.

[0152] The insulating film 118 contains either hydrogen or nitrogen, or both. 18 contains nitrogen and silicon. The insulating film 118 contains oxygen, hydrogen, water, and alkali. It has the function of blocking metals, alkaline earth metals, etc. By providing an insulating film 118 Therefore, the diffusion of oxygen from the oxide semiconductor film 108 to the outside and the insulating films 114 and 116 The diffusion of oxygen to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 108. It can be prevented.

[0153] For example, a nitride insulating film can be used as the insulating film 118. Examples include silicon nitride, silicon oxide nitride, aluminum nitride, and aluminum oxide nitride. These include:

[0154] Furthermore, the various films described above, such as conductive films, insulating films, and oxide semiconductor films, are produced by sputtering. It can be formed by the chemo- It may also be formed by the (Emical Vapor Deposition) method. Thermal CVD An example of the law is MOCVD (Metal Organic Chemical Vapor Deposition method, or ALD (Atomic Layer Deposition) Examples include the tion method.

[0155] Thermal CVD is a film deposition method that does not use plasma, so defects can occur due to plasma damage. It has the advantage of never being accomplished.

[0156] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber is subjected to atmospheric pressure. Alternatively, by applying reduced pressure and reacting the film near or on the substrate, the film can be deposited on the substrate. You may go.

[0157] Furthermore, the ALD method maintains atmospheric pressure or reduced pressure inside the chamber, and the raw material gas for the reaction is The gases may be introduced sequentially into the chamber, and the film deposition process may be carried out by repeating this gas introduction sequence.

[0158] Thermal CVD methods such as MOCVD and ALD are used for the conductive films, insulating films, and oxides of the above embodiments. It can form various films such as semiconductor films and metal oxide films, for example, In-Ga-Zn When forming an O film, trimethylindium, trimethylgallium, and dimethyl sulfate are used. Lead is used. The chemical formula for trimethylindium is In(CH3)3. Also, The chemical formula for trimethylgallium is Ga(CH3)3. Also, the chemical formula for dimethylzinc is... It is Zn(CH3)2. Furthermore, it is not limited to these combinations, trimethylgallium Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of um, Diethylzinc (chemical formula Zn(C2H5)2) can also be used instead of methylzinc.

[0159] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl A raw material gas obtained by vaporizing hafnium amides (such as amide hafnium (TDMAH)) and an acid Two types of gases, ozone (O3), are used as nitrifying agents. Note that tetrakisdimethylamide is also used. The chemical formula for humium is Hf[N(CH3)2]4. Other material liquids include tetrahedron. Examples include lacs(ethylmethylamide)hafnium.

[0160] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, A liquid containing a medium and an aluminum precursor compound (such as trimethylaluminum (TMA)) Two types of gases are used: a vaporized raw material gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other material solutions include Tris( Dimethylamide) Aluminum, Triisobutylaluminum, Aluminum Tris(2 Examples include 2,6,6-tetramethyl-3,5-heptanedione).

[0161] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Chlorodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, resulting in an oxidizing gas (O 2. A radical of nitrous oxide is supplied and reacted with the adsorbed material.

[0162] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 The initial tungsten film is formed by sequentially introducing gas and B2H6 gas, and then WF A tungsten film is formed using 6 gas and H2 gas. Note that S can be used instead of B2H6 gas. You may also use an IH4 gas stove.

[0163] For example, oxide semiconductor films, such as In-Ga-ZnO, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. An O layer is formed, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas. Furthermore, a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. Furthermore, these gases can be used to create In-Ga-O layers and In A mixed compound layer such as a -Zn-O layer or a Ga-Zn-O layer may be formed. Alternatively, H2O gas obtained by bubbling with an inert gas such as Ar may be used instead. It is preferable to use O3 gas that does not contain [unclear]. Alternatively, instead of In(CH3)3 gas, [unclear] (C2H5)3 gas may be used. Alternatively, Ga(C2) can be used instead of Ga(CH3)3 gas. H5)3 gas may be used. Alternatively, Zn(CH3)2 gas may be used.

[0164] <1-6. Transistor Fabrication Method 1> Next, regarding the method for fabricating a transistor 100J, which is a semiconductor device according to one aspect of the present invention, This will be explained using Figures 14 to 17. Figures 14 to 17 show the method for manufacturing a semiconductor device. These are cross-sectional diagrams illustrating the following: Figures 14(A)(C)(E), 15(A)(C)(E), and 1 Figures 6(A)(C)(E) and 17(A)(C)(E) show the channel length direction from X1 to X2. This is shown in Figures 14(B)(D)(F), 15(B)(D)(F), and 16(B)(D)( F), Figure 17(B)(D)(F) is a cross-sectional view in the channel width direction shown by Y1-Y2.

[0165] <<Process for forming the first gate electrode and the first gate insulating film>> First, a conductive film is formed on the substrate 102, and the conductive film is subjected to a lithography process and an etching process. The process is carried out to form a conductive film 104 that functions as the first gate electrode. Insulating films 106 and 107, which function as the first gate insulating film, are formed on the film 104 (Figure 14(A)(B)).

[0166] In this embodiment, a glass substrate is used as the substrate 102 and functions as the first gate electrode. The conductive film 104 consists of a titanium film with a thickness of 10 nm, a copper film with a thickness of 100 nm, and a 5 A 0 nm tantalum nitride film is formed by sputtering.

[0167] Furthermore, a silicon nitride film with a thickness of 400 nm is formed as insulating film 106 by the PECVD method. Then, a silicon oxidizride film with a thickness of 15 nm is formed as insulating film 107 by the PECVD method. Furthermore, the insulating film 106 can be a laminated structure of silicon nitride films. Specifically In particular, the insulating film 106 consists of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminated structure with a silicon dioxide film can be formed. An example of this three-layer laminated structure is as follows: It can be formed as shown below.

[0168] For example, the first silicon nitride film is silane at a flow rate of 200 sccm, and silane at a flow rate of 2000 sccm. PECVD using sccm of nitrogen and ammonia gas at a flow rate of 100 sccm as raw material gases. It supplies power to the reaction chamber of the apparatus, controls the pressure inside the reaction chamber to 100 Pa, and uses a high frequency of 27.12 MHz. By supplying 2000W of power using a wave power supply, you can form it to a thickness of 50nm. stomach.

[0169] The second silicon nitride film was a silane at a flow rate of 200 sccm, and a flow rate of 2000 sccm Nitrogen and ammonia gas at a flow rate of 2000 sccm are used as raw material gases in a PECVD apparatus. A 27.12 MHz high-frequency power supply is supplied to the reaction chamber, controlling the pressure inside the chamber to 100 Pa. By supplying 2000W of power using this method, the material can be formed to a thickness of 300nm.

[0170] The third silicon nitride film is a silane at a flow rate of 200 sccm, and a silane at a flow rate of 5000 sccm. A nitrogen atom at a concentration of 1 cm is supplied as a raw material gas to the reaction chamber of the PECVD apparatus, and the pressure inside the reaction chamber is set to 100. It is controlled to Pa and supplied with 2000W of power using a 27.12MHz high-frequency power supply, It should be formed so that the depth is 50 nm.

[0171] Furthermore, the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during formation can be kept below 350°C.

[0172] By making the insulating film 106 a three-layer laminated structure of silicon nitride films, for example, conductive film 10 When a conductive film containing copper (Cu) is used in step 4, the following effects are achieved.

[0173] The first silicon nitride film suppresses the diffusion of copper (Cu) elements from the conductive film 104. Yes, it is possible. The second silicon nitride film has the function of releasing hydrogen and functions as a gate insulating film. The dielectric strength of the insulating film can be improved. The third silicon nitride film is the third silicon nitride Low hydrogen release from the first film, and diffusion of hydrogen released from the second silicon nitride film. It can be suppressed.

[0174] The insulating film 107 is an oxide semiconductor film 108 that will be formed later (more specifically, an oxide To improve the interfacial properties with the semiconductor film 108b), an insulating film containing oxygen is formed. Preferably. Alternatively, oxygen may be added to the insulating film 107 after its formation. The oxygen added to membrane 107 can be oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecules. There are ions, etc. In addition, methods of addition include ion doping, ion implantation, plasma There are various processing methods, such as the M method.

[0175] <<Process for forming oxide semiconductor films>> Next, oxide semiconductor films 108b and 108c are formed on the insulating film 107. (See Figures 14(C) and 14(D)).

[0176] Figures 14(C) and (D) show the oxide semiconductor film 108 that will later be formed on the insulating film 107. This is a schematic cross-sectional view of the inside of a film deposition apparatus used for forming body membranes. Figures 14(C) and 14(D) show the film deposition apparatus. A sputtering device is used as the base, and a target is installed inside the sputtering device. The to 191 and the plasma 192 formed below the target 191 are schematically represented. It is.

[0177] First, when forming the oxide semiconductor film, the plasma is released in an atmosphere containing a first oxygen gas. To charge it. At that time, oxygen is added to the insulating film 107 which will be the surface on which the oxide semiconductor film is formed. Furthermore, when forming an oxide semiconductor film, in addition to the first oxygen gas, an inert gas (for example) is also used. Alternatively, helium gas, argon gas, xenon gas, etc. may be mixed in.

[0178] The first oxygen gas is one that is present at least when forming the oxide semiconductor film. The proportion of the first oxygen gas in the total deposition gas when forming an oxide semiconductor film is as follows: , greater than 0% and less than or equal to 100%, preferably 10% or more and less than or equal to 100%, more preferably It is between 30% and 100%.

[0179] In Figure 14(C)(D), the oxygen or excess oxygen added to the insulating film 107 is This is schematically represented by a dashed arrow.

[0180] Furthermore, the substrate temperature during the formation of oxide semiconductor film 108b and oxide semiconductor film 108c is the same. They may be the same or different. However, oxide semiconductor film 108b and oxide semiconductor film 108 By keeping the substrate temperature the same as that of c, manufacturing costs can be reduced, making it preferable. ru.

[0181] For example, the substrate temperature when depositing the oxide semiconductor film 108 is between room temperature and 340°C. A suitable temperature is, preferably above room temperature and below 300°C, more preferably between 100°C and 250°C, and Preferably, the temperature is between 100°C and 200°C. The oxide semiconductor film 108 is heated to form the film. This makes it possible to improve the crystallinity of the oxide semiconductor film 108. On the other hand, the substrate 102 and Furthermore, when using large glass substrates (e.g., 6th to 10th generation), oxide semiconductors When the substrate temperature during film formation of the body film 108 is set to 150°C or higher and less than 340°C, the substrate 102 It may deform (warp or bend). Therefore, when using a large glass substrate... In this case, the substrate temperature when depositing the oxide semiconductor film 108 is set to 100°C or higher and less than 150°C. This makes it possible to suppress deformation of the glass substrate.

[0182] Furthermore, it is necessary to increase the purity of the sputtering gas. For example, as a sputtering gas The oxygen gas or argon gas used has a dew point of -40°C or lower, preferably -80°C or lower. A gas that has been purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using this method, it is possible to prevent moisture and other substances from being incorporated into the oxide semiconductor film as much as possible. .

[0183] Furthermore, when depositing an oxide semiconductor film by sputtering, in the sputtering apparatus... The chamber is designed to remove as much water and other impurities as possible from the oxide semiconductor film. Using an adsorption-type vacuum pump such as an IO pump to create a high vacuum (5 × 10⁻¹⁰ -7 Pa to 1× 10 -4 It is preferable to exhaust the gas (to about Pa). Alternatively, use a turbomolecular pump and cold By combining traps, gases, especially those containing carbon or hydrogen, enter the chamber from the exhaust system. It is preferable to prevent backflow.

[0184] Furthermore, after the oxide semiconductor film that will later become the oxide semiconductor film 108b is formed, then, An oxide semiconductor film, which will become the oxide semiconductor film 108c, is formed. During film formation, the plasma should be discharged in an atmosphere containing a second oxygen gas.

[0185] Furthermore, the first oxygen gas used when forming the oxide semiconductor film that will later become the oxide semiconductor film 108b The proportion of s and the second acid used when forming the oxide semiconductor film that will later become the oxide semiconductor film 108c The proportion of the elemental gases may be the same or different.

[0186] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: Using a 2:4.1 [atomic ratio], the oxide semiconductor film 108 was later produced by sputtering. A b oxide semiconductor film is formed, and then in a vacuum, the In-Ga-Zn metal oxide film is continuously oxidized. Using a material target (In:Ga:Zn=1:1:1.2 [atomic ratio]), sputtering An oxide semiconductor film, which will later become an oxide semiconductor film 108c, is formed by the pulping method. The substrate temperature during the formation of the oxide semiconductor film is set to 170°C. Furthermore, the oxide semiconductor film 1 The deposition gas used when forming the oxide semiconductor film O8b is oxygen gas at a flow rate of 15 sccm. And, argon gas at a flow rate of 35 sccm is used. Also, later, oxide semiconductor film 108c The deposition gas used when forming the oxide semiconductor film is oxygen gas at a flow rate of 25 sccm, and Use 25 sccm of argon gas.

[0187] Next, the deposited oxide semiconductor film is processed into the desired shape to form an island-shaped oxide semiconductor film. Forms 108b and island-like oxide semiconductor films 108c (see Figures 14(E) and 14(F)). In this embodiment, the oxide semiconductor film 108b and the oxide semiconductor film 108c are This constitutes the oxide semiconductor film 108 (see Figures 14(E) and 14(F)).

[0188] Furthermore, after forming the oxide semiconductor film 108, a heat treatment (hereinafter referred to as the first heat treatment) is performed. It is preferable to perform the following. The first heat treatment removes the hydrogen contained in the oxide semiconductor film 108. Water and other elements can be reduced. Note that heat treatment aimed at reducing hydrogen, water, etc., is an oxide treatment. This may be performed before processing the semiconductor film 108 into island shapes. Note that the first heat treatment is performed on an oxide semiconductor. This is one of the processes used to improve the purity of conductive films.

[0189] The first heat treatment is, for example, 150°C or higher, but below the strain point of the substrate, preferably 200°C. The temperature can be between ℃ and 450℃, and more preferably between 250℃ and 350℃.

[0190] Furthermore, the first heat treatment is performed using an electric furnace, RTA (Rapid Thermal Annealing). l) Equipment can be used. By using an RTA device, the distortion of the substrate can be reduced for a short period of time. Heat treatment can be performed at temperatures above 10°C. Therefore, it is possible to shorten the heating time. Yes. Also, the first heat treatment involves nitrogen, oxygen, and ultra-dry air (with a water content of 20 ppm or less). (Air, preferably 1 ppm or less, preferably 10 ppb or less), or noble gas (Algon The process should be carried out in an atmosphere of nitrogen, oxygen, helium, etc. Note that the above-mentioned nitrogen, oxygen, ultra-dry air, or It is preferable that the noble gas does not contain hydrogen, water, etc. Furthermore, heating in a nitrogen or noble gas atmosphere is required. After processing, the film may be heated in an oxygen or ultra-dry air atmosphere. As a result, an oxide semiconductor film is formed. This process involves removing hydrogen, water, and other elements contained within, while simultaneously supplying oxygen to the oxide semiconductor film. Yes, it is possible. As a result, the oxygen vacancies contained in the oxide semiconductor film can be reduced.

[0191] <<Formation process for source electrode and drain electrode>> Next, the insulating film 107 and the oxide semiconductor film 108 are used to later form the source electrode and drain electrode. The conductive film 112 is then formed by sputtering (see Figures 15(A) and 15(B)). .

[0192] In this embodiment, the conductive film 112 is made up of conductive films 112_1, 112_2, and 112 Layer _3. A tungsten film with a thickness of 50 nm is used as conductive film 112_1, and conductive film 11 2_2 is a copper film with a thickness of 200 nm, and the conductive film 112_3 is a tungsten film with a thickness of 5 nm. A laminated film is formed by sequentially stacking a film and a strip film, and then depositing the laminated film by sputtering. In this case, conductive film 112_1 and conductive film 112_3 are formed using the same material, It is not limited to this. For example, a tungsten film with a thickness of 50 nm as the conductive film 112_1, Conductive film 112_2 is a copper film with a thickness of 200 nm, and conductive film 112_3 is a copper film with a thickness of 50 nm A laminated film in which a titanium film and a conductive film are sequentially deposited may also be used. Although this is described as a structure, it is not limited to this. For example, the conductive film 112 may be a two-layer laminated structure. It is also acceptable to have a laminated structure of four or more layers.

[0193] Next, masks 141a and 141b are formed on the desired region on the conductive film 112_3. Then, the conductive films 112_2 and 112_3 are processed using masks 141a and 141b. Then, the island-shaped conductive films 112a_2, 112b_2, and 112a_3 are separated from each other. , forming 112b_3 (see Figure 15(C)(D)).

[0194] In this embodiment, a wet etching apparatus is used to remove the conductive film 112_2. Process 112_3. However, the processing method for the conductive film 112 is not limited to this. For example, a dry etching apparatus may be used. Rather than processing the conductive film 112, the conductive film 112 is processed using a wet etching apparatus. This approach can reduce manufacturing costs.

[0195] Next, the edges of the conductive films 112a_2 and 112b_2 are silicided, thereby providing copper Regions 112a_2a and 112b_2a, and region 112a_2b having copper silicide , forming 112b_2b.

[0196] Figures 15(E) and 15(F) show the silicide treatment of the edges of the conductive films 112a_2 and 112b_2. This is a schematic cross-sectional view of the inside of the plasma device during the process. Figures 15(E) and 15(F) show the plasma device and Then, using a PECVD apparatus, the plasma 195 generated inside the PECVD apparatus is schematic Let's express it in a specific way.

[0197] The copper exposed at the edges of the conductive films 112a_2 and 112b_2 easily forms an oxide film on its surface. Therefore, as a pretreatment for silicide formation, the oxide film covering the surface of the copper is removed. Includes a reducing gas (e.g., hydrogen gas, ammonia gas) to remove it. Plasma is discharged in the atmosphere. At that time, the oxide film covering the copper surface is reduced, and the conductive film 11 Copper is exposed at the ends of 2a_2 and 112b_2. Furthermore, the reduction process to remove this oxide film is required. The method is not limited to plasma treatment. For example, a reducing gas (e.g., water) The copper surface is exposed to an atmosphere containing gases (such as ammonia gas) and then subjected to heat treatment to remove the gas. It may be used as is. Also, the substrate temperature when performing the plasma treatment and heat treatment described above is preferred. The temperature is 300°C or higher, more preferably 350°C or higher. In this embodiment, copper The substrate temperature used to remove the oxide film covering the surface is set to 350°C.

[0198] Next, it is exposed to an atmosphere containing silane gas, causing the copper to react with the silane gas, thereby producing conductivity. Copper silicides having copper and silicon are formed at the edges of films 112a_2 and 112b_2. Regions 112a_2b and 112b_2b are formed. Also, conductive films 112a_2 and 112b In region _2, the regions where copper silicide is not formed are designated as regions 112a_2a and 112b_2a. The substrate temperature when forming copper silicide is preferably 200°C to 400°C. More preferably, the temperature is between 220°C and 350°C. In this embodiment, copper silica The substrate temperature for forming the id was set to 220°C, and a silane gas flow rate of 300 sccm was used. A nitrogen gas flow rate of 500 sccm is used.

[0199] Furthermore, the substrate temperature when removing the oxide film from the copper surface and the substrate temperature when forming the copper silicide are also considered. To achieve the same degree of uniformity, oxide film removal and copper silicide formation should be performed in the same apparatus or chamber. This is preferable because it can be done internally. In this case, the substrate temperature when forming the copper silicide is set to 350°C. It is preferable to do so.

[0200] Furthermore, the gas used to form copper silicide contains at least silicon. For example, as the proportion of silicon-containing gas to the total gas when forming copper silicide. is greater than 0% and less than or equal to 100%, preferably 10% or more and less than or equal to 100%, and more preferably It is between 30% and 100%.

[0201] In Figures 15(E)(F), the conductive films 112a_2 and 112b_2 are added. Silicon or silane is schematically represented by a dashed arrow.

[0202] Furthermore, after forming the copper silicide, a plasma discharge is performed in an atmosphere of nitrogen-containing gas. The conductive films 112a_2 and 112b_2 contain copper silicide containing copper, silicon, and nitrogen. A tolide may be formed. Alternatively, the substrate may be exposed to a nitrogen-containing gas atmosphere and subjected to heat treatment. Therefore, the conductive films 112a_2 and 112b_2 contain copper, silicon, and nitrogen. A donitride may be formed.

[0203] Next, a portion on conductive film 112_1, and conductive films 112a_2, 112b_2, 112a _3, 112b_3 is used to form masks 142a and 142b in the desired region. Subsequently, By processing the conductive film 112_1 using scr 142a and 142b, each of them is able to process each other Separated island-shaped conductive films 112a_1 and 112b_1 are formed. By performing this process, , conductive film 1 having region 112a_1 and region 112a_2a and region 112a_2b A conductive film 112a having 12a_2 and conductive film 112_3, and conductive film 112b_1 , conductive film 112b_2 having region 112b_2a and region 112b_2b, and conductive film 1 A conductive film 112b having 12b_3 is formed (see Figures 16(A) and 16(B)).

[0204] In this embodiment, a dry etching apparatus is used to add the conductive film 112_1. Process. However, the processing method for the conductive film 112_1 is not limited to this, for example, A wet etching apparatus may be used. Rather than processing 112_1, the conductive film 112_1 is processed using a dry etching apparatus. This allows for the formation of finer patterns.

[0205] Furthermore, after the formation of conductive films 112a and 112b, the oxide semiconductor film 108 (more specifically) The surface (back channel side) of the oxide semiconductor film 108b) may be cleaned. For example, cleaning using a chemical solution such as phosphoric acid. By performing the cleaning, impurities attached to the surface of the oxide semiconductor film 108b (for example, conductive film 1 It is possible to remove elements (such as those contained in 12a and 112b). Note that this washing must be performed It is not necessary to do so, and in some cases, cleaning may not even be required.

[0206] Furthermore, either the step of forming conductive films 112a and 112b, or the cleaning step described above, In both cases, the region exposed from the conductive film 112a, 112b of the oxide semiconductor film 108. However, it may become thinner.

[0207] ≪Second gate insulating film formation process≫ Next, an insulating film 114 is applied to the oxide semiconductor film 108 and the conductive films 112a and 112b, and The insulating film 116 is formed (see Figure 16(C)(D)).

[0208] Furthermore, after forming the insulating film 114, the insulating film 116 is formed continuously without exposure to the atmosphere. It is preferable to do so. After forming the insulating film 114, do not open it to the atmosphere, and control the flow rate, pressure, and high of the raw material gas. By adjusting the frequency power and substrate temperature to one or more units, the insulating film 116 is formed continuously, The concentration of impurities originating from atmospheric components at the interface between the edge film 114 and the insulating film 116 is reduced. In addition, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. This makes it possible to reduce the amount of oxygen vacancies in the oxide semiconductor film 108. .

[0209] For example, a silicon oxide nitride film is formed as the insulating film 114 using the PECVD method. This is possible. In this case, the raw material gases include a silicon-containing sedimentary gas and an oxidizing gas. It is preferable to use [a specific type of gas]. Typical examples of silicon-containing sedimentary gases include silane and disila. Examples include nitrates, trisilanes, and silane fluorides. Oxidizing gases include nitrous oxide and nitrogen dioxide. There are elements such as [unclear]. Also, the flow rate of the oxidizing gas is greater than 20 times the flow rate of the sedimentary gas mentioned above. The pressure should be less than 100 times, preferably between 40 and 80 times, and the pressure inside the processing chamber should be less than 100 Pa. By using a PECVD method with a pressure of full, preferably 50 Pa or less, the insulating film 114 is treated with nitrogen This results in an insulating film that contains and has a low defect rate.

[0210] In this embodiment, the insulating film 114 is set to a temperature of 220°C for holding the substrate 102. The raw materials are silane at a flow rate of 50 sccm and nitrous oxide at a flow rate of 2000 sccm. The pressure inside the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz. Hz, 100W (power density is 1.6 × 10⁻⁶) -2 W / cm 2 The PECVD method is used as follows: A silicon oxide nitride film is formed using this method.

[0211] As the insulating film 116, the substrate placed in the vacuum-evacuated processing chamber of the PECVD apparatus Maintain the temperature between 180°C and 350°C, introduce the raw material gas into the processing chamber, and adjust the pressure within the processing chamber. The pressure is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. , 0.17 W / cm² is applied to the electrode installed in the processing chamber. 2 More than 0.5W / cm 2 Below, further better The current level is 0.25 W / cm². 2 More than 0.35W / cm 2 The following conditions apply to supplying high-frequency power: This then forms a silicon oxide film or a silicon oxide-nitride film.

[0212] As for the film deposition conditions for the insulating film 116, the above pressure is used in the reaction chamber and the above power density is used in the high-frequency current By supplying power, the decomposition efficiency of the raw material gas in the plasma increases, and the amount of oxygen radicals increases. As the oxidation of the raw material gas progresses, the oxygen content in the insulating film 116 becomes less than the stoichiometric composition. The number also increases. On the other hand, in films formed at the above temperature, the bonding force between silicon and oxygen Because the bond is weak, some of the oxygen in the film is removed by the subsequent heat treatment. As a result, stoichiometric An oxide containing more oxygen than the theoretically required oxygen composition, with some of the oxygen being removed upon heating. An insulating film can be formed.

[0213] Furthermore, in the process of forming the insulating film 116, the insulating film 114 protects the oxide semiconductor film 108. It forms a film. Therefore, while reducing damage to the oxide semiconductor film 108, the power density is The insulating film 116 can be formed using high-frequency power.

[0214] Furthermore, in the film formation conditions for the insulating film 116, silicon-containing deposition gas against oxidizing gas By increasing the flow rate of the material, it is possible to reduce the amount of defects in the insulating film 116. ESR measurement revealed that g=2.001 originates from the dangling bond of silicon. The spin density of the signal is 6 × 10 17 spins / cm 3 Less than 3 × 10 17 spins / cm 3 The following is preferably 1.5 × 10 17 spins / cm 3 The following is missing It is possible to form an oxide insulating film with fewer depressions. As a result, the signal of transistor 100 It can enhance reliability.

[0215] Furthermore, after forming the insulating films 114 and 116, a heat treatment (hereinafter referred to as the second heat treatment) is performed. It is preferable to perform the following: The second heat treatment removes nitrogen acid contained in the insulating films 114 and 116. The amount of oxidized material can be reduced by a second heat treatment. Some of the oxygen contained in the oxide semiconductor film 108 is transferred to the oxide semiconductor film 108. This can reduce the amount of oxygen deficiency.

[0216] The temperature of the second heat treatment is typically less than 400°C, preferably less than 375°C, and Preferably, the temperature is between 150°C and 350°C. The second heat treatment involves nitrogen, oxygen, and superdry Dry air (water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb) The procedure can be carried out under the atmosphere of air or a noble gas (argon, helium, etc.). Preferably, the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain hydrogen, water, etc. For heat treatment, electric furnaces, RTA devices, etc., can be used.

[0217] Next, a mask is formed on the insulating film 116 by a lithography process, and insulating films 114, 11 An opening 152c is formed in the desired region of 6. Note that the opening 152c is connected to the conductive film 112b. It is formed to reach (see Figures 16(E)(F)).

[0218] ≪Process for forming the second gate electrode≫ Next, conductive films 120a and 120b are formed on the insulating film 116 so as to cover the opening 152c. This is achieved (see Figures 17(A), (B), (C), and (D)).

[0219] Figures 17(A) and 17(B) show the formation of conductive films 120a and 120b on the insulating film 116. This is a schematic cross-sectional view of the inside of the film deposition apparatus. Figures 17(A) and (B) show a spade film deposition apparatus. Using a sputtering device, a target 193 installed inside the sputtering device, The plasma 194 formed below target 193 is schematically represented.

[0220] First, when forming the conductive films 120a and 120b, the atmosphere containing a third oxygen gas is used. The rasma is discharged. At that time, the insulating film 11 which will be the surface on which the conductive films 120a and 120b are formed Oxygen is added to 6. Also, when forming the conductive films 120a and 120b, a third acid In addition to primary gases, inert gases (such as helium, argon, and xenon) are also used. They may be mixed. For example, argon gas and a third oxygen gas may be used, and argon gas It is preferable to have a higher flow rate for the third oxygen gas than for the third oxygen gas. By increasing the amount, oxygen can be suitably added to the insulating film 116. For example, The conditions for forming the films 120a and 120b are as follows: the proportion of the fourth oxygen gas in the total film-forming gas. The ratio should be between 50% and 100%, preferably between 80% and 100%.

[0221] In Figures 17(A) and 17(B), the oxygen or excess oxygen added to the insulating film 116 is This is schematically represented by a dashed arrow.

[0222] Furthermore, the substrate temperature when depositing the conductive films 120a and 120b should be above room temperature and up to 340°C. Less than, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C. More preferably, the temperature is between 100°C and 200°C. The conductive films 120a and 120b are heated. By forming the film, the crystallinity of the conductive films 120a and 120b can be increased. On the other hand, the base When using a large glass substrate (for example, a 6th to 10th generation) as the plate 102, When the substrate temperature during the deposition of conductive films 120a and 120b is set to 150°C or higher and less than 340°C, In addition, the substrate 102 may deform (become warped or bent). Therefore, large glass substrates When using this method, the substrate temperature during the deposition of the conductive films 120a and 120b should be 100°C or higher. By keeping the temperature below 150°C, deformation of the glass substrate can be suppressed.

[0223] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: Using a 2:4.1 [atomic ratio], conductive films 120a and 120b were produced by sputtering. This is formed. Furthermore, the substrate temperature during the formation of conductive films 120a and 120b is set to 170°C. Furthermore, the deposition gas used during the formation of conductive films 120a and 120b was oxygen at a flow rate of 100 sccm. Use gas.

[0224] Note that conductive films 120a and 120b may be, for example, the oxide semiconductor film described above (for example) For example, In:Ga:Zn = 1:1:1 [atomic ratio], In:Ga:Zn = 1:3:2 [atomic ratio] [Atomic ratio] In:Ga:Zn=1:3:4 [Atomic ratio] In:Ga:Zn=1:3:6 [ [Atomic ratio] In:Ga:Zn=3:1:2 [Atomic ratio] In:Ga:Zn=4:2 You can use a ratio of 3 [atomic ratio], such as In:Ga:Zn=5:1:6 [atomic ratio].

[0225] In this embodiment, when forming the conductive films 120a and 120b, oxygen is added to the insulating film 116. The methods of addition are illustrated, but are not limited to these. For example, conductive films 120a, 120 After forming b, oxygen may be further added to the insulating film 116.

[0226] Methods for adding oxygen to the insulating film 116 include, for example, indium, tin, and silicon. Oxide target (also called ITSO) having (In2O3:SnO2:SiO2= Using 85:10:5 [weight %]), an ITSO film with a thickness of 5 nm is formed as an oxide conductive film. To accomplish.

[0227] In this case, the thickness of the oxide conductive film is 1 nm to 20 nm, or 2 nm or more. A wavelength of 10 nm or less is preferable because it allows for suitable oxygen permeation while suppressing oxygen release. Subsequently, oxygen is added to the insulating film 116 by passing it through the oxide conductive film. The method of adding oxygen and Examples include ion doping, ion implantation, and plasma treatment. When adding the element, applying a bias voltage to the substrate side effectively blocks oxygen from the insulating film 116. It can be added to the above bias voltage, for example, by using an ashing device. The power density of the bias voltage applied to the substrate side of the ashing device is 1 W / cm². 2 5W / cm 2 The following is acceptable. Furthermore, the substrate temperature when adding oxygen should be above room temperature or 300°C. By setting the temperature below ℃, preferably between 100℃ and 250℃, the insulating film 116 can be efficiently heated. Oxygen can be added.

[0228] Next, the deposited conductive film is processed into the desired shape to form island-shaped conductive films 120a, and islands A conductive film 120b is formed (see Figures 17(C) and 17(D)).

[0229] ≪Process for forming protective insulating film≫ Next, an insulating film 118 is formed on the insulating film 116 and the conductive films 120a and 120b (Figure 17(E)(F)).

[0230] The insulating film 118 contains either hydrogen or nitrogen, or both. For example, a silicon nitride film is preferable. Also, as the insulating film 118, for example For example, it can be formed using the sputtering method or the PECVD method. When depositing the edge film 118 by PECVD, the substrate temperature should be less than 400°C, preferably 375°C. The temperature is less than ℃, more preferably 180℃ or higher and 350℃ or lower. It is preferable to set the substrate temperature within the above-mentioned range, as this allows for the formation of a dense film. By setting the substrate temperature when depositing the insulating film 118 to the above range, the insulating film 114, 1 This makes it possible to transfer oxygen or excess oxygen from 16 to the oxide semiconductor film 108.

[0231] Furthermore, after forming the insulating film 118, an equivalent heat treatment to the first or second heat treatment described above is performed. A heat treatment (hereinafter referred to as the third heat treatment) may be performed. In this way, insulating film 118 During film formation, oxygen is added to the insulating film 116, and then the temperature is set to less than 400°C, preferably 375°C. By performing a heat treatment at a temperature of less than 350°C, more preferably between 180°C and 350°C, Oxygen or excess oxygen in the edge film 116 is removed from the oxide semiconductor film 108 (especially the oxide semiconductor film 108) b) It can be moved into the oxide semiconductor film 108 to fill in the oxygen vacancies.

[0232] Furthermore, an insulating film 106 is provided below the insulating film 107, and insulating films 114, 11 An insulating film 118 is provided above 6. The insulating films 106 and 118 have low oxygen permeability. By forming with a material such as silicon nitride, insulating films 107, 114, and 116 Because the oxygen contained within can be trapped on the oxide semiconductor film 108 side, oxidation can be suitably controlled. This makes it possible to transfer oxygen to the semiconductor film 108.

[0233] Furthermore, the insulating film 118 contains either hydrogen or nitrogen, or both. By forming the insulating film 118, the conductive films 120a and 120b in contact with the insulating film 118 are The addition of either hydrogen or nitrogen, or both, increases the carrier density. It can function as an oxide conductive film.

[0234] Furthermore, when forming a silicon nitride film as the insulating film 118 by the PECVD method, It is preferable to use a sedimentary gas containing nitrogen, nitrogen, and ammonia as raw material gases. By using a small amount of ammonia compared to the original, the ammonia dissociates in the plasma and becomes active. Seeds are generated. These active species bond silicon and hydrogen contained in the silicon-containing sedimentary gas. It breaks the triple bond between silicon and nitrogen. As a result, the bonding between silicon and nitrogen is promoted, It forms a dense silicon nitride film with fewer silicon and hydrogen bonds and fewer defects. Yes, it is possible. On the other hand, if the amount of ammonia relative to nitrogen is high, the sedimentary gas containing silicon and nitrogen The decomposition of the elements did not proceed, and silicon and hydrogen bonds remained, resulting in an increase in defects and a rough texture. A silicon nitride film is formed. For these reasons, in the raw material gas, ammonia It is preferable to set the nitrogen flow rate ratio to 5 to 50 times, or 10 to 50 times.

[0235] In this embodiment, the insulating film 118 is made using a PECVD apparatus, and silane and nitrogen A silicon nitride film with a thickness of 100 nm is formed using aluminium and ammonia as raw material gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The process is in sccm. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350°C, and the process is 27.12 MHz. A high-frequency power supply of z is used to supply 1000W of high-frequency power to the parallel plate electrodes. PECVD The device has an electrode area of ​​6000 cm². 2 It is a parallel plate type PECVD apparatus, and the supplied electricity Converting force to power per unit area (power density) gives 1.7 × 10⁻⁶. -1 W / cm 2 That is .

[0236] By following the above steps, the transistor 100J shown in Figures 9(A) and 9(B) can be fabricated.

[0237] Furthermore, in all manufacturing processes for the 100J transistor, the substrate temperature was kept below 400°C. The temperature should be less than 375°C, and more preferably between 180°C and 350°C, Even when using multi-layered substrates, the deformation (distortion or warping) of the substrate can be kept to a minimum. It is suitable. In addition, in the manufacturing process of transistor 100J, there is a step in which the substrate temperature becomes high. Typical examples include the substrate temperature during the deposition of insulating films 106 and 107 (less than 400°C, preferably...) (or 250°C to 350°C), the substrate temperature during deposition of the oxide semiconductor film 108 (room temperature or below) Above 340°C, preferably 100°C to 200°C, more preferably above 100°C (less than 150°C), substrate temperature during deposition of insulating films 116 and 118 (less than 400°C, preferably) Below 375°C, more preferably 180°C to 350°C), the first addition after oxygen is added. Heat treatment or second heat treatment (less than 400°C, preferably less than 375°C, more preferably Examples include temperatures between 180°C and 350°C.

[0238] <1-7. Method for Fabricating Transistors 2> Next, regarding the method for fabricating a transistor 100M, which is a semiconductor device according to one aspect of the present invention, This will be explained using Figures 18 to 20. Figures 18 to 20 show the method for manufacturing a semiconductor device. These are cross-sectional diagrams illustrating the following: Figures 18(A)(C)(E), 19(A)(C), and 20(A ) is in the channel length direction shown by X1-X2, as shown in Figures 18(B)(D)(F) and 19(B Figures 20(D) and 20(B) are cross-sectional views in the channel width direction shown by Y1-Y2.

[0239] Conductive film 104, insulating film 106, 107, oxide semiconductor film 108, conductive film 112_1, conductive Electrical film 112a_2 (area 112a_2a, 112a_2b), conductive film 112b_2 (area The shapes of conductive films 112b_2a, 112b_2b, conductive film 112a_3, and conductive film 112b_3. The formation method is the same as the formation method for transistor 100J mentioned earlier, therefore see Figure 14 and Figure You should take 15 into consideration.

[0240] In this embodiment, the conductive film 112_1 used for the conductive film 112 has a thickness of 50 nm. The tungsten film, the copper film with a thickness of 200 nm as conductive film 112_2, and conductive film 112_ As for 3, a multilayer film is used, which consists of a 50 nm thick titanium film and a layer stacked in sequence.

[0241] Next, conductive films 112a_2, 112b_2, and 112_3 are used as masks, and conductive film 112 By processing _1, island-shaped conductive films 112a_1 and 112b, which are separated from each other, are formed. _1 is formed. By performing this process, conductive film 112a_1, conductive film 112a_2 (area Conductive film 112a having regions 112a_2a, 112a_2b) and conductive film 112a_3 , conductive film 112b_1, conductive film 112b_2 (regions 112b_2a, 112b_2b) , and conductive film 112b having conductive film 112b_3 are formed (Figure 18(A)(B )reference).

[0242] The method for forming the conductive films 112a and 112b is the same as that used for transistor 100J. It can be used.

[0243] Next, insulating films 114, 11 are placed on the oxide semiconductor film 108 and the conductive films 112a, 112b. 6, and insulating film 118 are formed (see Figure 18(C)(D)(E)(F)). Insulating film 11 For the formation of 4, 116, and 118, the same method as for transistor 100J is used. It is possible.

[0244] Furthermore, after forming the insulating film 118, an equivalent heat treatment to the first or second heat treatment described above is performed. A heat treatment (hereinafter referred to as the third heat treatment) may be performed. In this way, insulating film 118 During film formation, oxygen is added to the insulating film 116, and then the temperature is set to less than 400°C, preferably 375°C. By performing a heat treatment at a temperature of less than 350°C, more preferably between 180°C and 350°C, Oxygen or excess oxygen in the edge film 116 is removed from the oxide semiconductor film 108 (especially the oxide semiconductor film 108) b) It can be moved into the oxide semiconductor film 108 to fill in the oxygen vacancies.

[0245] Here, we will explain the movement of oxygen into the oxide semiconductor film 108 using Figure 20. Figure 20 shows the substrate temperature (typically less than 375°C) during the deposition of insulating film 118, or the insulating film temperature. A second heat treatment (typically below 375°C) after the formation of 118 results in the oxide semiconductor film This is a model diagram representing the movement of oxygen into 10⁸. Note that in Figure 20, oxide semiconductor Oxygen (oxygen radical, oxygen atom, or oxygen molecule) shown in membrane 108 is represented by a dashed arrow. It is.

[0246] The oxide semiconductor film 108 shown in Figure 20 is adjacent to the insulating film (here Then, oxygen moves from insulating film 107 and insulating film 114) to fill the oxygen deficiency. In particular, in a semiconductor device according to one aspect of the present invention, the oxide semiconductor film 108b is sputtered. During ring deposition, oxygen gas is used to add oxygen to the insulating film 107, therefore insulating film 107 It has an excess oxygen region. Also, when using oxygen gas during sputtering deposition of oxide conductive films Furthermore, because oxygen is added to the insulating film 116, the insulating film 116 has an excess oxygen region. Therefore, the oxide semiconductor film 108 sandwiched between insulating films having excess oxygen regions preferably has oxygen vacancies. It will be compensated.

[0247] Next, a mask is formed on the insulating film 118 by a lithography process, and insulating films 114, 11 6. An opening 152c is formed in the desired region of 118. Note that the opening 152c is a conductive film It is formed to reach 112b (see Figure 19(A)(B)).

[0248] Next, conductive films 120a and 120b are formed on the insulating film 116 so as to cover the opening 152c. This is achieved (see Figure 19(C)(D)). The conductive films 120a and 120b are transistors. The same method as for 100J can be used.

[0249] By following the above steps, the transistor 100M shown in Figure 10(C) can be manufactured.

[0250] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments. They can be used together.

[0251] (Embodiment 2) In this embodiment, the composition of the oxide semiconductor that can be used in one aspect of the present invention The structure of oxide semiconductors and other related aspects will be explained with reference to Figures 21 to 28.

[0252] <2-1. Composition of Oxide Semiconductors> First, let's explain the composition of oxide semiconductors.

[0253] The oxide semiconductor preferably contains at least indium or zinc. In particular, indium Preferably, it contains aluminum and zinc. In addition, aluminum and gallium It is preferable that it contains yttrium or tin, as well as boron and silicon. Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from materials such as magnesium, neodymium, hafnium, tantalum, tungsten, or magnesium. It may include one or more of the specified types.

[0254] Here, we consider the case where the oxide semiconductor contains indium, element M, and zinc. Element M may be aluminum, gallium, yttrium, or tin. The elements applicable to element M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Examples include tungsten and magnesium. However, as element M, multiple sets of the aforementioned elements are used. There are cases where it's acceptable to combine them.

[0255] First, using Figures 21(A), 21(B), and 21(C), one aspect of the present invention is shown. Regarding the preferred range of atomic ratios of indium, element M, and zinc in the oxide semiconductor concerned I will explain this. Note that the atomic ratio of oxygen is not shown in Figure 21. Also, oxide semi-oxides The terms representing the atomic ratios of indium, element M, and zinc in the conductor are [In] and [M] respectively. Let ] and [Zn] be the two elements.

[0256] In Figures 21(A), 21(B), and 21(C), the dashed line represents [In]:[M The line where the atomic ratio of ]:[Zn]=(1+α):(1-α):1 (-1≦α≦1), [In]:[M]:[Zn]=(1+α):(1-α):2 is the line where the atomic ratio is, In]:[M]:[Zn]=(1+α):(1-α):3 is the line where the atomic ratio is [I The line where the atomic ratio of n]:[M]:[Zn]=(1+α):(1-α):4, and [In]:[M]:[Zn]=(1+α):(1-α):5 represents the atomic ratio. vinegar.

[0257] Furthermore, the dashed line represents the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0) The line where the atomic ratio is [In]:[M]:[Zn]=1:2:β, [In [In]:[M]:[Zn] = 1:3:β is the atomic ratio line, [In]:[M]:[Zn The line with an atomic ratio of ]=1:4:β, and the original [In]:[M]:[Zn]=2:1:β The line representing the atom ratio, and the line representing the atomic ratio of [In]:[M]:[Zn]=5:1:β. It represents "in".

[0258] Furthermore, the dotted line represents atoms with the configuration [In]:[M]:[Zn]=(1+γ):2:(1-γ). This represents the line where the numerical ratio is (-1≦γ≦1). Also, as shown in Figure 21, [In]:[M]:[ Oxide semiconductors with an atomic ratio of Zn = 0:2:1 or near that value have a spinel-type crystal structure. It is easy to construct.

[0259] Figures 21(A) and 21(B) show the indicators of an oxide semiconductor according to one embodiment of the present invention. An example of a preferred range for the atomic ratio of um, element M, and zinc is shown.

[0260] As an example, Figure 22 shows InMZn, where [In]:[M]:[Zn]=1:1:1. Figure 22 shows the crystal structure of O4. Figure 22 also shows the InMZ crystal structure when viewed from a direction parallel to the b-axis. This is the crystal structure of nO4. Note that the layer containing M, Zn, and oxygen shown in Figure 22 (hereinafter referred to as (M, In the Zn layer, the metallic element represents element M or zinc. In this case, element M and sub Assume the proportion of lead is equal. Element M and zinc are substituted for each other, and their arrangement is irregular. ru.

[0261] InMZnO4 has a layered crystalline structure (also called a layered structure), as shown in Figure 22. A layer containing indium and oxygen (hereinafter referred to as the In layer) is divided into 1 part, and elements M, zinc, and The (M,Zn) layer containing oxygen is 2.

[0262] Furthermore, indium and element M are mutually substitutable. Therefore, the (M,Zn) layer The element M can be substituted with indium, and the layer can also be represented as an (In,M,Zn) layer. In that case, In It has a layered structure with one layer and two (In,M,Zn) layers.

[0263] In oxide semiconductors with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is For every 1, it takes on a layered structure with 3 (M,Zn) layers. In other words, [In] and [M] In contrast, when [Zn] becomes large, if the oxide semiconductor crystallizes, the (M,Z) relative to the In layer The proportion of layer n) increases.

[0264] However, in an oxide semiconductor, the In layer has a value of 1, while the (M,Zn) layer has a value of a non-integer. In some cases, there are multiple types of layered structures where the number of In layers is 1 and the number of (M,Zn) layers is an integer. For example, if [In]:[M]:[Zn]=1:1:1.5, then the In layer is 1. Furthermore, a mixture of layered structures with two (M,Zn) layers and layered structures with three (M,Zn) layers exists. It may take on a layered structure.

[0265] For example, when depositing an oxide semiconductor film using a sputtering apparatus, the atomic ratio of the target A film with an atomic ratio that deviates from the target is formed. In particular, depending on the substrate temperature during film formation, the target In some cases, the [Zn] content of the film may be smaller than the [Zn] content of the surrounding material.

[0266] Furthermore, multiple phases may coexist within an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence). For example, the atomic ratios that are close to the atomic ratio [In]:[M]:[Zn]=0:2:1 In this material, two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. Also, [In]: In atomic ratios that are near the atomic ratio [M]:[Zn]=1:0:0, the Bixbar Two phases, one with a crystalline structure and the other with a layered structure, can easily coexist. Multiple phases in oxide semiconductors When they coexist, grain boundaries (also called grain boundaries) exist between different crystal structures. It may form.

[0267] Furthermore, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor can be improved. The mobility can be increased. This is an oxide semiconductor containing indium, element M, and zinc. In conductors, the s orbitals of heavy metals primarily contribute to carrier conduction, and the indium content... By increasing the s orbital, the region where the s orbitals overlap becomes larger, thus increasing the indium content. Oxide semiconductors with a high indium content have higher carrier mobility compared to oxide semiconductors with a low indium content. This is because it will increase.

[0268] On the other hand, when the content of indium and zinc in oxide semiconductors decreases, carrier mobility Therefore, the atomic ratio that shows [In]:[M]:[Zn]=0:1:0, and In the vicinity of that value, the atomic ratio (for example, region C shown in Figure 21(C)), the insulating properties are high. .

[0269] Therefore, an oxide semiconductor according to one aspect of the present invention has high carrier mobility and few grain boundaries. It is preferable to have an atomic ratio that tends to form a layered structure, as shown in region A of Figure 21(A). It's nice.

[0270] Furthermore, region B shown in Figure 21(B) is 4 from [In]:[M]:[Zn]=4:2:3 .1 and its neighboring values ​​are shown. Neighboring values ​​include, for example, atomic ratios [In]:[M The region B contains oxide semiconductors with an atomic ratio of 5:3:4, as shown in region B. It is an excellent oxide semiconductor, particularly possessing high crystallinity and high carrier mobility.

[0271] Note that the conditions for the oxide semiconductor to form a layered structure are not uniquely determined by the atomic ratio. There is a difference in the difficulty of forming a layered structure depending on the atomic ratio. On the other hand, even with the same atomic ratio, depending on the formation conditions, there may be cases where a layered structure is formed and cases where a layered structure is not formed. Therefore, the illustrated region indicates the atomic ratio at which the oxide semiconductor has a layered structure, and the boundary between region A and region C is not precise. Note that the conditions for the oxide semiconductor to form a layered structure are not uniquely determined by the atomic ratio. There is a difference in the difficulty of forming a layered structure depending on the atomic ratio. On the other hand, even with the same atomic ratio there may be cases where a layered structure is formed and cases where a layered structure is not formed depending on the formation conditions. Therefore, the illustrated region indicates the atomic ratio at which the oxide semiconductor has a layered structure, and the boundary between region A and region C is not precise.

[0272] <2-2. Structure using the oxide semiconductor in a transistor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0273] Note that by using the above oxide semiconductor in a transistor, carrier scattering at grain boundaries and the like can be reduced, so that a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0274] Also, it is preferable to use an oxide semiconductor with a low carrier density for the transistor. For example, the carrier density of the oxide semiconductor is less than 8×10 11 / cm 3 preferably less than 1×1 0 11 / cm 3 more preferably less than 1×10 10 / cm 3 and it is sufficient to be 1×10 -9 / cm 3 or more.

[0275] Note that an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, so that the carrier density can be lowered. Also, an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, so that the trap level density is also low. Note that an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, so that the carrier density can be lowered. Also, an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, so that the trap level density is also low. ​​​ There are cases where this is the case.

[0276] Furthermore, the time required for charges trapped in the trap levels of an oxide semiconductor to disappear is... It can behave for a long time, almost like a fixed charge. Therefore, the trap level density is high. In transistors where a channel region is formed in an oxide semiconductor, the electrical properties become unstable. There is a match.

[0277] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is Reducing it is effective. Furthermore, in order to reduce the impurity concentration in oxide semiconductors, It is also preferable to reduce the concentration of impurities in the adjacent membrane. Examples of impurities include hydrogen, nitrogen, and Examples include potassium metals, alkaline earth metals, iron, nickel, and silicon.

[0278] Here, we will explain the effects of various impurities in oxide semiconductors.

[0279] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, oxidation occurs. Defect levels are formed in silicon semiconductors. Therefore, in oxide semiconductors, silicon and carbon The concentration of the element and the concentrations of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration obtained is 2 × 10 18 atoms / cm 3 The following is preferably 2 × 10 17 a toms / cm 3 The following applies:

[0280] Furthermore, if an alkali metal or alkaline earth metal is present in the oxide semiconductor, the defect levels will be When formed, carriers may be generated. Therefore, an alkali metal or an alkaline earth metal A transistor using an oxide semiconductor containing it tends to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10[[ID=⑨]] 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0281] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, and the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×10 17 atoms / cm 3 or less.

[0282] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, resulting in the formation of oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons as carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms, and the It can generate electrons that act as carriers. Therefore, an oxide semiconductor containing hydrogen is used. Transistors with this characteristic tend to exhibit normally-on properties. Therefore, hydrogen in oxide semiconductors It is preferable that the SI is reduced as much as possible. Specifically, in oxide semiconductors, The hydrogen concentration obtained by MS is 1 × 10 20 atoms / cm 3 Less than 1x 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 less than More preferably 1 × 10 18 atoms / cm 3 Less than.

[0283] Using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor. This allows for the provision of stable electrical characteristics.

[0284] <2-3. Layered Structure of Oxide Semiconductors> Next, we will discuss the case where the oxide semiconductor has a two-layer or three-layer structure. An insulator in contact with a stacked structure of a monocrystalline semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3 The band diagram and the bands of the insulator in contact with the layered structure of oxide semiconductor S2 and oxide semiconductor S3. Figure 23 will be used to explain the relationship between Figure D and Figure 23.

[0285] Figure 23(A) shows insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S Figure 23 is an example of a band diagram in the film thickness direction of a laminated structure having 3 and an insulator I2. (B) comprises an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. This is an example of a band diagram in the film thickness direction of a laminated structure. Note that the band diagram is presented for ease of understanding. Insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2 This shows the energy level (Ec) at the lower end of the conduction band.

[0286] Oxide semiconductors S1 and S3 have a lower energy band than oxide semiconductor S2. The Ghee level is close to the vacuum level, and typically, it is the energy level at the lower end of the conduction band of oxide semiconductor S2. The difference between the position and the energy level at the lower end of the conduction band of oxide semiconductor S1 and oxide semiconductor S3 is 0 The voltage must be 0.15 eV or higher, or 0.5 eV or higher and 2 eV or lower, or 1 eV or lower. This is preferable. That is, the electron affinity of oxide semiconductor S1 and oxide semiconductor S3 is less important than the electron affinity of oxide semiconductor S3. The electron affinity of the monocrystalline semiconductor S2 is high, while the electron affinity of oxide semiconductors S1 and S3 is low. The difference between this and the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more. And preferably it is 2 eV or less, or 1 eV or less.

[0287] As shown in Figures 23(A) and 23(B), oxide semiconductor S1, oxide semiconductor S 2. In oxide semiconductor S3, the energy level at the lower end of the conduction band changes smoothly. In other words, it can be said that it changes continuously or is continuously joined. Such a band diagram In order to have this, the interface between oxide semiconductor S1 and oxide semiconductor S2, or the oxide semiconductor Lowering the defect level density of the mixed layer formed at the interface between S2 and the oxide semiconductor S3 good.

[0288] Specifically, oxide semiconductor S1 and oxide semiconductor S2, oxide semiconductor S2 and oxide semiconductor S3 has a common element other than oxygen (it is the main component), resulting in a low defect level density. A composite layer can be formed. For example, if the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor In the case of a body, the oxide semiconductor S1 and oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. Ga-Zn oxide semiconductors, gallium oxide, etc., are good choices to use.

[0289] In this case, the main carrier pathway is through the oxide semiconductor S2. Oxide semiconductor S1 and oxide Defects at the interface with the material semiconductor S2, and at the interface between the oxide semiconductor S2 and the oxide semiconductor S3. Because the depression density can be reduced, the influence of interfacial scattering on carrier conduction is small. This allows for a high on-current.

[0290] When an electron is trapped in a trap level, the trapped electron behaves like a fixed charge. Therefore, the transistor's threshold voltage shifts in the positive direction. Oxide semiconductor S1 By providing the oxide semiconductor S3, the trap level is moved further away from the oxide semiconductor S2. This configuration allows the threshold voltage of the transistor to shift in the positive direction. This can prevent it from happening.

[0291] Oxide semiconductors S1 and S3 have sufficient conductivity compared to oxide semiconductor S2. Low-quality materials are used. At this time, oxide semiconductor S2, oxide semiconductor S2 and oxide semiconductor S The interface with 1, and the interface between oxide semiconductor S2 and oxide semiconductor S3, are mainly channel regions. It functions as follows. For example, in oxide semiconductor S1 and oxide semiconductor S3, as shown in Figure 21(C) Therefore, an oxide semiconductor with the atomic ratio shown in region C, where insulation is high, should be used. The region C shown in 21(C) is [In]:[M]:[Zn]=0:1:0, or its vicinity. This shows the ratio of the number of atoms, which is a value.

[0292] In particular, when using an oxide semiconductor with the atomic ratio shown in region A for the oxide semiconductor S2, acid The oxide semiconductor S1 and the oxide semiconductor S3 have a [M] / [In] ratio of 1 or more, preferably 2. It is preferable to use an oxide semiconductor that is as described above. Furthermore, as the oxide semiconductor S3, it is sufficient Oxides that can obtain high insulating properties, such as those with an [M] / ([Zn]+[In]) ratio of 1 or more. It is preferable to use semiconductors.

[0293] <2-4. Structure of Oxide Semiconductors> The structure of oxide semiconductors will be described below.

[0294] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It is possible. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Solid semiconductor, nc-OS (nanocrystalline oxide semiconductor) ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- (like oxide semiconductors) and amorphous oxide semiconductors, etc. be.

[0295] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxides. Semiconductors can be divided into two categories. Crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC. Examples include -OS, polycrystalline oxide semiconductors, and nc-OS.

[0296] Amorphous structures are generally isotropic and lack heterogeneity; they are metastable states with a specific arrangement of atoms. The position is not fixed, the connection angle is flexible, and it has short-range order but not long-range order. It is said that there isn't any.

[0297] In other words, a stable oxide semiconductor is completely amorphous. s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, periodic in a minute region). Oxide semiconductors that have a structure cannot be called perfectly amorphous oxide semiconductors. On the other hand, al Ike OS is an unstable structure that is not isotropic but contains voids (also called porous structures). In terms of instability, a-like OS is physically close to amorphous oxide semiconductors. stomach.

[0298] ≪CAAC-OS≫ First, let me explain CAAC-OS.

[0299] CAAC-OS is an oxide having multiple c-axis oriented crystalline portions (also called pellets). It is a type of semiconductor.

[0300] CAAC-OS was analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as having the space group R-3m. Structural analysis was performed on CAAC-OS, which has crystals, using the out-of-plane method. Then, as shown in Figure 24(A), a peak appears near 31° at the diffraction angle (2θ). The mark is attributed to the (009) plane of the InGaZnO4 crystal, therefore CAAC-OS Therefore, the crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also known as the film-forming surface). It can be confirmed that it is facing in a direction approximately perpendicular to the upper surface. Note that 2θ is 31 In addition to the peak near °, a peak may also appear when 2θ is near 36°. The nearby peaks are due to a crystal structure classified as space group Fd-3m. Therefore, CAA It is preferable that C-OS does not exhibit this peak.

[0301] On the other hand, for CAAC-OS, in-pl X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ANE method reveals a peak near 2θ = 56°. This peak is... It is attributed to the (110) plane of the InGaZnO4 crystal. And 2θ is fixed near 56°. Then, the sample is rotated around the normal vector of the sample surface as the axis (φ axis) while being analyzed (φ scan). Even after performing this procedure, no clear peak appears, as shown in Figure 24(B). On the other hand, single crystal InGa When 2θ is fixed near 56° and a φ scan is performed on ZnO4, the result is shown in Figure 24(C). Six peaks are observed that are attributed to the crystal plane equivalent to the (110) plane. Therefore, Structural analysis using XRD revealed that CAAC-OS has irregular orientations in the a-axis and b-axis. This can be confirmed.

[0302] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGa For CAAC-OS having ZnO4 crystals, a pro is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 24(D) is produced. This is also called a limited-field electron diffraction pattern. A specific diffraction pattern may appear. The nGaZnO4 crystal contains spots originating from the (009) plane. Therefore, electrons Diffraction also reveals that the pellets contained in CAAC-OS exhibit c-axis orientation, and the c-axis is formed. It can be seen that it is oriented in a direction approximately perpendicular to the surface or top surface. On the other hand, for the same sample, the sample surface Figure 24 shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the surface. As shown in Figure 24(E), a ring-shaped diffraction pattern can be observed. Therefore, Pro Electron diffraction using an electron beam with a beam diameter of 300 nm also revealed the presence of particles in CAAC-OS. It can be seen that the a-axis and b-axis of Lett do not have orientation. Note that in Figure 24(E) The first ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, etc. It is thought that the second ring in Figure 24(E) is caused by the (110) plane, etc. It is thought that...

[0303] Furthermore, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using an icroscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., the grain boundaries, are not visible. Also called boundary.) There are cases where it is not possible to clearly confirm this. Therefore, CAA C-OS is less prone to the decrease in electron mobility caused by grain boundaries.

[0304] Figure 25(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High spherical aberration correction function was used. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, the JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. Therefore, it can be observed.

[0305] From Figure 25(A), we can identify the pellet, which is a region in which metal atoms are arranged in layers. This is possible. The size of a single pellet can be 1 nm or larger, or 3 nm or larger. I understand. Therefore, pellets can be called nanocrystals (nc). It can also be done as follows: CAAC-OS can be changed to CANC(C-Axis Aligned na It can also be called an oxide semiconductor having nocrystals. The pellet is CAA The C-OS film reflects the unevenness of the surface or top surface to which it is formed, and the CAAC-OS film reflects the unevenness of the surface to which it is formed. It will be parallel to the top surface.

[0306] Furthermore, Figures 25(B) and 25(C) show CAA observed from a direction approximately perpendicular to the sample surface. The Cs-corrected high-resolution TEM images of the C-OS plane are shown. Figures 25(D) and 25(E) are shown. These are images obtained by image processing Figure 25(B) and Figure 25(C), respectively. Below, we will discuss image processing. Let's explain the method. First, Figure 25(B) is the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, In the obtained FFT image, the origin is referenced at 2.8 nm. -1 from 5.0nm -1 The range between Next, we perform a masking process on the masked FFT image. Then, we perform an inverse Fast Fourier Transform (IFFT) on the masked FFT image. By processing with an Inverse Fast Fourier Transform, the image is transformed. The processed image is obtained. This obtained image is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and This shows the child array.

[0307] In Figure 25(D), areas with disordered grid arrangement are shown with dashed lines. The area enclosed by the dashed lines is It is a single pellet. The area indicated by the dashed line is the connection point between the pellets. Yes. The dashed line is hexagonal, indicating that the pellet is hexagonal. The shape of a lett is not always a regular hexagon; it is often a non-regular hexagon.

[0308] In Figure 25(E), a point is drawn between a region with a aligned grid arrangement and another region with a aligned grid arrangement. The dotted line indicates the grain boundary. Even near the dotted line, a clear grain boundary cannot be observed. Connecting neighboring grid points to surrounding grid points creates distorted hexagons, pentagons, and / or seven-sided grids. Angular shapes can be formed. In other words, by distorting the lattice arrangement, the formation of grain boundaries is suppressed. This indicates that CAAC-OS has a dense atomic arrangement in the ab-plane direction. This is because, for example, the substitution of metal elements changes the bond distance between atoms. This is thought to be because it allows for distortion to be tolerated.

[0309] As described above, CAAC-OS has c-axis orientation and in the ab-plane direction Multiple pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, C AAC-OS, CAA crystal(c-axis-aligned abp It can also be called a lane-anchored crystal.

[0310] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the impurities. CAAC-OS may decrease in quality due to impurities and defects. It can be described as an oxide semiconductor with few oxygen vacancies.

[0311] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition gold. There are group elements, for example. For example, silicon and other metal elements that make up oxide semiconductors are more acidic than the metal elements that make up oxide semiconductors. Elements with strong bonding forces can remove oxygen from oxide semiconductors, thereby altering the atomic arrangement of the oxide semiconductor. This disrupts the crystallinity and reduces its properties. Also, heavy metals such as iron and nickel, and argon, Because carbon dioxide and other elements have large atomic radii (or molecular radii), the atomic arrangement of oxide semiconductors This disrupts the crystallinity and reduces its properties.

[0312] ≪nc-OS≫ Next, I will explain nc-OS.

[0313] This section describes the case of analyzing nc-OS using XRD. For example, when analyzing nc-OS... Furthermore, when structural analysis is performed using the out-of-plane method, peaks indicating orientation do not appear. In other words, nc-OS crystals do not have orientation.

[0314] Furthermore, for example, nc-OS having InGaZnO4 crystals is thinned, and the thickness is 34n When an electron beam with a probe diameter of 50 nm is incident on the region m parallel to the surface to be formed, Figure 2 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 6(A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 26(B). From Figure 26(B), a ring-shaped region is observed. Multiple spots are observed within the region. Therefore, nc-OS has a probe diameter of 50 nm. Order is not observed when an electron beam is incident, but when an electron beam with a probe diameter of 1 nm is used... Order can be confirmed by applying an incident beam of light.

[0315] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 26(C), an electron diffraction pattern is observed in which the spots are arranged in a roughly regular hexagonal shape. It may be measured. Therefore, in the range of thickness less than 10 nm, nc-OS is It can be seen that there are regions with high order, i.e., crystals. Furthermore, the crystals are oriented in various directions. Therefore, there are regions where a regular electron diffraction pattern is not observed.

[0316] Figure 26(D) shows the Cs-corrected height of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. The high-resolution TEM image is shown. nc-OS is the area indicated by the auxiliary line in the high-resolution TEM image. How can we identify regions where the crystalline structure can be observed, and regions where the crystalline structure cannot be clearly identified? It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. The size is often between 1 nm and 3 nm. Oxide semiconductors with a wavelength greater than 10 nm but less than or equal to 100 nm are called microcrystalline oxide semiconductors (MICR). It is called a crystalline oxide semiconductor. Yes, nc-OS is useful in situations where, for example, grain boundaries cannot be clearly identified in high-resolution TEM images. There is a possibility that the nanocrystals share the same origin as the pellets in CAAC-OS. It has properties. Therefore, in the following, the crystalline portion of nc-OS may be referred to as a pellet.

[0317] Thus, nc-OS is suitable for very small regions (for example, regions between 1 nm and 10 nm, etc.) The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Also, nc-OS There is no regularity in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from crystalline oxide semiconductors.

[0318] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS , an oxidation having RANC (Random Aligned nanocrystals) Material semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0319] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density compared to CAAC-OS.

[0320] ≪a-like OS≫ a-like OS is an oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a semiconductor.

[0321] Figure 27 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 27(A) This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 27( B) is 4.3 × 10 8 e - / nm 2 electrons (e - ) a-like OS after irradiation This is a high-resolution cross-sectional TEM image. From Figures 27(A) and 27(B), a-like O It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed in S. Furthermore, it can be seen that the shape of the bright region changes after electron irradiation. Note that the bright region is porous or low This is presumed to be a density region.

[0322] Due to its porous nature, a-like OS has an unstable structure. Below, a-lik This demonstrates that e OS has a less stable structure compared to CAAC-OS and nc-OS. Therefore, it shows the structural changes caused by electron irradiation.

[0323] Prepare a-like OS, nc-OS, and CAAC-OS as samples. This sample is also an In-Ga-Zn oxide.

[0324] First, high-resolution cross-sectional TEM images are obtained for each sample. All materials contain crystalline parts.

[0325] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn -It is known to have a structure in which a total of 9 layers, including 6 O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the grid plane spacing (also called the d value) of the (009) plane and They are of similar magnitude, and their value has been determined to be 0.29 nm from crystal structure analysis. Therefore, In the following, areas where the grid pattern spacing is between 0.28 nm and 0.30 nm are defined as InGaZ This was considered to be the crystalline portion of nO4. The lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. do.

[0326] Figure 28 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice stripes mentioned above is used to define the size of the crystal portion. From Figure 28, a-lik e OS grows larger in the crystal region in accordance with the cumulative amount of electrons irradiated, such as when acquiring TEM images. It can be seen that in the initial stages of TEM observation, the size is about 1.2 nm. The separated crystalline region (also called the initial nucleus) contains electrons (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, n c-OS and CAAC-OS have a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, no change in the size of the crystal portion can be observed. (Figure 28) Therefore, regardless of the cumulative electron irradiation dose, the size of the crystal portion of nc-OS and CAAC-OS is It can be seen that these are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation streaks The case involves an acceleration voltage of 300kV and a current density of 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0327] Thus, in a-like OS, crystalline growth can be observed upon electron irradiation. Yes. On the other hand, in nc-OS and CAAC-OS, the growth of the crystal portion by electron irradiation is almost entirely... It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. This reveals that it is an unstable structure.

[0328] Furthermore, because it is porous, a-like OS is compared to nc-OS and CAAC-OS. All of them are low-density structures. Specifically, the density of a-like OS is low compared to single-layer structures of the same composition. The density of the crystals is between 78.6% and 92.3%. Also, the density of nc-OS and CAA The density of C-OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a crystal density of less than 78% are inherently difficult to deposit into films.

[0329] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 That is. For example, in an oxide semiconductor that satisfies In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 More than 6.3g / cm 3 It is less than.

[0330] If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By combining these, it is possible to estimate the density equivalent to a single crystal at the desired composition. The density corresponding to a single crystal of the desired composition is determined by the ratio of single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to estimate by combining the factors.

[0331] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, and nc-OS. The laminated film may have two or more types of CAAC-OS.

[0332] <2-5. Carrier density of oxide semiconductors> Next, the carrier density of oxide semiconductors will be explained below.

[0333] Factors that affect the carrier density of oxide semiconductors include oxygen vacancies in oxide semiconductors. Examples include (Vo) or impurities in oxide semiconductors.

[0334] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen atoms bond to these oxygen vacancies (this state is called VoH). (Also known as) When this occurs, the defect level density increases. Or, when there are many impurities in the oxide semiconductor Consequently, the defect level density increases due to the impurity. Therefore, defects in oxide semiconductors By controlling the energy level density, the carrier density of oxide semiconductors can be controlled.

[0335] Now, let's consider a transistor that uses an oxide semiconductor in the channel region.

[0336] Suppression of negative shift of transistor threshold voltage, or transistor off-current When the goal is to reduce [the amount of i. When lowering the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor is reduced. The degree should be lowered, and the defect level density should be lowered. In this specification, the impurity concentration is low, A low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. The carrier density of the ion semiconductor is 8 × 10⁻⁶. 15 cm -3 Less than 1 × 10 1 1 cm -3 Less than 1 × 10 10cm -3 It is less than 1 × 10 -9 cm -3 That should suffice.

[0337] On the other hand, improving the on-current of the transistor, or improving the field-effect mobility of the transistor. When this is the objective, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor is slightly reduced. To increase it, or to slightly increase the defect level density of the oxide semiconductor, It is desirable to make the band gap of a semiconductor smaller. For example, the Id-V of a transistor. Within the range where the on / off ratio of the g characteristic can be obtained, the impurity concentration is slightly high, or the defect level is... Oxide semiconductors with a slightly higher electron density can be considered virtually intrinsic. Also, high electron affinity As a result, the band gap becomes smaller, and consequently, the thermally excited electrons ( Oxide semiconductors with increased electron density can be considered virtually intrinsic. When using oxide semiconductors with high summing power, the threshold voltage of the transistor becomes lower. ru.

[0338] The oxide semiconductor with the increased carrier density mentioned above is slightly n-type. Therefore Therefore, even if an oxide semiconductor with increased carrier density is called "Slightly-n", good.

[0339] The carrier density of a virtually intrinsic oxide semiconductor is 1 × 10⁻⁶ 5 cm -3 The above 1 x 10 18 cm -3 Less than 1 × 10 is preferable. 7 cm -3 The above 1 x 10 17 cm-3 The following are preferred , 1 x 10 9 cm -3 The above 5 x 10 16 cm -3 The following is even more preferable: 1 × 10 1 0 cm -3 The above 1 x 10 16 cm -3 The following is even more preferable: 1 × 10 11 cm -3 That's all. 1 x 10 15 cm -3 The following are even more preferable.

[0340] The configuration shown in this embodiment may be appropriately combined with the configurations shown in other embodiments or other examples. They can be used in combination.

[0341] (Embodiment 3) In this embodiment, the display device having a transistor as illustrated in the previous embodiment An example will be explained below using Figures 29 to 35.

[0342] Figure 29 is a top view showing an example of a display device. The display device 700 shown in Figure 29 is the first A pixel section 702 provided on the substrate 701 and a source drive provided on the first substrate 701 The Pixel circuit section 704 and the gate driver circuit section 706, and the pixel section 702 and the source driver circuit A sealing material 712 is arranged to surround the path section 704 and the gate driver circuit section 706. It includes a second substrate 705 provided opposite the first substrate 701. The first substrate 701 and the second substrate 705 are sealed by a sealing material 712. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are It is sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in Figure 29, a display element is provided between the first substrate 701 and the second substrate 705. It gets kicked.

[0343] Furthermore, the display device 700 is surrounded by a sealing material 712 on the first substrate 701. In a region different from the region, there is a pixel section 702, a source driver circuit section 704, and a gate driver circuit. FPC terminals electrically connected to the path section 706 and the gate driver circuit section 706, respectively. A sub-unit 708 (FPC: Flexible printed circuit) is provided. Furthermore, FPC716 is connected to FPC terminal 708, and FPC716 controls the drawing. Various signals are sent to the element section 702, the source driver circuit section 704, and the gate driver circuit section 706. These are supplied. Also, the pixel unit 702, source driver circuit unit 704, gate driver circuit Signal lines 710 are connected to the path section 706 and the FPC terminal section 708, respectively. The various signals supplied by 716 are transmitted via the signal line 710 to the pixel unit 702 and sourced Provided to the driver circuit section 704, the gate driver circuit section 706, and the FPC terminal section 708 ru.

[0344] Furthermore, the display device 700 may be provided with multiple gate driver circuit units 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example is shown in which the pixel portion 702 is formed on the same first substrate 701, this configuration is not limited to this example. It is not necessary. For example, the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit section 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit or gate driver circuit, etc., is formed (for example, a single-wired board) A drive circuit substrate (formed from a crystalline semiconductor film or a polycrystalline semiconductor film) is formed on the first substrate 701. This configuration is also acceptable. Furthermore, the method of connecting the separately formed drive circuit board is not particularly limited. Instead, methods such as COG (Chip On Glass) and wire bonding are used. You can use it.

[0345] Furthermore, the display device 700 includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit section 706 has a plurality of transistors, and is a semiconductor device according to one aspect of the present invention. A transistor can be applied to this.

[0346] Furthermore, the display device 700 can have various elements. An example of such elements is: For example, electroluminescent (EL) elements (EL elements including organic and inorganic materials, (Mechanical EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (light-emitting depending on the current) Transistors, electron emission elements, liquid crystal elements, electron ink elements, electrophoretic elements, electro Lowwetting elements, plasma displays (PDPs), MEMS (microelectronics) (Tro-Mechanical System) Display (e.g., Grating Light Bulb (G LV), Digital Micromirror Device (DMD), Digital Microshutter (DMS elements, interferometric modulation (IMOD) elements, etc.) Examples include piezoelectric ceramic displays.

[0347] Another example of a display device using EL elements is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat display (SED: Surface-conductivity Examples include (n Electron-emitter Display), which uses liquid crystal elements. Examples of such display devices include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays). Display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display Examples include (Ray). An example of a display device using an electronic ink element or electrophoretic element is: Examples include electronic paper. Furthermore, there are semi-transmissive liquid crystal displays and reflective liquid crystal displays. If implemented, some or all of the pixel electrodes would function as reflective electrodes. This is how it should be done. For example, some or all of the pixel electrodes could be made of aluminum, silver, etc. It would be good to have it. Furthermore, in that case, a memory circuit such as SRAM should be placed below the reflective electrode. It is also possible to implement this feature. This will further reduce power consumption.

[0348] The display method used in the display device 700 is either progressive or interlaced. These can be used. Also, when displaying in color, the color elements controlled by pixels include R It is not limited to the three colors GB (R stands for red, G for green, and B for blue). For example, if the pixels have R and G It may consist of four pixels: a pixel, a B pixel, and a W (white) pixel. Alternatively, a pentile arrangement. As shown in the column, two of the RGB colors make up one color element, and each color element produces two different colors. You may also select and configure this option. Alternatively, you can add one or more colors to RGB, such as yellow, cyan, magenta, etc. Additional elements may be added. Note that the size of the display area for each color element dot may differ. However, the disclosed invention is not limited to a color display device, but also includes a monochrome display device. It can also be applied to the display device shown.

[0349] In addition, the backlight (organic EL elements, inorganic EL elements, LEDs, fluorescent lamps, etc.) emits white light. (W) is used to enable the display device to display in full color, and the coloring layer (also called a color filter) You may also use ( ). The colored layer may be, for example, red (R), green (G), blue (B ), yellow (Y), etc. can be used in appropriate combinations. By using a colored layer This allows for higher color reproduction compared to cases where a colored layer is not used. By arranging a region having a colored layer and a region without a colored layer, a region without a colored layer is created. White light in the area may be used directly for display. A portion of the area may be placed without a colored layer. By placing it in this position, the reduction in brightness caused by the colored layer during bright displays can be minimized, and power consumption is reduced by 2 In some cases, the emission can be reduced by 10% to 30%. However, this is due to the spontaneous generation of organic EL elements and inorganic EL elements. When using optical elements for full-color display, R, G, B, Y, and W are used, each with its own emitted color. It is also acceptable to emit light from the element. By using a self-luminescent element, it is possible to achieve better results than when using a colored layer. Furthermore, it may be possible to reduce power consumption even further.

[0350] Furthermore, the colorization method involves passing a portion of the light emitted from the white light source through a color filter. In addition to the method of converting to red, green, and blue (color filter method), red, green, blue A method that uses each color of light emission separately (three-color method), or a method that uses red or a portion of the light emitted from blue light emission. A method for converting to green (color conversion method, quantum dot method) may also be applied.

[0351] In this embodiment, regarding the configuration in which liquid crystal elements and EL elements are used as display elements: This will be explained using Figures 30 and 32. Figure 30 is shown in Figure 29, where the dashed line QR is located. Figure 32 is a cross-sectional view of the device, which uses a liquid crystal element as the display element. This is a cross-sectional view of the dashed-dotted line QR shown in 29, and it is a configuration using an EL element as the display element. That is the case.

[0352] First, I will explain the common parts shown in Figures 30 and 32, and then I will explain the different parts. I will explain below.

[0353] <3-1. Explanation of Common Parts of Display Devices> The display device 700 shown in Figures 30 and 32 includes a wiring section 711 and a pixel section 702. It has a source driver circuit section 704 and an FPC terminal section 708. The line section 711 has a signal line 710. The pixel section 702 has a transistor 750 and It has a capacitive element 790. The source driver circuit section 704 also has a transistor 752. To possess.

[0354] Transistors 750 and 752 are similar to transistor 100 shown above. This is the configuration. Note that the configurations of transistors 750 and 752 are as described above. Other transistors shown in the embodiment may also be used.

[0355] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can reduce the off-current. Therefore, the image The holding time of electrical signals such as signals can be extended, and the writing interval is also extended when the power is on. It can be set to a certain value. Therefore, the frequency of refresh operations can be reduced, thus reducing power consumption. It has the effect of suppressing force.

[0356] Furthermore, the transistor used in this embodiment is capable of obtaining a relatively high field-effect mobility. Therefore, high-speed operation is possible. For example, a transistor capable of such high-speed operation can be used in a liquid crystal display. By using it in a display device, the switching transistors in the pixel section and the drive circuit section are used. Driver transistors can be formed on the same substrate. That is, they can be used as a separate drive circuit. Therefore, since there is no need to use semiconductor devices formed from silicon wafers, etc., This reduces the number of parts. In addition, the pixel section also has a transistor that can be driven at high speed. By using ZISTA, high-quality images can be provided.

[0357] Capacitive element 790 has a conductive film that functions with the first gate electrode of transistor 750. The lower electrode is formed through a process of processing the same conductive film, and the transistor 750 has The process involves fabricating a conductive film identical to the conductive film that functions as both the source electrode and the drain electrode. It has an upper electrode that is formed, and a transistor between the lower electrode and the upper electrode. A process of forming an insulating film identical to the insulating film that functions as the first gate insulating film of 750. An insulating film is provided, formed through the process. That is, the capacitive element 790 is provided, which induces between the pair of electrodes. It is a multilayer structure in which an insulating film that functions as an electrostatic film is sandwiched between layers.

[0358] Furthermore, in Figures 30 and 32, transistor 750, transistor 752, and A planarizing insulating film 770 is provided on the quantitative element 790.

[0359] The planarizing insulating film 770 can be polyimide resin, acrylic resin, or polyimideamide resin. , heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin These can be used. Furthermore, by stacking multiple insulating films formed from these materials... A planarizing insulating film 770 may be formed. Alternatively, a configuration without a planarizing insulating film 770 may be provided. That's fine.

[0360] Furthermore, in Figures 30 and 32, the transistor 750 of the pixel unit 702 and - The transistor 752 in the driver circuit section 704 and a transistor with the same structure While examples of configurations have been given, the system is not limited to these. For example, a pixel unit 702 and a source Different transistors may be used for the driver circuit section 704. Specifically, the pixel section 7 A staggered transistor is used in 02, and the source driver circuit section 704 is shown in Embodiment 1. A configuration using an inverse staggered transistor, or the pixel section 702 as shown in Embodiment 1. An inverse staggered transistor is used, and a staggered transistor is used in the source driver circuit section 704. Configurations using a gate are one example. Note that the above source driver circuit section 704 is gate This can also be interpreted as the driver circuit section.

[0361] Furthermore, signal line 710 is connected to the source and drain electrodes of transistors 750 and 752. It is formed through the same process as a conductive film that functions as a signal line 710, for example, a copper element When using materials containing [specific material], signal delays caused by wiring resistance are reduced, and large-screen displays are possible. It becomes Noh.

[0362] Furthermore, the FPC terminal section 708 includes a connecting electrode 760, an anisotropic conductive film 780, and FPC 71 It has 6. The connecting electrode 760 is the source electrode of transistors 750 and 752 and It is formed through the same process as the conductive film that functions as a rain electrode. Also, the connecting electrode 760 is The terminals of the FPC716 are electrically connected via the anisotropic conductive film 780.

[0363] Furthermore, for example, glass substrates can be used as the first substrate 701 and the second substrate 705. This is possible. Also, the first substrate 701 and the second substrate 705 are flexible substrates. A flexible substrate may be used. Examples of such flexible substrates include plastic substrates. ru.

[0364] Furthermore, a structure 778 is provided between the first substrate 701 and the second substrate 705. The fabricated body 778 is a columnar spacer obtained by selectively etching an insulating film. It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. It is possible to use a spherical spacer as the structure 778.

[0365] Furthermore, the second substrate 705 side has a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, and a light-shielding film 738 and a film in contact with the colored film 736 An insulating film 734 is provided.

[0366] <3-2. Example of a display device configuration using liquid crystal elements> The display device 700 shown in Figure 30 has a liquid crystal element 775. The liquid crystal element 775 is a conductive film It has 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is on the second substrate 705 It is provided on the side and functions as a counter electrode. The display device 700 shown in Figure 30 is a conductive film The orientation state of the liquid crystal layer 776 changes depending on the voltage applied to 772 and the conductive film 774. By controlling the transmission and opacity of light, an image can be displayed.

[0367] Furthermore, the conductive film 772 serves as the source electrode and drain electrode of the transistor 750. It is electrically connected to a conductive film that functions as a conductive film. The conductive film 772 is formed on the planar insulating film 770. It functions as a pixel electrode, that is, one of the electrodes of the display element. Furthermore, the conductive film 772, It functions as a reflective electrode. The display device 700 shown in Figure 30 utilizes ambient light and the conductive film 7 This is a so-called reflective type color liquid crystal display device that reflects light with 72 and displays it through a colored film 736. be.

[0368] The conductive film 772 is a conductive film that is transparent in visible light, or a conductive film that is transparent in visible light. A conductive film with light-transmitting properties can be used. Examples of conductive films that are transparent in visible light include: For example, a material containing one element selected from indium (In), zinc (Zn), and tin (Sn). It is advisable to use a material. Examples of conductive films that are reflective in visible light include aluminum. Alternatively, a material containing silver may be used. In this embodiment, the conductive film 772 is, A reflective conductive film is used in the visible light spectrum.

[0369] In Figure 30, the conductive film 772 is used as the drain electrode of the transistor 750. The examples given illustrate configurations for connecting to a conductive film, but the model is not limited to these. For example, see Figure 31. As shown, conductive film 772 is sandwiched between conductive film 777, which functions as a connecting electrode. It can also be configured to electrically connect to a conductive film that functions as the drain electrode of the ZISTA 750. Furthermore, the conductive film 777 functions as the second gate electrode of the transistor 750. Because it is formed through a process that processes the same conductive film as the conductive film, it does not increase the manufacturing process. It can be formed.

[0370] Furthermore, the display device 700 shown in Figure 30 is an example of a reflective color liquid crystal display device. However, it is not limited to this; for example, a conductive film 772 that is transparent in visible light By using this, it can be used as a transmissive color liquid crystal display device. Alternatively, a reflective color liquid crystal display device can be used. A so-called semi-transmissive color liquid crystal display combining a crystal display device and a transmissive color liquid crystal display device. It may also be used as a crystal display device.

[0371] Here, an example of a transmissive color liquid crystal display device is shown in Figure 33. Figure 33 is shown in Figure 29. This is a cross-sectional view of the dashed-dotted QR code, and it is a configuration using liquid crystal elements as display elements. Furthermore, the display device 700 shown in Figure 33 uses a transverse electric field method (for example, F) as the driving method for the liquid crystal elements. This is an example of a configuration using FS mode. In the configuration shown in Figure 33, the pixel electrode functions An insulating film 773 is provided on the conductive film 772, and a conductive film 774 is provided on the insulating film 773. In this case, the conductive film 774 has the function of a common electrode. The electric field generated between the conductive film 772 and the conductive film 774 via the insulating film 773 causes the liquid The orientation state of the crystal layer 776 can be controlled.

[0372] Also, although not shown in Figures 30 and 33, conductive film 772 or conductive film 774 The configuration includes providing an alignment film on one or both sides of the offset, on the side that is in contact with the liquid crystal layer 776. It is also possible to use polarizing members, phase difference members, and reflectors, although these are not shown in Figures 30 and 33. Optical components (optical substrates) such as protective members may be provided as appropriate. For example, polarizing substrates and position Circular polarization using a phase-difference substrate may also be used. Furthermore, backlights and sidelights may be used as light sources. You may use any of these.

[0373] When using liquid crystal elements as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and polymer liquid crystals are used. Crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. Depending on the conditions, the liquid crystal material can be classified into cholesteric phase, smectic phase, cubic phase, and chi. It exhibits the ranematic phase, isotropic phase, etc.

[0374] Furthermore, when employing a transverse electric field method, it is also possible to use a liquid crystal that exhibits a blue phase without using an alignment layer. The blue phase is one of the liquid crystal phases, and as the temperature of cholesteric liquid crystal is increased, the cholesteric phase This phase appears just before the transition from the blue phase to the isotropic phase. The blue phase only appears within a narrow temperature range. To improve the temperature range, a liquid crystal assembly containing several weight percent or more of chiral agent was mixed in. The resulting product is used in the liquid crystal layer. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is Because of its short response speed and optical isotropy, orientation treatment is unnecessary. Furthermore, it eliminates the need for an orientation film. Since this is sufficient, rubbing treatment is also unnecessary, thus eliminating the electrostatic discharge caused by rubbing treatment. This can prevent damage and reduce defects and breakage of liquid crystal display devices during the manufacturing process. It is possible. Also, liquid crystal materials that exhibit the blue phase have little dependence on the viewing angle.

[0375] Furthermore, when using liquid crystal elements as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin (Field Switching) mode, ASM (Axially Symmetry) tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferroe) lectric Liquid Crystal) mode, AFLC (AntiFerr Features such as the (electric Liquid Crystal) mode can be used. .

[0376] Furthermore, a normally black type liquid crystal display device, for example, one that employs vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes can be listed. For example, MVA (Multi-Domain Vertical Alignment) ) Mode, PVA (Patterned Vertical Alignment) Mode You can use modes such as ASV mode.

[0377] <3-3. Display devices using light-emitting elements> The display device 700 shown in Figure 32 has a light-emitting element 782. The light-emitting element 782 is made of a conductive film It has 772, an EL layer 786, and a conductive film 788. The display device 700 shown in Figure 32 is The EL layer 786 of the optical element 782 emits light, allowing an image to be displayed. Furthermore, the EL layer 786 contains organic compounds or inorganic compounds such as quantum dots.

[0378] Examples of materials that can be used with organic compounds include fluorescent materials or phosphorescent materials. It can be made. Also, as a material that can be used for quantum dots, colloidal quantum dots Materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, These are some examples. Also, the origins of groups 12 and 16, 13 and 15, or 14 and 16. Materials containing elementary groups may be used. Alternatively, cadmium (Cd), selenium (Se), Zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (P) b) Quantum having elements such as gallium (Ga), arsenic (As), and aluminum (Al). Dot material may also be used.

[0379] Furthermore, the display device 700 shown in Figure 32 has an insulating film 770 and a conductive film 772 on which an insulating film is applied. A border film 730 is provided. The insulating film 730 covers a portion of the conductive film 772. 782 is a top emission structure. Therefore, the conductive film 788 is translucent, E It transmits the light emitted by the L layer 786. In this embodiment, top emission The structure is illustrated as an example, but is not limited to this. For example, light is emitted towards the conductive film 772 side. The bottom emission structure and the dual emission of light to both conductive film 772 and conductive film 788 It can also be applied to ammonium emission structures.

[0380] Furthermore, a colored film 736 is provided in a position that overlaps with the light-emitting element 782, and overlaps with the insulating film 730. A light-shielding film 738 is provided at the location, the routing wiring section 711, and the source driver circuit section 704. Furthermore, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Furthermore, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. (See Figure 32) In the display device 700 shown, an example was given of a configuration in which a colored film 736 is provided, It is not limited to this. For example, when the EL layer 786 is formed by coloring, A configuration without the film 736 is also possible.

[0381] <3-4. Example of a configuration in which an input / output device is provided to the display device> Furthermore, an input / output device may be provided to the display device 700 shown in Figures 32 and 33. Examples of power devices include touch panels.

[0382] The configuration in which a touch panel 791 is provided on the display device 700 shown in Figures 32 and 33 is shown in Figure 34. This is shown in Figure 35.

[0383] Figure 34 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in Figure 32. Figure 35 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in Figure 33. be.

[0384] First, the touch panel 791 shown in Figures 34 and 35 will be explained below.

[0385] The touch panel 791 shown in Figures 34 and 35 is provided between the substrate 705 and the colored film 736. It is a so-called in-cell type touch panel. The touch panel 791 has a light-shielding film 738 The colored film 736 may be formed on the substrate 705 side before the colored film 705 is formed.

[0386] The touch panel 791 consists of a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode. It has 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, a finger or When a detected object such as a tyrus comes into close proximity, the mutual capacitance between electrode 793 and electrode 794 changes. It can detect transformation.

[0387] Furthermore, above the transistor 750 shown in Figures 34 and 35, there is an electrode 793 and The intersection with electrode 794 is clearly indicated. Electrode 796 is an opening provided in the insulating film 795. Through this, electrode 794 is electrically connected to the two electrodes 793 that sandwich it. (See Figure 34) Figure 35 illustrates a configuration in which the region where the electrode 796 is provided is located in the pixel section 702. However, it is not limited to this, and for example, it may be formed in the source driver circuit section 704.

[0388] Electrodes 793 and 794 are provided in the region overlapping with the light-shielding film 738. Also, see Figure 34. As shown, it is preferable that the electrode 793 is provided so as not to overlap with the light-emitting element 782. Furthermore, as shown in Figure 35, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. It is preferable that the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. It has an opening in the region. That is, the electrode 793 has a mesh shape. By doing so, the electrode 793 is configured not to block the light emitted by the light-emitting element 782. This is possible. Alternatively, the electrode 793 can be configured not to block the light transmitted through the liquid crystal element 775. This is possible. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Because it is small, it is possible to realize a display device that has high visibility and reduced power consumption. The Extreme 794 should have a similar configuration.

[0389] Furthermore, since electrodes 793 and 794 do not overlap with the light-emitting element 782, electrodes 793 and A metal material with low visible light transmittance can be used for electrode 794. Alternatively, electrode 7 Since electrode 93 and electrode 794 do not overlap with liquid crystal element 775, electrodes 793 and 794 This allows the use of metal materials with low visible light transmittance.

[0390] Therefore, compared to electrodes using oxide materials with high visible light transmittance, electrode 793 and This makes it possible to lower the resistance of electrode 794, improving the sensor sensitivity of the touch panel. It is possible.

[0391] For example, conductive nanowires may be used for electrodes 793, 794, and 796. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size should be less than or equal to m, more preferably between 5 nm and 25 nm. The wires include metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. A wire or carbon nanotube can be used. For example, electrodes 793, 7 When using Ag nanowires for either 94 or 796, or all of them, in visible light The light transmittance must be 89% or higher, and the sheet resistance must be between 40Ω / □ and 100Ω / □. can.

[0392] Furthermore, Figures 34 and 35 illustrate the configuration of an in-cell type touch panel. However, it is not limited to this. For example, a so-called on-cell type tactile paving can be formed on the display device 700. A so-called out-cell type touch panel, used by being attached to a touch panel or display device 700. That is also acceptable.

[0393] Thus, the display device according to one aspect of the present invention can be combined with various forms of touch panels. It can be used.

[0394] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0395] (Embodiment 4) In this embodiment, Figure 36 shows a display device having a semiconductor device according to one aspect of the present invention. We will use it to explain.

[0396] <4. Circuit configuration of the display device> The display device shown in Figure 36(A) has a region having pixels of the display element (hereinafter referred to as the pixel portion 502 and ( ) and a circuit section ( ) which is located outside the pixel section 502 and has a circuit for driving the pixels. Hereinafter referred to as the drive circuit section 504, and a circuit having a function to protect the element (hereinafter referred to as the protection circuit 504) It has a (6) and a terminal section 507. Note that the protection circuit 506 is not provided. That's fine.

[0397] Part or all of the drive circuit section 504 is formed on the same substrate as the pixel section 502. This is desirable. This allows for a reduction in the number of components and terminals. Drive circuit section 504 If part or all of it is not formed on the same substrate as the pixel section 502, the drive cycle Part or all of road section 504 is COG or TAB (Tape Automated B It can be implemented by (onding).

[0398] The pixel section 502 is arranged in X rows (where X is a natural number greater than or equal to 2) and Y columns (where Y is a natural number greater than or equal to 2). It has a circuit for driving multiple display elements (hereinafter referred to as the pixel circuit 501), and the drive cycle The path section 504 is a circuit that outputs a signal (scan signal) for selecting pixels (hereinafter referred to as a gate driver). 504a) is used to supply signals (data signals) for driving the pixel display elements. It has a drive circuit such as the circuit (hereinafter referred to as source driver 504b).

[0399] The gate driver 504a has a shift register, etc. The gate driver 504a is A signal to drive the shift register is input via terminal 507, and the signal is output. For example, the gate driver 504a receives input such as a start pulse signal and a clock signal. The gate driver 504a outputs a pulse signal. The scanning signal is applied to the wiring (and It has the function of controlling the potential of the scan lines (referred to as GL_1 to GL_X) below. Multiple drivers 504a are provided, and multiple gate drivers 504a are used to control the scan line GL_1 The path to GL_X may be divided and controlled. Alternatively, the gate driver 504a may use an initialization signal. It has the function of supplying, however, the gate driver 50 4a can also supply another signal.

[0400] The source driver 504b has a shift register, etc. The source driver 504b Through terminal 507, in addition to signals for driving the shift register, the data signals are generated. A signal (image signal) is input. The source driver 504b uses the image signal to create a pixel circuit. It has the function of generating data signals to write to 501. Also, source driver 504b The data signal is transmitted according to the pulse signal obtained by inputting the start pulse, clock signal, etc. It has the function of controlling the output of the number. In addition, the source driver 504b is given a data signal. It has the function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, source driver 504b may have the ability to supply initialization signals. However, this is not limited to the source driver 504b, which may also supply other signals. It is possible.

[0401] The source driver 504b is configured using, for example, multiple analog switches. The source driver 504b sequentially turns on multiple analog switches, The image signal can be time-divided and output as a data signal. It can also use shift registers, etc. You may use this to configure source driver 504b.

[0402] Each of the multiple pixel circuits 501 receives a scan signal from one of the multiple scan lines GL. A pulse signal is input via one of several data lines DL to which a data signal is supplied. A data signal is input. Also, each of the multiple pixel circuits 501 is a gate driver. 504a controls the writing and retention of data in the data signal. For example, m rows and n columns. The pixel circuit 501 of the eye is connected to the gate driver via the scan line GL_m (where m is a natural number less than or equal to X). A pulse signal is input from 504a, and the data line DL_n( A data signal is input from the source driver 504b via n (where n is a natural number less than or equal to Y).

[0403] The protection circuit 506 shown in Figure 36(A) is, for example, a gate driver 504a and a pixel circuit 5 It is connected to scan line GL, which is the wiring between 01. Alternatively, the protection circuit 506 is connected to source driver It is connected to the data line DL, which is the wiring between the light bar 504b and the pixel circuit 501. Alternatively, The protection circuit 506 is connected to the wiring between the gate driver 504a and the terminal section 507. Yes, it is possible. Alternatively, the protection circuit 506 provides a connection between the source driver 504b and the terminal section 507. It can be connected to a wire. The terminal 507 is used to supply power and to the display device from an external circuit. This refers to the part equipped with terminals for inputting control signals and image signals.

[0404] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires.

[0405] As shown in Figure 36(A), the pixel section 502 and the drive circuit section 504 each have a protection circuit 50 By providing 6, ESD (Electrostatic Discharge: This can improve the resistance of display devices to overcurrents generated by electrostatic discharge, etc. However, the configuration of the protection circuit 506 is not limited to this, for example, the gate driver 504a Configuration with protection circuit 506 connected, or with protection circuit 506 connected to source driver 504b. This configuration is also possible. Alternatively, a configuration in which the protection circuit 506 is connected to the terminal 507. It can also be done this way.

[0406] Furthermore, in Figure 36(A), the gate driver 504a and the source driver 504b are Therefore, although an example is shown in which the drive circuit section 504 is formed, the configuration is not limited to this. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) is put into practice. It can also be used as a mounting configuration.

[0407] Furthermore, the multiple pixel circuits 501 shown in Figure 36(A) have, for example, the configuration shown in Figure 36(B). It can be done this way.

[0408] The pixel circuit 501 shown in Figure 36(B) includes a liquid crystal element 570, a transistor 550, and It has a quantitative element 560 and a transistor 550 as shown in the previous embodiment. It can be applied.

[0409] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 in each row One of the electrodes may be given a different potential.

[0410] For example, the driving method for a display device equipped with a liquid crystal element 570 is TN mode, STN mode Code, VA mode, ASM (Axially Symmetric Aligned Motor) icro-cell) mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liqu id Crystal) mode, AFLC (AntiFerroelectric Li) quid Crystal) mode, MVA mode, PVA (Patterned Ve (Critical Alignment) mode, IPS mode, FFS mode, or TBA You may also use modes such as (Transverse Bend Alignment). In addition, as a method of driving the display device, there is also ECB (Electric Ally Controlled Birefringence) mode, PDLC (P Olymer Dispersed Liquid Crystal (PNLC) mode, (Polymer Network Liquid Crystal) mode, guest host There are modes such as St Mode. However, this is not limited to these, and various types of liquid crystal elements and their driving methods exist. Various materials can be used.

[0411] In the pixel circuit 501 of row m, column n, the source electrode or drain electrode of transistor 550 One electrode is electrically connected to the data line DL_n, and the other is connected to a pair of liquid crystal elements 570. It is electrically connected to the other electrode. Also, the gate electrode of transistor 550 is connected to the scan line G It is electrically connected to L_m. Transistor 550 writes data to the data signal. It has a control function.

[0412] One of the pair of electrodes of the capacitive element 560 is connected to a wiring to which a potential is supplied (hereinafter referred to as the potential supply line VL). ) is electrically connected to the other end, and the other end is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The potential value of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitive element 560 functions as a holding capacitor to retain the written data.

[0413] For example, in a display device having the pixel circuit 501 shown in Figure 36(B), for example, Figure 36(A) The gate driver 504a shown in the diagram sequentially selects the pixel circuit 501 for each row, and the transistor Turn on 550 to write the data signal.

[0414] When data is written to the pixel circuit 501, the transistor 550 turns off. The image is then held. By performing this process row by row, the image can be displayed.

[0415] Furthermore, the multiple pixel circuits 501 shown in Figure 36(A) have, for example, the configuration shown in Figure 36(C). It can be done this way.

[0416] Furthermore, the pixel circuit 501 shown in Figure 36(C) consists of transistors 552 and 554, and a capacitance element It has a child 562 and a light-emitting element 572. Transistor 552 and transistor 554 The transistors shown in the previous embodiment can be applied to either one or both of them. .

[0417] One of the source and drain electrodes of transistor 552 is supplied with a data signal. It is electrically connected to the wiring (hereinafter referred to as the signal line DL_n). Furthermore, transistor 55 The gate electrode of 2 supplies electrical signals to the wiring to which the gate signal is supplied (hereinafter referred to as scan line GL_m). It connects to the target.

[0418] Transistor 552 has the function of controlling the writing of data to the data signal.

[0419] One of the pair of electrodes of the capacitive element 562 is connected to a wiring to which a potential is supplied (hereinafter referred to as the potential supply line VL). It is electrically connected to (a), and the other is the source electrode and drain of transistor 552. It is electrically connected to the other electrode.

[0420] The capacitive element 562 functions as a holding capacitor to retain the written data.

[0421] One of the source and drain electrodes of transistor 554 is connected to the potential supply line VL_a. They are electrically connected. Furthermore, the gate electrode of transistor 554 is connected to the gate electrode of transistor 552. It is electrically connected to the other of the source electrode and drain electrode.

[0422] One of the anodes and cathodes of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other end is electrically connected to the source and drain electrodes of transistor 554. It will be done.

[0423] Examples of light-emitting elements 572 include organic electroluminescent elements (also known as organic EL elements). (For example) can be used. However, the light-emitting element 572 is not limited to this. Inorganic EL elements made of inorganic materials may also be used.

[0424] Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied.

[0425] In a display device having the pixel circuit 501 shown in Figure 36(C), for example, the ge shown in Figure 36(A) The driver 504a sequentially selects the pixel circuit 501 for each row, and the transistor 552 Turn it on and write the data signal.

[0426] When data is written to the pixel circuit 501, the transistor 552 turns off. It enters a holding state. Furthermore, in accordance with the potential of the written data signal, transistor 554 The amount of current flowing between the source electrode and the drain electrode is controlled, and the light-emitting element 572 controls the amount of current flowing through it. It emits light with brightness corresponding to the flow rate. By performing this sequentially for each row, an image can be displayed.

[0427] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0428] (Embodiment 5) In this embodiment, the applicable circuit configuration of the transistor described in the above embodiment is An example will be explained using Figures 37 to 40.

[0429] In this embodiment, the tra having the oxide semiconductor described in the previous embodiment The following explanation will refer to the transistor as an OS transistor.

[0430] <5. Example of Inverter Circuit Configuration> Figure 37(A) shows how it can be applied to shift registers, buffers, etc., in the drive circuit. The circuit diagram of the inverter is shown. Inverter 800 is a signal that inverts the logic of the input terminal IN. The signal is output to the output terminal OUT. The inverter 800 has multiple OS transistors. . signal S BG This is a signal that can switch the electrical characteristics of an OS transistor.

[0431] Figure 37(B) shows an example of inverter 800. Inverter 800 is an OS Transistor It has a sta 810 and an OS transistor 820. The inverter 800 is n-channel. Because it can be fabricated using only type transistors, CMOS (Complementary (Metal Oxide Semiconductor) inverter (CMOS It can be manufactured at a lower cost compared to manufacturing a converter.

[0432] Furthermore, the inverter 800, which has an OS transistor, is composed of Si transistors. It can also be placed on a CMOS. The inverter 800 is placed on top of the CMOS circuit. Therefore, the increase in circuit area due to adding the inverter 800 can be minimized.

[0433] OS transistors 810 and 820 have a first gate that functions as the front gate, and a bass A second gate that functions as a back gate, and a third gate that functions as either a source or a drain. It has one terminal and a second terminal that functions as either a source or a drain.

[0434] The first gate of OS transistor 810 is connected to the second terminal of OS transistor 810. The second gate of the OS transistor 810 receives the signal S. BG Connected to the wiring that supplies power. The first terminal of the OS transistor 810 is connected to the wiring that supplies the voltage VDD. The second terminal of the Rangista 810 is connected to the output terminal OUT.

[0435] The first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the TA820 is connected to the input terminal IN. The first terminal of the OS transistor 820 The child is connected to the output terminal OUT. The second terminal of OS transistor 820 is connected to the voltage VSS. It is connected to the wiring that provides the power.

[0436] Figure 37(C) is a timing chart illustrating the operation of inverter 800. In the timing chart of Figure 37(C), the signal waveform of the input terminal IN and the output terminal OUT are shown. Signal waveform, signal S BG The signal waveform and the change in the threshold voltage of the OS transistor 810. This indicates that.

[0437] signal S BG By applying this to the second gate of the OS transistor 810, the OS transistor The threshold voltage of the 810 can be controlled.

[0438] signal S BG This is the voltage V used to negatively shift the threshold voltage. BG_A ,threshold Voltage V for shifting the voltage to the positive side BG_B It has a voltage V applied to the second gate. BG_A By applying this, the OS transistor 810 will have a threshold voltage V TH_A Shifted to a negative value It can be done. Also, a voltage V can be applied to the second gate. BG_B By providing this, OS transitions The TA810 has a threshold voltage V TH_B It can be shifted to a positive value.

[0439] To visualize the above explanation, Figure 38(A) shows one of the electrical characteristics of a transistor. This shows an Id-Vg curve.

[0440] The electrical characteristics of the OS transistor 810 described above are such that the voltage at the second gate is V BG_A of By making it larger in this way, it shifts to the curve represented by the dashed line 840 in Figure 38(A). This is possible. Also, the electrical characteristics of the OS transistor 810 mentioned above are that the voltage of the second gate is Voltage V BG_B By making it smaller as shown, the curve represented by the solid line 841 in Figure 38(A) It can be shifted to this. As shown in Figure 38(A), the OS transistor 810 is signal S BG Voltage V BG_A Or voltage V BG_B By switching in this way, The key voltage can be shifted positively or negatively.

[0441] The threshold voltage is the threshold voltage V TH_B By shifting to a positive value, OS transitions The TA810 can be made to a state where current is difficult to flow. Figure 38(B) shows this state. Visualize and show.

[0442] As shown in Figure 38(B), the current I flowing through the OS transistor 810 B Extremely small It can be cut. Therefore, the signal applied to the input terminal IN is at a high level and OS transistor When the ZISTA 820 is ON, it causes the voltage at the output terminal OUT to drop sharply. It is possible.

[0443] As shown in Figure 38(B), the current flowing through the OS transistor 810 is difficult to control. Therefore, the output terminals in the timing chart shown in Figure 37(C) The signal waveform 831 can be changed abruptly. This is achieved by using a wire that provides voltage VDD and voltage VS. Because the through-current flowing between the wiring that provides S can be reduced, low power consumption It can perform the action.

[0444] Also, the threshold voltage is the threshold voltage V TH_A By shifting to a negative value, the OS The transistor 810 can be made to a state where current flows easily. Figure 38(C) shows this The state is visualized and shown. As illustrated in Figure 38(C), the current I flowing at this time A less Even if the current is I B It can be made larger than that. Therefore, the signal given to the input terminal IN is When the OS transistor 820 is in the OFF state at a low level, the power of the output terminal OUT The pressure can be increased rapidly. As shown in Figure 38(C), OS transistor This allows the current to flow more easily through 810, as shown in Figure 37(C). The signal waveform 832 at the output terminal in the mining chart can be changed sharply.

[0445] Note that signal S BG The threshold voltage of the OS transistor 810 is controlled by the OS transistor It is best to do this before the state of the ZISTA 820 changes, that is, before time T1 or T2. For example, as shown in Figure 37(C), the signal applied to the input terminal IN is high level. Before the time T1 when it switches to the new mode, the threshold voltage V TH_A From, threshold voltage V TH _B It is preferable to switch the threshold voltage of the OS transistor 810. Also, Figure 3 As shown in 7(C), the time T when the signal applied to the input terminal IN switches to a low level Before step 2, the threshold voltage V TH_B From threshold voltage V TH_A OS transistor It is preferable to switch the threshold voltage of the 810.

[0446] In Figure 37(C), the timing chart shows that the signal applied to the input terminal IN corresponds to the signal. No. S BG The configuration shown involves switching between these, but other configurations are also possible. For example, the threshold voltage is The voltage for control is set at the second gate of the floating OS transistor 810. A configuration in which it is held is also possible. Figure 39 shows an example of a circuit configuration that can realize this configuration. (A) is shown.

[0447] Figure 39(A) shows the circuit configuration shown in Figure 37(B), plus an OS transistor 850. The first terminal of OS transistor 850 is connected to the second gate of OS transistor 810. It is connected to the second terminal of the OS transistor 850, which has a voltage of V BG_B (or electric Pressure V BG_A The first gate of the OS transistor 850 is connected to the wiring that gives the signal. No. S F It is connected to the wiring that gives the voltage V. The second gate of the OS transistor 850 is connected to the wiring that gives the voltage V. BG _B (or voltage V) BG_A It is connected to the wiring that provides the following:

[0448] The operation shown in Figure 39(A) will be explained using the timing chart in Figure 39(B).

[0449] The voltage used to control the threshold voltage of the OS transistor 810 is applied to the input terminal IN. Before the time T3 when the signal switches to high level, the second gate of the OS transistor 810 The configuration will be applied to the signal S.F The OS transistor 850 is turned ON as a high level State, node N BG Voltage V for controlling the threshold voltage BG_B Give.

[0450] Node N BG Voltage V BG_B After that, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-current, so it can be kept in the off state. So, once we reach node N BG The threshold voltage V held at this level BG_B It can hold. Therefore, a voltage V is applied to the second gate of the OS transistor 850. BG_B The number of actions that give the result decreases. Therefore, voltage V BG_B This reduces the power consumption required for rewriting the data.

[0451] Note that in the circuit configurations of Figures 37(B) and 39(A), the second OS transistor 810 We have shown a configuration in which the voltage applied to the gate is supplied by external control, but we have also shown another configuration. This may also be done. For example, a voltage to control the threshold voltage is applied to the input terminal IN. This configuration may be used to generate the signal and apply it to the second gate of the OS transistor 810. An example of a circuit configuration that can achieve this is shown in Figure 40(A).

[0452] In Figure 40(A), in the circuit configuration shown in Figure 37(B), the input terminal IN and OS Transistor are shown. A CMOS inverter 860 is located between the second gate of the inverter 810. The input terminal of the inverter 860 is connected to the input terminal IN. The power terminal is connected to the second gate of the OS transistor 810.

[0453] The operation shown in Figure 40(A) will be explained using the timing chart in Figure 40(B). In the timing chart of Figure 40(B), the signal waveform of the input terminal IN and the signal of the output terminal OUT are shown. Waveform of the first wave, output waveform IN_B of the CMOS inverter 860, and OS transistor 810 This shows the change in threshold voltage.

[0454] The output waveform IN_B, which is the signal obtained by inverting the logic of the signal applied to the input terminal IN, is an OS trace. This can be used as a signal to control the threshold voltage of the inverter 810. Therefore, see Figure 38. As explained in (A) to Figure 38(C), the threshold voltage of the OS transistor 810 is controlled It can be controlled. For example, when time T4 occurs in Figure 40(B), the signal given to the input terminal IN When the voltage is high, the OS transistor 820 turns on. At this time, the output waveform IN_ B becomes low level. Therefore, the OS transistor 810 is in a state where current does not easily flow. This allows for a sharp decrease in the voltage rise at the output terminal OUT.

[0455] Furthermore, when time T5 occurs in Figure 40(B), the signal applied to the input terminal IN is low. The OS transistor 820 turns off when the bell is activated. At this time, the output waveform IN_B is high-frequency. It becomes a bell. Therefore, the OS transistor 810 can be made to a state where current flows easily. This allows for a rapid increase in the voltage at the output terminal OUT.

[0456] As described above, in the configuration of this embodiment, the inverter having an OS transistor The voltage of the back gate is switched according to the logic of the signal at the input terminal IN. This configuration allows control of the threshold voltage of the OS transistor. Input terminal The threshold voltage of the OS transistor is controlled by the signal applied to IN, and the output terminal The voltage at OUT can be changed abruptly. Also, through-voltage between wiring supplying the power supply voltage can be reduced. The current can be reduced. Therefore, power consumption can be lowered.

[0457] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0458] (Embodiment 6) In this embodiment, the transistor having the oxide semiconductor described in the above embodiment ( Figures 41 to 44 show an example of a semiconductor device that uses OS transistors in multiple circuits. I will explain using number 4.

[0459] <6. Examples of Semiconductor Device Circuit Configurations> Figure 41(A) is a block diagram of the semiconductor device 900. The semiconductor device 900 is powered by a power supply. Path 901, Circuit 902, Voltage generating circuit 903, Circuit 904, Voltage generating circuit 905 and It has road 906.

[0460] The power supply circuit 901 uses a reference voltage V ORG This is a circuit that generates voltage V. ORG teeth, It doesn't have to be a single voltage; it can be multiple voltages. ORG Is it outside the semiconductor device 900? It can be generated based on the voltage V0 that is given from the outside. The semiconductor device 900 is given Based on a single power supply voltage, the voltage V ORG It can generate. Therefore, the semiconductor device 900, It can operate without requiring multiple external power supply voltages.

[0461] Circuits 902, 904, and 906 are circuits that operate with different power supply voltages. For example, The power supply voltage for circuit 902 is voltage V ORG and voltage V SS (V ORG >V SS ) applied by This is the voltage that is applied. Also, for example, the power supply voltage of circuit 904 is the voltage V POG and voltage V SS ( V POG >V ORG ) is the voltage applied by and . Also, for example, the power supply of circuit 906 Voltage is, Voltage V ORG and voltage V NEG (V ORG >V SS >V NEG ) applied by This is the voltage. SS If it is at the same potential as ground (GND), then the power supply circuit The types of voltages generated by the 901 can be reduced.

[0462] The voltage generation circuit 903 generates a voltage V POG This is a circuit that generates voltage. Voltage generation circuit 903 is Voltage V supplied from power supply circuit 901 ORG Based on the voltage V POG It can generate. The semiconductor device 900, having circuit 904, operates based on a single power supply voltage supplied from an external source. It can be made.

[0463] Voltage generation circuit 905 generates voltage V NEG This is a circuit that generates voltage. Voltage generation circuit 905 is Voltage V supplied from power supply circuit 901 ORG Based on the voltage V NEG It can generate. The semiconductor device 900, having circuit 906, operates based on a single power supply voltage supplied from an external source. It can be made.

[0464] Figure 41(B) shows the voltage V POGFigure 41(C) shows an example of circuit 904 in operation. This is an example of a signal waveform used to operate the device.

[0465] Figure 41(B) shows transistor 911. The signal to be applied is, for example, a voltage V POG and voltage V SS It is generated based on the following: Voltage V when the inverter 911 is in a conductive state. POG Voltage during operation to create a non-conductive state V SS Let's assume the voltage is V. POG As shown in Figure 41(C), the voltage V ORG larger Therefore, transistor 911 conducts between its source (S) and drain (D). This allows the operation to be performed more reliably. As a result, the malfunction of circuit 904 is reduced. It can be made into a circuit.

[0466] Figure 41(D) shows the voltage V NEG Figure 41(E) shows an example of circuit 906 in operation. This is an example of a signal waveform used to operate the device.

[0467] Figure 41(D) shows transistor 912 with a back gate. The signal applied to the gate of the STA912 is, for example, a voltage V. ORG and voltage V SS Generated based on The signal is generated when transistor 911 is in a conductive state, and the voltage V ORG , Voltage V when operating in the connected state SS This is how it is done. Also, the back gate of transistor 912 is The voltage is, NEG It is generated based on the voltage V. NEG This is illustrated in Figure 41(E). As such, voltage V SSIt is smaller than (GND). Therefore, the threshold voltage of transistor 912 is It can be controlled to shift positively. Therefore, transistor 912 is It is possible to reliably create a non-conductive state, and the current flowing between the source (S) and drain (D) This can be made smaller. As a result, the circuit 906 is less prone to malfunction and has lower power consumption. It can be made into a circuit.

[0468] Note that voltage V NEG This can also be configured to directly supply power to the back gate of transistor 912. Good. Or, voltage V ORG and voltage V NEG Based on this, the gate of transistor 912 is supplied This configuration generates a signal and applies that signal to the back gate of transistor 912. good.

[0469] Figures 42(A) and 42(B) also show modified examples of Figures 41(D) and 42(E).

[0470] In the circuit diagram shown in Figure 42(A), a control circuit is located between the voltage generation circuit 905 and the circuit 906. Transistor 922 whose conduction state can be controlled by path 921 is shown. Transistor 922 This is an n-channel OS transistor. The control signal S is output by the control circuit 921. BG This is a signal that controls the conduction state of transistor 922. Also, the transistors in circuit 906 Transistors 912A and 912B are OS transistors, just like transistor 922.

[0471] The timing chart in Figure 42(B) shows the control signal S BG And, transistor 912A, The potential state of the back gate of the 912B is shown at node N. BG This is shown by the change in potential. Control signal S B G When the signal level is high, transistor 922 becomes conductive, and node N BG Voltage V N EG This is what happens. Then, the control signal S BG Node N when it is low level BG Electrically flow This results in a low off-current. Transistor 922 is an OS transistor, so the off-current is small. Therefore, node N BG Even if it is electrically floating, once the voltage V is applied NEG It can hold.

[0472] Furthermore, Figure 43(A) shows an example of a circuit configuration applicable to the voltage generation circuit 903 described above. As shown in Figure 43(A), the voltage generation circuit 903 consists of diodes D1 to D5 and a capacitor. This is a five-stage charge pump with C1 to C5 and inverter INV. The signal CLK is supplied either directly to capacitors C1 through C5 or via inverter INV. It can be done. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS Applied by If the voltage is such that the clock signal CLK causes the voltage V ORG It is boosted to a positive voltage five times greater. Voltage V POG This can be obtained. Note that the forward voltage of diodes D1 to D5 is 0V It is stated that by changing the number of stages in the charge pump, the desired voltage V can be achieved. POG To obtain It is possible.

[0473] Furthermore, Figure 43(B) shows an example of a circuit configuration applicable to the voltage generation circuit 905 described above. As shown in Figure 43(B), the voltage generation circuit 905 consists of diodes D1 to D5 and a capacitor. This is a four-stage charge pump with C1 to C5 and an inverter INV. The signal CLK is supplied either directly to capacitors C1 through C5 or via inverter INV. It can be done. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS Applied by If the voltage is such that the clock signal CLK is directed to ground, i.e., voltage V SS From Pressure V ORG The voltage V is stepped down to four times the negative voltage. NEG You can obtain the Dio The forward voltage of components D1 through D5 is set to 0V. Also, the number of stages in the charge pump is changed. By doing so, the desired voltage V NEG You can obtain this.

[0474] Furthermore, the circuit configuration of the voltage generation circuit 903 described above is the same as the configuration shown in the circuit diagram in Figure 43(A). It is not limited to this. For example, modified versions of the voltage generation circuit 903 are shown in Figures 44(A) to 44(C). Modified versions of the voltage generation circuit 903 are shown in Figures 44(A) to 44(C). In circuits 903A to 903C, the voltage applied to each wire is changed, or the element This can be achieved by changing the arrangement of the elements.

[0475] The voltage generation circuit 903A shown in Figure 44(A) consists of transistors M1 to M10, capacitors It has terminals C11 to C14 and inverter INV1. The clock signal CLK is transmitted via The gates of inverters M1 to M10 are supplied either directly or via inverter INV1. The clock signal CLK controls the voltage V ORG The voltage V is boosted to four times the positive voltage. PO G This can be obtained. Furthermore, by changing the number of stages, the desired voltage V can be obtained. POGTo obtain Yes, it is possible. The voltage generation circuit 903A shown in Figure 44(A) uses transistors M1 to M10. By using an S-transistor, the off-current can be reduced and held by capacitors C11 to C14. This can suppress the leakage of the generated charge. Therefore, the voltage V can be efficiently controlled. ORG From voltage V POG Ascending It can measure pressure.

[0476] Furthermore, the voltage generation circuit 903B shown in Figure 44(B) uses transistors M11 to M14. It has capacitors C15 and C16, and inverter INV2. The clock signal CLK is , directly to the gates of transistors M11 to M14, or via inverter INV2 The voltage V is given by the clock signal CLK. ORG The voltage was boosted to twice the positive voltage. Pressure V POG This can be obtained. The voltage generation circuit 903B shown in Figure 44(B) is a transient By using OS transistors for M11 to M14, the off-current can be reduced, and the capacitance... This suppresses the leakage of charge held in C15 and C16. Therefore, it efficiently applies voltage V ORG From voltage V POG It is possible to increase the voltage to [a certain level].

[0477] Furthermore, the voltage generation circuit 903C shown in Figure 44(C) includes an inductor Ind1 and a transistor It has a transistor M15, a diode D6, and a capacitor C17. Transistor M15 is The conduction state is controlled by the control signal EN. The voltage V is controlled by the control signal EN. ORG but Boosted voltage V POG This can be obtained. The voltage generation circuit 903C is shown in Figure 44(C). This uses inductor Ind1 to boost the voltage, thus achieving high conversion efficiency in voltage boosting. It is possible.

[0478] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is It can be generated internally. Therefore, semiconductor devices can reduce the number of externally supplied power voltages. It can be reduced.

[0479] The configurations shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible to be there.

[0480] (Embodiment 7) In this embodiment, a display module and electronic device having a semiconductor device according to one aspect of the present invention are provided. This will be explained using Figures 45 to 48.

[0481] <7-1. Display Module> The display module 7000 shown in Figure 45 consists of an upper cover 7001 and a lower cover 7002. In between, the touch panel 7004 connected to FPC7003 and the FPC7005 are connected Display panel 7006, backlight 7007, frame 7009, printed circuit board 701 0, has battery 7011.

[0482] A semiconductor device according to one aspect of the present invention can be used, for example, as a display panel 7006.

[0483] The upper cover 7001 and the lower cover 7002 are the touch panel 7004 and the display panel. The shape and dimensions can be appropriately modified to match the size of the 7006.

[0484] The 7004 touch panel is a display panel using either a resistive or capacitive touch panel. It can be used superimposed on 7006. Also, the opposing substrate (sealing substrate) of the display panel 7006 It is also possible to give the board a touch panel function. It is also possible to install a light sensor in each pixel of 006 to create an optical touch panel.

[0485] The backlight 7007 has a light source 7008. Note that in Figure 45, the backlight The example given shows a configuration in which the light source 7008 is placed on the T7007, but it is not limited to this. For example, a light source 7008 is placed at the edge of the backlight 7007, and a light diffuser plate is also used. It may also be made into a component. Furthermore, when using self-emissive light-emitting elements such as organic EL elements, or when using reflection In the case of type panels, etc., a configuration without backlight 7007 is also acceptable.

[0486] Frame 7009 provides protection for the display panel 7006, as well as the movement of the printed circuit board 7010. It has the function of an electromagnetic shield to block electromagnetic waves generated by the operation. The 7009 may also function as a heat sink.

[0487] The printed circuit board 7010 contains power supply circuits and signals for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. Alternatively, a separate power source, battery 7011, may be used. This can be omitted when using commercial power.

[0488] Furthermore, the display module 7000 includes components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided.

[0489] <7-2.Electronic equipment 1> Next, Figures 46(A) to 46(E) show examples of electronic devices.

[0490] Figure 46(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0491] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0492] Here, we'll use camera 8000 and replace lens 8006 by removing it from housing 8001. The configuration allows for this, but the lens 8006 and the housing may be integrated.

[0493] Camera 8000 can take an image by pressing the shutter button 8004. Furthermore, the display unit 8002 also functions as a touch panel, and touching the display unit 8002... This also makes it possible to take images.

[0494] The camera 8000's housing 8001 has a mount with electrodes, and the viewfinder 810 In addition to the above, a strobe device and other equipment can be connected.

[0495] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0496] The housing 8101 has a mount that engages with the mount of the camera 8000, and The mount 8100 can be attached to the camera 8000. The mount also has electrodes. The electrode has the ability to display images and other data received from the camera 8000 on the display unit 8102. It can be done.

[0497] Button 8103 functions as a power button. Button 8103 controls the display. You can switch the display of 8102 on or off.

[0498] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied.

[0499] Note that in Figure 46(A), the camera 8000 and the viewfinder 8100 are separate electronic devices. These components are designed to be detachable, and the camera 8000's housing 8001 is equipped with a display device. It may also have a built-in viewfinder.

[0500] Figure 46(B) shows the external appearance of the head-mounted display 8200.

[0501] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0502] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 82 03 is equipped with a wireless receiver and displays video information such as received image data on the display unit 8204. It can also detect the movement of the user's eyeballs and eyelids using a camera located on the main unit 8203. By capturing the user's perspective and calculating the coordinates of their viewpoint based on that information, the user's viewpoint is determined. It can be used as an input method.

[0503] Furthermore, the attachment portion 8201 may be provided with multiple electrodes in positions that come into contact with the user. The main unit 8203 detects the current flowing through the electrodes in response to the user's eye movements, It may also have a function to recognize the user's viewpoint. Furthermore, it may detect the current flowing through the electrode. By doing so, it may have a function to monitor the user's pulse. Also, the attachment part 820 1 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may also have a function to display the user's biometric information. The movement of the unit is detected, and the image displayed on the display unit 8204 is changed in accordance with that movement. That's good too.

[0504] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0505] Figures 46(C),(D), and(E) show the external appearance of the head-mounted display 8300. Yes. The head-mounted display 8300 consists of a housing 8301, a display unit 8302, and It comprises a band-shaped fixing device 8304 and a pair of lenses 8305.

[0506] The user can view the display on the display unit 8302 through the lens 8305. Furthermore, it is preferable to arrange the display unit 8302 in a curved shape. This allows users to experience a high level of realism.

[0507] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. A display device having a semiconductor device in one embodiment has extremely high resolution, as shown in Figure 46(E). Even when magnified using the Uni lens 8305, the pixels are not visible to the user. It can display highly realistic images.

[0508] <7-3.Electronic equipment 2> Next, Figure 4 shows the electronic equipment shown in Figures 46(A) to 46(E), and an example of a different electronic equipment. This is shown in Figures 7(A) through 47(G).

[0509] The electronic device shown in Figures 47(A) to 47(G) consists of a housing 9000, a display unit 9001, and Speaker 9003, operation key 9005 (including power switch or operation switch), connection terminal Child 9006, Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, (Including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared radiation), Microphone It has n9008, etc.

[0510] The electronic devices shown in Figures 47(A) to 47(G) have various functions. For example, various Functions to display various information (still images, videos, text images, etc.) on the display unit, touch panel function Features that display a calendar, date or time, and various software (programs). Functions to control processing, wireless communication functions, and various computers using wireless communication functions It has the ability to connect to a network and transmit or receive various types of data using wireless communication. The function reads programs or data recorded on the recording medium and displays them on the display unit. It can have functions such as the above. Furthermore, the electronic devices shown in Figures 47(A) to 47(G) The functions it can possess are not limited to these, and it can have a variety of functions. Although not shown in Figures 47(A) to 47(G), electronic devices have multiple display units. The configuration may also include a camera or the like to capture still images. The camera has a function to record videos and save the captured images to a recording medium (external or built into the camera). It may also have functions such as displaying captured images on a display unit.

[0511] Details of the electronic equipment shown in Figures 47(A) to 47(G) will be explained below.

[0512] Figure 47(A) is a perspective view showing the television equipment 9100. 100 means the display unit 9001 is a large screen, for example, 50 inches or more, or 100 inches or more. It is possible to incorporate the display unit 9001.

[0513] Figure 47(B) is a perspective view showing the personal digital assistant 9101. The personal digital assistant 9101 is It has one or more functions selected from, for example, a telephone, a notebook, or an information viewing device. Physically, it can be used as a smartphone. Furthermore, the mobile information terminal 9101 is... A speaker 9003, connection terminal 9006, sensor 9007, etc. may be provided. The information terminal 9101 can display text and image information on multiple sides. For example, 3 Two operation buttons 9050 (also called operation icons or simply icons) are displayed on the display unit 9001 It can be displayed on one side. Also, the information 9051 shown by the dashed rectangle is displayed on the display unit 900. It can be displayed on other sides of 1. For example, information 9051 can be sent via email or A display that notifies you of incoming calls from social networking services (SNS) or phone calls. Subject of emails and social media posts, sender's name, date, time, and timestamp. This includes things like remaining battery power and antenna reception strength. Or, information 9051 is displayed. Instead of displaying information 9051, you may also display operation button 9050 or the like.

[0514] Figure 47(C) is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, This shows an example where information 9053 and information 9054 are displayed on different sides. For example, The user of the mobile information terminal 9102 stores the mobile information terminal 9102 in the breast pocket of their clothing. In this state, you can check the display (information 9053 in this case). Specifically, when an incoming call is received... The phone number or name of the caller can be observed from above the mobile information terminal 9102. The information is displayed on the device. The user can view the information without taking the portable information terminal 9102 out of their pocket. This allows you to check and decide whether or not to answer the call.

[0515] Figure 47(D) is a perspective view showing the wristwatch-type personal information terminal 9200. Personal information terminal The 9200 is a mobile phone, email, document viewing and creation, music playback, and internet communication. It can run various applications such as computer games. The display unit 9001 has a curved display surface, and displays are performed along the curved display surface. It can do this. Furthermore, the personal information terminal 9200 can perform standardized short-range wireless communication. This is possible. For example, by communicating with a wireless headset, It is also possible to make calls using the free-call function. In addition, the mobile information terminal 9200 has a connection terminal 9006. It has the capability to directly exchange data with other information terminals via a connector. Charging can also be performed via connection terminal 9006. Note that the charging operation is performed via connection terminal 900 This may also be done by wireless power transfer without using 6.

[0516] Figures 47(E),(F), and(G) are perspective views showing a foldable portable information terminal 9201. Furthermore, Figure 47(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and Figure 47 (F) changes the mobile information terminal 9201 from one state to the other, either unfolded or folded. This is a perspective view of the device in the process of being folded, with Figure 47(G) showing the portable information terminal 9201 in its folded state. This is a perspective view of the device. The 9201 portable information terminal offers excellent portability when folded, and when unfolded... In this configuration, the seamless, wide display area provides excellent readability. (Portable Information Terminal 92) The display unit 9001 of 01 is connected by three housings 9000 via a hinge 9055. It is supported by bending the two housings 9000 via the hinge 9055. Furthermore, the mobile information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. This is possible. For example, the mobile information terminal 9201 can bend with a radius of curvature of 1 mm or more and 150 mm or less. It is possible to do so.

[0517] Furthermore, Figures 48(A) and 48(B) are perspective views of a display device having multiple display panels. Oh, Figure 48(A) is a perspective view of the configuration in which multiple display panels are rolled up, and Figure 48(B) This is a perspective view with multiple display panels deployed.

[0518] The display device 9500 shown in Figures 48(A) and 48(B) consists of multiple display panels 9501 and a shaft portion 9 It has 511 and a bearing portion 9512. In addition, the multiple display panels 9501 have a display area It has a region 9502 and a translucent region 9503.

[0519] Furthermore, the multiple display panels 9501 are flexible. Also, two adjacent display panels The 9501 is provided such that parts of them overlap each other. For example, two adjacent The translucent areas 9503 of the display panel 9501 can be superimposed. By using the display panel 9501, a large-screen display device can be created. Depending on the situation, the display panel 9501 can be rolled up, making it a highly versatile display. It can be used as a display device.

[0520] Furthermore, in Figures 48(A)(B), the display area 9502 is adjacent to the display panel 950 The diagram illustrates the state of separation at point 1, but it is not limited to this; for example, adjacent display panels 9 By overlapping the 501 display area 9502 without any gaps, a continuous display area 9502 and You may do so.

[0521] The electronic device described in this embodiment has a display unit for displaying some kind of information. It is characterized by having the following characteristics. However, one embodiment of the present invention is an electronic device that does not have a display unit. It can also be applied to containers.

[0522] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0523] (Embodiment 8) In this embodiment, it is possible to retain the contents of the memory even when power is not supplied, and write Figure 4 shows a semiconductor device (memory device) with no limit on the number of operations, and a CPU that includes it. This will be explained using Figures 9 to 51. The CPU described in this embodiment is, for example, the CPU of the previous embodiment. It can be used in electronic devices described by their form.

[0524] <8-1. Storage device> It can retain stored data even when power is not supplied, and there is no limit to the number of write cycles. An example of a semiconductor device (memory device) without a semiconductor is shown in Figure 49. Note that Figure 49(B) is a copy of Figure 49(A). This is a diagram showing the circuit diagram.

[0525] The semiconductor device shown in Figures 49(A) and (B) is a transistor using the first semiconductor material. A transistor 3300 using 3200 and a second semiconductor material, and a capacitive element 3400 I have it.

[0526] The first and second semiconductor materials are materials with different energy gaps. This is preferable. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon( (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide (e.g., aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.) The second semiconductor material can be an oxide semiconductor. Other materials besides oxide semiconductors can also be used. Transistors using crystalline silicon, for example, are easy to operate at high speeds. On the other hand, oxide semiconductors... Transistors made using the body have low off-current.

[0527] Transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. The 3300 transistor is used because it has a low off-current. It is possible to retain memory content for a longer period of time. In other words, refresh operations are unnecessary. To create a semiconductor memory device that does not require refresh operations, or one that requires extremely infrequent refresh operations. This makes it possible to significantly reduce power consumption.

[0528] In Figure 49(B), the first wiring 3101 is connected to the source electrode of transistor 3200. Connected electrically, the second wire 3102 is electrically connected to the drain electrode of transistor 3200. They are connected. Also, the third wire 3103 is the source electrode of transistor 3300 or Electrically connected to one of the drain electrodes, the fourth wire 3104 is connected to transistor 3300. It is electrically connected to the gate electrode of transistor 3200. The source electrode or drain electrode of transistor 3300, and the other side of the source electrode, are connected to capacitive element 3400. The fifth wiring 3105 is electrically connected to one of the electrodes of the capacitive element 3400, and the other electrode of the capacitive element 3400 is connected to the other electrode of the capacitive element 3400. It is electrically connected to it.

[0529] In the semiconductor device shown in Figure 49(A), the potential of the gate electrode of transistor 3200 is maintained. By taking advantage of this capability, it is possible to write, store, and read information as follows: be.

[0530] The writing and retention of information will be explained. First, the potential of the fourth wiring 3104 is set to The potential is set to turn on transistor 3300, thereby turning on transistor 3300. This causes the potential of the third wiring 3103 to be the gate electrode of transistor 3200. And is supplied to the capacitance element 3400. That is, the gate of transistor 3200 is supplied A constant charge is given (written). Here, a charge that gives two different potential levels ( Let's assume that either a low-level charge or a high-level charge is given. After that, the potential of the fourth wire 3104 is set to the potential at which transistor 3300 is in the off state. By turning off transistor 3300, the gate of transistor 3200 is affected. The given charge is retained (retained).

[0531] Because the off-current of transistor 3300 is extremely small, the gate of transistor 3200 The charge is retained for a long time.

[0532] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3101. When the appropriate potential (readout potential) is applied to the fifth wiring 3105 while the current is being applied, the transient Depending on the amount of charge held at the gate of terminal 3200, the second wiring 3102 has a different potential. To take. Generally, if transistor 3200 is an n-channel type, then the transistor 3200 The apparent threshold Vth_H when a high-level charge is applied to the gate electrode is The apparent case when a low level charge is applied to the gate electrode of transistor 3200 This is because it becomes lower than the threshold voltage Vth_L. Here, the apparent threshold voltage is This refers to the potential of the fifth wiring 3105 required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3105 is set to the potential V0 between Vth_H and Vth_L. By doing so, the charge applied to the gate of transistor 3200 can be determined. For example, During writing, if a high-level charge is applied, the fifth wiring 3105 When the potential becomes V0 (>Vth_H), transistor 3200 enters the "on state". If a low-level charge is applied, the potential of the fifth wiring 3105 is V0( <Vt Even when h_L) is reached, transistor 3200 remains in the "off state". Therefore, By determining the potential of wiring 3102, the stored information can be read. .

[0533] The semiconductor device shown in Figure 49(C) is different from Figure 49 in that it does not have transistor 3200. This differs from A). In this case, the same operation as above is used for writing and holding information. This is possible.

[0534] Next, we will explain how to read information from the semiconductor device shown in Figure 49(C). When the 3300 is turned ON, the floating third wiring 3103 and the capacitive element 3400 The two circuits become conductive, and the charge is redistributed between the third wiring 3103 and the capacitive element 3400. As a result, the potential of the third wiring 3103 changes. The amount of change in the potential of the third wiring 3103 is the capacitance. The potential of one electrode of element 3400 (or the charge accumulated in the capacitive element 3400) They take on different values.

[0535] For example, let V be the potential of one electrode of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and The capacitive component of the third wiring 3103 is CB, and the third wiring 3103 before the charge is redistributed. If the potential of is VB0, then the potential of the third wiring 3103 after the charge has been redistributed is (CB The formula becomes (×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is a capacitive element. If one electrode of the 3400 takes on two potential states, V1 and V0 (V1 > V0), then the potential The potential of bit line BL when V1 is held is (= (CB × VB0 + C × V1) / (CB The potential of bit line BL when potential V0 is maintained is (CB × VB0 + C)) = (CB × VB0 + C It can be seen that it is higher than ×V0) / (CB+C)).

[0536] Then, by comparing the potential of the third wiring 3103 with a predetermined potential, the information can be read out. It is possible.

[0537] In this case, the first semiconductor material described above is applied to the drive circuit for driving the memory cell. Using a transistor, a second semiconductor material was applied to transistor 3300. The inverters can be stacked on top of the drive circuit.

[0538] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-voltage applications. By using transistors with extremely low current, it is possible to retain memory content for extremely long periods of time. It is possible to do so. In other words, a refresh operation will become unnecessary, or a refresh will be required. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. It is possible. Also, in the absence of power supply (however, it is desirable that the potential be fixed). Even if memory is impaired, it is possible to retain the contents of that memory over a long period of time.

[0539] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information. There are no issues with element degradation. For example, unlike conventional non-volatile memory, floating-point memory... Because there is no need to inject electrons into the gate or extract electrons from the floating gate. Furthermore, problems such as degradation of the gate insulating film do not occur at all. In other words, the semiconductor shown in this embodiment In this device, there is no limitation on the number of rewrite cycles, which is a problem with conventional non-volatile memory. Reliability improves dramatically. Furthermore, information is obtained depending on the on and off states of the transistor. Because data is written to the system, high-speed operation can be easily achieved.

[0540] The above-mentioned storage device is, for example, a CPU (Central Processing Unit). In addition to the Unit, there is also a DSP (Digital Signal Processor), LSIs, PLDs (Programmable Logic Devices), etc. SI, RF-ID (Radio Frequency Identification) It can also be applied to other areas.

[0541] <8-2.CPU> The following describes the CPU, including the storage device mentioned above.

[0542] Figure 50 is a block diagram showing an example configuration of a CPU including the storage device described above.

[0543] The CPU shown in Figure 50 is an ALU2191 (ALU: Arithmetic) mounted on board 2190. tic logic unit (arithmetic circuit), ALU controller 2192, instruction Action decoder 2193, interrupt controller 2194, timing controller R2195, Register 2196, Register Controller 2197, Bus Interface 2198 (Bus I / F), rewritable ROM2199, and ROM interface It has a ROM I / F (2189). The substrate 2190 is a semiconductor substrate, SOI base A plate, glass substrate, etc., is used. ROM2199 and ROM interface2189 are, It may also be provided on a separate chip. Of course, the CPU shown in Figure 50 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. A configuration including the CPU or arithmetic circuit shown in Figure 50 is considered one core, and a configuration including multiple such cores is considered. Alternatively, the configuration may be such that each core operates in parallel. Also, the CPU's internal calculations The number of bits that can be handled by a path or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits. It can be written as ".net" or similar.

[0544] Instructions input to the CPU via the bus interface 2198 are instructions The signal is input to the decoder 2193, decoded, and then processed by the ALU controller 2192. Trap controller 2194, register controller 2197, timing controller This is entered into Ra2195.

[0545] ALU controller 2192, interrupt controller 2194, register controller The 2197 and 2195 timing controllers perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 2192 controls the operation of the ALU 2191. It generates a signal to do so. In addition, the interrupt controller 2194 generates a signal for the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 2197 processes the state of register 2196. It generates a dress and reads or writes to register 2196 depending on the CPU state. .

[0546] Furthermore, the timing controller 2195 is ALU2191, ALU controller 21 92, instruction decoder 2193, interrupt controller 2194, and It generates signals that control the timing of the operation of the register controller 2197. For example, The timing controller 2195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0547] In the CPU shown in Figure 50, a memory device is provided in register 2196.

[0548] In the CPU shown in Figure 50, the register controller 2197 receives from ALU2191 Following the instructions, select the hold operation in register 2196. That is, register 2 In the memory device of 196, data is retained using flip-flops, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory device in register 2196. If data retention in the capacitive element is selected, then data rewriting to the capacitive element is This can be done to stop the supply of power voltage to the memory device in register 2196.

[0549] Figure 51 is an example of a circuit diagram of a memory element that can be used as register 2196. The memory element 2200 includes a circuit 2201 in which the stored data is volatile when the power is cut off, and a memory element 2200 that volatilizes when the power is cut off. Circuit 2202 that prevents data loss, switch 2203, switch 2204, and logic It comprises element 2206, capacitive element 2207, and circuit 2220 having a selection function. The circuit 2202 has a capacitive element 2208, a transistor 2209, and a transistor 2210. , has. The memory element 2200 may include a diode, a resistor, an industrial diode as needed. It may also have other elements such as connectors.

[0550] Here, the memory device described above can be used in circuit 2202. Memory element 220 When the power supply voltage to 0 is cut off, the gate of transistor 2209 in circuit 2202 A configuration in which the ground potential (0V) or the potential that turns off transistor 2209 is continuously input. For example, in a configuration where the gate of transistor 2209 is grounded via a load such as a resistor, do.

[0551] Switch 2203 uses a single-conductivity (e.g., n-channel) transistor 2213. The switch 2204 is configured to have a conductivity type opposite to that of a single-conductivity type (e.g., p-channel type). An example is shown using transistor 2214. Here, the first of switch 2203 The terminals correspond to one of the source and drain terminals of transistor 2213, and the other terminal of switch 2203. Terminal 2 corresponds to the source and drain of transistor 2213, and switch 2203 The control signal RD input to the gate of transistor 2213 controls the first terminal and the second terminal. The continuity or non-continuity between the terminals (i.e., the ON or OFF state of transistor 2213) The state is selected. The first terminal of switch 2204 is connected to the source and dot of transistor 2214. Corresponding to one side of the rain, the second terminal of switch 2204 is the source of transistor 2214. Corresponding to the other side of the drain, switch 2204 is input to the gate of transistor 2214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of transistor 2214 is selected.

[0552] One of the sources and drains of transistor 2209 is connected to the pair of electrodes of capacitive element 2208. One of them is electrically connected to the gate of transistor 2210. Here, the connection part Let node M2. One of the sources and drains of transistor 2210 is at a low power supply potential. It is electrically connected to a wire (e.g., a GND wire) that can supply power, and the other is a switch. The first terminal of 2203 (one of the source and drain of transistor 2213) is electrically connected. The second terminal of switch 2203 (source and drain of transistor 2213) On the other hand, the first terminal of switch 2204 (the source and drain of transistor 2214) is the first terminal of switch 2204. It is electrically connected to the second terminal of switch 2204 (the terminal of transistor 2214). The other end of the drain is electrically connected to wiring that can supply the power potential VDD. The second terminal of switch 2203 (the other of the source and drain of transistor 2213) ) and the first terminal of switch 2204 (one of the source and drain of transistor 2214) ) and the input terminal of logic element 2206 and one of the pair of electrodes of capacitive element 2207, These are electrically connected. Here, the connection point is called node M1. A pair of capacitive elements 2207. The other electrode can be configured to receive a constant potential. For example, a low potential The system can be configured to receive either a source potential (such as GND) or a high power supply potential (such as VDD) as input. The other electrode of the pair of electrodes of the capacitive element 2207 is a distribution capable of supplying a low power supply potential. It is electrically connected to a wire (for example, a GND wire). This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 220 The other of the pair of electrodes (8) is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to a wire.

[0553] Capacitive elements 2207 and 2208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0554] The control signal WE is input to the first gate (first gate electrode) of transistor 2209. Switches 2203 and 2204 receive a different control signal RD than control signal WE. Therefore, a conductive or non-conductive state is selected between the first terminal and the second terminal, and one of the switches When there is electrical conductivity between the first and second terminals of one switch, the first and second terminals of the other switch... The terminals are in a non-conductive state.

[0555] The source and drain of transistor 2209 are connected to the data held in circuit 2201. A signal corresponding to the traffic signal is input. In Figure 51, the signal output from circuit 2201 is the traffic signal. An example is shown where the source and the other drain of the inverter 2209 are input. Switch 2203 The signal output from the second terminal (the other of the source and drain of transistor 2213) is The logic value is inverted by the logic element 2206, becoming an inverted signal, and then transmitted through the circuit 2220. This is then input to circuit 2201.

[0556] Note that in Figure 51, the second terminal of switch 2203 (the source of transistor 2213 and The signal output from the other side of the drain is routed through logic element 2206 and circuit 2220. An example of input to path 2201 is shown, but it is not limited to this. The second terminal of switch 2203 The signal output from (the other side of the source and drain of transistor 2213) is the inverse of the logic value. It may be input to circuit 2201 without being converted. For example, within circuit 2201, If there is a node that holds a signal that is the inverted logical value of the signal input from the input terminal The second terminal of switch 2203 (the other of the source and drain of transistor 2213) The signal output from this node can be input to the node in question.

[0557] Furthermore, in Figure 51, among the transistors used in the memory element 2200, The transistors other than STA2209 are made of a layer or substrate 21 made of a semiconductor other than an oxide semiconductor. A transistor can be formed with a channel at 90. For example, a silicon layer or This can be a transistor in which a channel is formed on a silicon substrate. All transistors used in the 2200 have channels formed from oxide semiconductor films. It can also be a transistor. Alternatively, the memory element 2200 is a transistor 2209 or higher. In addition, it may include transistors in which the channel is formed of an oxide semiconductor film, and the rest The transistor has a channel formed in a layer or substrate 2190 made of a semiconductor other than an oxide semiconductor. It can also be considered a transistor.

[0558] In the circuit 2201 in Figure 51, for example, a flip-flop can be used. Furthermore, logic elements 2206 can be, for example, inverters or clocked inverters. It is possible.

[0559] In the semiconductor device shown in this embodiment, while the power supply voltage is not supplied to the memory element 2200, The data stored in circuit 2201 is transferred to the capacitive element 2208 provided in circuit 2202. It can be held by.

[0560] Furthermore, transistors with channels formed in oxide semiconductor films exhibit extremely low off-currents. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film depends on the crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, a transistor in which a channel is formed in an oxide semiconductor film is called transistor 2209. By using it in this way, the capacitive element 22 can operate even when the power supply voltage is not supplied to the memory element 2200. The signal held in 08 is retained for a long period of time. In this way, the memory element 2200 is powered by...

Claims

1. A first conductive film having the function of a gate electrode, A first insulating film having a region located above the first conductive film and functioning as a gate insulating film, An oxide semiconductor film having a region located above the first insulating film and having a channel-forming region, A second conductive film having a region located above the oxide semiconductor film and functioning as either a source electrode or a drain electrode, A third conductive film having a region located above the oxide semiconductor film and functioning as either a source electrode or a drain electrode, A second insulating film having a region located above the second conductive film, A fourth conductive film having a region located above the second insulating film and functioning as a pixel electrode, A fifth conductive film having a region that overlaps with the fourth conductive film via a third insulating film and having a function as a common electrode, The oxide semiconductor film comprises a first semiconductor film having a region on its lower surface that contacts the upper surface of the first insulating film, and a second semiconductor film having a region that contacts the upper surface of the first semiconductor film and a region on its upper surface that contacts the lower surface of the second conductive film. The oxide semiconductor film has a first region in which the second semiconductor film and the second conductive film are in contact. In the first region, the thickness of the second semiconductor film is greater than the thickness of the first semiconductor film. The fourth conductive film has a region in contact with the second conductive film, In a cross-sectional view, the fourth conductive film does not overlap with the third conductive film in the semiconductor device.

2. A first conductive film having the function of a gate electrode, A first insulating film having a region located above the first conductive film and functioning as a gate insulating film, An oxide semiconductor film having a region located above the first insulating film and having a channel-forming region, A second conductive film having a region located above the oxide semiconductor film and functioning as either a source electrode or a drain electrode, A third conductive film having a region located above the oxide semiconductor film and functioning as either a source electrode or a drain electrode, A second insulating film having a region located above the second conductive film, A fourth conductive film having a region located above the second insulating film and functioning as a pixel electrode, A fifth conductive film having a region that overlaps with the fourth conductive film via a third insulating film and functioning as a common electrode, The device comprises a spacer having a region located above the fifth conductive film, The oxide semiconductor film comprises a first semiconductor film having a region on its lower surface that contacts the upper surface of the first insulating film, and a second semiconductor film having a region that contacts the upper surface of the first semiconductor film and a region on its upper surface that contacts the lower surface of the second conductive film. The oxide semiconductor film has a first region in which the second semiconductor film and the second conductive film are in contact. In the first region, the thickness of the second semiconductor film is greater than the thickness of the first semiconductor film. The fourth conductive film has a region in contact with the second conductive film, In a cross-sectional view, the fourth conductive film does not overlap with the third conductive film. The spacer is a semiconductor device having a region that overlaps with the oxide semiconductor film.

3. In claim 1 or claim 2, The first semiconductor film and the second semiconductor film each comprise In, Zn, and M (where M represents Al, Ga, Y, or Sn).

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