Semiconductor equipment

Abstract

To provide an inexpensive semiconductor device with improved moisture resistance. [Solution] The front surface of the semiconductor substrate 40 has an outer peripheral step 25 on the channel stopper region 32 at the outer periphery of the semiconductor substrate 40, where the fourth surface 40d, which includes the scribe region 3 at the outer periphery of the semiconductor substrate 40, is recessed from the fourth surface 40d toward the chip center. The insulating layer 33 is provided with a constant thickness over the entire surface of the front surface of the semiconductor substrate 40 in the edge termination region 2. The surface protective film 34 covers the outer peripheral step 25 of the front surface of the semiconductor substrate 40 via the insulating layer 33. The upper surface of the surface protective film 34 has a fifth upper surface 34e that slopes more gently and has a smaller inclination angle than the outer peripheral step 25 on the portion of the outer peripheral step 25 of the front surface of the semiconductor substrate 40. The surface protective film 34 terminates toward the chip center toward the edge of the semiconductor substrate 40, exposing the scribe region 3, and has a tapered outer end surface 34f on the fourth surface 40d of the front surface of the semiconductor substrate 40.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 below describes an apparatus that improves moisture resistance to moisture penetrating into the polyimide protective film by providing a protective metal film from the outer edge of the oxide protective film to the surface of the epitaxial layer. Patent Document 2 below describes an apparatus that improves moisture resistance to moisture penetrating from the outer edge of the organic insulating film by providing a plurality of grooves extending along the outer edge of the organic insulating film on the upper surface of the semiconductor substrate in the terminal region. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 7085959 [Patent Document 2] Japanese Patent Publication No. 2023-172987 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the above-mentioned Patent Documents 1 and 2, the length of the termination region (the length in the lateral direction from the center to the outer edge of the semiconductor substrate) increases by arranging a protective metal film and grooves, respectively. As a result, the surface area (chip area) of the semiconductor substrate increases, and costs increase.

[0005] This disclosure aims to provide an inexpensive semiconductor device with improved moisture resistance. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of this disclosure is as follows: A semiconductor substrate comprises an active region through which a main current flows and a termination region surrounding the active region. The termination region includes a scribe line remaining on the outer periphery of the semiconductor substrate, an insulating layer covering a first main surface of the semiconductor substrate, and a surface protective film provided on the insulating layer. The first main surface has a step formed by recessing a first surface including the scribe line toward the second main surface of the semiconductor substrate toward a second main surface of the semiconductor substrate toward a second surface inside the first surface. The surface protective film covers the step via the insulating layer. [Effects of the Invention]

[0007] The semiconductor device described herein offers the advantage of improving moisture resistance while suppressing cost increases. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the layout of the semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] Figure 2 is a cross-sectional view showing a magnified view of the area near the tip of the chip. [Figure 4] This is a cross-sectional view (part 1) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 5] This is a cross-sectional view (part 2) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 6] This is a cross-sectional view (part 3) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 7] This is a cross-sectional view (part 4) showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 8] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2. [Figure 9] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3. [Modes for carrying out the invention]

[0009] <Summary of the embodiments of this disclosure> (1) A semiconductor device according to one aspect of this disclosure is as follows: A semiconductor substrate comprises an active region through which a main current flows, and a termination region surrounding the active region. The termination region comprises a scribe line remaining on the outer periphery of the semiconductor substrate, an insulating layer covering a first main surface of the semiconductor substrate, and a surface protective film provided on the insulating layer. The first main surface has a step formed by recessing a first surface including the scribe line toward the second main surface of the semiconductor substrate toward a second main surface of the semiconductor substrate toward a second surface that is inside the first surface. The surface protective film covers the step via the insulating layer.

[0010] According to the disclosure described above, moisture (water vapor) flowing in from the outer edge of the surface protective film is less likely to flow inward from the step (outer edge step) on the first main surface of the semiconductor substrate, thereby improving the moisture resistance of the semiconductor device. The step on the front surface of the semiconductor substrate has a simple structure and can be easily formed by etching or the like, thus suppressing an increase in costs.

[0011] (2) Another semiconductor device according to one aspect of this disclosure is as follows: A semiconductor substrate comprises an active region through which a main current flows and a termination region surrounding the active region. The termination region comprises a channel stopper region provided on the outer periphery of the semiconductor substrate, an insulating layer covering a first main surface of the semiconductor substrate, and a surface protective film provided on the insulating layer. The channel stopper region is provided along the first main surface. The first main surface has a step on the channel stopper region, where a first surface extending inward from the outer periphery of the semiconductor substrate by a predetermined width is recessed toward the second main surface of the semiconductor substrate than a second surface located inside the first surface. The surface protective film covers the step via the insulating layer.

[0012] According to the disclosure described above, moisture (water vapor) flowing in from the outer edge of the surface protective film is less likely to flow inward from the step (outer edge step) on the first main surface of the semiconductor substrate, thereby improving the moisture resistance of the semiconductor device. The step on the front surface of the semiconductor substrate has a simple structure and can be easily formed by etching or the like, thus suppressing an increase in costs.

[0013] (3) In addition, in the semiconductor device according to this disclosure, in (1) or (2) above, the surface protective film is terminated on the first surface via the insulating layer, and the semiconductor device may have an inclined surface on the first surface that is inclined at a predetermined inclination angle with respect to the first surface.

[0014] According to the disclosure described above, the portion of the surface protective film on the scribe line is removed before cutting (dicing) individual semiconductor chips (semiconductor substrates) from the semiconductor wafer, resulting in an inclined outer edge of the surface protective film. By eliminating the presence of the surface protective film on the scribe line during semiconductor wafer dicing, contamination by processing debris from dicing blades and the like can be suppressed.

[0015] (4) In addition, in any one of (1) to (3) described above, the semiconductor device according to this disclosure may have a tapered step on the first main surface, wherein the inclination angle of the third surface connecting the first surface and the second surface is 45 degrees or more and 90 degrees or less with respect to the second surface.

[0016] According to the disclosure described above, the inflow of moisture from the outer peripheral step of the first main surface of the semiconductor substrate into the interior can be further suppressed.

[0017] (5) In addition, in any one of (1) to (3) described above, the semiconductor device according to this disclosure may have the first main surface having the step in the shape of an inverted taper, wherein the inclination angle of the third surface connecting the first surface and the second surface is 45 degrees or more and 90 degrees or less with respect to the first surface.

[0018] According to the disclosure described above, the inflow of moisture from the outer peripheral step of the first main surface of the semiconductor substrate into the interior can be further suppressed.

[0019] (6) The semiconductor device according to this disclosure may also have a sub-trench on the first surface in any one of (1) to (4) described above, and the insulating layer may be provided along the inner wall of the sub-trench.

[0020] According to the disclosure described above, the inflow of moisture from the outer peripheral step of the first main surface of the semiconductor substrate into the interior can be further suppressed.

[0021] (7) In addition, in the semiconductor device relating to this disclosure, the depth of the sub-trench may be 0.1 μm or more and 1 μm or less as described in (6) above.

[0022] According to the disclosure described above, the coverage of the insulating layer can be improved.

[0023] (8) In addition, in the semiconductor device relating to this disclosure, a channel stopper region may be provided on the outer periphery of the semiconductor substrate along the step, as described in (1) above.

[0024] According to the disclosure described above, when the semiconductor device is turned off, it is possible to suppress electric field concentration at the outer peripheral step of the first main surface of the semiconductor substrate.

[0025] (9) In addition, in any one of (2) to (8) described above, the semiconductor device according to this disclosure, the channel stopper region may be provided along the first surface and extend inward from the first surface along the step to the second surface.

[0026] According to the above disclosure, when the semiconductor device is turned off, the spreading of the depletion layer from the center outward of the semiconductor substrate can be suppressed near the second surface of the first main surface of the semiconductor substrate.

[0027] (10) In addition, in any one of the above-described semiconductor devices (1) to (9), the surface protective film may be made of polyimide.

[0028] According to the disclosure described above, the stress generated in the semiconductor substrate can be reduced by the surface protective film. Furthermore, adverse effects on semiconductor devices due to environmental changes can be mitigated. Therefore, the reliability of semiconductor devices can be improved.

[0029] <Knowledge forming the basis of this disclosure> Generally, semiconductor devices have a surface protective film made of polyimide on the outermost surface of the semiconductor substrate (semiconductor chip) in the edge termination region. Over time, moisture (water vapor) from the air absorbed by the surface protective film can penetrate from the outer edge (the edge on the chip end side). Moisture that flows in from the outer edge of the surface protective film flows along the interface between the surface protective film and the insulating layer beneath it toward the active region (the chip center side), which may cause peeling of the surface protective film or adverse effects on the pressure-resistant structure of the edge termination region. Patent documents 1 and 2 disclose structures for improving moisture resistance to moisture flowing in from the outer edge of the surface protective film.

[0030] However, in the above-mentioned Patent Documents 1 and 2, the chip area increases and product costs increase due to the arrangement of structures to improve moisture resistance (a protective metal film with high moisture resistance and multiple grooves with a trapezoidal cross-sectional shape inside the internal space). Furthermore, in Patent Document 1, the process becomes complicated due to the need for a photomask or additional process to partially leave the protective metal film. In Patent Document 2, the process for forming grooves with a trapezoidal cross-sectional shape inside the internal space becomes complicated. As a result, manufacturing costs increase. In addition, in Patent Document 1, depending on the arrangement of the protective metal film, the protective metal film may be scraped off by a dicing blade or the like, which may cause metal chips to scatter or the protective metal film to peel off.

[0031] One of the problems to be solved in this embodiment is to provide an inexpensive semiconductor device with improved moisture resistance and a structure that can be easily formed. In addition, the adhesion between the semiconductor device and the resin of the package on which it is mounted is also improved.

[0032] Preferred embodiments of the semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0033] (Details of Embodiment 1) The semiconductor device according to Embodiment 1, which solves the above-mentioned problems, is described below. Figure 1 is a plan view showing the layout of the semiconductor device according to the embodiment as seen from the front side of the semiconductor substrate. Figure 2 is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. Figure 3 is a cross-sectional view showing an enlarged view of the vicinity of the chip edge in Figure 2. In Figure 3, in order to clarify the structure near the chip edge, the structure on the chip center side of the channel stopper region 32 is simplified or omitted from the illustration, and the length of the edge termination region 2 (the length in the lateral direction from the chip center side to the chip edge) is shown at a different ratio than in Figure 2.

[0034] The semiconductor device 10 according to the embodiment shown in Figures 1 to 3 includes a step (hereinafter referred to as the outer edge step) 25 formed by recessing the front surface of the semiconductor substrate 40 along the outer edge (chip edge) of the semiconductor substrate 40, in the outer periphery including the scribe region 3 (the remaining portion of the scribe line 50b of the semiconductor wafer 50: see Figure 7 described later) of the semiconductor substrate 40. The material of the semiconductor substrate 40 can also be a semiconductor with a wider band gap than Si (hereinafter referred to as a wide-bandgap semiconductor), such as silicon carbide (SiC) or gallium nitride (GaN). The material of the semiconductor substrate 40 may also be silicon (Si).

[0035] As shown in Figure 1, the semiconductor substrate 40 has an active region 1 and an edge termination region 2. The active region 1 has a roughly rectangular planar shape and is located approximately in the center of the semiconductor substrate 40 (center of the chip). The active region 1 is described later as p + This is the portion from the outer edge of the outer peripheral region 22a inward (towards the center of the chip). Multiple cells (functional units of elements) of the same structure are arranged in parallel in the central part 1a of the active region 1. The central part 1a of the active region 1 has, for example, a roughly rectangular planar shape and is the region through which the main current (drift current) flows when the semiconductor device 10 is turned on. The outer peripheral part 1b of the active region 1 surrounds the central part 1a of the active region 1 in a roughly rectangular shape.

[0036] The outer periphery 1b of the active region 1 may contain, for example, circuit sections or wiring layers (not shown) for protecting and controlling elements located in the central part 1a of the active region 1. If the semiconductor device 10 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) or an IGBT (Insulated Gate Bipolar Transistor: an insulated gate type bipolar transistor), gate pads or gate runners (not shown) are located in the outer periphery 1b of the active region 1.

[0037] The edge termination region 2 is the region between the active region 1 and the tip edge, and surrounds the active region 1 in a roughly rectangular shape. The edge termination region 2 has the function of mitigating the electric field on the front side of the semiconductor substrate 40 and maintaining the breakdown voltage. A predetermined breakdown voltage structure 30 (see Figure 2), such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring, is arranged in the edge termination region. Breakdown voltage is the upper limit voltage at which the semiconductor device 10 does not malfunction or break down at the operating voltage.

[0038] The edge termination region 2 has a scribe region 3 around the entire outer circumference of the semiconductor substrate 40. The scribe region 3 is the remaining portion of the cutting allowance (scribe line 50b of the semiconductor wafer 50: see Figure 7) when cutting individual semiconductor chips (semiconductor substrate 40) from the semiconductor wafer 50 using a dicing blade or the like. The width of the scribe line 50b of the semiconductor wafer 50 is, for example, about 100 μm or several tens of μm wider, and the blade width of a typical dicing blade is, for example, about 60 μm. The width w1 of the scribe region 3 of the semiconductor substrate 40 is, for example, about 20 μm from the chip edge towards the chip center. The chip edge side of the scribe region 3 may have a pattern or alignment mark for process monitoring. The chip edge side of the scribe region 3 may have a channel stopper region 32 or an insulating layer 33 without a pattern or alignment mark for process monitoring.

[0039] As shown in Figures 2 and 3, the semiconductor substrate 40 is made of, for example, a wide-bandgap semiconductor n + The semiconductor substrate 40 is formed by sequentially epitaxially growing each epitaxial layer 42, 43 on the front surface of a starting substrate (bulk substrate) 41. The first main surface on the side of the epitaxial layer 43 is the front surface, n + The second main surface on the mold starting substrate 41 side is designated as the back surface. For example, if the material of the semiconductor substrate 40 is Si, the semiconductor substrate 40 may be composed only of a bulk substrate. Here, we will explain using the example where the material of the semiconductor substrate 40 is SiC and the semiconductor device 10 is, for example, an n-channel MOSFET with a trench gate structure.

[0040] n + The starting substrate 41 is n + This is a type drain region 11. The epitaxial layers 42 and 43 are n -It becomes the n-type drift region 12 and the p-type base region 13. When the epitaxial layer 43 is p-type, a part of the edge termination region 2 of the epitaxial layer 43 is removed by, for example, etching or the like, and a step (hereinafter referred to as a boundary step) 24 is formed on the front surface of the semiconductor substrate 40 in the vicinity of the boundary with the edge termination region 2. The front surface of the semiconductor substrate 40 is recessed toward the n-type drain region 11 side at the part of the edge termination region 2 (hereinafter referred to as the second surface (second surface)) 40b rather than the part of the active region 1 (hereinafter referred to as the first surface (second surface)) 40a with the boundary step 24 as a boundary. + The type drain region 11 side is recessed.

[0041] The portion (hereinafter referred to as the third surface) 40c connecting the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40 may be a vertical surface forming a substantially right angle with respect to the second surface 40b of the front surface of the semiconductor substrate 40, or may be a tapered inclined surface forming an obtuse angle. The second surface 40b of the front surface of the semiconductor substrate 40 is the exposed surface of the n-type epitaxial layer 42 exposed at the time of forming the boundary step 24. The boundary step 24 on the front surface of the semiconductor substrate 40 surrounds the periphery of the active region 1. The third surface 40c of the front surface of the semiconductor substrate 40 is the side surface (exposed surface) of the epitaxial layer 43 exposed at the time of forming the boundary step 24. The epitaxial layer 42 may be exposed on the third surface 40c of the front surface of the semiconductor substrate 40. - Also, on the outer peripheral portion of the semiconductor substrate 40, the surface layer of the second surface 40b (the exposed surface of the epitaxial layer 42 in the edge termination region 2) of the front surface of the semiconductor substrate 40 is partially removed by, for example, etching or the like, and an outer peripheral step 25 having a substantially right angle or a tapered shape is formed on the front surface of the semiconductor substrate 40. The outer peripheral step 25 on the front surface of the semiconductor substrate 40 surrounds the periphery of the withstand voltage structure 30. The front surface of the semiconductor substrate 40 is recessed toward the chip end side (hereinafter referred to as the fourth surface (first surface)) 40d rather than the second surface 40b on the chip center side with the outer peripheral step 25 as a boundary.

[0042] Further, on the outer peripheral portion of the semiconductor substrate 40, the surface layer of the second surface 40b (the exposed surface of the epitaxial layer 42 in the edge termination region 2) of the front surface of the semiconductor substrate 40 is partially removed by, for example, etching or the like, and an outer peripheral step 25 having a substantially right angle or a tapered shape is formed on the front surface of the semiconductor substrate 40. The outer peripheral step 25 on the front surface of the semiconductor substrate 40 surrounds the periphery of the withstand voltage structure 30.The front surface of the semiconductor substrate 40 is recessed toward the chip end side (hereinafter referred to as the fourth surface (first surface)) 40d rather than the second surface 40b on the chip center side with the outer peripheral step 25 as a boundary. +It is recessed on the side of the mold drain region 11. The fourth surface 40d of the front surface of the semiconductor substrate 40 extends from the outer peripheral step 25 to the scribe region 3 and reaches the chip edge. The fourth surface 40d of the front surface of the semiconductor substrate 40 may be gently sloped so as to slightly increase or slightly decrease the thickness of the semiconductor substrate 40 toward the chip edge.

[0043] The portion 40e connecting the second surface 40b and the fourth surface 40d of the front surface of the semiconductor substrate 40 (hereinafter referred to as the fifth surface (third surface)) may be a vertical surface that is approximately perpendicular to the fourth surface 40d of the front surface of the semiconductor substrate 40, or it may be a tapered inclined surface that forms an obtuse angle. Specifically, the inclination angle of the fifth surface 40e with respect to the extension line of the second surface 40b of the front surface of the semiconductor substrate 40 (hereinafter simply referred to as the inclination angle of the fifth surface 40e (inclination angle of the outer peripheral step 25)) is preferably, for example, 45 degrees or more and 90 degrees or less. This facilitates the formation of the outer peripheral step 25 of the front surface of the semiconductor substrate 40. The inclination angle of the fifth surface 40e on the front surface of the semiconductor substrate 40 is the angle remaining after subtracting the angle θ1 that the fifth surface 40e on the front surface of the semiconductor substrate 40 makes with the fourth surface 40d on the front surface of the semiconductor substrate 40 from the horizontal plane (=180 degrees).

[0044] The outer peripheral step 25 on the front surface of the semiconductor substrate 40 (i.e., the fourth surface 40d and the fifth surface 40e) is formed on the channel stopper region 32, described later, in the outer peripheral area including the scribe region 3, and is located outside the inner peripheral edge of the channel stopper region 32. The fifth surface 40e on the front surface of the semiconductor substrate 40 may be formed in the scribe region 3. By forming the outer peripheral step 25 on the front surface of the semiconductor substrate 40 in the outer peripheral area including the scribe region 3 of the semiconductor substrate 40, the chip area (surface area of ​​the semiconductor substrate 40) does not increase, and the operation of the semiconductor device 10 and the function of the breakdown structure 30 are not adversely affected by the outer peripheral step 25. The height difference (thickness difference of the semiconductor substrate 40) t1 between the second surface 40b and the fourth surface 40d due to the outer peripheral step 25 on the front surface of the semiconductor substrate 40 is, for example, about 0.5 μm to 5.0 μm.

[0045] The outer peripheral step 25 on the front surface of the semiconductor substrate 40 is formed either after the formation of the boundary step 24 on the front surface of the semiconductor substrate 40 (i.e., after removing the edge termination region 2 of the epitaxial layer 43 to expose the epitaxial layer 42 which becomes the second surface 40b of the front surface of the semiconductor substrate 40), or before or after the formation of the channel stopper region 32 (i.e., before selective ion implantation of the exposed surface of the epitaxial layer 42 to form the channel stopper region 32). The outer peripheral step 25 on the front surface of the semiconductor substrate 40 may be formed simultaneously with the trench 16, which will be described later.

[0046] A boundary step 24 does not need to be formed on the surface of the semiconductor substrate 40 (see Figure 3). A case in which a boundary step 24 is not formed on the surface of the semiconductor substrate 40 is, for example, when the outermost layer of the semiconductor substrate 40 is n-type or n - When an epitaxial layer 43 of type n is epitaxially grown, or when the semiconductor substrate 40 is n - This is the case when a bulk substrate of the type is used. If no boundary step 24 is formed on the front surface of the semiconductor substrate 40, the second surface 40b and the third surface 40c are not formed on the front surface of the semiconductor substrate 40, the first surface 40a extends from the active region 1 to the channel stopper region 32 described later, and is connected to the fourth surface 40d by the fifth surface 40e.

[0047] In the central part 1a of the active region 1, on the first surface 40a side of the front surface of the semiconductor substrate 40, there are p-type base regions 13 and n + Type source area 14, p ++ A trench gate structure is provided, consisting of a type contact region 15, a trench 16, a gate insulating film 17, and a gate electrode 18. - The drift region 12 is n - The epitaxial layer 42 of type 1,2p, which will be described later. + This is the portion excluding the n-type regions 21, 22, the n-type current diffusion region (not shown), the FLR 31, and the channel stopper region 32, and these regions and n + These regions are provided between the mold starting substrate 41 and the active region 1, extending from the active region 1 to the edge termination region 2, in contact with these regions.

[0048] The p-type base region 13 is the n of the p-type epitaxial layer 43. + Type source region 14 and p ++ This is the portion excluding the type contact region 15. The p-type base region 13 is the first surface 40a and n of the front surface of the semiconductor substrate 40. - It is provided throughout the entire area between the type drift region 12. + Type source region 14 and p ++ The contact region 15 is a diffusion region selectively formed inside the epitaxial layer 43 by ion implantation. + Type source region 14 and p ++ Each type contact region 15 is selectively provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base region 13, in contact with the p-type base region 13.

[0049] n + Type source region 14 and p ++ The type contact region 15 is in contact with the source electrode 20 on the first surface 40a of the front surface of the semiconductor substrate 40. ++ The type contact area 15 does not need to be provided. In this case, p ++ Instead of the type contact region 15, the p-type base region 13 reaches the first surface 40a of the front surface of the semiconductor substrate 40. The outermost surface layer of the semiconductor substrate 40 is n-type or n - When an epitaxial layer 43 of type n is epitaxially grown, or when the semiconductor substrate 40 is n - When a bulk substrate of a certain type is used, the p-type base region 13 is selectively formed inside the epitaxial layer 43 by ion implantation.

[0050] n - Between the p-type drift region 12 and the p-type base region 13, n is greater than the bottom surface of the trench 16. + Deep within the drain region 11, p + Type regions 21, 22 and n-type current diffusion regions may be provided. + The type regions 21 and 22 have the function of mitigating the electric field applied to the bottom surface of the trench 16. +The mold region 21 is provided separately from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. + The type region 21 is fixed at the potential of the source electrode 20 in a part not shown in the figure. + Type region 21 is, for example, p + It is selectively formed on the epitaxial layer 42 (42a) at the same time as the lower part of the mold region 22.

[0051] p + The type region 22 has p between adjacent trenches 16. + It is provided separately from the mold region 21 and the trench 16, and is in contact with the p-type base region 13. + Type region 22 is, for example, n - n is in the drift region 12. - Each time an epitaxial layer 42(42a,42b) of type p is epitaxially grown, p-type impurities are ion-implanted into epitaxial layers 42a and 42b, respectively. + The type region 22 is p selectively formed in epitaxial layers 42a and 42b, respectively. + type domains (p + The lower and upper parts of the type region 22 are connected to each other.

[0052] The n-type current spreading region is a so-called current spreading layer that reduces the carrier spreading resistance. The n-type current spreading region consists of adjacent p + It is provided between type regions 21 and 22, and these regions, p-type base region 13 and n - It is in contact with the n-type drift region 12. The n-type current diffusion region is connected to the p-type base region 13 and p + The distance between the n-type region 21 and the trench 16 is reached. If an n-type current diffusion region is not provided, n - Type drift regions 12 are adjacent to each other p + Between type regions 21 and 22, the p-type base region 13 and p + It extends between the mold region 21 and the trench 16.

[0053] The trench 16 extends in the depth direction from the first surface 40a of the front surface of the semiconductor substrate 40 to the depth direction n+ The source region 14 and the base region 13 of type p penetrate through, n - It terminates within the type drift region 12 (or the n-type current diffusion region if an n-type current diffusion region is provided), or p + It terminates inside the mold region 21. Inside the trench 16, a gate electrode 18 is provided via a gate insulating film 17. The interlayer insulating film 19 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 18. The interlayer insulating film 19 is, for example, a silicon oxide (SiO2) film such as BPSG (Boro Phospho Silicate Glass).

[0054] The source electrode 20 is provided on the interlayer insulating film 19 over substantially the entire central portion 1a of the active region 1. The source electrode 20 is connected to the interlayer insulating film 19 via a contact hole. + Type source region 14 and p ++ The source electrode 20 makes ohmic contact with the p-type contact region 15 and is electrically connected to these regions and the p-type base region 13. The source electrode 20 may extend outward (towards the chip edge) on the interlayer insulating film 19 and terminate at the outer periphery 1b of the active region 1. The drain electrode 26 is on the back surface (n) of the semiconductor substrate 40. + Provided on the entire surface of the back surface of the mold starting substrate 41, n + Type drain region 11(n + It is electrically connected to the starting substrate 41).

[0055] In the outer peripheral portion 1b of the active region 1, the first surface 40a of the front surface of the semiconductor substrate 40 and n - A p-type outer region is provided throughout the entire area between the type drift region 12 and the other region. The p-type outer region is n - From the drift region 12 side, p + Outer peripheral region 22a, p-type base extension portion 13a and p ++ The outer peripheral contact regions 15a are stacked sequentially, and surround the central part 1a of the active region 1 in a roughly rectangular shape. + Outer periphery regions 22a and p ++ The outer peripheral contact region 15a of the type is p + Type region 22 and p ++It is formed simultaneously with the type contact region 15. The p-type base extension 13a is the outer periphery of the p-type base region 13.

[0056] p + Outer peripheral region 22a, p-type base extension portion 13a and p ++ The outer peripheral contact region 15a of the mold is p (part not shown). ++ Outer peripheral contact area 15a(p ++ If the outer peripheral contact area 15a is not provided, it is electrically connected to the source electrode 20 via the p-type base extension portion 13a). + Outer peripheral region 22a, p-type base extension portion 13a and p ++ The outer peripheral contact region 15a of the mold reaches the third surface 40c of the front surface of the semiconductor substrate 40. + The outer periphery region 22a extends outward from the boundary step 24 along the third surface 40c of the front surface of the semiconductor substrate 40, and reaches the second surface 40b of the front surface of the semiconductor substrate 40.

[0057] In the edge termination region 2, the second surface 40b (first surface 40a if no boundary step 24 is formed) of the front surface of the semiconductor substrate 40 and n - Between the drift region 12 and the pressure-resistant structure 30, p + A type region 31 (hatched dot area) is selectively provided. The breakdown structure 30 may be a multizone JTE structure, a spatially modulated JTE structure, or an FLR structure, which are mainly used when the semiconductor substrate 40 is made of SiC (Figure 2 shows an FLR structure). The multizone JTE structure is a structure in which three or more p-type regions fixed to the potential of the source electrode 20 are arranged concentrically adjacent to the active region, such that the p-type regions with lower impurity concentrations are located further away from the active region.

[0058] The spatially modulated JTE structure is an improved JTE structure in which a p-type spatially modulated region is placed between two adjacent p-type regions, adjacent to these two p-type regions, and having an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between the two p-type regions, thereby gradually decreasing the impurity concentration distribution of the entire JTE structure outward. The spatially modulated region is formed by repeatedly arranging two p-type sub-regions with approximately the same impurity concentration as the p-type regions adjacent to each of its sides in a predetermined pattern, concentrically surrounding the active region 1. The FLR structure consists of multiple p-type regions with the same impurity concentration and floating potential. + This structure, also known as a guard ring structure, consists of type regions 31 (FLR) arranged concentrically and spaced apart from each other, surrounding the active region 1.

[0059] In the edge termination region 2, the fourth surface 40d and the fifth surface 40e of the front surface of the semiconductor substrate 40 and n - A channel stopper region 32 (hatched area) is provided along the fourth surface 40d and fifth surface 40e of the front surface of the semiconductor substrate 40, encompassing the entire area between the type drift region 12. The channel stopper region 32 is provided outside the breakdown structure 30, separate from the breakdown structure 30, and surrounds the breakdown structure 30. The channel stopper region 32 is, for example, n + n formed simultaneously with the type source region 14 + It could be a type domain, or for example, p + p formed simultaneously with type regions 21 and 22 + It may also be a type domain (not shown).

[0060] The channel stopper region 32 is n - It is surrounded by a type drift region 12. The channel stopper region 32 and the outermost p + Between the type region 31, n -The type drift region 12 reaches the front surface of the semiconductor substrate 40. The channel stopper region 32 is exposed on the fourth surface 40d, the fifth surface 40e of the front surface of the semiconductor substrate 40, and the chip end portion. The channel stopper region 32 extends inward along the fourth surface 40d and the fifth surface 40e along the front surface of the semiconductor substrate 40 and along the outer peripheral step 25, and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40 (when the boundary step 24 is not formed, it is the first surface 40a).

[0061] The inner peripheral end of the channel stopper region 32 is preferably located at substantially the same depth as the p-type regions (p-type regions 21, 22, p + type outer peripheral region 22a) that form the main junction (pn junction) of the active region 1 and the p + type region 31 that constitutes the breakdown voltage structure 30. The channel stopper region 32 suppresses the depletion layer spreading from the pn junction by the p-type region 31 of the main junction of the active region 1 and the breakdown voltage structure 30 from reaching the chip end portion during the off state of the semiconductor device 10, and has a function of suppressing the electric field concentration on the outer peripheral step 25 of the front surface of the semiconductor substrate 40. A field plate or a channel stopper electrode is not provided, and the channel stopper region 32 has a floating potential. + type region 31. +

[0062] The width w11 by which the channel stopper region 32 extends inward from the outer peripheral step 25 of the front surface of the semiconductor substrate 40 is, for example, about 10 μm. The width w12 (the width in the lateral direction from the chip center side to the chip end portion) by which the channel stopper region 32 faces the fifth surface 40e of the front surface of the semiconductor substrate 40 in the longitudinal direction (the direction orthogonal to the lateral direction from the chip center side to the chip end portion) varies depending on the inclination angle of the fifth surface 40e. The width w13 by which the channel stopper region 32 faces the fourth surface 40d of the front surface of the semiconductor substrate 40 in the longitudinal direction is equal to the width of the fourth surface 40d of the front surface of the semiconductor substrate 40, and is, for example, 40 μm or more and about 50 μm.

[0063] ​The entire surface of the first to fifth surfaces 40a to 40e of the front surface of the semiconductor substrate 40 in the outer peripheral region 1b and edge termination region 2 of the active region 1 is covered with an insulating layer 33. The insulating layer 33 may be a single-layer structure of interlayer insulating film 19 (Figure 2), or a laminated structure of field oxide film, gate insulating film 17, and interlayer insulating film 19 (not shown). The thickness t11 of the insulating layer 33 is substantially constant across the entire front surface of the semiconductor substrate 40. For this reason, steps with substantially the same height difference as the steps 24 and 25 are formed on the upper surface of the insulating layer 33, on the parts above the steps 24 and 25 on the front surface of the semiconductor substrate 40.

[0064] In other words, the first to fifth surfaces 40a to 40e of the front surface of the semiconductor substrate 40 and the first to fifth upper surfaces 33a to 33e of the insulating layer 33 on these first to fifth surfaces 40a to 40e are approximately parallel to each other. The inclination angle of the fifth upper surface 33e with respect to the extension of the second upper surface 33b of the insulating layer 33 (hereinafter simply referred to as the inclination angle of the fifth upper surface 33e) is approximately the same as the inclination angle of the fifth surface 40e of the front surface of the semiconductor substrate 40 (= 180 degrees - θ1). The inclination angle of the fifth upper surface 33e of the insulating layer 33 is the angle remaining after subtracting the angle θ2 that the fifth upper surface 33e of the insulating layer 33 makes with the fourth upper surface 33d of the insulating layer 33 from the horizontal plane (180 degrees) (= 180 degrees - θ2).

[0065] A surface protective film 34 made of polyimide is provided on the outermost surface of the front surface of the semiconductor substrate 40. The entire surface of the front surface of the semiconductor substrate 40, excluding the electrode pads and the scribe region 3, is covered by the surface protective film 34. In the scribe region 3, the outermost surface of the front surface of the semiconductor substrate 40 is an insulating layer 33. The portion of the source electrode 20 exposed to the opening 35 of the surface protective film 34 functions as a source pad (electrode pad). The surface protective film 34 is provided on the insulating layer 33 in the outer peripheral portion 1b and the edge termination region 2 of the active region 1, and covers the steps 24 and 25 on the front surface of the semiconductor substrate 40 via the insulating layer 33.

[0066] On the upper surface of the surface protective film 34, steps with different height differences from the steps 24 and 25 on the front surface of the semiconductor substrate 40 are formed on the portions of the steps 24 and 25, respectively. The first surfaces 40a, 2 surfaces 40b, and 4 surfaces 40d of the front surface of the semiconductor substrate 40 and the first upper surfaces 34a, 2 upper surfaces 34b, and 4 upper surfaces 34d of the surface protective film 34 on these first surfaces 40a, 2 surfaces 40b, and 4 surfaces 40d are all approximately parallel. The surface protective film 34 has a constant thickness t12 of, for example, about 10 μm on the portions of the first surfaces 40a and 2 surfaces 40b of the front surface of the semiconductor substrate 40, and the thickness t12 changes according to the inclination angle in the portions where the upper surface is inclined (the third upper surface 34c, the fifth upper surface 34e, and the outer end surface 34f described later).

[0067] The third upper surface 34c of the surface protective film 34, which connects the first upper surface 34a and the second upper surface 34b, is located on the third surface 40c of the front surface of the semiconductor substrate 40. The inclination angle of the third upper surface 34c with respect to the extension of the first upper surface 34a of the surface protective film 34 is slightly smaller and gentler than the inclination angle of the third surface 40c of the front surface of the semiconductor substrate 40. The fifth upper surface 34e of the surface protective film 34, which connects the second upper surface 34b and the fourth upper surface 34d, is located on the fifth surface 40e of the front surface of the semiconductor substrate 40. The inclination angle of the fifth upper surface 34e with respect to the extension of the second upper surface 34b of the surface protective film 34 (hereinafter simply referred to as the inclination angle of the fifth upper surface 34e) is slightly smaller and gentler than the inclination angle of the fifth surface 40e of the front surface of the semiconductor substrate 40. The inclination angle of the fifth upper surface 34e of the surface protective film 34 is the remaining angle (= 180 degrees - θ3) obtained by subtracting the angle θ3 that the fifth upper surface 34e of the surface protective film 34 makes with respect to the horizontal plane from the fourth upper surface 34d of the surface protective film 34.

[0068] The second upper surface 34b of the surface protective film 34 is inclined even if the fifth surface 40e of the front surface of the semiconductor substrate 40 is substantially vertical. The outer edge of the surface protective film 34 terminates at the inner edge of the scribe region 3 and does not reach the chip edge. This is because the portion of the surface protective film 34 that covers the scribe line 50b of the semiconductor wafer 50 is removed before dicing the semiconductor wafer (cutting individual semiconductor chips (semiconductor substrates 40) from the semiconductor wafer 50). This prevents the scattering of processing debris (polyimide) of the surface protective film 34 by dicing blades, etc., during semiconductor wafer dicing. Furthermore, since it does not have a protective metal film that extends to the chip edge of the semiconductor substrate 40 as shown in Figure 7 of the above-mentioned Patent Document 1, metal debris is not scattered by dicing blades, etc., during semiconductor wafer dicing.

[0069] The outer end surface (side surface) 34f connecting the outer peripheral edge of the surface protective film 34 to the fourth upper surface 34d is a tapered inclined surface that forms an obtuse angle with respect to the fourth upper surface 33d of the insulating layer 33. The inclination angle of the outer end surface 34f with respect to the extension of the fourth upper surface 34d of the surface protective film 34 (hereinafter simply referred to as the inclination angle of the outer end surface 34f) may be greater and steeper than the inclination angle of the fifth surface 40e of the front surface of the semiconductor substrate 40. The inclination angle of the outer end surface 34f of the surface protective film 34 is the angle remaining after subtracting the angle θ4 that the outer end surface 34f of the surface protective film 34 makes with respect to the horizontal plane (= 180 degrees - θ4).

[0070] In other words, the surface protective film 34 covers the withstand voltage structure 30 and the outer peripheral step 25 on the front surface of the semiconductor substrate 40 via the insulating layer 33. The surface protective film 34 covers the channel stopper region 32 via the insulating layer 33 in the portion excluding the scribe region 3. The surface protective film 34 is relatively n by the outer peripheral step 25 on the front surface of the semiconductor substrate 40. +On the side of the trench drain region 11, there are tapered inclined surfaces (specifically, the fifth upper surface 34e and the outer end surface 34f) that are inclined at an inclination angle of less than 90 degrees with respect to the first upper surface 34a and the second upper surface 34b, facing in the depth direction to the recessed portions (the fourth surface 40d and the fifth surface 40e of the front surface of the semiconductor substrate 40).

[0071] The outer peripheral end of the surface protection film 34 is located on the fourth surface 40e (n + the recessed portion on the side of the trench drain region 11) of the front surface of the semiconductor substrate 40, so that even if moisture (water vapor) in the air flows in from the outer peripheral end of the surface protection film 34 and flows toward the center of the chip along the interface between the surface protection film 34 and the insulating layer 33, the intrusion of moisture from the outer peripheral step 25 on the front surface of the semiconductor substrate 40 to the inside can be suppressed. Therefore, the moisture resistance of the semiconductor device 10 can be improved. By locally removing the surface layer of the front surface of the semiconductor substrate 40, the outer peripheral step 25 can be easily formed on the front surface of the semiconductor substrate 40, so that an increase in cost can be suppressed.

[0072] The manufacturing method of the semiconductor device 10 according to Embodiment 1 will be described. FIGS. 4 to 7 are cross-sectional views showing the states during the manufacture of the semiconductor device according to Embodiment 1. FIGS. 4 to 7 show only the outer peripheral portion 1b of the active region 1 and the edge termination region 2 (see FIG. 2) of one chip region 50a, and the central portion 1a of the active region 1 will be described with reference to FIG. 2. The chip region 50a is a region that is cut out from the semiconductor wafer 50 along the scribe line 50b by a dicing blade or the like and becomes a semiconductor chip (semiconductor substrate 40).

[0073] First, as shown in FIG. 4, an n + type starting substrate 41, an n + type starting wafer 51, an n - type drift region 12, an n - type epitaxial layer 42a is epitaxially grown. Next, by photolithography and ion implantation of p-type impurities, using the same ion implantation mask, for example, p + type regions 21, p +Lower part of type region 22, p + Lower part 52 of the outer peripheral region 22a of the mold, and p of the pressure-resistant structure 30 + Type region 31 and are selectively formed.

[0074] Next, as shown in Figure 5, further n - By epitaxially growing a p-type epitaxial layer 42b to increase its thickness, an epitaxial layer 42 (42a, 42b) with the thickness of the product (semiconductor device 10) is formed. Next, by photolithography and ion implantation of p-type impurities, p-type impurities are implanted into the epitaxial layer 42b. + Upper part of type region 22 and p + The upper part 53 of the outer periphery region 22a of the mold is formed, and each is p in the depth direction. + Lower part of type region 22 and p + It is connected to the lower part 52 of the outer periphery region 22a of the mold.

[0075] At this time, by not performing ion implantation in the epitaxial layer 42b in the edge termination region 2, n - n remains as the drift region 12. - In the epitaxial layer 42b of type P, all p + The type region 31 may be covered. Alternatively, p + Upper part of type region 22 and p + Simultaneously with the formation of the upper part 53 of the outer peripheral region 22a, p-type impurities are selectively ion-implanted into the epitaxial layer 42b in the edge terminal region 2, + The thickness of the mold region 31 may be increased (not shown).

[0076] Next, a p-type epitaxial layer 43, which will become the p-type base region 13, is epitaxially grown on the surface of the epitaxial layer 42. + n - A semiconductor wafer 50 is completed by sequentially epitaxially growing each epitaxial layer 42, 43, which will become the p-type drift region 12 and the p-type base region 13, respectively.

[0077] n -n is in the drift region 12. - Each time the type epitaxial layers 42a and 42b are epitaxially grown, the lower and upper parts of the n-type current diffusion region may be formed over the entire active region 1 by photolithography and ion implantation of n-type impurities, so as to be connected in the depth direction to the epitaxial layers 42a and 42b, respectively.

[0078] Next, as shown in Figure 6, the edge termination region 2 of the epitaxial layer 43 is removed by photolithography and etching, leaving the p-type epitaxial layer 43 only in the active region 1. This makes the outer peripheral portion (second surface 40b) of the chip region 50a on the front surface of the semiconductor wafer 50 more prominent than the central portion (first surface 40a) of the chip region 50a. + A lowered (recessed) boundary step 24 is formed on the mold starting wafer 51 side.

[0079] In the edge termination region 2 of each chip region 50a of the semiconductor wafer 50, on the front surface (second surface 40b) of the semiconductor wafer 50, n - The epitaxial layer 42b of the type is exposed. Each chip region 50a of the semiconductor wafer 50 is surrounded by scribe lines 50b. For example, in the semiconductor wafer 50, multiple chip regions 50a are arranged in a matrix, and scribe lines 50b are formed in a grid pattern surrounding all chip regions 50a.

[0080] Next, as shown in Figure 7, the surface layer of the epitaxial layer 42 at the scribe line 50b of the semiconductor wafer 50 is removed by photolithography and etching to form a grid-like recess 54 surrounding the chip region 50a. At this time, by making the width of the recess 54 wider than the width of the scribe line 50b, the surface layer of the epitaxial layer 42 at the outer periphery of each chip region 50a is also removed.

[0081] As a result, in each chip region 50a of the semiconductor wafer 50, the outer edge of the chip region 50a (fourth surface 40d) is more pronounced than the central part of the chip region 50a (second surface 40b) on the front surface of the semiconductor wafer 50. + A lowered (recessed) outer peripheral step 25 is formed on the mold starting wafer 51 side. The entire area of ​​the scribe line 50b is also the same as the outer periphery of the chip region 50a, and the front surface of the semiconductor wafer 50 is n + It becomes lower on the mold starting wafer 51 side.

[0082] Next, by photolithography and ion implantation, n is implanted in the surface region of the first surface 40a on the front surface of the semiconductor wafer 50 (the surface region of the p-type epitaxial layer 43). + Type source area 14, p ++ Type contact area 15 and p ++ The outer peripheral contact regions 15a of the mold are selectively formed. By photolithography and ion implantation, the surface regions (n) of the second surface 40b, fourth surface 40d, and fifth surface 40e of the front surface of the semiconductor wafer 50 are formed. - (Surface region of type epitaxial layer 42) + A channel stopper region 32 of a specific type is selectively formed.

[0083] The channel stopper region 32 is formed across adjacent chip regions 50a, or n + It may be formed simultaneously with the type source region 14. - P type epitaxial layer 42, + type region 21,22, p + Type outer peripheral region 22a, n-type current diffusion region, p + The portion excluding the type region 31 and the channel stopper region 32 is n - This becomes a type drift region 12. The n of the p-type epitaxial layer 43. + Type source area 14, p ++ Type contact area 15 and p ++ The portion excluding the outer peripheral contact region 15a of the type becomes the p-type base region 13.

[0084] Next, the ion-implanted impurities are activated by heat treatment. Then, the trench 16, gate insulating film 17, gate electrode 18, interlayer insulating film 19, source electrode 20, drain electrode 26, and surface protective film 34 are formed by a general method. Next, by photolithography and etching, an opening 35 that exposes the portion of the source electrode 20 that will become the electrode pad, and an opening 36 that exposes the outer periphery of the chip region 50a and the scribe line 50b are formed in the surface protective film 34.

[0085] Subsequently, the semiconductor wafer 50 is cut (diced) along the scribe lines 50b using a dicing blade or the like, separating each chip region 50a of the semiconductor wafer 50 into individual semiconductor chips (semiconductor substrate 40). The remaining portion of the scribe lines 50b of the semiconductor wafer 50 remains as a scribe region 3 around the entire outer circumference of the semiconductor substrate 40. The side walls of the openings 36 of the surface protective film 34 become the outer end faces 34f of the surface protective film 34. This completes the semiconductor device 10 shown in Figures 1-3.

[0086] As described above, according to Embodiment 1, an outer peripheral step is formed on the front surface of the semiconductor substrate (semiconductor chip) in the outer peripheral portion including the scribe line remaining along the outer periphery of the semiconductor substrate. The surface protective film on the outermost surface of the front surface of the semiconductor substrate covers the outer peripheral step on the front surface of the semiconductor substrate, and the fourth surface of the front surface of the semiconductor substrate (relatively due to the outer peripheral step) + It terminates on the recessed portion on the drain region side. As a result, even if moisture (water vapor) flows in from the outer edge of the surface protective film and flows towards the center of the chip along the interface between the surface protective film and the insulating layer beneath it, it is difficult for it to flow towards the center of the chip from the outer edge step on the front surface of the semiconductor substrate. Therefore, the moisture resistance of the semiconductor device can be improved, and the reliability of the semiconductor device can be improved.

[0087] Furthermore, according to Embodiment 1, the peripheral step on the front surface of the semiconductor substrate (a structure for improving moisture resistance) is a simple structure and can be easily formed by etching or the like. In addition, the etching process for forming the peripheral step on the front surface of the semiconductor substrate can be easily added to existing semiconductor device manufacturing methods, and the manufacturing process does not become complicated. Therefore, an increase in manufacturing costs can be suppressed. Moreover, since the peripheral step on the front surface of the semiconductor substrate is formed on the outer periphery including the scribe line, an increase in chip area can be suppressed, and an increase in product cost can be suppressed. Therefore, a semiconductor device with improved moisture resistance can be easily manufactured while maintaining the chip area and suppressing an increase in cost.

[0088] (Details of Embodiment 2) The semiconductor device according to Embodiment 2, which solves the above-mentioned problems, will be described below. Figure 8 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. The difference between the semiconductor device 60 according to Embodiment 2 and the semiconductor device 10 according to Embodiment 1 (see Figure 3) is that the outer peripheral step 61 formed on the channel stopper region 32 on the front surface of the semiconductor substrate 40 has an inverse taper shape.

[0089] In Embodiment 2, the front surface of the semiconductor substrate 40 is divided by the outer peripheral step 61, with the fourth surface 40d on the chip edge side being more symmetrical than the second surface 40b on the chip center side (the first surface 40a if the boundary step 24 is not formed). + It is recessed on the drain region 11 side. The fifth surface (third surface) 40f, which connects the second surface 40b and the fourth surface 40d of the front surface of the semiconductor substrate 40, is an inclined surface with an inverse taper shape that forms an acute angle with respect to the fourth surface 40d of the front surface of the semiconductor substrate 40.

[0090] The second surface 40b of the front surface of the semiconductor substrate 40 protrudes toward the chip edge side beyond the boundary between the fifth surface 40f and the fourth surface 40d of the front surface of the semiconductor substrate 40. The angle θ11 that the fifth surface 40f of the front surface of the semiconductor substrate 40 makes with the fourth surface 40d of the front surface of the semiconductor substrate 40 is the inclination angle of the fifth surface 40f with respect to the fourth surface 40d of the front surface of the semiconductor substrate 40 (the inclination angle of the outer peripheral step 61), and is, for example, 45 degrees or more and less than 90 degrees.

[0091] The reverse-tapered outer periphery step 61 can be formed, for example, in the manufacturing method of the semiconductor device 10 according to the above-described embodiment 1, by using an anisotropic etching method that can form a recess with a substantially rectangular cross-sectional shape, which is used to form a recess (corresponding to the recess 54 formed on the outer periphery of the chip region 50a and the scribe line 50b of the semiconductor wafer 50 in Figure 6) formed by removing the surface layer of the epitaxial layer 42 in the outer periphery including the scribe region 3 of the semiconductor substrate 40.

[0092] By appropriately setting the conditions for the anisotropic etching, a recess having a reverse tapered sidewall (a recess with a trapezoidal cross-sectional shape that widens towards the depth) can be formed on the front surface of the semiconductor substrate 40. In this case, the angle θ11 that the fifth surface 40f of the front surface of the semiconductor substrate 40 makes with the fourth surface 40d of the front surface of the semiconductor substrate 40 can be less than 90 degrees and close to 90 degrees (for example, about 80 degrees or more).

[0093] The first to fifth surfaces 40a to 40f of the front surface of the semiconductor substrate 40 and the first to fifth upper surfaces 33a to 33f of the insulating layer 33 on these first to fifth surfaces 40a to 40f are substantially parallel to each other, as in Embodiment 1. The angle θ12 that the fifth upper surface 33f of the insulating layer 33 makes with the fourth upper surface 33d of the insulating layer 33 is substantially the same as the angle θ11 that the fifth surface 40f of the front surface of the semiconductor substrate 40 makes with the fourth surface 40d of the front surface of the semiconductor substrate 40.

[0094] The configuration of the outer peripheral step 61, other than its inverse taper shape, is the same as that of the outer peripheral step 25 in Embodiment 1. In the semiconductor device 60 according to Embodiment 2, the configuration of the outer peripheral step 61 on the front surface of the semiconductor substrate 40, other than its inverse taper shape on the fifth upper surface 33f of the insulating layer 33 thereon, is the same as that of Embodiment 1. If the height difference t1 between the second surface 40b and the fourth surface 40d on the front surface of the semiconductor substrate 40 is about 1 μm or less, the inclination angle of the fifth upper surface 34e of the surface protective film 34 will be the same as in Embodiment 1.

[0095] As described above, Embodiment 2 provides the same effects as Embodiment 1. Moisture that flows in from the outer edge of the surface protective film and flows towards the center of the chip along the interface between the surface protective film and the insulating layer stagnates within the inverse tapered outer step on the front surface of the semiconductor substrate and within the inverse tapered step on the upper surface of the insulating layer above the outer step, making it difficult for it to flow towards the center of the chip. This further enhances the effect of improving the moisture resistance of the semiconductor device.

[0096] (Details of Embodiment 3) The semiconductor device according to Embodiment 3, which solves the above-mentioned problems, is described below. Figure 9 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3. The difference between the semiconductor device 70 according to Embodiment 3 and the semiconductor device 10 according to Embodiment 1 (see Figure 3) is that the outer peripheral step 25 on the front surface of the semiconductor substrate 40 relatively n + A sub-trench (groove) 71 is formed in the recessed portion on the drain region 11 side.

[0097] In Embodiment 3, a sub-trench 71 is provided on the fourth surface 40d of the front surface of the semiconductor substrate 40, extending to a predetermined depth d1 from the fourth surface 40d. The sub-trench 71 surrounds the periphery of the pressure-resistant structure 30. The side wall of the sub-trench 71 on the chip center side may be continuous with the fifth surface 40e of the front surface of the semiconductor substrate 40, or it may be positioned away from the fifth surface 40e of the front surface of the semiconductor substrate 40, with the fourth surface 40d interposed between it and the fifth surface 40e.

[0098] The sub-trench 71 may have a cross-sectional shape, for example, an inverted triangular shape, with its side walls inclined so that the width narrows as it approaches the depth. In this case, the inclination angle of the side walls of the sub-trench 71 with respect to the fourth surface 40d of the front surface of the semiconductor substrate 40 may be approximately the same as the inclination angle of the fifth surface 40e of the front surface of the semiconductor substrate 40. The sub-trench 71 may reach the scribe region 3, or part or all of it may be located within the scribe region 3.

[0099] For example, during etching to form an outer peripheral step 25 on the front surface of the semiconductor substrate 40, the fourth surface 40d of the front surface of the semiconductor substrate 40 is etched slightly deeper near the boundary with the fifth surface 40e than on the chip edge side, which tends to create a depression. However, the depth of this depression is shallower than the depth d1 of the sub-trench 71. In Embodiment 3, the sub-trench 71 is formed by actively and selectively removing the fourth surface 40d of the front surface of the semiconductor substrate 40.

[0100] The depth d1 of the sub-trench 71 is such that the sub-trench 71 terminates within the channel stopper region 32, for example, about 0.1 μm to 1 μm. The sub-trench 71 can be formed, for example, in the manufacturing method of the semiconductor device 10 according to Embodiment 1 described above, either before or after the formation of the channel stopper region 32, after etching to form the outer peripheral step 25 on the front surface of the semiconductor substrate 40, for example, by etching.

[0101] The insulating layer 33 is provided along the inner wall of the sub-trench 71 on the fourth surface 40d of the front surface of the semiconductor substrate 40. It is preferable that a groove 72 corresponding to the depth d1 of the sub-trench 71 is formed on the fourth upper surface 33d of the insulating layer 33. The surface protective film 34 covers the sub-trench 71 via the insulating layer 33. If the depth d1 of the sub-trench 71 is about 1 μm or less, the inclination angle of the fifth upper surface 34e of the surface protective film 34 will be the same as in Embodiment 1.

[0102] As described above, Embodiment 3 provides the same effects as Embodiment 1. Moisture that flows in from the outer edge of the surface protective film and flows towards the center of the chip along the interface between the surface protective film and the insulating layer remains in the sub-trench of the outer edge step on the front surface of the semiconductor substrate and in the groove on the upper surface of the insulating layer on the sub-trench, making it difficult for it to flow towards the center of the chip. This further enhances the effect of improving the moisture resistance of the semiconductor device.

[0103] In summary, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. For example, instead of a MOSFET element structure, an IGBT or diode element structure may be formed in the central part of the active region. Also, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, this disclosure is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0104] As described above, the semiconductor device according to this disclosure is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for semiconductor devices made of wide-bandgap semiconductors. [Explanation of symbols]

[0105] 1 active area 1a Central part of the active region 1b Periphery of the active region 2 Edge Termination Region 3. Scribe area 10,60,70 Semiconductor devices 11 n + Type drain region 12 n - Type drift region 13 p-type base region 13a p type base extension 14 n + Type source area 15 p ++ Type Contact Area 15a p ++Outer peripheral contact area 16 Trench 17 Gate insulating film 18 Guard gate 19 Interlayer insulating film 20 source electrodes pp. 21, 22 + type area 22a p + Mold outer area 24. Boundary step on the surface of the semiconductor substrate 25,61 Outer edge step on the front surface of the semiconductor substrate 26 Drain electrode 30 Pressure-resistant structure 31 p + type area 32 Channel stopper area 33 Insulating layer 33a~33f Upper surface of the insulating layer 34 Surface protective film 34a~34e Top surface of the protective film 34f Outer edge of surface protective film 35. Openings of the surface protective film 40 Semiconductor substrates 40a~40f Front surface of semiconductor substrate 41 n + Mold starting substrate 42, 42a, 42b, 43 Epitaxial layer 50 semiconductor wafers 50a Chip area of ​​semiconductor wafer 50b Semiconductor wafer scribe line 51 n + Mold starting wafer 52 p + Lower part of the type domain 53 p + Top of the type region 54 Recesses on the front surface of a semiconductor wafer 71 Subtrench d1 Depth of sub-trench t1 Height difference due to the outer edge step on the front surface of the semiconductor substrate t11 Thickness of the insulating layer t12 Thickness of the surface protective film θ1, θ11: Angle formed by the front surfaces of the semiconductor substrate. θ2, θ12 Angle formed by the upper surfaces of the insulating layer θ3 Angle formed by the upper surface of the protective film θ4 Angle formed by the outer end face of the surface protective film

Claims

1. Semiconductor substrate, The active region through which the main current flows, The active region comprises a terminal region surrounding the active region, In the aforementioned terminal region, The scribe lines remaining on the outer circumference of the semiconductor substrate, An insulating layer covering the first main surface of the semiconductor substrate, The insulating layer comprises a surface protective film provided on the insulating layer, The first main surface has a step formed by recessing the first surface including the scribe line toward the second main surface of the semiconductor substrate toward the second main surface of the semiconductor substrate, which is inward from the first surface. The semiconductor device is characterized in that the surface protective film covers the step through the insulating layer.

2. Semiconductor substrate, The active region through which the main current flows, The active region comprises a terminal region surrounding the active region, In the aforementioned terminal region, A channel stopper region provided on the outer periphery of the semiconductor substrate, An insulating layer covering the first main surface of the semiconductor substrate, The insulating layer comprises a surface protective film provided on the insulating layer, The channel stopper region is provided along the first main surface, The first main surface has a step on the channel stopper region, where the first surface extending inward from the outer periphery of the semiconductor substrate by a predetermined width is recessed toward the second main surface of the semiconductor substrate than the second surface located inside the first surface. The semiconductor device is characterized in that the surface protective film covers the step through the insulating layer.

3. The semiconductor device according to claim 1 or 2, characterized in that the surface protective film is terminated on the first surface via the insulating layer, and has an inclined surface on the first surface that is inclined at a predetermined inclination angle with respect to the first surface.

4. The semiconductor device according to claim 1 or 2, characterized in that the first main surface has a tapered step in which the inclination angle of the third surface connecting the first surface and the second surface is 45 degrees or more and 90 degrees or less with respect to the second surface.

5. The semiconductor device according to claim 1 or 2, characterized in that the first main surface has the step in the shape of an inverted taper, wherein the inclination angle of the third surface connecting the first surface and the second surface is 45 degrees or more and 90 degrees or less with respect to the first surface.

6. The first surface has a sub-trench, The semiconductor device according to claim 1 or 2, characterized in that the insulating layer is provided along the inner wall of the sub-trench.

7. The semiconductor device according to claim 6, characterized in that the depth of the sub-trench is 0.1 μm or more and 1 μm or less.

8. The semiconductor device according to claim 1, characterized in that a channel stopper region is provided on the outer periphery of the semiconductor substrate along the step.

9. The semiconductor device according to claim 2 or 8, wherein the channel stopper region is provided along the first surface and extends inward from the first surface along the step to reach the second surface.

10. The semiconductor device according to claim 1 or 2, characterized in that the surface protective film is made of polyimide.

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