Semiconductor device and power conversion device

Abstract

A semiconductor device of the present application includes a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The second main surface has a cell region and a peripheral region between the cell region and a peripheral edge of the second main surface when viewed in plan. The silicon carbide substrate has a termination structure and a channel stopper ring formed in the second main surface in the peripheral region. The channel stopper ring is located outward of the termination structure when viewed in plan. The silicon carbide substrate and the channel stopper ring have a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface in the peripheral region so as to overlap the termination structure when viewed in plan and at least partially overlap the channel stopper ring when viewed in plan.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and power conversion devices. Background Technology

[0002] Japanese Patent Application Publication No. 2023-85505 discloses a semiconductor device. The semiconductor device disclosed in Japanese Patent Application Publication No. 2023-85505 has a frame wiring formed of aluminum, which, when viewed from above, has a terminal structure located on the outer side that ensures the voltage withstand capability of the active cells. Furthermore, in the semiconductor device disclosed in Japanese Patent Application Publication No. 2023-85505, the insulating film does not reach the outer periphery of the silicon carbide substrate when viewed from above, and the passivation film is in contact with the silicon carbide substrate.

[0003] In the semiconductor device described in Japanese Patent Application Publication No. 2023-85505, there is a concern about the reduction in reliability, and more specifically, the reduction in THB (Thermal Humidity Bias) tolerance caused by silicon carbide products generated from aluminum contained in the frame wiring and silicon carbide contained in the silicon carbide substrate. Summary of the Invention

[0004] This disclosure provides a semiconductor device for improving THB tolerance.

[0005] The semiconductor device disclosed herein includes a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The second main surface, when viewed from above, has a cell region and an outer peripheral region located between the cell region and the outer periphery of the second main surface. The silicon carbide substrate has a termination structure and a channel cut-off ring formed within the silicon carbide substrate on the second main surface located in the outer peripheral region. The channel cut-off ring, when viewed from above, is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel cut-off ring are both a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region in a manner that overlaps with the termination structure when viewed from above and at least partially overlaps with the channel cut-off ring when viewed from above. The insulating film is formed on the second main surface to cover the field oxide film. The wiring layer is formed on the insulating film in a manner that, when viewed from above, is located inside the termination structure.

[0006] The above and other objects, features, aspects and advantages of the invention will become clear from the following detailed description of the invention as understood in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a top view of the semiconductor device 100.

[0008] Figure 2 yes Figure 1 The sectional view at point II-II.

[0009] Figure 3 yes Figure 1 The sectional view at point III-III.

[0010] Figure 4 This is a manufacturing process diagram of semiconductor device 100.

[0011] Figure 5A This is the first cross-sectional view illustrating the process S2 for forming the impurity diffusion region.

[0012] Figure 5B This is the second cross-sectional view illustrating the process S2 for forming the impurity diffusion region.

[0013] Figure 6 This is a cross-sectional view illustrating the field oxide film formation process S3.

[0014] Figure 7 This is a cross-sectional view illustrating the gate insulating film formation process S4.

[0015] Figure 8A This is a first cross-sectional view illustrating the gate electrode formation process S5.

[0016] Figure 8B This is a second cross-sectional view illustrating the gate electrode formation process S5.

[0017] Figure 9A This is the first cross-sectional view illustrating the insulating film formation process S6.

[0018] Figure 9B This is a second cross-sectional view illustrating the insulating film formation process S6.

[0019] Figure 10A This is the first cross-sectional view illustrating the wiring layer formation process S7.

[0020] Figure 10B This is a second sectional view illustrating the wiring layer formation process S7.

[0021] Figure 11 This is a cross-sectional view illustrating the passivation film formation process S8.

[0022] Figure 12A This is the first cross-sectional view illustrating the process S9 for forming the impurity diffusion region.

[0023] Figure 12B This is the second cross-sectional view illustrating the process S9 for forming the impurity diffusion region.

[0024] Figure 13A This is the first cross-sectional view illustrating the drain electrode formation process S10.

[0025] Figure 13B This is a second cross-sectional view illustrating the drain electrode formation process S10.

[0026] Figure 14 This is a cross-sectional view of semiconductor device 100A.

[0027] Figure 15 This is a table representing the results of the THB tolerance test.

[0028] Figure 16 This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 1.

[0029] Figure 17A This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 2.

[0030] Figure 17B This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 3.

[0031] Figure 18 This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 4.

[0032] Figure 19 This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 5.

[0033] Figure 20 This is an enlarged top view of the semiconductor device 100 involved in Modified Example 6.

[0034] Figure 21 This is an enlarged top view of the semiconductor device 100 involved in Modified Example 7.

[0035] Figure 22 This is a block diagram showing the structure of the power conversion system of the power conversion device involved in Implementation Method 2. Detailed Implementation

[0036] The embodiments of this disclosure will be described in detail with reference to the accompanying drawings. In the following drawings, the same or equivalent parts are labeled with the same reference numerals, and the descriptions are not repeated.

[0037] Implementation Method 1

[0038] The semiconductor device according to Embodiment 1 will be described. The semiconductor device according to Embodiment 1 is defined as semiconductor device 100.

[0039] (Structure of semiconductor device 100)

[0040] The structure of the semiconductor device 100 will be described below.

[0041] Figure 1This is a top view of the semiconductor device 100. Figure 2 yes Figure 1 The sectional view at point II-II. Figure 3 yes Figure 1 The sectional view at point III-III. (See image.) Figures 1-3 As shown, the semiconductor device 100 includes a silicon carbide substrate 10, a field oxide film 20, a gate insulating film 30, a gate electrode 40, an insulating film 50, a wiring layer 60, a passivation film 70, a protective film 80, and a drain electrode 90.

[0042] The silicon carbide substrate 10 is formed from single-crystal silicon carbide. The silicon carbide substrate 10 has a main surface 10a and a main surface 10b. The main surfaces 10a and 10b form end faces in the thickness direction of the silicon carbide substrate 10. The main surface 10b is the opposite surface of the main surface 10a. When viewed from above, the main surface 10b has a unit area 10ba and a peripheral area 10bb. The peripheral area 10bb is the area located between the unit area 10ba and the outer periphery of the main surface 10b.

[0043] The silicon carbide substrate 10 has a base layer 11, an epitaxial layer 12, and a buffer layer 13. A main surface 10a is formed on the lower surface of the base layer 11. A main surface 10b is formed on the upper surface of the epitaxial layer 12. The epitaxial layer 12 is formed on the base layer 11 via the buffer layer 13. The conductivity type of the base layer 11, the epitaxial layer 12, and the buffer layer 13 is a first conductivity type. For example, the first conductivity type is n-type.

[0044] The silicon carbide substrate 10 has a drain region 14, a source region 15, and a body region 16. The drain region 14 is formed on a main surface 10a within the silicon carbide substrate 10 (base layer 11). The source region 15 is formed on a main surface 10b located in a cell region 10ba within the silicon carbide substrate 10 (epitaxy layer 12). The body region 16 is formed on the main surface 10b located in the cell region 10ba within the silicon carbide substrate 10 (epitaxy layer 12) surrounding the source region 15. The conductivity type of the drain region 14 and the source region 15 is a first conductivity type. The conductivity type of the body region 16 is a second conductivity type. The second conductivity type is, for example, p-type.

[0045] The silicon carbide substrate 10 also has a back gate region 17. The back gate region 17 is formed within the silicon carbide substrate 10 (epitaxial layer 12) on the main surface 10b of the cell region 10ba. When viewed from above, the back gate region 17 is located at the outer periphery of the cell region 10ba. The back gate region 17 is surrounded by the body region 16. The conductivity type of the back gate region 17 is the second conductivity type.

[0046] The silicon carbide substrate 10 also has a plurality of guard rings 18 and a channel stopper 19. The guard rings 18 are formed within the silicon carbide substrate 10 (epitaxial layer 12) on the main surface 10b located in the outer peripheral region 10bb. When viewed from above, the plurality of guard rings 18 are spaced apart along a direction from the inner periphery of the outer peripheral region 10bb toward the outer periphery of the outer peripheral region 10bb (the outer periphery of the main surface 10b). The guard rings 18 are formed in a ring shape when viewed from above. The conductivity type of the guard rings 18 is a second conductivity type. The plurality of guard rings 18 form a termination structure for maintaining the insulation withstand voltage of the semiconductor device 100. The channel stopper 19 is formed within the silicon carbide substrate 10 (epitaxial layer 12) on the main surface 10b located in the outer peripheral region 10bb. When viewed from above, the channel stopper 19 is located outside the termination structure (the plurality of guard rings 18) described above. The channel cutoff ring 19 has the first conductivity type. When viewed from above, the channel cutoff ring 19 forms a ring shape.

[0047] The field oxide film 20 is formed, for example, of silicon oxide that does not contain boron or phosphorus. The field oxide film 20 is formed on the main surface 10b. The inner and outer peripheries of the field oxide film 20 are located on the unit region 10ba and the outer periphery region 10bb, respectively. That is, the field oxide film 20 traverses the boundary between the unit region 10ba and the outer periphery region 10bb. When viewed from above, the field oxide film 20 overlaps with the aforementioned terminal structure (multiple guard rings 18). When viewed from above, the field oxide film 20 partially overlaps with the channel cutoff ring 19. Furthermore, an opening 20a is formed in the field oxide film 20. The opening 20a penetrates the field oxide film 20. When viewed from above, the opening 20a overlaps with the back gate region 17.

[0048] The gate insulating film 30 is formed, for example, of silicon oxide. The gate insulating film 30 is formed on the main surface 10b located between two adjacent source regions 15. The gate electrode 40 is formed, for example, of polycrystalline silicon. The gate electrode 40 is formed on the gate insulating film 30. Furthermore, the gate electrode 40 is also formed on the field oxide film 20. The drain region 14 and source region 15 respectively form the drain region and source region of the vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region 16 forms the body region of the vertical MOSFET. The epitaxial layer 12 forms the drift region of the vertical MOSFET.

[0049] An insulating film 50 is formed on the main surface 10b to cover the field oxide film 20, the gate insulating film 30, and the gate electrode 40. When viewed from above, the insulating film 50 extends to the outer periphery of the main surface 10b, covering the remaining portion of the channel cutoff ring 19 not covered by the field oxide film 20. The insulating film 50 may also have multiple layers. Figures 1-3 In the example shown, the insulating film 50 has a first layer 51 and a second layer 52 formed on the first layer 51. The first layer 51 is formed, for example, of BPSG (Boron Phosphorous Silicate Glass). The second layer 52 is formed, for example, of silicon oxide that does not contain boron or phosphorus. Alternatively, the uppermost layer of the plurality of layers of the insulating film 50 may be formed of a material that does not contain boron or phosphorus.

[0050] Contact holes 50a, 50b, and 50c are formed in the insulating film 50. Contact holes 50a, 50b, and 50c penetrate the insulating film 50. Contact hole 50a overlaps with the source region 15 when viewed from above. The source region 15 is exposed through contact hole 50a. Contact hole 50b overlaps with the opening 20a and the back gate region 17 when viewed from above. The back gate region 17 is exposed through contact hole 50b. Contact hole 50c overlaps with the gate electrode 40 located above the field oxide film 20 when viewed from above. The gate electrode 40 located above the field oxide film 20 is exposed through contact hole 50c.

[0051] The wiring layer 60 is formed, for example, of aluminum or an aluminum alloy. The wiring layer 60 is formed on the insulating film 50 located above the cell region 10ba. From another viewpoint, the wiring layer 60 does not have a portion formed outside the cell region 10ba when viewed from above. The wiring layer 60 has a gate wiring 61, a source electrode 62, and a gate pad 63. The gate wiring 61 is located above the outer periphery of the cell region 10ba when viewed from above. The source electrode 62 is surrounded by the gate wiring 61 when viewed from above. The gate pad 63 is surrounded by the gate wiring 61 and the source electrode 62 when viewed from above, and is connected to the gate wiring 61.

[0052] Although not shown, barrier metals are formed between the wiring layer 60 and the insulating film 50, between the wiring layer 60 and the silicon carbide substrate 10 (source region 15, back gate region 17), and between the wiring layer 60 and the gate electrode 40. The barrier metals are, for example, titanium nitride films, titanium films, or laminates thereof.

[0053] Gate wiring 61 is also formed within contact hole 50c. Thus, gate wiring 61 is electrically connected to gate electrode 40. Source electrode 62 is also formed within contact holes 50a and 50b. Thus, source electrode 62 is electrically connected to source region 15 and back gate region 17.

[0054] The passivation film 70 is formed, for example, of silicon nitride. The passivation film 70 is formed on the insulating film 50 in a manner that covers the wiring layer 60. When viewed from above, the outer periphery of the passivation film 70 is away from the outer periphery of the main surface 10b. That is, the insulating film 50 located at the outer periphery is exposed from the passivation film 70. An opening is formed in the passivation film 70 to expose the source electrode 62 and an opening to expose the gate pad 63.

[0055] The protective film 80 is formed, for example, of polyimide. The protective film 80 is formed on the insulating film 50 via the passivation film 70, covering the wiring layer 60. When viewed from above, the outer periphery of the protective film 80 is located further inward than the outer periphery of the passivation film 70. The outer periphery of the protective film 80 does not overlap with the steps of the insulating film 50. The protective film 80 has openings exposing the source electrode 62 and the gate pad 63. The drain electrode 90 is formed, for example, of titanium or titanium nitride. The drain electrode 90 is formed on the main surface 10a. The drain electrode 90 is electrically connected to the drain region 14.

[0056] (Method for manufacturing semiconductor device 100)

[0057] The manufacturing method of the semiconductor device 100 will be described below.

[0058] Figure 4 This is a manufacturing process diagram of semiconductor device 100. (Example) Figure 4 As shown, the manufacturing method of the semiconductor device 100 includes a preparation step S1, an impurity diffusion region formation step S2, a field oxide film formation step S3, a gate insulating film formation step S4, a gate electrode formation step S5, an insulating film formation step S6, a wiring layer formation step S7, a passivation film formation step S8, an impurity diffusion region formation step S9, a drain electrode formation step S10, a protective film formation step S11, and a monolithization step S12.

[0059] In the preparation process S1, a silicon carbide substrate 10 is prepared. Figure 5A This is the first cross-sectional view illustrating the process S2 for forming the impurity diffusion region. Figure 5B This is the second cross-sectional view illustrating process S2, which describes the formation of the impurity diffusion region. For example... Figure 5A as well as Figure 5B As shown, in the impurity diffusion region formation process S2, ion implantation is performed, for example, from the main surface 10b side, thereby forming the source region 15, the body region 16, the back gate region 17, the guard ring 18, and the channel cutoff ring 19.

[0060] Figure 6 This is a cross-sectional view illustrating the field oxide film formation process S3. (For example...) Figure 6As shown, in the field oxide film formation step S3, a field oxide film 20 is formed. In the field oxide film formation step S3, firstly, a TEOS (Tetra Ethylene Orthosilicate)-CVD (Chemical Vapor Deposition) method is performed, for example, to form a film of the constituent material of the field oxide film 20 on the main surface 10b. Secondly, a resist pattern is formed on the constituent material of the field oxide film 20. The resist pattern is formed by coating a photoresist and patterning the photoresist using photolithography. Thirdly, the constituent material of the field oxide film 20 is dry-etched through the openings of the resist pattern to pattern the constituent material of the field oxide film 20, thereby forming the field oxide film 20.

[0061] Figure 7 This is a cross-sectional view illustrating the gate insulating film formation process S4. (Example) Figure 7 As shown, for example, the main surface 10b is thermally oxidized to form a gate insulating film 30. Figure 8A This is a first cross-sectional view illustrating the gate electrode formation process S5. Figure 8B This is a second cross-sectional view illustrating the gate electrode formation process S5. (See attached image.) Figure 8A as well as Figure 8B As shown, in the gate electrode formation process S5, a gate electrode 40 is formed. In the gate electrode formation process S5, firstly, a CVD method is performed, for example, to form the constituent material of the gate electrode 40 on the field oxide film 20 and the gate insulating film 30. Secondly, a resist pattern is formed on the constituent material of the gate electrode 40. Thirdly, the constituent material of the gate electrode 40 is dry-etched through the openings of the resist pattern to pattern the constituent material of the gate electrode 40, thereby forming the gate electrode 40.

[0062] Figure 9A This is the first cross-sectional view illustrating the insulating film formation process S6. Figure 9B This is a second cross-sectional view illustrating the insulating film formation process S6. (For example...) Figure 9A as well as Figure 9B As shown, in the insulating film formation step S6, an insulating film 50 is formed. In the insulating film formation step S6, firstly, a first layer 51 is formed, for example, by a CVD method. Secondly, the first layer 51 is planarized by heat treatment to allow the constituent material (BPSG) of the first layer 51 to flow. Thirdly, a second layer 52 is formed, for example, by a TEOS-CVD method.

[0063] Figure 10A This is the first cross-sectional view illustrating the wiring layer formation process S7. Figure 10B This is a second cross-sectional view illustrating the wiring layer formation process S7. (For example...) Figure 10A as well as Figure 10BAs shown, in the wiring layer formation process S7, a wiring layer 60 is formed. In the wiring layer formation process S7, firstly, a resist pattern is formed on the insulating film 50, and secondly, the insulating film 50 is dry-etched through the openings of the resist pattern to form contact holes 50a, 50b, and 50c.

[0064] Third, for example, a barrier metal is formed on the insulating film 50, the inner wall surface of the contact hole 50a, the inner wall surface of the contact hole 50b, the inner wall surface of the contact hole 50c, the source region 15 exposed from the contact hole 50a, the back gate region 17 exposed from the contact hole 50b, and the gate electrode 40 exposed from the contact hole 50c by sputtering. Fourth, for example, a material constituting the wiring layer 60 is formed on the barrier metal by sputtering. Fifth, a resist pattern is formed on the material constituting the wiring layer 60. Sixth, the material constituting the wiring layer 60 is dry-etched through the openings of the resist pattern, thereby patterning the material constituting the wiring layer 60 and the barrier metal to form the wiring layer 60.

[0065] Figure 11 This is a cross-sectional view illustrating the passivation film formation process S8. (For example...) Figure 11 As shown, in the passivation film formation process S8, a passivation film 70 is formed. In the passivation film formation process S8, firstly, a constituent material of the passivation film 70 is formed, for example, by a CVD method. Secondly, a resist pattern is formed on the constituent material of the passivation film 70. Thirdly, the constituent material of the passivation film 70 is patterned by dry etching through the openings of the resist pattern, thereby forming the passivation film 70.

[0066] Figure 12A This is the first cross-sectional view illustrating the process S9 for forming the impurity diffusion region. Figure 12B This is a second cross-sectional view illustrating the process S9 where the impurity diffusion region is formed. For example... Figure 12A as well as Figure 12B As shown, in the impurity diffusion region formation process S9, ion implantation is performed, for example, from the main surface 10a side, thereby forming the drain region 14. Figure 13A This is the first cross-sectional view illustrating the drain electrode formation process S10. Figure 13B This is a second cross-sectional view illustrating the drain electrode formation process S10. (Example) Figure 13A as well as Figure 13BAs shown, for example, a drain electrode 90 is formed on the main surface 10a by sputtering. In the protective film formation process S11, the constituent material of the protective film 80 is coated on the passivation film 70 and the constituent material of the protective film 80 is cured to form the protective film 80. In the monolithization process S12, the silicon carbide substrate 10 and the insulating film 50 are cut along the dicing line, thereby monolithizing the wafer that has undergone the processes up to the protective film formation process S11 into multiple semiconductor devices 100. Based on the above, it is possible to obtain Figures 1-3 The semiconductor device 100 with the structure shown is shown.

[0067] (Effect of semiconductor device 100)

[0068] The effects of semiconductor device 100 will be compared with those of the semiconductor device in the comparative example below. The semiconductor device in the comparative example will be referred to as semiconductor device 100A.

[0069] Figure 14 This is a cross-sectional view of semiconductor device 100A. Among them, Figure 14 Indicates and Figure 1 The cross-section at the location corresponding to II-II in the diagram. For example... Figure 14 As shown, in semiconductor device 100A, the outer periphery of insulating film 50 is located away from the outer periphery of main surface 10b when viewed from above. That is, in semiconductor device 100A, the outer periphery of main surface 10b is exposed from insulating film 50. In semiconductor device 100A, wiring layer 60 has a portion located outside the terminal structure (multiple protective rings 18) when viewed from above. More specifically, in semiconductor device 100A, wiring layer 60 also has border wiring 64. Border wiring 64 is formed over the outer periphery of main surface 10b exposed from insulating film 50 and over the outer periphery of insulating film 50.

[0070] In the semiconductor device 100A, the border wiring 64 is susceptible to corrosion due to reaction with moisture. In particular, since a silicon carbide substrate 10 is used in the semiconductor device 100A, an electric field is easily applied to the outer periphery of the semiconductor device 100A, which facilitates the corrosion of the border wiring 64. As a result, silicon carbide products sometimes form from the silicon carbide contained in the silicon carbide substrate 10 and the aluminum contained in the wiring layer 60 (border wiring 64), which can sometimes reduce the THB tolerance. These silicon carbide products refer to corrosion products originating from silicon carbide or silicon oxides formed by the corrosion of silicon carbide.

[0071] On the other hand, in the semiconductor device 100, the wiring layer 60 is located inside the terminal structure when viewed from above, and does not have a border wiring 64. Therefore, even if a stronger electric field is applied to the outer periphery of the semiconductor device 100, it is difficult for the wiring layer 60 to corrode or for silicon carbide to form, thus ensuring the THB tolerance of the semiconductor device 100.

[0072] Figure 15 This is a table showing the results of the THB endurance test. Sample 1 and Sample 2 were prepared for the THB endurance test. Sample 1 and Sample 2 correspond to semiconductor device 100 and semiconductor device 100A, respectively. That is, Sample 2 has border wiring 64, while Sample 1 does not have border wiring 64. Furthermore, both Sample 1 and Sample 2 have a passivation film 70. Figure 15 As shown, in sample 2, 6 out of 10 samples experienced insulation failure, while in sample 1, only 2 out of 10 samples experienced insulation failure. This demonstrates that THB withstand capability is improved by omitting a portion of the wiring layer 60 that is positioned outside the termination structure (multiple guard rings 18) when viewed from above (omitting the border wiring 64).

[0073] In the semiconductor device 100, the insulating film 50 is formed such that it reaches the outer periphery of the main surface 10b. Therefore, when the semiconductor device 100 is sealed with molding resin, the molding resin contacts the insulating film 50 instead of the silicon carbide substrate 10. Thus, according to the semiconductor device 100, the adhesion between the molding resin and the semiconductor device 100 can be improved.

[0074] Materials containing boron and phosphorus have high hygroscopicity. However, in the semiconductor device 100, the second layer 52 (the uppermost of the multiple layers of the insulating film 50) is formed of a material that does not contain boron or phosphorus. Therefore, according to the semiconductor device 100, the insulating film 50 is less likely to absorb moisture, its moisture resistance, water resistance, and adhesion to the molding resin are improved, and it can suppress the corrosion of the silicon carbide substrate 10.

[0075] (Variation Example 1)

[0076] Figure 16 This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 1. Furthermore, Figure 16 Indicates and Figure 1The cross-section at position II-II is shown. A portion of the outer periphery of the silicon carbide substrate 10, when viewed from above, forms a dicing line (refer to the monolithization process S12). The insulating film 50 may not cover the main surface 10b located along the dicing line. Alternatively, the outer periphery of the insulating film 50 may be located further inward than the outer periphery of the main surface 10b. When the insulating film 50 is also formed on the main surface 10b along the dicing line, cracks sometimes develop in the insulating film 50 during dicing. Therefore, by not covering the main surface 10b along the dicing line with the insulating film 50, the development of such cracks into the insulating film 50 can be suppressed, thereby maintaining the waterproof performance of the insulating film 50.

[0077] (Modified Example 2 and Modified Example 3)

[0078] Figure 17A This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 2. Furthermore, Figure 17A Indicates and Figure 1 The cross-section at the location corresponding to II-II in the diagram. For example... Figure 17A As shown, the outer periphery of the protective film 80 can also be positioned further outward than the outer periphery of the passivation film 70 when viewed from above. In this case, the adhesion between the protective film 80 and the insulating film 50 is improved by ensuring that the outer periphery of the protective film 80 does not overlap with the step of the insulating film 50.

[0079] Figure 17B This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 3. Furthermore, Figure 17B Indicates and Figure 1 The cross-section at the location corresponding to II-II in the diagram. For example... Figure 17B As shown, the insulating film 50 can also be composed of a single layer formed of a material (silicon oxide) that does not contain boron or phosphorus.

[0080] (Variation Example 4)

[0081] Figure 18 This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 4. Furthermore, Figure 18 Indicates and Figure 1 The cross-section at the location corresponding to II-II in the diagram. For example... Figure 18As shown, the field oxide film 20 can also extend such that its outer periphery reaches the outer periphery of the main surface 10b when viewed from above. The field oxide film 20 can also be thicker than any of the multiple layers of the insulating film 50. In this case, since the thickest field oxide film 20 reaches the outer periphery of the main surface 10b, moisture is unlikely to contact the silicon carbide substrate 10 at the location where a strong electric field is applied during semiconductor device 100 operation. Furthermore, in this case, even if corrosion occurs, it will stop at the end of the thickest field oxide film 20, thus suppressing the progression of corrosion to the active cells.

[0082] Furthermore, the field oxide film 20 extends to the outer periphery of the main surface 10b, resulting in a flat surface without steps on the outer peripheral region 10bb, where the insulating film 50 and the passivation film 70 are formed. Therefore, in this case, the adhesion of the protective film 80 and the adhesion of the molding resin can be improved.

[0083] (Variation Example 5)

[0084] Figure 19 This is a cross-sectional view of the semiconductor device 100 involved in Modified Example 5. Furthermore, Figure 19 Indicates and Figure 1 The cross-section at the location corresponding to II-II in the diagram. For example... Figure 19 As shown, the channel cutoff ring 19 may not be formed in a manner that reaches the outer periphery of the main surface 10b when viewed from above. That is, the channel cutoff ring 19 may also be covered by the field oxide film 20. In this case, there is no interface between the molding resin and the channel cutoff ring 19. As a result, no electron transduction or retransmission occurs at the interface between the molding resin and the channel cutoff ring 19, and the peeling of the molding resin caused by chemical reactions at this interface can be suppressed.

[0085] (Modification 6 and Modification 7)

[0086] Figure 20 This is an enlarged top view of the semiconductor device 100 involved in Modified Example 6. Furthermore, Figure 20 Indicates and Figure 1 An enlarged top view of the location corresponding to XX in the diagram. For example... Figure 20 As shown, when viewed from above, the corners of the outer periphery of the protective film 80 can also have multiple faces. Two adjacent faces among the multiple faces forming the corners of the outer periphery of the protective film 80 form an angle greater than 90°. Figure 20 In the example shown, the corner of the outer periphery of the protective film 80 has surfaces 80a, 80b, and 80c. Surface 80c is connected to surface 80a at one end and to surface 80b at the other end. The angle between surfaces 80a and 80c, and the angle between surfaces 80b and 80c, are greater than 90°.

[0087] Figure 21This is an enlarged top view of the semiconductor device 100 involved in Modified Example 7. Furthermore, Figure 21 Indicates and Figure 1 An enlarged top view of the location corresponding to XX in the diagram. For example... Figure 21 As shown, when viewed from above, the corners of the outer periphery of the protective film 80 can also be rounded. Cracks sometimes occur at the corners of the outer periphery of the protective film 80 due to thermal stress from the molding resin. In these cases, by chamfering or rounding the corners of the protective film 80, stress concentration at the corners of the protective film 80 is mitigated, the formation of the aforementioned cracks is suppressed, and water resistance is improved.

[0088] (Variation Example 8)

[0089] In the above description, the case in which a vertical MOSFET is formed as a semiconductor element in the semiconductor device 100 is used as an example. However, other power semiconductor elements besides the vertical MOSFET can also be formed in the semiconductor device 100, such as Schottky barrier diodes, IGBTs (Insulated Gate Bipolar Transistors), etc.

[0090] Implementation Method 2

[0091] This embodiment describes the application of the semiconductor device described in Embodiment 1 to a power conversion device. This disclosure is not limited to any specific power conversion device; hereinafter, Embodiment 2 will describe the application of this disclosure to a three-phase inverter.

[0092] Figure 22 This is a block diagram showing the structure of a power conversion system that uses the power conversion device described in Embodiment 2.

[0093] Figure 22 The power conversion system shown consists of a power conversion device 200, a power supply 300, and a load 310. The power supply 300 is a DC power source that supplies DC power to the power conversion device 200. The power supply 300 can be composed of various components, such as a DC system, solar cells, or a battery, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power supply 300 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0094] The power conversion device 200 is a three-phase inverter connected between the power source 300 and the load 310, which converts the DC power supplied from the power source 300 into AC power and supplies AC power to the load 310. Figure 22As shown, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs control signals to the main conversion circuit 201.

[0095] Load 310 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 310 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as motors for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0096] The power conversion device 200 will now be described in detail. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power source 300 into AC power and supplies it to the load 310. Although the specific circuit structure of the main conversion circuit 201 varies, the main conversion circuit 201 according to Embodiment 1 is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in anti-parallel with each switching element. At least one of the switching elements and freewheeling diodes of the main conversion circuit 201 is a switching element or freewheeling diode equivalent to any of the semiconductor devices in Embodiment 1 described above. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 310.

[0097] Additionally, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. This drive circuit can be integrated into the semiconductor device 202 or it can be a separate structure from the semiconductor device 202. The drive circuit generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements in the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is held in the on state, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is held in the off state, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0098] The control circuit 203 controls the switching elements of the main conversion circuit 201 in a manner that supplies the desired power to the load 310. Specifically, based on the power to be supplied to the load 310, the time (on-time) during which each switching element of the main conversion circuit 201 should be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Moreover, a control command (control signal) is output to the drive circuit of the main conversion circuit 201 in a manner that outputs an on signal to the switching element that should be in the on state at each time and an off signal to the switching element that should be in the off state. According to the control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0099] In the power conversion device according to Embodiment 2, since the semiconductor device (semiconductor device 100) according to Embodiment 1 is used as the semiconductor device 202 constituting the main conversion circuit 201, the THB tolerance of the semiconductor device 202 can be ensured.

[0100] In Embodiment 1, an example of applying this disclosure in a two-level three-phase inverter was described, but this disclosure is not limited to this and can be applied to various power conversion devices. Although Embodiment 1 is configured as a two-level power conversion device, it can also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, this disclosure can also be applied in a single-phase inverter. Furthermore, when supplying power to DC loads, etc., this disclosure can also be applied to DC / DC converters and AC / DC converters.

[0101] Furthermore, the power conversion device using this disclosure is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machines, induction heating cookers, contactless power supply systems, and can also be used as a power regulator for solar power generation systems, energy storage systems, etc.

[0102] [Postscript]

[0103] The various methods disclosed herein are recorded as appendices.

[0104] <Postscript 1>

[0105] A semiconductor device, wherein,

[0106] have:

[0107] Silicon carbide substrate;

[0108] Field oxide film;

[0109] Insulating film; and

[0110] Wiring layer

[0111] The aforementioned silicon carbide substrate has a first main surface and a second main surface that is opposite to the first main surface.

[0112] When viewed from above, the aforementioned second principal surface has a unit area and an outer peripheral area located between the unit area and the outer periphery of the aforementioned second principal surface.

[0113] The aforementioned silicon carbide substrate has a terminal structure formed on the second main surface located in the outer peripheral region within the silicon carbide substrate, and a channel cut-off ring.

[0114] When viewed from above, the aforementioned channel cutoff ring is located on the outer side of the aforementioned terminal structure.

[0115] The conductivity type of the aforementioned silicon carbide substrate and the conductivity type of the aforementioned channel cutoff ring are the first conductivity type.

[0116] The aforementioned terminal structure has a second conductivity type that is opposite to the first conductivity type.

[0117] The aforementioned field oxide film is formed on the second main surface located in the aforementioned peripheral region in such a manner that it overlaps with the aforementioned terminal structure when viewed from above and at least partially overlaps with the aforementioned channel cutoff ring when viewed from above.

[0118] The aforementioned insulating film is formed on the second main surface in a manner that covers the aforementioned field oxide film.

[0119] The aforementioned wiring layer is formed on the aforementioned insulating film in such a way that it is located inside the aforementioned terminal structure when viewed from above.

[0120] <Appendix 2>

[0121] According to the semiconductor device described in Appendix 1, wherein,

[0122] When viewed from above, the outer periphery of the aforementioned insulating film is located on the inner side of the outer periphery of the aforementioned second main surface.

[0123] <Appendix 3>

[0124] According to the semiconductor device described in Appendix 1 or 2, wherein,

[0125] The aforementioned insulating film is formed from a material that does not contain boron or phosphorus.

[0126] <Appendix 4>

[0127] According to the semiconductor device described in Appendix 1 or 2, wherein,

[0128] The aforementioned insulating film has multiple stacked layers.

[0129] The aforementioned insulating film extends to the outer periphery of the aforementioned second main surface when viewed from above.

[0130] The topmost layer of the above layers is formed of a material that does not contain boron or phosphorus.

[0131] <Appendix 5>

[0132] According to any one of the appendices 1 to 4, the semiconductor device wherein,

[0133] It also has a protective film.

[0134] The protective film is formed on the insulating film in such a way that the outer periphery of the protective film does not overlap with the step of the insulating film when viewed from above.

[0135] <Appendix 6>

[0136] According to the semiconductor device described in Appendix 1, wherein,

[0137] The aforementioned insulating film has multiple stacked layers.

[0138] The aforementioned field oxide film is thicker than any of the aforementioned layers.

[0139] The aforementioned field oxide film extends to the outer periphery of the aforementioned second principal surface when viewed from above.

[0140] <Appendix 7>

[0141] According to the semiconductor device described in Appendix 1, wherein,

[0142] The aforementioned field oxide film is formed on the aforementioned second main surface in such a way as to cover the aforementioned channel cut-off ring.

[0143] <Postscript 8>

[0144] According to any one of the appendices 1 to 7, the semiconductor device wherein,

[0145] It also has a protective film.

[0146] The aforementioned protective film is formed on top of the aforementioned insulating film.

[0147] When viewed from above, the corners of the outer periphery of the aforementioned protective film have multiple surfaces.

[0148] The angle between any two adjacent faces in the above-mentioned planes is greater than 90°.

[0149] <Postscript 9>

[0150] According to any one of the appendices 1 to 7, the semiconductor device wherein,

[0151] It also has a protective film.

[0152] The aforementioned protective film is formed on top of the aforementioned insulating film.

[0153] When viewed from above, the corners of the outer periphery of the aforementioned protective film are rounded.

[0154] <Postscript 10>

[0155] A power conversion device, wherein,

[0156] have:

[0157] The main conversion circuit has the semiconductor device described in any one of Appendix 1 to 9, and converts and outputs the input power;

[0158] The driving circuit outputs a driving signal to the semiconductor device; and

[0159] The control circuit outputs the control signal that controls the drive circuit to the drive circuit.

[0160] Embodiments of the present invention have been described, but the embodiments disclosed herein should be considered illustrative in all respects and not intended to limit the invention. The scope of the invention is defined by the scope of the claims and is intended to include equivalents and all modifications within that scope.

Claims

1. A semiconductor device, wherein, have: Silicon carbide substrate; Field oxide film; Insulating film; as well as Wiring layer The silicon carbide substrate has a first main surface and a second main surface that is opposite to the first main surface. When viewed from above, the second main surface has a unit area and an outer peripheral area located between the unit area and the outer periphery of the second main surface. The silicon carbide substrate has a terminal structure formed on the second main surface located in the outer peripheral region within the silicon carbide substrate, and a channel cut-off ring. When viewed from above, the channel cutoff ring is located on the outer side of the terminal structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel cutoff ring are both of the first conductivity type. The terminal structure is a second conductivity type, which is opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region in such a manner that it overlaps with the terminal structure when viewed from above and at least partially overlaps with the channel cutoff ring when viewed from above. The insulating film is formed on the second main surface in a manner that covers the field oxide film. The wiring layer is formed on the insulating film in such a way that it is located inside the terminal structure when viewed from above.

2. The semiconductor device according to claim 1, wherein, When viewed from above, the outer periphery of the insulating film is located inside the outer periphery of the second main surface.

3. The semiconductor device according to claim 1, wherein, The insulating film is formed of a material that does not contain boron or phosphorus.

4. The semiconductor device according to claim 1, wherein, The insulating film has multiple stacked layers. The insulating film extends to the outer periphery of the second main surface when viewed from above. The uppermost of the plurality of layers is formed of a material that does not contain boron or phosphorus.

5. The semiconductor device according to claim 1, wherein, It also has a protective film. The protective film is formed on the insulating film in such a way that the outer periphery of the protective film does not overlap with the step of the insulating film when viewed from above.

6. The semiconductor device according to claim 1, wherein, The insulating film has multiple stacked layers. The field oxide film is thicker than any of the plurality of layers. The field oxide film extends in such a way that it reaches the outer periphery of the second master surface when viewed from above.

7. The semiconductor device according to claim 1, wherein, The field oxide film is formed on the second main surface in such a way that it covers the channel cutoff ring.

8. The semiconductor device according to claim 1, wherein, It also has a protective film. The protective film is formed on the insulating film. When viewed from above, the corners of the outer periphery of the protective film have multiple surfaces. The angle between any two adjacent faces in the plurality of faces is greater than 90°.

9. The semiconductor device according to claim 1, wherein, It also has a protective film. The protective film is formed on the insulating film. When viewed from above, the corners of the outer periphery of the protective film are rounded.

10. A power conversion device, wherein, have: The main conversion circuit has the semiconductor device described in any one of claims 1 to 9, and converts and outputs the input power; The driving circuit outputs a driving signal to the semiconductor device. as well as The control circuit outputs control signals to the drive circuit.

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