Semiconductor devices, power supply systems, and vehicles

Abstract

This allows for greater flexibility in setting the startup timing of the power supply circuit. [Solution] The semiconductor device (1) includes a multi-channel power supply circuit (51-57), a first input section (EN terminal) configured to receive a first input signal, and a second input section (ADDEN1 terminal or I2C communication terminal) configured to receive a second input signal. The device is configured to allow setting of channels of the power supply circuit to an enable function using the first input signal and an additional enable function using the second input signal, a first delay time information relating to the elapsed time from when the first input signal indicating startup is received until the channel assigned the enable function is started, and a second delay time information relating to the elapsed time from when the second input signal indicating startup is received until the channel assigned the additional enable function is started.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, a PMIC (Power Management IC) having a plurality of channels for a power supply circuit has been known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In a PMIC, the activation timing of each channel is determined according to user requirements. For example, a PMIC for an in-vehicle SoC (System on a chip) is required to set various activation timings in order to control all the electronic components mounted on the vehicle.

[0005] A semiconductor device according to one aspect of the present disclosure includes a power supply circuit having a plurality of channels, a first input unit configured to receive a first input signal, a second input unit configured to receive a second input signal, and is configured to be able to set the assignment of channels of the power supply circuit to each of an enable function using the first input signal and an additional enable function using the second input signal, first delay time information regarding the elapsed time from when the first input signal indicating activation is input until the channel assigned the enable function is activated, and second delay time information regarding the elapsed time from when the second input signal indicating activation is input until the channel assigned the additional enable function is activated.

Brief Description of the Drawings

[0006] [Figure 1] Figure 1 is a block diagram showing the configuration of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 2] Figure 2 shows a plan view of the semiconductor device as seen from above. [Figure 3] Figure 3 shows a register map for setting the delay time to determine the startup timing. [Figure 4] Figure 4 shows a register map for setting the enable / disable status of the first additional enable function or the second additional enable function, respectively. [Figure 5] Figure 5 is a timing chart showing an example of startup timing control operation in a semiconductor device. [Figure 6] Figure 6 is a timing chart showing another example of startup timing control in a semiconductor device. [Figure 7] Figure 7 shows a register map for setting the delay time to determine the shutdown timing. [Figure 8A] Figure 8A shows an example of a register map used for startup and shutdown timing control in a modified example. [Figure 8B] Figure 8B shows an example of a register map used for startup and shutdown timing control in the modified version. [Figure 9] Figure 9 shows the configuration of a power supply system using semiconductor devices. [Figure 10] Figure 10 shows an example of another power supply system using semiconductor equipment. [Figure 11] Figure 11 is an external view showing an example of a vehicle.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <1. PMIC Configuration> Figure 1 is a block diagram showing the configuration of a semiconductor device 1 according to an exemplary embodiment of the present disclosure. The semiconductor device 1 is configured as a PMIC. The semiconductor device 1 includes a multi-channel power supply circuit (BUCK1-4, LDO5-7) as described later.

[0009] The semiconductor device 1 is equipped with the following external terminals for establishing an electrical connection with the outside: VIN terminal, STBY terminal, EN terminal, VREG15 terminal, VREGIN terminal, SYNC_ADDEN2 terminal, SCL terminal, SDA terminal, PRSTB terminal, IF1_ADDEN1 terminal, IF2 terminal, ERRB_ADDPRSTB2 terminal, INTB_ADDPRSTB1 terminal, and GND terminal.

[0010] The semiconductor device 1 includes, internally, an internal power supply circuit 2, a SYNC circuit 3, a control unit (control logic) 4, step-down power supply circuits 51-54, and LDO (Low Drop Out) circuits 55-57. The semiconductor device 1 integrates the above internal configuration onto a single chip. Specifically, the semiconductor device 1 includes four channels of step-down power supply circuits and three channels of LDO circuits, for a total of seven power supply circuits.

[0011] The semiconductor device 1 is equipped with external terminals corresponding to the step-down power supply circuits 51 to 54, namely PVIN1 to PVIN4 terminals, SW1 to SW4 terminals, FBP1 to FBP4 terminals, and FBN1 to FBN4 terminals. In addition, an external terminal PGND12 is provided corresponding to step-down power supply circuits 51 and 52, and an external terminal PGND34 is provided corresponding to step-down power supply circuits 53 and 54.

[0012] Furthermore, the semiconductor device 1 is equipped with PVIN5 to PVIN7 terminals and VOUT5 to VOUT7 terminals as external terminals corresponding to LDO55 to 57. In addition, an external terminal GATE7 terminal is provided for LDO57.

[0013] An external input voltage VIN is applied to the VIN terminal, and a bypass capacitor C1 is externally connected between it and ground.

[0014] A standby signal STBY is input to the STBY terminal from the outside. An enable signal EN is input to the EN terminal from the outside.

[0015] The internal power supply circuit 2 generates an internal power supply voltage VREG15 based on the input voltage VIN. The internal power supply voltage VREG15 is a voltage of 1.5V, which is used as the power supply voltage inside the IC and is output from the VREG15 terminal. A capacitor C2, which is a pass capacitor, is connected between the VREG15 terminal and the ground. The internal power supply voltage VREG15 is input to the VREGIN terminal and supplied to the control unit 4 and each power supply circuit (51 to 57).

[0016] The SYNC_ADDEN2 terminal is a terminal commonly used for both the SYNC (synchronization) function and the second additional enable function. With the SYNC_ADDEN2 terminal, the second additional enable function can be added without increasing the number of terminals. Note that the second additional enable function and the first additional enable function described later are functions added to the enable function by the enable signal EN. When the SYNC function is valid, an external clock signal is input to the SYNC_ADDEN2 terminal, and the switching periods of the step-down power supply circuits 51 to 54 are synchronized with the external clock signal. Also, when the second additional enable function is valid, an additional enable signal ADD_EN2 is input to the SYNC_ADDEN2 terminal. Which of the SYNC function and the second additional enable function is made valid is set in the register 41 (included in the control unit 4) in the semiconductor device 1.

[0017] The SCL terminal and the SDA terminal are provided for I2C (Inter-Integrated Circuit) communication. I2C is a type of serial communication standard. The clock signal SCL is transmitted and received between the SCL terminal and an external device, and the data signal SDA is transmitted and received between the SDA terminal and the external device. The above external device includes an EEPROM (Electrically Erasable Programmable Read-Only Memory) 10. The SCL terminal and the SDA terminal are pulled up by pull-up resistors Rp1 and RP2, respectively. Note that the serial communication is not limited to I2C, and for example, SPI (Serial Peripheral Interface) etc. may be used.

[0018] The PRSTB (Power-On Reset) terminal is a terminal for outputting a reset signal PRSTB, and is pulled up by a pull-up resistor Rp3. The reset signal PRSTB is an open-drain signal and indicates an active (reset state) at a low level.

[0019] The IF1_ADDEN1 terminal is a terminal commonly used for the IF (interface) function and the first additional enable function. With the IF1_ADDEN1 terminal, the first additional enable function can be added without increasing the number of terminals. The IF function is a terminal for communication between the semiconductor device 1 and an external PMIC. When the IF function is valid, the clock for the above communication is input and output to the IF1_ADDEN1 terminal. Also, when the first additional enable function is valid, an additional enable signal ADD_EN1 is input to the IF1_ADDEN1 terminal. Which of the IF function and the first additional enable function is made valid is set in register 41. The IF1_ADDEN1 terminal is pulled up by a pull-up resistor Rp4.

[0020] The IF2 terminal is a terminal used for the IF function, and a clock is input and output. The IF2 terminal is pulled up by a pull-up resistor Rp5.

[0021] The ERRB_ADDPRSTB2 terminal is used for both the error notification function and the second additional power-on reset function. The ERRB_ADDPRSTB2 terminal allows for the addition of a second additional power-on reset function without increasing the number of terminals. The second additional power-on reset function and the first additional power-on reset function (described later) are added to the power-on reset function that uses the reset signal PRSTB. When the error notification function is enabled, an error signal is output from the ERRB_ADDPRSTB2 terminal. Also, when the second additional power-on reset function is enabled, the additional reset signal ADD_PRSTB2 is output from the ERRB_ADDPRSTB2 terminal. Whether to enable the error notification function or the second additional power-on reset function is set in register 41. The ERRB_ADDPRSTB2 terminal is pulled up by the pull-up resistor Rp6. The ERRB_ADDPRSTB2 terminal is active at a low level via open drain.

[0022] The INTB_ADDPRSTB1 terminal is used in common by both the interrupt function and the first additional power-on reset function. The INTB_ADDPRSTB1 terminal allows for the addition of the first additional power-on reset function without increasing the number of terminals. When the interrupt function is enabled, the interrupt signal is output from the INTB_ADDPRSTB1 terminal. When the first additional power-on reset function is enabled, the additional reset signal ADD_PRSTB1 is output from the INTB_ADDPRSTB1 terminal. Whether to enable the interrupt function or the first additional power-on reset function is set in register 41. The INTB_ADDPRSTB1 terminal is pulled up by the pull-up resistor Rp7. The INTB_ADDPRSTB1 terminal is active at a low level due to its open-drain configuration.

[0023] Next, the step-down power supply circuit will be described. Here, the step-down power supply circuit 51 will be described as a representative example. The step-down power supply circuit 51 comprises a half-bridge consisting of a high-side switch and a low-side switch (neither shown), and a control circuit (not shown) that drives and controls the high-side switch and the low-side switch. The step-down power supply circuit 51, inductor Lo1, and output capacitor Co1 constitute a DC / DC converter (switching regulator) that steps down the input voltage VIN to generate the output voltage VOUT1.

[0024] An external input voltage VIN is input to the PVIN1 terminal. Ground potential is applied to the PGND12 terminal. Here, as an example, the high-side switch is composed of a P-channel MOSFET and the low-side switch is composed of an N-channel MOSFET. The source of the high-side switch is connected to the PVIN terminal, the drain of the high-side switch is connected to the drain of the low-side switch, and the source of the low-side switch is connected to the PGND12 terminal. In other words, the high-side switch and the low-side switch are connected between the PVIN terminal and the PGND12 terminal. The node to which the drains of the high-side switch and the drain of the low-side switch are connected is connected to the SW1 terminal. One end of inductor Lo1 is externally connected to the SW1 terminal. The other end of inductor Lo1 is connected to one end of output capacitor Co1. The other end of output capacitor Co1 is connected to ground. One end of output capacitor Co1 is connected to the FBP1 terminal, and the other end of output capacitor Co1 is connected to the FBN1 terminal. The voltage between the FBP1 terminal and the FBN1 terminal is input to the step-down power supply circuit 51 as a feedback voltage, and the control circuit is used to provide feedback control so that the output voltage VOUT1 reaches the target voltage. The ground applied to the PGND12 terminal is shared by the step-down power supply circuits 51 and 52, and the ground applied to the PGND34 terminal is shared by the step-down power supply circuits 53 and 54.

[0025] Next, the LDO circuit will be described. Here, the LDO circuit 55 will be described as a representative example. The LDO circuit 55 has an output transistor and a control circuit (neither of which is shown) that drives and controls the output transistor. The LDO circuit 55 is a DC / DC converter (series regulator) that steps down the input voltage VIN to generate the output voltage VOUT5. The output transistor is composed of a P-channel MOSFET.

[0026] An external input voltage VIN is input to the PVIN5 terminal. The PVIN5 terminal is connected to the source of the output transistor. The VOUT5 terminal is connected to the drain of the output transistor. The output voltage VOUT5 generated at the VOUT5 terminal is fed back to the control circuit, and feedback control is performed so that the output voltage VOUT5 becomes the target voltage.

[0027] The GATE7 terminal is used to drive the gate of an external output transistor when an external output transistor is used for the LDO circuit 57.

[0028] <Layout of external terminals> Figure 2 shows a plan view of the semiconductor device 1 as seen from above. Figure 2 shows the layout of the external terminals (pin numbers 1 to 48). In Figure 2, the first direction X (vertical direction on the paper) is shown as one side X1 and the other side X2 of the first direction, and the second direction Y (horizontal direction on the paper) is shown as one side Y1 and the other side Y2 of the second direction.

[0029] The semiconductor device 1 has a rectangular shape when viewed from above and has a first side L1, a second side L2, a third side L3, and a fourth side L4. The first side L1 and the third side L3 extend in a first direction, and the second side L2 and the fourth side L4 extend in a second direction. The first side L1 and the third side L3 face each other in a second direction, and the second side L2 and the fourth side L4 face each other in a first direction. The other end of the first side L1 in the first direction is connected to one end of the second side L2 in the second direction. The other end of the second side L2 in the second direction is connected to the other end of the third side L3 in the first direction. One end of the third side L3 in the first direction is connected to the other end of the fourth side L4 in the second direction. One end of the fourth side L4 in the second direction is connected to one end of the first side L1 in the first direction.

[0030] Along the first side L1, in order from one side in the first direction, the following terminals are arranged: IF1_EN1 terminal, IF2 terminal, VREG15 terminal, VREG15IN terminal, SDA terminal, SCL terminal, EN terminal, INT_BPRSTB1 terminal, SYNC_EN2 terminal, VIN terminal, NC (unconnected) terminal, and NC terminal.

[0031] Along the second side L2, the following terminals are arranged in order from one side in the second direction: FBP1 terminal, FBN1 terminal, PVIN1 terminal, SW1 terminal, PGND12 terminal, SW2 terminal, PVIN2 terminal, FBN2 terminal, FBP2 terminal, NC terminal, NC terminal, and GATE7 terminal.

[0032] Along the third side L3, the following terminals are arranged in order from the other side in the first direction: NC terminal, NC terminal, PVIN7 terminal, VOUT7 terminal, PVIN6 terminal, VOUT6 terminal, GND terminal, VOUT5 terminal, PVIN5 terminal, STBY terminal, PRSTB terminal, and ERRB_PRSTB2 terminal.

[0033] Along the fourth side L4, in the second direction from the other side, the following terminals are arranged in order: FBP3 terminal, FBN3 terminal, PVIN3 terminal, SW3 terminal, SW3 terminal, PGND34 terminal, PGND34 terminal, SW4 terminal, SW4 terminal, PVIN4 terminal, FBN4 terminal, and FBP4 terminal.

[0034] Furthermore, heat dissipation pads (EXP-PADs) are placed on the underside of the semiconductor device 1 and at the four rectangular corners.

[0035] <Startup timing control> Next, the startup timing control in semiconductor device 1 will be described. Startup timing control is the control of the startup timing (the timing at which the output voltage starts to rise) in each of the step-down power supply circuits 51-54 and LDO circuits 55-57. Startup timing control is performed by the control unit 4. Here, the register map in register 41 for setting startup timing control will be described.

[0036] Figure 3 shows a register map for setting the delay time to determine the startup timing. In the register maps shown in Figure 3 and subsequent figures, the register address, data name, and setting data are shown. The setting data is, for example, 8-bit data (Bit[7] to Bit[0]). The delay time set here is the delay time after one of the enable signal EN, additional enable signal ADD_EN1, or additional enable signal ADD_EN2 rises.

[0037] BUCK1_DELAY_PON to BUCK4_DELAY_PON are data used to set the delay time for each of the step-down power supply circuits 51 to 54, respectively. LDO5_DELAY_PON to LDO7_DELAY_PON are data used to set the delay time for each of the LDO circuits 55 to 57, respectively. PRSTB_DELAY_PON is data used to set the delay time for the reset signal PRSTB.

[0038] Figure 4 (the bottom two rows) shows the register map for setting the enable / disable status of the first additional enable function or the second additional enable function, respectively.

[0039] In Figure 4, "ADD_EN1" represents data for enabling or disabling the first additional enable function. In ADD_EN1, one bit at a time is stored from the least significant bit, from BUCK1_ADD_EN1 to BUCK4_ADD_EN1, LDO5_ADD_EN1 to LDO7_ADD_EN1, and PRSTB_ADD_EN1. BUCK1_ADD_EN1 to BUCK4_ADD_EN1 are data for enabling or disabling the first additional enable function for each of the step-down power supply circuits 51 to 54, respectively. LDO5_ADD_EN1 to LDO7_ADD_EN1 are data for enabling or disabling the first additional enable function for each of the LDO circuits 55 to 57, respectively. PRSTB_ADD_EN1 is data for enabling or disabling the first additional enable function for the reset signal PRSTB.

[0040] If all bit values ​​among BUCK1_ADD_EN1 through BUCK4_ADD_EN1, LDO5_ADD_EN1 through LDO7_ADD_EN1, and PRSTB_ADD_EN1 are set to "0", the first additional enable function is disabled.

[0041] On the other hand, if at least one bit value among BUCK1_ADD_EN1 to BUCK4_ADD_EN1, LDO5_ADD_EN1 to LDO7_ADD_EN1, and PRSTB_ADD_EN1 is set to "1", the first additional enable function is activated for the step-down power supply circuits 51-54, LDO circuits 55-57, and the reset signal PRSTB that corresponds to the data set to "1". When the first additional enable function is activated, channel startup timing control or reset release of the reset signal PRSTB is performed based on the additional enable signal ADD_EN1.

[0042] In Figure 4, "ADD_EN2" represents the data used to enable or disable the second additional enable function. This data is explained by replacing "EN1" with "EN2" and the first additional enable function with the second additional enable function, as described above, so a detailed explanation is omitted.

[0043] Furthermore, for channels and reset signals PRSTB that are set to "0" in both "ADD_EN1" and "ADD_EN2", the enable function is activated, and startup timing control is performed based on the enable signal EN.

[0044] Thus, according to the register map shown in Figure 4, it becomes possible to configure which channel among the multiple-channel power supply circuits will enable the first additional enable function or the second additional enable function.

[0045] Next, an example of startup timing control operation will be described. Figure 5 is a timing chart showing an example of startup timing control operation in semiconductor device 1. Figure 5 shows an example of operation when both the first additional enable function and the second additional enable function are set to disabled, and only the enable function is set to enabled. In Figure 5, from top to bottom, the following are shown: input voltage VIN, internal power supply voltage VREG15, standby signal STBY, enable signal EN, internal state, I2C communication state, output voltages corresponding to step-down power supply circuits 51-54, output voltages corresponding to LDO circuits 55-57, reset signal PRSTB, error signal ERRB, and interrupt signal INTB. Note that in this case, the error notification function and interrupt function are set to enabled.

[0046] At timing t1, the input voltage VIN begins to rise. Then, at timing t2, the standby signal STBY rises, activating the internal power supply circuit 2, and the internal power supply voltage VREG15 begins to rise. At timing t3, the UVLO (Under Voltage Lock Out) of the internal power supply voltage VREG15 is released. The internal state is shut off until timing t2, and VREG15 is ON from timing t2 to t3.

[0047] From timing t3 onward, the internal state transitions in the following order: digital BIST (built-in self-test) for the control unit 4, OTP (One Time Programmable ROM) read state, EEPROM read state, and analog BIST for various protection circuits.

[0048] Subsequently, at timing t4, the internal state enters standby mode. Then, at timing t5, the enable signal EN rises. At each timing that has elapsed from timing t5 according to the register map shown in Figure 3 (BUCK1_DELAY_PON~BUCK4_DELAY_PON, and LDO5_DELAY_PON~LDO7_DELAY_PON), the step-down power supply circuits 51~54 and LDO circuits 55~57 are started up. At these start timings, each output voltage begins to rise.

[0049] Furthermore, the reset signal PRSTB is set to the reset state (low level) at timing t3, and transitions to the reset release state (high level) after a delay time (PRSTB_DELAY_PON) set by the register map shown in Figure 3 has elapsed from timing t5.

[0050] For power supply circuits with enabled functionality, the channel or reset signal PRSTB is set as follows, for example, in the register map shown in Figure 3. If the setting data is 0x00, the delay time is 2μs. If the setting data is 0x01 to 0x80, the delay time is 128 μs to 16.384 ms (step = 128 μs). If the setting data is 0x80 to 0xA0, the delay time is 16.384ms to 24.576ms (step = 256μs). If the setting data is 0xA0 to 0xC0, the delay time is 24.576ms to 40.960ms (step = 512μs). If the setting data is 0xC0 to 0xE0, the delay time is 40.960 μs to 73.728 ms (step = 1.024 ms). If the setting data is 0xE0 to 0xFF, the delay time is 73.728 μs to 137.216 ms (step = 2.048 ms).

[0051] In this way, the longer the delay time, the longer the step size. This allows for setting a delay time over as wide a range as possible while suppressing an increase in the number of bits in the configuration data.

[0052] Next, Figure 6 is a timing chart showing another example of startup timing control in semiconductor device 1. Figure 6 shows an example of operation when both the first additional enable function and the second additional enable function are set to enabled. Specifically, the first additional enable function is enabled for the buck power supply circuit 51 and LDO circuit 55, and the second additional enable function is enabled for the buck power supply circuit 52 and LDO circuit 56. That is, in the register map of Figure 4, in "ADD_EN1", BUCK1_ADD_EN1 and LDO5_ADD_EN1 are set to "1", and the others to "0", and in "ADD_EN2", BUCK2_ADD_EN2 and LDO6_ADD_EN2 are set to "1", and the others to "0". In this case, the enable function is enabled for the buck power supply circuits 53, 54 and LDO circuit 57.

[0053] In Figure 6, compared to Figure 5, the additional enable signals ADD_EN1 and ADD_EN2 are shown between the enable signal EN and the internal state. The lowermost INTB_ADDPRSTB1 and ERRB_ADDPRSTB2 in Figure 6 will be discussed later.

[0054] Since the first additional enable function is enabled, the step-down power supply circuit 51 and the LDO circuit 55 are started at the timings set by the respective delay times (BUCK1_DELAY_PON and LDO5_DELAY_PON) set by the register map shown in Figure 3, starting from the timing ta when the additional enable signal ADD_EN1 rises.

[0055] Since the second additional enable function is enabled, the step-down power supply circuit 52 and the LDO circuit 56 are started at the timings set by the respective delay times (BUCK2_DELAY_PON and LDO6_DELAY_PON) set by the register map shown in Figure 3, which are determined by the timing tb when the additional enable signal ADD_EN2 rises.

[0056] Furthermore, for the channel or reset signal PRSTB of a power supply circuit where the first additional enable function or the second additional enable function is enabled, the setting data for the register map shown in Figure 3 is set as follows, for example. The upper 4 bits (Bit[7] to Bit[4]) are ignored. If the setting data is 0x0, the delay time is 2μs. If the setting data is 0x1 to 0xF, the delay time is 1.024ms to 15.360ms (step = 1.024ms). The reason why the register map setting data shown in Figure 3 differs from that when enabling the aforementioned enable function is to avoid increasing the circuit area. However, if there are no constraints on circuit area, the setting data may be the same.

[0057] Furthermore, since the enable function is enabled for the step-down power supply circuits 53, 54 and the LDO circuit 57, each step-down power supply circuit 53, 54 and the LDO circuit 57 are started at the respective timings set by the register map shown in Figure 3 (BUCK3_DELAY_PON, BUCK4_DELAY_PON, and LDO7_DELAY_PON) from the timing tb when the enable signal EN rises.

[0058] Furthermore, since the enable function is active for the reset signal PRSTB, the reset signal PRSTB transitions to the reset-released state at a timing set by the delay time (PRSTB_DELAY_PON) set by the register map shown in Figure 3, which is the activation timing, from the timing tb when the enable signal EN rises.

[0059] If the semiconductor device 1 does not have an additional enable function and only has an enable function, the startup timing will be set within a range where a delay time set in the register has elapsed from the rising edge of the enable signal EN. However, in this embodiment, since the first and second additional enable functions are provided, the range of setting the startup timing can be expanded. For example, with only the enable function, the latest controllable startup timing is the timing where the maximum delay time set in the register has elapsed from the rising edge of the enable signal EN. However, by providing an additional enable function, it becomes possible to set the startup timing to a later timing than that startup timing.

[0060] <Shutdown timing control> Furthermore, the semiconductor device 1 according to this embodiment also has a function to control the timing of shutdown in addition to startup. The shutdown timing control is performed by the control unit 4.

[0061] Figure 7 shows a register map for setting delay times to determine the shutdown timing. BUCK1_DELAY_POFF to BUCK4_DELAY_POFF are data for setting delay times for each of the step-down power supply circuits 51 to 54, respectively. LDO5_DELAY_POFF to LDO7_DELAY_POFF are data for setting delay times for each of the LDO circuits 55 to 57, respectively. PRSTB_DELAY_POFF is data for setting the delay time for the reset signal PRSTB.

[0062] Shutdown timing control will be explained using Figure 6 as an example. In Figure 6, as mentioned earlier, the first additional enable function is enabled for the step-down power supply circuit 51 and LDO circuit 55, the second additional enable function is enabled for the step-down power supply circuit 52 and LDO circuit 56, and the enable function is set to be enabled for the step-down power supply circuits 53, 54 and LDO circuit 57.

[0063] Therefore, as shown in Figure 6, the step-down power supply circuit 51 and the LDO circuit 55 shut down at each timing that has elapsed from the timing tc when the additional enable signal EN1 falls down, by the respective delay times (BUCK1_DELAY_POFF and LDO5_DELAY_POFF) set by the register map shown in Figure 7. The shutdown timing is the timing when the output voltage starts to fall.

[0064] Furthermore, for the step-down power supply circuit 52 and the LDO circuit 56, the shutdown timing is set to the timing after the additional enable signal EN2 has fallen, and the respective delay times (BUCK2_DELAY_POFF and LDO6_DELAY_POFF) set by the register map shown in Figure 7 have elapsed, and the step-down power supply circuit 52 and the LDO circuit 56 shut down accordingly.

[0065] Furthermore, for the step-down power supply circuits 53 and 54 and the LDO circuit 57, the shutdown timing is set at each timing that has elapsed from the timing td when the enable signal EN falls down, according to the register map shown in Figure 7 (BUCK3_DELAY_POFF, BUCK4_DELAY_POFF, and LDO7_DELAY_POFF), and the step-down power supply circuits 53 and 54 and the LDO circuit 57 shut down accordingly.

[0066] Furthermore, the reset signal PRSTB transitions to the reset state (low level) after a delay time (PRSTB_DELAY_POFF) set by the register map shown in Figure 7 has elapsed from the timing td when the enable signal EN falls.

[0067] Furthermore, the delay time value set by the register map shown in Figure 7 also changes depending on whether the enable function or the additional enable function is enabled, similar to the register map (for startup) shown in Figure 3 mentioned earlier. The setting value may be the same as or different from that for startup.

[0068] <Additional power-on reset function> Next, we will explain the additional power-on reset function. In the register map shown in Figure 4, "ADD_PRSTB" indicates the setting data for the additional power-on reset function.

[0069] The ADD_PRSTB1 stored in the first and second bits from the least significant is data for enabling or disabling the first additional power-on reset function. Specifically, for example, If ADD_PRSTB1=00, the first additional power-on reset function is disabled, meaning the interrupt function is enabled. When ADD_PRSTB1=10, the first additional power-on reset function is enabled for the additional enable signal EN1. If ADD_PRSTB1=11, the first additional power-on reset function is enabled for the additional enable signal EN2.

[0070] The ADD_PRSTB1_DELAY values ​​stored in the third and fourth bits from the lowest position are data for setting the delay time for the first additional power-on reset function. If the first additional power-on reset function is enabled for the additional enable signal EN1, the additional reset signal ADD_PRSTB1 will transition to the reset-release state (high level) after the delay time set by ADD_PRSTB1_DELAY has elapsed since the completion of startup of the channel that starts up the latest among the channels for which the first additional enable function is enabled. If the first additional power-on reset function is enabled for the additional enable signal EN2, the additional reset signal ADD_PRSTB1 will transition to the reset-release state after the delay time set by ADD_PRSTB1_DELAY has elapsed since the completion of startup of the channel that starts up the latest among the channels for which the second additional enable function is enabled.

[0071] The ADD_PRSTB2 stored in the 5th and 6th bits from the lowest position is data used to enable or disable the second additional power-on reset function. Specifically, for example, If ADD_PRSTB2=00, the second additional power-on reset function is disabled, meaning the error notification function is enabled. When ADD_PRSTB2=10, the second additional power-on reset function is enabled for the additional enable signal EN1. When ADD_PRSTB2=11, the second additional power-on reset function is enabled for the additional enable signal EN2.

[0072] The ADD_PRSTB2_DELAY values ​​stored in the 7th and 8th bits from the lowest position are data for setting the delay time for the second additional power-on reset function. If the second additional power-on reset function is enabled for the additional enable signal EN1, the additional reset signal ADD_PRSTB2 will transition to the reset-release state after the delay time set by ADD_PRSTB2_DELAY has elapsed since the completion of startup of the channel that starts up the latest among the channels for which the first additional enable function is enabled. If the second additional power-on reset function is enabled for the additional enable signal EN2, the additional reset signal ADD_PRSTB2 will transition to the reset-release state after the delay time set by ADD_PRSTB2_DELAY has elapsed since the completion of startup of the channel that starts up the latest among the channels for which the second additional enable function is enabled.

[0073] ADD_PRSTB1_DELAY and ADD_PRSTB2_DELAY are set as follows, for example. If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY = 00, the delay time = 2μs If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY=01, the delay time is 1.211ms. If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY = 10, the delay time = 4.845 ms If ADD_PRSTB1_DELAY or ADD_PRSTB2_DELAY = 11, the delay time = 9.690 ms

[0074] As illustrated in the example in Figure 6, since the first additional power-on reset function is enabled for the additional enable signal EN1, the additional reset signal ADD_PRSTB1 transitions to the reset-off state after the delay time set by ADD_PRSTB1_DELAY has elapsed from the timing tf when the output voltage of the slower-starting of the two step-down power supply circuit 51 and LDO circuit 55, for which the first additional enable function is enabled, rises to a steady value (startup completion timing).

[0075] Furthermore, since the second additional power-on reset function is enabled for the additional enable signal EN2, the additional reset signal ADD_PRSTB2 transitions to the reset-off state after the delay time set by ADD_PRSTB2_DELAY has elapsed from the timing tg when the output voltage of the slower-starting of the two step-down power supply circuit 52 and LDO circuit 56, for which the second additional enable function is enabled, rises to a steady value (startup completion timing).

[0076] This additional power-on reset function allows for the generation of a reset signal in conjunction with the additional enable function.

[0077] <Variation> In situations where the above-mentioned additional enable signals cannot be used, startup and shutdown timing control according to the following modified example may be implemented. Figure 8A shows an example of a register map used in the startup and shutdown timing control according to the modified example. In addition, the register maps shown in Figures 3 and 7, and the register map shown in Figure 4, mentioned above, are also used in the modified example.

[0078] In the register map shown in Figure 8A, ON_ADD_EN1, OFF_ADD_EN1, ON_ADD_EN2, and OFF_ADD_EN2, which are 1-bit data, are stored.

[0079] When "1" is written to ON_ADD_EN1 via I2C communication, the power supply circuit for channels whose first additional enable function has been enabled by "ADD_EN1" in the register map shown in Figure 4 will be activated after a delay time set by the register map shown in Figure 3 has elapsed since the value was written to ON_ADD_EN1.

[0080] When "1" is written to OFF_ADD_EN1 via I2C communication, the power supply circuit for channels whose first additional enable function has been enabled by "ADD_EN1" in the register map shown in Figure 4 will shut down after a delay time set by the register map shown in Figure 7 has elapsed since the value was written to OFF_ADD_EN1.

[0081] When "1" is written to ON_ADD_EN2 via I2C communication, the power supply circuit for channels whose second additional enable function has been enabled by "ADD_EN2" in the register map shown in Figure 4 will be activated after the delay time set in the register map shown in Figure 3 has elapsed since the value was written to ON_ADD_EN2.

[0082] When "1" is written to OFF_ADD_EN2 via I2C communication, the power supply circuit for channels whose second additional enable function has been enabled by "ADD_EN2" in the register map shown in Figure 4 will shut down after the delay time set in the register map shown in Figure 7 has elapsed since the value was written to OFF_ADD_EN2.

[0083] In the modified example, the register map shown in Figure 8B may be used. Here, ON / OFF_ADD_EN1 and ON / OFF_ADD_EN2, which are 1-bit data, are stored.

[0084] When "1" is written to ON / OFF_ADD_EN1 via I2C communication, the power supply circuit for channels whose first additional enable function has been enabled by "ADD_EN1" in the register map shown in Figure 4 will be activated after the delay time set in the register map shown in Figure 3 has elapsed since the value was written to ON / OFF_ADD_EN1.

[0085] When ON / OFF_ADD_EN1 is overwritten to "0" via I2C communication, the power supply circuit for channels whose first additional enable function is enabled by "ADD_EN1" in the register map shown in Figure 4 will shut down after the delay time set in the register map shown in Figure 7 has elapsed since the value was written to ON / OFF_ADD_EN1.

[0086] When "1" is written to ON / OFF_ADD_EN2 via I2C communication, the power supply circuit for channels whose second additional enable function has been enabled by "ADD_EN2" in the register map shown in Figure 4 will be activated after the delay time set in the register map shown in Figure 3 has elapsed since the value was written to ON / OFF_ADD_EN2.

[0087] When ON / OFF_ADD_EN2 is overwritten to "1" and written to "0" via I2C communication, the power supply circuit for channels whose second additional enable function is enabled by "ADD_EN2" in the register map shown in Figure 4 will shut down after the delay time set in the register map shown in Figure 7 has elapsed since the value was written to ON / OFF_ADD_EN2.

[0088] In this modified example, instead of an additional enable signal, startup and shutdown timing control can be triggered by writing to a register via I2C communication.

[0089] <Power supply system> Next, an example of the configuration of a power supply system (also called a power tree) using the semiconductor device 1 according to the embodiment of this disclosure described above will be explained.

[0090] Figure 9 shows the configuration of a power supply system 25 using a semiconductor device 1. The power supply system 25 comprises the semiconductor device 1, an EEPROM 10, a primary DC / DC converter 15, and an SoC 20.

[0091] The primary DC / DC converter 15 supplies the input voltage VIN generated by the DC / DC conversion to the semiconductor device 1 and the EEPROM 10. The primary DC / DC converter 15 also inputs a standby signal STBY and an enable signal EN to the semiconductor device 1. The SoC 20 is supplied with the output voltages generated by the step-down power supply circuits 51-54 (BUCK1-BUCK4) and LDO circuits 55,56 (LDO5,6) in the semiconductor device 1.

[0092] The SoC20 inputs additional enable signals ADD_EN1 and ADD_EN2 to the semiconductor device 1. This allows for startup and shutdown timing control according to the timings occurring on the SoC20 side. In addition, the reset signal PRSTB and additional reset signals ADD_PRSTB1 and ADD_PRSTB2 are input from the semiconductor device 1 to the SoC20. The additional reset signals ADD_PRSTB1 and ADD_PRSTB2 notify the SoC20 that the startup of the channels for which the first and second additional enable functions have been enabled is complete.

[0093] Note that the additional enable signal ADD_EN1 and the additional reset signal ADD_PRSTB1 For each of the pairs, including the additional enable signal ADD_EN2 and the additional reset signal ADD_PRSTB2, a separate SoC may be provided.

[0094] Figure 10 shows an example of another power supply system using semiconductor device 1. The power supply system 35 shown in Figure 10 differs from the power supply system 25 shown in Figure 9 in that it includes a sequencer 30. The sequencer 30 inputs additional enable signals ADD_EN1 and ADD_EN2 to the semiconductor device 1. This allows for startup and shutdown timing control according to the timing commanded by the sequencer 30.

[0095] The configuration of the power supply system using the semiconductor device 1 is not limited to the above and can take various forms. For example, the additional enable signal may be input to the semiconductor device 1 from the primary DC / DC converter 15, or it may be input to the semiconductor device 1 from the microcontroller. Also, the additional reset signal may be input to the microcontroller from the semiconductor device 1.

[0096] Furthermore, if an additional enable signal is not used, startup and shutdown timing control can be performed, for example, by I2C communication between the SoC and the semiconductor device 1, as in the modified example described above.

[0097] <Vehicle> Figure 11 is an external view showing one example configuration of vehicle X. In this example configuration, vehicle X is equipped with various electronic devices X11 to X18 that operate using power supplied from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in Figure 11 may differ from those in reality for illustrative purposes.

[0098] Electronic device X11 is an engine control unit that performs engine-related controls (such as injection control, electronic throttle control, idle control, oxygen sensor heater control, and auto cruise control).

[0099] Electronic device X12 is a lamp control unit that controls the on / off state of lights such as HID (high-intensity discharged lamps) and DRL (daytime running lamps).

[0100] Electronic device X13 is a transmission control unit that performs control related to the transmission.

[0101] The electronic device X14 is a body control unit that performs control related to the motion of vehicle X (such as ABS [anti-lock brake system] control, EPS [electric power steering] control, and electronic suspension control).

[0102] Electronic device X15 is a security control unit that controls the operation of door locks, burglary alarms, and other devices.

[0103] Electronic equipment X16 consists of electronic components that are installed in vehicle X at the factory as standard equipment or manufacturer options, including wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroof, and power seats.

[0104] Electronic equipment X17 is an electronic device that can be optionally installed in vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0105] Electronic equipment X18 is a type of electronic equipment equipped with high-voltage motors, such as automotive blowers, oil pumps, water pumps, and battery cooling fans.

[0106] Furthermore, the power supply system including the aforementioned semiconductor device 1 may be applied to any of the electronic devices X11 to X18.

[0107] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0108] <Note> As described above, the semiconductor device (1) according to one aspect of this disclosure is Multiple channel power supply circuits (51-57), A first input section (EN terminal) configured to receive the first input signal, A second input section (ADDEN1 terminal or I2C communication terminal) configured to receive a second input signal, Equipped with, The assignment of channels in the power supply circuit to the enable function using the first input signal and the additional enable function using the second input signal, respectively, First delay time information relating to the elapsed time from when the first input signal indicating activation is input until the channel to which the enable function is assigned is activated, The system is configured to allow setting of a second delay time information relating to the elapsed time from when the second input signal indicating activation is input until the channel to which the additional enable function is assigned is activated (first configuration).

[0109] This configuration allows for greater flexibility in setting the startup timing of the power supply circuit.

[0110] Furthermore, in the first configuration described above, the first input signal is an enable signal that can take on a high level or a low level. The channel to which the enable function is assigned may be configured to start up at a time corresponding to the elapsed time indicated by the first delay time information after the enable signal switches to a level indicating activation (second configuration).

[0111] Furthermore, in the second configuration described above, the second input signal is an additional enable signal that can take a high level or a low level. The channel to which the additional enable function is assigned may be configured to start up at a time equal to the elapsed time indicated by the second delay time information after the additional enable signal switches to a level indicating activation (third configuration).

[0112] Furthermore, in the third configuration described above, the additional enable signal may be configured to be input to the first input unit for the enable function and a function other than the additional enable function (fourth configuration).

[0113] Furthermore, in the fourth configuration described above, the other function may be a synchronization function for synchronizing the switching frequency of the power supply circuit with an external clock, or a communication function with another semiconductor device (fifth configuration).

[0114] Furthermore, in the second configuration described above, a register is further provided, The aforementioned second input signal is a serial communication signal. The channel to which the additional enable function has been assigned may be configured to activate when information indicating activation is written to the register by the serial communication signal, at a timing equal to the elapsed time indicated by the second delay time information after the information has been written (sixth configuration).

[0115] Furthermore, in any of the above configurations 1 to 6, the first delay time information may be configured such that the step length increases as the set time increases (configuration 7).

[0116] Furthermore, in any of the first to seventh configurations described above, a third delay time information relating to the elapsed time from when the first input signal indicating shutdown is input until the channel to which the enable function is assigned shuts down, The system may be configured to allow setting of a fourth delay time information relating to the elapsed time from when the second input signal indicating shutdown is input until the channel to which the additional enable function is assigned shuts down (eighth configuration).

[0117] Furthermore, in any of the above configurations 1 to 8, a first output unit configured to output a reset signal is further provided. Assignment of the reset signal to the additional enable function, The system may also be configured to allow setting of a fifth delay time information relating to the elapsed time from when the second input signal indicating startup is input until the reset signal transitions to the reset release state (ninth configuration).

[0118] Furthermore, the ninth configuration described above further includes a second output unit configured to output an additional reset signal, Assignment of the additional reset signal to the additional enable function, The system may be configured to allow setting of a sixth delay time information relating to the elapsed time from when the last channel to be started up among the channels to which the additional enable function is assigned completes to start up until the additional reset signal transitions to the reset release state (10th configuration).

[0119] Furthermore, in the tenth configuration described above, the additional reset signal may be configured to be output from the second output unit for a function other than the power-on reset function (eleventh configuration).

[0120] Furthermore, a power supply system (25) according to one aspect of the present disclosure comprises a semiconductor device having any of the first to eleventh configurations described above, and an external device (20) configured to supply an output voltage generated based on the power supply circuit (the twelfth configuration).

[0121] Furthermore, in the 12th configuration described above, the second input signal may be configured to be input from the external device to the semiconductor device (13th configuration).

[0122] Furthermore, in the 13th configuration described above, the external device may be configured to be an SoC (14th configuration).

[0123] Furthermore, in any of the configurations described in the 12th to 14th above, a sequencer (30) may be further provided, and the second input signal may be configured to be input from the sequencer to the semiconductor device (configuration 15th).

[0124] Furthermore, a vehicle (X) according to one aspect of this disclosure includes a power supply system with any of the configurations described in the 12th to 15th (configuration 16th).

[0125] Furthermore, the communication system of the 10th configuration described above may be mountable in a vehicle (11th configuration). [Industrial applicability]

[0126] This disclosure can be used, for example, in power supply systems for various applications. [Explanation of Symbols]

[0127] 1 Semiconductor device 2 Internal power circuit 3 SYNC circuit 4. Control Unit 15 Primary DC / DC Converter 25 Power supply systems 30 Sequencer 35 Power supply system 41 Registers 51-54 Step-down power supply circuit 55-57 LDO Circuit C1, C2 Capacitors Co1 Output Capacitor Lo1 Inductor L1, first side L2, second side L3, third side L4, 4th side Rp1~RP7 Pull-up resistors X Vehicle X11~X18 Electronic Machines

Claims

1. A multi-channel power supply circuit, A first input section configured to receive a first input signal, A second input section configured to receive a second input signal, Equipped with, The assignment of channels in the power supply circuit to the enable function using the first input signal and the additional enable function using the second input signal, respectively, First delay time information relating to the elapsed time from when the first input signal indicating activation is input until the channel to which the enable function is assigned is activated, A semiconductor device configured to allow setting of a second delay time information relating to the elapsed time from when the second input signal indicating startup is input until the channel to which the additional enable function is assigned is activated.

2. The first input signal is an enable signal that can take a high or low level. The semiconductor device according to claim 1, wherein the channel to which the enable function is assigned is activated at a timing equal to the elapsed time indicated by the first delay time information after the enable signal switches to a level indicating activation.

3. The second input signal is an additional enable signal that can take a high or low level. The semiconductor device according to claim 2, wherein the channel to which the additional enable function is assigned is activated at a timing equal to the elapsed time indicated by the second delay time information after the additional enable signal switches to a level indicating activation.

4. The semiconductor device according to claim 3, wherein the additional enable signal can be input to the first input for the enable function and a function other than the additional enable function.

5. The semiconductor device according to claim 4, wherein the other function is a synchronization function for synchronizing the switching frequency of the power supply circuit with an external clock, or a communication function with another semiconductor device.

6. With additional registers, The aforementioned second input signal is a serial communication signal. The semiconductor device according to claim 2, wherein the channel to which the additional enable function is assigned is activated when information indicating activation is written to the register by the serial communication signal, at a timing equal to the elapsed time indicated by the second delay time information after the information has been written.

7. The semiconductor device according to claim 1, wherein the steps of the first delay time information become longer as the set time increases.

8. Third delay time information relating to the elapsed time from when the first input signal indicating shutdown is input until the channel to which the enable function is assigned shuts down, The semiconductor device according to claim 1, configured to set a fourth delay time information relating to the elapsed time from when the second input signal indicating shutdown is input until the channel to which the additional enable function is assigned shuts down.

9. The system further includes a first output section configured to output a reset signal, Assignment of the reset signal to the additional enable function, The semiconductor device according to claim 1, configured to allow setting of a fifth delay time information relating to the elapsed time from when the second input signal indicating startup is input until the reset signal transitions to the reset release state.

10. The system further includes a second output section configured to output an additional reset signal, Assignment of the additional reset signal to the additional enable function, The semiconductor device according to claim 9, wherein it is configured to set a sixth delay time information relating to the elapsed time from when the last channel to be started among the channels to which the additional enable function is assigned has finished starting up until the additional reset signal transitions to the reset release state.

11. The semiconductor device according to claim 10, wherein the additional reset signal can be output from the second output unit for a function other than the power-on reset function.

12. A power supply system comprising a semiconductor device according to claim 1, and an external device configured to supply an output voltage generated based on the power supply circuit.

13. The power supply system according to claim 12, wherein the second input signal can be input to the semiconductor device from the external device.

14. The power supply system according to claim 13, wherein the external device is an SoC.

15. Equipped with a sequencer, The power supply system according to claim 12, wherein the second input signal can be input from the sequencer to the semiconductor device.

16. A vehicle comprising the power supply system according to any one of claims 12 to 15.

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