Memory drive device, information processing device, and control method

Abstract

The present invention provides a memory drive device, an information processing device, and a control method that reduce data corruption due to retention characteristics and improve reliability. [Solution] The SSD (Solid State Drive) in the information processing device 100 comprises a data storage unit including a data storage area and a test storage area, and a control unit. The data storage area is composed of rewritable non-volatile memory and stores data used for information processing. The test storage area is composed of non-volatile memory and stores predetermined test data. The control unit determines that a predetermined data retention period has been reached if the date and time information obtained from the information processing device is accurate and the power outage period based on the date and time information exceeds a threshold period. If the date and time information is inaccurate, the control unit determines that a predetermined data retention period has been reached based on an index value related to storage failures in the test storage area and performs a rewrite of the already stored data to the data storage area.

Description

Technical Field

[0001] The present invention relates to a memory drive device, an information processing device, and a control method.

Background Art

[0002] In recent years, memory drive devices such as SSDs (Solid State Drives) are known (for example, see Patent Document 1). In such a memory drive device, for example, a non-volatile memory such as a NAND type (negative logic product type) flash memory is used.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a rewritable non-volatile memory such as a NAND type flash memory, the written data may be corrupted over time. Such a characteristic that data corruption occurs over time is called a retention characteristic, and this data retention period is called a retention period. In the conventional memory drive device described above, it is difficult to grasp how much time has passed since the data was written. Therefore, for example, when the retention period is exceeded, data corruption may occur.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide a memory drive device, an information processing device, and a control method capable of reducing data corruption due to retention characteristics and improving reliability.

Means for Solving the Problems

[0006] To solve the above problems, one aspect of the present invention is a memory drive device having a rewritable non-volatile memory, comprising: a data storage area composed of the non-volatile memory and capable of storing data used for information processing; a test storage area composed of the non-volatile memory and storing predetermined test data; and a control unit that, when a predetermined data retention period is reached, rewrites the data already stored in the data storage area. The control unit calculates the power-off period of the host device based on date and time information obtained from a host device to which the memory drive device is connected, and determines that the predetermined data retention period has been reached if the obtained date and time information is accurate and the power-off period exceeds a threshold period. If the date and time information is inaccurate, the control unit determines that the predetermined data retention period has been reached based on an index value related to storage failures in the test storage area where the predetermined test data is pre-stored.

[0007] Furthermore, in one aspect of the present invention, in the memory drive device described above, the power-off period may be calculated based on first date and time information, which is date and time information obtained when the higher-level device is started, obtained from the BIOS (Basic Input Output System) of the higher-level device, and second date and time information, which is date and time information when the memory drive device is powered off. Based on the time relationship between the first date and time information and the second date and time information, it may be determined whether or not the acquired date and time information is accurate.

[0008] Furthermore, in one aspect of the present invention, in the memory drive device described above, the index value includes the bit error rate when reading the test data from the test storage area, and the control unit may determine that the predetermined data retention period has been reached based on the bit error rate as the index value if the date and time information is inaccurate.

[0009] Furthermore, in one aspect of the present invention, in the memory drive device described above, the control unit may, when the date and time information is accurate, adopt the longer of a first power-off period calculated based on the first date and time information and the second date and time information and a second power-off period estimated based on the bit error rate as the power-off period; when the date and time information is inaccurate, adopt the second power-off period as the power-off period; and when the power-off period exceeds the threshold period, determine that the predetermined data retention period has been reached and perform a rewrite of the already stored data to the data storage area.

[0010] Furthermore, in one aspect of the present invention, the memory drive device may be equipped with a warning processing unit that, when the acquired date and time information is accurate, estimates the mean ambient temperature of the host device based on the difference between the first power-off period and the second power-off period, and outputs warning information to the host device when the mean ambient temperature is equal to or greater than a threshold temperature.

[0011] Furthermore, in one aspect of the present invention, the memory drive device described above includes an estimation correction unit that estimates the second power outage period using an estimation model that estimates the power outage period from the bit error rate, and corrects the estimation model so that the first power outage period and the second power outage period coincide if the difference between the first power outage period and the second power outage period is greater than or equal to a certain period.

[0012] Furthermore, in one aspect of the present invention, in the memory drive device described above, the control unit may rewrite the already stored data to the data storage area if the date and time information is inaccurate and the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached.

[0013] Furthermore, in one aspect of the present invention, in the memory drive device described above, the control unit may rewrite the already stored data to the data storage area if the date and time information is inaccurate and the amount of change in the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached.

[0014] Furthermore, one aspect of the present invention is an information processing device which is a higher-level device that includes the above-mentioned memory drive device and performs information processing using the data stored in the memory drive device.

[0015] Furthermore, one aspect of the present invention is a control method for a memory drive device having a rewritable non-volatile memory, comprising a data storage area composed of the non-volatile memory and capable of storing data used for information processing, and a test storage area composed of the non-volatile memory and storing predetermined test data, wherein the control unit calculates the power-off period of the host device based on date and time information obtained from the host device to which the memory drive device is connected, determines that a predetermined data retention period has been reached if the obtained date and time information is accurate and the power-off period exceeds a threshold period, determines that a predetermined data retention period has been reached if the date and time information is inaccurate, determines that the predetermined data retention period has been reached based on an index value related to storage failures for the test storage area in which the predetermined test data is previously stored, and when the predetermined data retention period has been reached, performs a control method to rewrite the data already stored in the data storage area. [Effects of the Invention]

[0016] According to the above embodiment of the present invention, data corruption due to retention characteristics can be reduced, thereby improving reliability. [Brief explanation of the drawing]

[0017] [Figure 1] This figure shows an example of the main hardware configuration of the information processing device and SSD according to the first embodiment. [Figure 2]It is a block diagram showing an example of the functional configuration of the SSD according to the first embodiment. [Figure 3] It is a flowchart showing an example of the operation of the SSD according to the first embodiment. [Figure 4] It is a flowchart showing an example of the correction process of the estimation model of the SSD according to the first embodiment. [Figure 5] It is a flowchart showing an example of the warning process of the SSD according to the first embodiment. [Figure 6] It is a block diagram showing an example of the functional configuration of the SSD according to the second embodiment. [Figure 7] It is a flowchart showing an example of the operation of the SSD according to the second embodiment. [Figure 8] It is a block diagram showing an example of the functional configuration of the SSD according to the third embodiment. [Figure 9] It is a flowchart showing an example of the operation of the SSD according to the third embodiment.

Modes for Carrying Out the Invention

[0018] Hereinafter, a memory drive device, an information processing device, and a control method according to an embodiment of the present invention will be described with reference to the drawings.

[0019] [First Embodiment] FIG. 1 is a diagram showing an example of the main hardware configuration of the information processing device 100 and the SSD 40 according to the first embodiment. As shown in FIG. 1, the information processing device 100 is, for example, a notebook personal computer, and includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40.

[0020] The CPU (Central Processing Unit) 11 executes various arithmetic processes under program control and controls the entire information processing device 100.

[0021] Main memory 12 is writable memory used as a reading area for the CPU 11's executable program, or as a work area for writing processing data for the executable program. Main memory 12 is composed of, for example, multiple DRAM (Dynamic Random Access Memory) chips. This executable program includes the OS (operating system), various drivers for hardware operation of peripheral devices, various services / utilities, application programs, etc.

[0022] The video subsystem 13 is a subsystem for implementing functions related to image display and includes a video controller. This video controller processes drawing commands from the CPU 11, writes the processed drawing information to video memory, reads this drawing information from video memory, and outputs it to the display unit 14 as drawing data (display data).

[0023] The display unit 14 is, for example, a liquid crystal display, and displays a screen based on drawing data (display data) output from the video subsystem 13.

[0024] The chipset 21 includes controllers for USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count) bus, and multiple devices are connected to it. In Figure 1, as examples of devices, the BIOS memory 22 and SSD 40 are connected to the chipset 21. The CPU 11 and chipset 21 correspond to the main control unit 10.

[0025] The BIOS (Basic Input Output System) memory 22 consists of electrically rewritable non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) or flash ROM (flash memory). The BIOS memory 22 stores the BIOS and system firmware for controlling the embedded controller 31, etc.

[0026] The SSD (Solid State Drive) 40 (an example of a memory drive device) is a memory drive device having rewritable non-volatile memory, and stores the OS, various drivers, various services / utilities, application programs, and various data. The information processing device 100 performs various information processing using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21, for example, by serial ATA or PCI-Express bus. The SSD 40 may also be connected to the CPU 11. In this embodiment, the SSD 40 is assumed to be connected to the chipset 21 by an NVMe connection using a PCI-Express bus. The SSD 40 also includes multiple flash memory devices 41 and a memory controller 42.

[0027] Flash memory 41 is, for example, NAND flash memory, an example of rewritable non-volatile memory. Flash memory 41 writes data ("0") or erases data ("1") to memory cells by injecting or extracting electrons from the floating gate of the memory cell. In flash memory 41, data corruption may occur over time as electrons move in the floating gate. In flash memory 41, this characteristic of data corruption occurring over time is called retention characteristic, and this data retention period is called retention period. Furthermore, this retention period tends to be shorter as the temperature increases.

[0028] The memory controller 42 is a processor that includes, for example, a CPU, ROM, RAM, etc. (not shown), and comprehensively controls the SSD 40. The memory controller 42 performs processes such as controlling the host interface (host I / F) with the chipset 21, controlling the memory interface (memory I / F) with the flash memory 41, and managing the data of the flash memory 41.

[0029] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing device 100. The embedded controller 31 also has a power management function that controls the power supply circuit 33. The embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and is equipped with multiple channels of A / D input terminals, D / A output terminals, a timer, and digital input / output terminals. The embedded controller 31 is connected to, for example, the input unit 32 and the power supply circuit 33 via these input / output terminals, and the embedded controller 31 controls the operation of these components.

[0030] The input unit 32 is, for example, an input device such as a keyboard, a pointing device, or a touchpad.

[0031] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, and an AC / DC adapter, and converts a DC voltage supplied from an external power source or battery into multiple voltages necessary to operate the information processing device 100. The power supply circuit 33 also supplies power to each part of the information processing device 100 based on control from the embedded controller 31.

[0032] Next, with reference to Figure 2, the functional configuration of the SSD40 according to this embodiment will be described. Figure 2 is a block diagram showing an example of the functional configuration of the SSD40 according to this embodiment.

[0033] As shown in Figure 2, the SSD 40 comprises a data storage unit 50 and a control unit 60. The SSD40 is connected to the main control unit 10 of the higher-level device (information processing device 100) via an NVMe connection.

[0034] The main control unit 10 is a functional unit realized by the CPU 11 and chipset 21 executing programs stored in the main memory 12, and it performs various processes based on the OS. For example, the main control unit 10 performs information processing using data stored in the SSD 40. The main control unit 10 also starts the OS (for example, Windows®) by executing a BIOS program. The main control unit 10 includes, for example, a BIOS processing unit 101.

[0035] The BIOS processing unit 101 is a functional unit that is implemented by having the CPU 11 execute the BIOS program, and it performs various BIOS processes. For example, the BIOS processing unit 101 performs the process of starting the OS. Also, when the information processing unit 100 is started, the BIOS processing unit 101 sends a timestamp (date and time information) to the SSD 40 using the NVMe Timestamp function.

[0036] The data storage unit 50 is a storage unit composed of, for example, the above-described multiple flash memories 41, and includes, for example, a data storage area 51, an ECC (Error Correction Code) storage area 52, a test storage area 53, a timestamp storage area 54, and an estimated model storage unit 55.

[0037] The data storage area 51 is composed of flash memory 41 and is a storage area capable of storing data used for information processing. The data storage area 51 stores, for example, the OS, various drivers, various services / utilities, application programs, and various data.

[0038] The ECC memory area 52 is composed of flash memory 41 and is a memory area that stores error correction codes (ECC) that correct errors in the data stored in the data memory area 51 and the test memory area 53. For example, when data is stored (written) in the data memory area 51 or the test memory area 53, the error correction code (ECC) corresponding to that data is stored in the ECC memory area 52.

[0039] The test storage area 53 is composed of flash memory 41 and stores predetermined test data. The test storage area 53 stores test data for determining whether a predetermined data retention period, which indicates a predetermined period of time since data writing, has been reached. For example, test data is stored in the test storage area 53 when the information processing device 100 is shipped. In addition, for example, the test data may be re-stored (rewritten) in the test storage area 53 when the OS is reinstalled after the information processing device 100 has been shipped.

[0040] The timestamp storage area 54 is composed of flash memory 41 and stores BIOS timestamps (startup timestamps) obtained from the BIOS, shutdown timestamps (power-off timestamps), etc. The timestamp storage area 54 may also store a history of past BIOS timestamps and power-off timestamps.

[0041] The estimation model storage unit 55 is composed of flash memory 41 and stores an estimation model for estimating the power-off read time from the bit error rate (hereinafter referred to as BER (Bit Error Rate)) when reading test data from the test storage area 53. The power-off read time indicates the period during which the information processing device 100 is powered off.

[0042] The estimation model estimates the power-off lead time from the BER by using, for example, the following equation (1) which shows the estimable data retention period (AF), and historical values ​​of BER and power-off lead time.

[0043]

number

[0044] In equation (1), k represents the Boltzmann constant and H represents the activation energy. T1 represents the test temperature (43°C = 316.15 K (Kelvin)), and T2 represents the actual temperature.

[0045] The control unit 60 is a functional unit realized by the memory controller 42 described above, and performs various processes on the SSD 40. The control unit 60 comprises a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65, a count processing unit 66, a correction processing unit 67, and a warning processing unit 68.

[0046] The host I / F processing unit 61 controls the interface between the chipset 21 and the SSD 40. For example, the host I / F processing unit 61 controls the PCI-Express bus (NVMe) interface and accepts commands such as data writing and reading from the chipset 21. The host I / F processing unit 61 also outputs output information, such as data read from the data storage unit 50, to the chipset 21 via the PCI-Express bus (NVMe) interface. The host I / F processing unit 61 may also control the interface between the CPU 11 and the SSD 40.

[0047] The memory I / F processing unit 62 controls the interface between the control unit 60 (memory controller 42) and the data storage unit 50 (multiple flash memories 41). The memory I / F processing unit 62 controls the flash memories 41 by outputting commands such as erase, write, and read commands to the flash memories 41.

[0048] The data management unit 63 manages the correspondence between the logical address of the SSD 40 used for control from the information processing device 100 and the physical address of the data storage unit 50 (flash memory 41), and also manages the data stored in the data storage unit 50. The data management unit 63 executes various processes based on various commands received from the chipset 21 by the host I / F processing unit 61.

[0049] The ECC processing unit 64 (an example of a correction processing unit) corrects errors in the data read from the data storage unit 50 based on the ECC (error correction code). For example, the ECC processing unit 64 determines whether or not data corruption (bit corruption) has occurred based on the read data and the ECC corresponding to the read data, and if data corruption (bit corruption) has occurred, it performs error correction processing using the ECC to correct the data corruption.

[0050] The test processing unit 65 performs a rewrite of the already stored data to at least the data storage area 51 when the SSD 40 reaches a predetermined data retention period. The test processing unit 65 determines whether the predetermined data retention period has been reached by switching between, for example, a power-off read time A (first power-off period) based on a timestamp (BIOS timestamp) obtained from the main control unit 10 (higher-level device) and a power-off read time B (second power-off period) based on the BER of the test storage area 53.

[0051] The test processing unit 65 calculates the power-off lead time (power-off period) of the host device (main control unit 10 of the information processing device 100) to which the SSD 40 is connected, based on the BIOS timestamp (date and time information) obtained from the host device. For example, the test processing unit 65 calculates the power-off lead time A by the difference between the obtained BIOS timestamp (first date and time information) and the timestamp stored in the timestamp storage area 54 (past timestamps such as the power-off timestamp (second power-off period)).

[0052] Furthermore, the test processing unit 65 estimates the power-off read time B based on an index value related to storage failures for the test storage area 53, in which predetermined test data is pre-stored. The index value related to storage failures includes, for example, the bit error rate (BER) when reading the test data from the test storage area 53. The test processing unit 65 calculates the BER from the test storage area 53 and estimates the power-off read time B from the calculated BER, for example, using an estimation model stored in the estimation model storage unit 55.

[0053] Furthermore, the test processing unit 65 determines whether the acquired BIOS timestamp is accurate. The test processing unit 65 determines whether the acquired BIOS timestamp is accurate based, for example, on whether there is a discrepancy between the acquired BIOS timestamp and the timestamp stored in the timestamp storage area 54. In other words, the test processing unit 65 determines whether the acquired BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp.

[0054] Possible reasons for an inaccurate BIOS timestamp include, for example, the RTC (Real Time Clock) on the chipset 21 of the information processing unit 100 being reset, or the battery (backup power supply) for the RTC running out of power.

[0055] The test processing unit 65 adopts the longer of power-off lead time A and power-off lead time B as the power-off lead time if the acquired BIOS timestamp is accurate. If the acquired BIOS timestamp is inaccurate, the test processing unit 65 adopts power-off lead time B as the power-off lead time.

[0056] Furthermore, the test processing unit 65 determines that a predetermined data retention period has been reached when the power-off read time exceeds a threshold period, and performs a rewrite of the already stored data to the data storage area 51. In other words, the test processing unit 65 determines that a predetermined data retention period has been reached when the acquired BIOS timestamp is accurate and the power-off read time exceeds a threshold period, and performs a rewrite of the already stored data to the data storage area 51.

[0057] The test processing unit 65, via the memory I / F processing unit 62, saves the data already stored in the data storage area 51 to a buffer storage unit composed of RAM (not shown), and then rewrites (restores) the data.

[0058] Furthermore, if the acquired BIOS timestamp is inaccurate, the test processing unit 65 adopts the power-off lead time B as the power-off lead time. Therefore, if the timestamp is inaccurate, it determines that a predetermined data retention period has been reached based on an index value (e.g., BER) related to memory failures in the test storage area 53.

[0059] Furthermore, when the test processing unit 65 performs a rewrite of data already stored in the data storage area 51, it may also rewrite data in other areas (such as the test storage area 53, timestamp storage area 54, and estimated model storage unit 55) at the same time.

[0060] The counting unit 66 stores the acquired BIOS timestamp in the timestamp storage area 54 and uses the SSD 40's internal clock to count the date and time from the BIOS timestamp.

[0061] The correction processing unit 67 corrects the estimated model so that power-off lead time A and power-off lead time B match if the difference between power-off lead time A and power-off lead time B is greater than a certain period of time. For example, the correction processing unit 67 adjusts the activation energy H in equation (1) above to correct the estimated model so that power-off lead time A and power-off lead time B match. The correction processing unit 67 stores the corrected estimated model in the estimated model storage unit 55.

[0062] The warning processing unit 68 estimates the mean ambient temperature of the information processing device 100 (higher-level device) based on the difference between power-off lead time A and power-off lead time B, provided that the acquired BIOS timestamp is accurate. The warning processing unit 68 estimates the mean ambient temperature of the information processing device 100 (higher-level device) using, for example, the equation (1) described above. If the mean ambient temperature is above the threshold temperature, the warning processing unit 68 outputs warning information (for example, a warning message) to the higher-level device (the main control unit 10 of the information processing device 100). Here, the threshold temperature is, for example, a predetermined temperature that exceeds the upper limit of the guaranteed storage temperature of the SSD 40, and the warning processing unit 68 sends a message to the main control unit 10 warning that the SSD 40 was stored above the upper limit of the guaranteed storage temperature, causing the information processing device 100 to output it.

[0063] Next, the operation of the SSD40 according to this embodiment will be described with reference to the drawings. Figure 3 is a flowchart illustrating an example of the operation of the SSD 40 according to this embodiment. Here, we will explain the process by which the SSD 40 prevents data corruption due to retention.

[0064] As shown in Figure 3, the control unit 60 of the SSD 40 first obtains a timestamp from the BIOS of the information processing device 100 (step S101). The test processing unit 65 of the control unit 60 obtains the timestamp transmitted by the BIOS processing unit 101 of the main control unit 10 using the NVMe Timestamp function as the BIOS timestamp (first date and time information). The count processing unit 66 of the control unit 60 stores the obtained BIOS timestamp in the timestamp storage area 54 and counts the date and time from the BIOS timestamp using the internal clock of the SSD 40.

[0065] Next, the test processing unit 65 calculates the power-off lead time A based on the acquired timestamp and the timestamp of the previous power-off (step S102). For example, the test processing unit 65 calculates the power-off lead time A by the difference between the acquired BIOS timestamp and the power-off timestamp stored in the timestamp storage area 54.

[0066] Next, the test processing unit 65 calculates the BER of the test memory area 53 (step S103). The test processing unit 65 reads the test data from the test memory area 53 via the memory I / F processing unit 62 and calculates the BER.

[0067] Next, the test processing unit 65 estimates the power-off lead time B from the BER (step S104). The test processing unit 65 estimates the power-off lead time B from the BER using the estimation model stored in the estimation model storage unit 55.

[0068] Next, the test processing unit 65 determines whether the timestamp obtained from the BIOS is accurate (step S105). The test processing unit 65 determines whether the obtained BIOS timestamp is accurate based, for example, on whether there is a discrepancy between the obtained BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65 determines whether the obtained BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp. If the BIOS timestamp is accurate (step S105: YES), the test processing unit 65 proceeds to step S106. If the BIOS timestamp is not accurate (step S105: NO), the test processing unit 65 proceeds to step S107.

[0069] In step S106, the test processing unit 65 adopts the longer of power-off lead time A and power-off lead time B as the power-off lead time. After the processing in step S106, the test processing unit 65 proceeds to step S108.

[0070] Furthermore, in step S107, the test processing unit 65 adopts power-off lead time B as the power-off lead time. After the processing in step S107, the test processing unit 65 proceeds to step S108.

[0071] Next, in step S108, the test processing unit 65 determines whether the power-off lead time has exceeded the threshold period. If the power-off lead time has exceeded the threshold period (step S108: YES), the test processing unit 65 determines that the predetermined data retention period has been reached and proceeds to step S109. If the power-off lead time has not exceeded the threshold period (is less than or equal to the threshold period) (step S108: NO), the test processing unit 65 determines that the predetermined data retention period has not been reached and proceeds to step S110.

[0072] In step S109, the test processing unit 65 performs a data refresh process. The test processing unit 65, for example, via the memory I / F processing unit 62, saves the data already stored in the data storage area 51 to a buffer storage unit composed of RAM (not shown), and then rewrites (restores) the data.

[0073] Next, in step S110, the test processing unit 65 determines whether or not it has received a shutdown request from the BIOS. The test processing unit 65 determines whether or not it has received a shutdown request command from the BIOS via the host I / F processing unit 61. If the test processing unit 65 has received a shutdown request from the BIOS (step S110: YES), it proceeds to step S111. If the test processing unit 65 has not received a shutdown request from the BIOS (step S110: NO), it returns to step S110.

[0074] In step S111, the test processing unit 65 stores a timestamp in the timestamp storage area 54 before shutdown. The test processing unit 65 stores the power-off timestamp (second date and time information) counted by the count processing unit 66 using the internal clock of the SSD 40 in the timestamp storage area 54. After the processing in step S111, the test processing unit 65 executes the shutdown process for the SSD 40 and terminates the process.

[0075] Next, with reference to Figure 4, the correction process for the SSD40 estimation model will be explained. Figure 4 is a flowchart showing an example of the correction process for the estimation model of SSD40 according to this embodiment.

[0076] As shown in Figure 4, the correction processing unit 67 of the control unit 60 determines whether the timestamp obtained from the BIOS is accurate (step S201). If the timestamp obtained from the BIOS (BIOS timestamp) is accurate (step S201: YES), the correction processing unit 67 proceeds to step S202. If the timestamp obtained from the BIOS (BIOS timestamp) is not accurate (step S201: NO), the correction processing unit 67 returns to step S201.

[0077] In step S202, the correction processing unit 67 determines whether the difference between power-off lead time A and power-off lead time B is greater than or equal to a certain period of time. If the difference between power-off lead time A and power-off lead time B is greater than or equal to a certain period of time (step S202: YES), the correction processing unit 67 proceeds to step S203. If the difference between power-off lead time A and power-off lead time B is less than a certain period of time (step S202: NO), the correction processing unit 67 returns to step S201.

[0078] In step S203, the correction processing unit 67 corrects the estimated model by recalibrating the test memory area 53. The correction processing unit 67 corrects the estimated model so that the power-off lead time A and the power-off lead time B match. For example, the correction processing unit 67 adjusts the activation energy H in equation (1) above so that the power-off lead time A and the power-off lead time B match. The correction processing unit 67 stores the corrected estimated model in the estimated model memory unit 55. After the processing in step S203, the correction processing unit 67 returns to step S201.

[0079] Next, we will explain the warning processing for SSD40, referring to Figure 5. Figure 5 is a flowchart showing an example of the warning processing of SSD40 according to this embodiment.

[0080] As shown in Figure 5, the warning processing unit 68 of the control unit 60 determines whether the timestamp obtained from the BIOS is accurate (step S301). If the timestamp obtained from the BIOS (BIOS timestamp) is accurate (step S301: YES), the warning processing unit 68 proceeds to step S302. If the timestamp obtained from the BIOS (BIOS timestamp) is not accurate (step S301: NO), the warning processing unit 68 returns to step S301.

[0081] In step S302, the warning processing unit 68 estimates the mean ambient temperature from the difference between power-off lead time A and power-off lead time B. The warning processing unit 68 estimates the mean ambient temperature of the information processing device 100 (higher-level device) using, for example, equation (1) described above.

[0082] Next, the warning processing unit 68 determines whether the mean ambient temperature is above or below the threshold temperature (step S303). If the mean ambient temperature is above or below the threshold temperature (step S303: YES), the warning processing unit 68 proceeds to step S303. If the mean ambient temperature is below the threshold temperature (step S303: NO), the warning processing unit 68 returns to step S301.

[0083] In step S304, the warning processing unit 68 sends a warning message to the information processing unit 100. For example, the warning processing unit 68 sends a warning message to the main control unit 10, which causes the information processing unit 100 to output a message warning that the product was stored above the upper limit of the guaranteed storage temperature. After processing in step S203, the warning processing unit 68 returns to step S201.

[0084] As described above, the SSD 40 (memory drive device) according to this embodiment is a memory drive device having a rewritable flash memory 41 (non-volatile memory), and comprises a data storage area 51, a test storage area 53, and a control unit 60. The data storage area 51 is composed of the flash memory 41 and is an area capable of storing data used for information processing. The test storage area 53 is composed of the flash memory 41 and stores predetermined test data. When a predetermined data retention period is reached, the control unit 60 performs a rewrite of the data already stored in the data storage area 51. Based on the BIOS timestamp (date and time information) obtained from the host device (information processing device 100) to which the SSD 40 is connected, the control unit 60 calculates the power-off read time (power-off period) of the host device, and determines that the predetermined data retention period has been reached if the obtained BIOS timestamp is accurate and the power-off read time exceeds a threshold period. If the timestamp is inaccurate, the control unit 60 determines that the predetermined data retention period has been reached based on an index value (e.g., BER) related to storage failures for the test storage area 53 where predetermined test data is pre-stored.

[0085] As a result, the SSD 40 (memory drive device) according to this embodiment switches between determining when a predetermined data retention period has been reached based on the power-off read time (power-off period) derived from the BIOS timestamp (date and time information) acquired from the higher-level device (information processing device 100), and determining when a predetermined data retention period has been reached based on an index value (e.g., BER). Therefore, the SSD 40 (memory drive device) according to this embodiment can appropriately and reliably determine when a predetermined data retention period has been reached, allowing for appropriate rewriting to the data storage area 51 before data corruption occurs, thereby reducing data corruption due to retention characteristics and improving reliability.

[0086] In this embodiment, the control unit 60 calculates the power-off lead time based on the BIOS timestamp (first date and time information), which is a timestamp obtained from the BIOS of the host device when the host device is started up, and the power-off timestamp (second date and time information), which is a timestamp when the SSD 40 is powered off. The control unit 60 also determines whether the obtained BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp.

[0087] As a result, the SSD 40 according to this embodiment can easily calculate the power-off read time using the BIOS timestamp (first date and time information) and the power-off timestamp (second date and time information). Furthermore, the SSD 40 according to this embodiment can appropriately determine whether the BIOS timestamp is accurate or not based on the time relationship between the BIOS timestamp and the power-off timestamp. Therefore, the SSD 40 according to this embodiment can improve reliability by appropriately utilizing the power-off read time calculated from the BIOS timestamp to reduce data corruption due to retention characteristics.

[0088] Furthermore, in this embodiment, the index value includes the bit error rate (BER) when reading test data from the test storage area 53. If the BIOS timestamp is inaccurate, the control unit 60 determines that a predetermined data retention period has been reached based on the bit error rate (BER) as the index value.

[0089] As a result, the SSD 40 according to this embodiment can accurately determine the possibility of data corruption due to retention by utilizing the bit error rate (BER), even when it is not possible to know, for example, when the information processing device 100 is not running or when temperature changes have occurred. Therefore, the SSD 40 according to this embodiment can more appropriately reduce data corruption due to the retention characteristics of the flash memory 41.

[0090] Furthermore, in this embodiment, if the BIOS timestamp is accurate, the control unit 60 adopts the longer of the power-off lead time A (first power-off period) calculated based on the BIOS timestamp and the power-off timestamp, and the power-off lead time B (second power-off period) estimated based on the bit error rate (BER), as the power-off lead time. If the BIOS timestamp is inaccurate, the control unit 60 adopts power-off lead time B as the power-off lead time. When the power-off lead time exceeds a threshold period, the control unit 60 determines that a predetermined data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0091] As a result, the SSD 40 according to this embodiment can appropriately and accurately determine when a predetermined data retention period has been reached by using the more appropriate power-off read time among power-off read time A (first power-off period) and power-off read time B (second power-off period), thereby more appropriately reducing data corruption due to the retention characteristics of the flash memory 41.

[0092] Furthermore, the SSD 40 according to this embodiment includes a warning processing unit 68. If the acquired BIOS timestamp is accurate, the warning processing unit 68 estimates the mean ambient temperature of the host device based on the difference between power-off lead time A and power-off lead time B, and outputs warning information to the host device if the mean ambient temperature is above a threshold temperature. Here, the threshold temperature is, for example, a predetermined temperature that exceeds the upper limit of the guaranteed storage temperature of the SSD 40.

[0093] As a result, the SSD 40 according to this embodiment can output a warning to the user when it is stored in a high-temperature environment, such as when it is stored at a temperature exceeding the upper limit of the SSD 40's guaranteed storage temperature.

[0094] Furthermore, in this embodiment, the control unit 60 estimates the power-off read time B using an estimation model that estimates the power-off read time from the bit error rate. The SSD 40 according to this embodiment includes a correction processing unit 67. The correction processing unit 67 corrects the estimation model so that the power-off read time A and the power-off read time B match when the difference between the power-off read time A and the power-off read time B is greater than a certain period of time.

[0095] As a result, the SSD40 according to this embodiment can appropriately correct the estimation model when the difference between the power-off lead time A based on the BIOS timestamp and the power-off lead time B based on the BER becomes large, thereby improving the accuracy of power-off lead time estimation.

[0096] Furthermore, the information processing device 100 according to this embodiment is a higher-level device that includes the SSD 40 described above and performs information processing using the data stored in the SSD 40. As a result, the information processing device 100 according to this embodiment achieves the same effects as the SSD 40 according to this embodiment described above, reducing data corruption due to retention characteristics and improving reliability.

[0097] Furthermore, the control method according to this embodiment is a control method for an SSD 40 having a rewritable flash memory 41, a data storage area 51 composed of the flash memory 41 capable of storing data used for information processing, and a test storage area 53 composed of the flash memory 41 for storing predetermined test data, and includes a first processing step, a second processing step, and a third processing step. In the first processing step, the control unit 60 calculates the power-off read time of the host device (information processing device 100) to which the SSD 40 is connected based on a BIOS timestamp obtained from the host device, and determines that a predetermined data retention period has been reached if the obtained BIOS timestamp is accurate and the power-off read time exceeds a threshold period. In the second processing step, if the BIOS timestamp is inaccurate, the control unit 60 determines that a predetermined data retention period has been reached based on an index value (e.g., BER) related to storage failures for the test storage area 53 in which predetermined test data is pre-stored. In the third processing step, if the predetermined data retention period has been reached, the control unit 60 performs a rewrite of the data already stored in the data storage area 51.

[0098] As a result, the control method according to this embodiment has the same effect as the SSD40 according to this embodiment described above, reducing data corruption due to retention characteristics and improving reliability.

[0099] [Second Embodiment] Next, with reference to the drawings, the SSD40a according to the second embodiment will be described. In the second embodiment, a modified example is described in which the determination of whether a predetermined data retention period based on BER has been reached is made without using the power-off lead time.

[0100] Figure 6 is a block diagram showing an example of the functional configuration of the SSD40a according to this embodiment. As shown in Figure 6, the SSD 40a (an example of a memory drive device) comprises a data storage unit 50a and a control unit 60a.

[0101] In this figure, components identical to those in Figure 2 are given the same reference numerals, and their descriptions are omitted. Furthermore, the hardware configuration of the SSD 40a and the information processing device 100 according to this embodiment is the same as that of the first embodiment shown in Figure 1, and therefore its description is omitted here.

[0102] The data storage unit 50a is a storage unit composed of the above-described plurality of flash memories 41, and includes, for example, a data storage area 51, an ECC storage area 52, a test storage area 53, and a timestamp storage area 54. In this embodiment, the data storage unit 50a differs from the data storage unit 50 of the first embodiment in that it does not include an estimated model storage unit 55.

[0103] The control unit 60a is a functional unit realized by the memory controller 42 described above, and performs various processes on the SSD 40a. The control unit 60a comprises a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65a, and a count processing unit 66.

[0104] In this embodiment, the control unit 60a differs from the control unit 60 of the first embodiment in that it does not include a correction processing unit 67 and a warning processing unit 68, and the processing performed by the test processing unit 65a is different.

[0105] The test processing unit 65a calculates the power-off read time based on the BIOS timestamp if the BIOS timestamp is accurate. If the BIOS timestamp is accurate and the power-off read time exceeds a threshold period, the test processing unit 65a determines that a predetermined data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0106] Furthermore, the test processing unit 65a calculates the BER for the test storage area 53. If the BIOS timestamp is inaccurate and the BER reaches a predetermined threshold indicating that the predetermined data retention period has been reached, it determines that the predetermined data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0107] The details of the power-off lead time calculation process and the BER calculation process by the test processing unit 65a are the same as those of the test processing unit 65 in the first embodiment described above, so their explanation is omitted here.

[0108] Next, the operation of the SSD40a according to this embodiment will be described with reference to Figure 7. Figure 7 is a flowchart illustrating an example of the operation of the SSD40a according to this embodiment. Here, we will explain the process by which the SSD40a prevents data corruption due to retention.

[0109] In Figure 7, the processes from step S401 to step S403 are the same as the processes from step S101 to step S103 shown in Figure 3 above, so their explanation is omitted here. In this embodiment, in step S402, the test processing unit 65a calculates the power-off lead time A as the power-off lead time.

[0110] Next, in step S404, the test processing unit 65a determines whether the timestamp obtained from the BIOS is accurate. The test processing unit 65a determines whether the obtained BIOS timestamp is accurate based, for example, on whether there is a discrepancy between the obtained BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65a determines whether the obtained BIOS timestamp is accurate based on the time relationship between the BIOS timestamp and the power-off timestamp. If the BIOS timestamp is accurate (step S404: YES), the test processing unit 65a proceeds to step S405. If the BIOS timestamp is not accurate (step S404: NO), the test processing unit 65a proceeds to step S406.

[0111] In step S405, the test processing unit 65a determines whether the power-off lead time has exceeded the threshold period. If the power-off lead time has exceeded the threshold period (step S405: YES), the test processing unit 65a determines that the predetermined data retention period has been reached and proceeds to step S407. If the power-off lead time has not exceeded the threshold period (is less than or equal to the threshold period) (step S405: NO), the test processing unit 65a determines that the predetermined data retention period has not been reached and proceeds to step S408.

[0112] Furthermore, in step S406, the test processing unit 65a determines whether the BER is above a predetermined threshold. Here, the predetermined threshold is a value that indicates that a predetermined data retention period has been reached. That is, the test processing unit 65a determines, based on the BER, whether or not the predetermined data retention period has been reached. If the BER is above the predetermined threshold (step S406: YES), the test processing unit 65a proceeds to step S407. If the BER is below the predetermined threshold (step S406: NO), the test processing unit 65a proceeds to step S408.

[0113] In step S407, the test processing unit 65a performs a data refresh process. The test processing unit 65a, for example, via the memory I / F processing unit 62, saves the data already stored in the data storage area 51 to a buffer storage unit composed of RAM (not shown), and then rewrites (restores) the data.

[0114] The processes in steps S408 and S409 are the same as those in steps S110 and S111 shown in Figure 3 above, so their explanation is omitted here.

[0115] As described above, the SSD 40a according to this embodiment comprises a data storage area 51, a test storage area 53, and a control unit 60a. The control unit 60a calculates the power-off read time (power-off period) of the host device based on the BIOS timestamp (date and time information) obtained from the host device to which the SSD 40 is connected. If the obtained BIOS timestamp is accurate and the power-off read time exceeds a threshold period, the control unit 60a determines that a predetermined data retention period has been reached. Furthermore, if the timestamp is inaccurate, the control unit 60a determines that a predetermined data retention period has been reached based on an index value (e.g., BER) related to storage failures for the test storage area 53 where predetermined test data is pre-stored. When the predetermined data retention period has been reached, the control unit 60a performs a rewrite of the already stored data to the data storage area 51.

[0116] As a result, the SSD 40a according to this embodiment, like the SSD 40 of the first embodiment described above, can appropriately rewrite to the data storage area 51 before data corruption occurs, thereby reducing data corruption due to retention characteristics and improving reliability.

[0117] Furthermore, in this embodiment, if the BIOS timestamp is inaccurate and the bit error rate (BER) reaches a predetermined threshold indicating that a predetermined data retention period has been reached, the control unit 60a performs a rewrite of the already stored data to the data storage area 51.

[0118] As a result, the SSD40a according to this embodiment achieves the same effects as the SSD40 of the first embodiment described above, reducing data corruption due to retention characteristics and improving reliability.

[0119] [Third Embodiment] Next, with reference to the drawings, a third embodiment of the SSD40b will be described. In the third embodiment, a modification of the second embodiment is described in which the arrival of a predetermined data retention period is determined by the change in the metric value (BER).

[0120] Figure 8 is a block diagram showing an example of the functional configuration of the SSD40b according to this embodiment. As shown in Figure 8, the SSD 40b (an example of a memory drive device) comprises a data storage unit 50b and a control unit 60b.

[0121] In this figure, components identical to those in Figure 6 are given the same reference numerals, and their descriptions are omitted. Furthermore, the hardware configuration of the SSD 40b and the information processing device 100 according to this embodiment is the same as that of the first embodiment shown in Figure 1, and therefore its description is omitted here.

[0122] The data storage unit 50b is a storage unit composed of the above-described plurality of flash memories 41, and includes, for example, a data storage area 51, an ECC storage area 52, a test storage area 53, a timestamp storage area 54, and a BER storage area 56.

[0123] The BER memory area 56 is composed of flash memory 41 and stores the initial value of the BER in the test memory area 53. The initial value of the BER is updated when data is rewritten to the data memory area 51 by the test processing unit 65b.

[0124] The control unit 60b is a functional unit realized by the memory controller 42 described above, and performs various processes on the SSD 40b. The control unit 60b comprises a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65b, and a count processing unit 66.

[0125] The test processing unit 65b calculates the power-off read time based on the BIOS timestamp, provided that the BIOS timestamp is accurate. If the BIOS timestamp is accurate and the power-off read time exceeds a threshold period, the test processing unit 65b determines that a predetermined data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0126] Furthermore, the test processing unit 65a calculates the BER for the test storage area 53. If the BIOS timestamp is inaccurate and the amount of change in the BER reaches a predetermined threshold indicating that the predetermined data retention period has been reached, it determines that the predetermined data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0127] For example, the test processing unit 65b calculates the BER of the test memory area 53 and obtains the initial value of the BER stored in the BER memory area 56. The test processing unit 65b determines that a predetermined data retention period has been reached when the amount of change from the initial value of the calculated BER becomes greater than or equal to a predetermined threshold ΔR1. Here, the predetermined threshold ΔR1 is set, for example, based on the retention characteristics of the flash memory 41 (the relationship between the passage of time and data corruption), as the amount of change in BER corresponding to the period during which the data in the test memory area 53 can be error corrected by the error correction process performed by the ECC processing unit 64.

[0128] Furthermore, when the change in BER exceeds a predetermined threshold ΔR1, the test processing unit 65b rewrites the data already stored in the data storage area 51 and updates the initial value of BER stored in the BER storage area 56 to the calculated current BER value.

[0129] In this embodiment, the processing of the test processing unit 65b differs in that it has been modified to determine when a predetermined data retention period has been reached based on the change in the aforementioned index value (BER). Other processing is the same as that of the test processing unit 65a in the second embodiment.

[0130] Next, with reference to Figure 9, the operation of the SSD40b according to this embodiment will be described. Figure 9 is a flowchart illustrating an example of the operation of the SSD40b according to this embodiment. Here, we will explain the process by which the SSD40b prevents data corruption due to retention.

[0131] In Figure 9, the processes from step S501 to step S505 are the same as the processes from step S401 to step S405 shown in Figure 7 above, so their explanation is omitted here.

[0132] In step S506, the test processing unit 65b obtains the initial value of BER (past BER values) from the BER storage area 56. The test processing unit 65b obtains the initial value of BER stored in the BER storage area 56 via the memory I / F processing unit 62.

[0133] Next, the test processing unit 65b determines whether the change in BER is greater than or equal to a predetermined threshold ΔR1 (step S507). Here, the predetermined threshold ΔR1 is a value that indicates that a predetermined data retention period has been reached. The test processing unit 65b calculates the change in BER by the difference between the calculated BER and the initial value of BER, and determines whether the change in BER is greater than or equal to the predetermined threshold ΔR1. If the change in BER is greater than or equal to the predetermined threshold ΔR1 (step S507: YES), the test processing unit 65b proceeds to step S508. If the change in BER is less than the predetermined threshold ΔR1 (step S507: NO), the test processing unit 65b proceeds to step S510.

[0134] In step S508, the test processing unit 65b rewrites the data in the data storage area 51. The test processing unit 65b performs the same process as in step S109 in Figure 3 described above.

[0135] Next, the test processing unit 65b stores the BER in the BER storage area 56 (step S509). That is, the test processing unit 65b updates the initial value of the BER stored in the BER storage area 56 to the calculated current BER value. After the processing in step S509, the test processing unit 65b proceeds to step S510.

[0136] The processes in steps S510 and S511 are the same as those in steps S408 and S409 shown in Figure 7 above, so their explanation is omitted here.

[0137] Furthermore, the test processing unit 65b may perform a rewrite of the already stored data to the data storage area 51 and the test storage area 53 when a predetermined data retention period is reached.

[0138] As described above, in this embodiment, if the BIOS timestamp is inaccurate and the change in the bit error rate (BER) reaches a predetermined threshold ΔR1 indicating that a predetermined data retention period has been reached, the control unit 60b performs a rewrite of the already stored data to the data storage area 51.

[0139] As a result, the SSD 40b (memory drive device) and information processing device 100 according to this embodiment have the same effects as those of the first and second embodiments described above, and can reduce data corruption due to the retention characteristics of the flash memory 41 and improve reliability.

[0140] It should be noted that the present invention is not limited to the embodiments described above, and can be modified without departing from the spirit of the invention. For example, in each of the embodiments described above, the information processing device 100 was described as a notebook-type personal computer, but it is not limited to this, and may be other information processing devices such as a desktop personal computer or a tablet terminal device.

[0141] Furthermore, in each of the above embodiments, an example was described in which BER is used as an index value indicating the rate of memory failures in the test memory area 53. However, the invention is not limited to this, and other index values ​​may be used, for example, such as the cell applied voltage, which is the applied voltage value corresponding to the change in the cell VT voltage. In addition, in each of the above embodiments, for example, BER and the cell applied voltage may be used in combination as index values.

[0142] Furthermore, in each of the above embodiments, the processing by the control unit 60 (60a, 60b) (test processing unit 65 (65a, 65b)) was described as being performed as internal processing of the SSD 40 (40a, 40b). However, the invention is not limited to this, and the information processing device 100 may perform a part of the processing of the test processing unit 65 (65a, 65b).

[0143] Furthermore, in each of the above embodiments, the test processing unit 65 (65a, 65b) has been described as performing a determination process for reaching a predetermined data retention period and a rewrite process for rewriting data to the data storage area 51 in succession. However, it is not limited to this, and the determination process and the rewrite process may be performed separately. The test processing unit 65 (65a, 65b) may, for example, be configured to execute the rewrite process triggered by a background media scan of the SSD 40 (40a, 40b).

[0144] Furthermore, the test processing unit 65 (65a, 65b) may perform the rewrite process on blocks (or pages) of the flash memory 41 where data in the data storage area 51 is written. Also, the test processing unit 65 (65a, 65b) may, for example, detect blocks (or pages) with a high BER that have been rescued by the ECC function in the data storage area 51, and perform the rewrite process on the detected blocks (or pages) with a high BER.

[0145] Furthermore, in each of the above embodiments, the SSD 40 (40a, 40b) is described as having an ECC processing unit 64 as a functional unit realized by the memory controller 42, but it is not limited to this, and for example, the flash memory 41 may also be equipped with an ECC processing unit 64.

[0146] Furthermore, each component of the SSD 40 (40a, 40b) and the information processing device 100 described above has a computer system inside. The processing in each component of the SSD 40 (40a, 40b) and the information processing device 100 may be performed by recording a program for realizing the functions of each component on a computer-readable recording medium, loading the program recorded on this recording medium into the computer system, and executing it. Here, "loading the program recorded on the recording medium into the computer system and executing it" includes installing the program into the computer system. Here, "computer system" includes hardware such as the OS and peripheral devices. Furthermore, "computer system" may include multiple computer devices connected via a network, including communication lines such as the Internet, WAN, LAN, and dedicated lines. "Computer-readable recording medium" refers to portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. Thus, the recording medium storing the program may be a non-transient recording medium such as a CD-ROM.

[0147] Furthermore, the recording medium also includes internal or external recording media accessible from the distribution server for distributing the program. The program may be divided into multiple parts, downloaded at different times, and then combined in the SSD 40 (40a, 40b) and the information processing device 100, or each of the divided programs may be distributed by a different distribution server. Additionally, "computer-readable recording medium" includes volatile memory (RAM) within computer systems that act as servers or clients when a program is transmitted over a network, which retains the program for a certain period of time. Moreover, the program may be intended to implement only a portion of the functions described above. Furthermore, the program may be a so-called differential file (differential program) that can implement the functions described above in combination with a program already recorded in the computer system.

[0148] Furthermore, some or all of the above-mentioned functions may be implemented as integrated circuits such as LSIs (Large Scale Integrations). Each of the above-mentioned functions may be implemented as an individual processor, or some or all of them may be integrated into a single processor. In addition, the method of implementing integrated circuits is not limited to LSIs; they may also be implemented using dedicated circuits or general-purpose processors. Furthermore, if advances in semiconductor technology lead to the emergence of integrated circuit technologies that can replace LSIs, integrated circuits using such technologies may be used. [Explanation of symbols]

[0149] 10 Main Control Unit 11 CPU 12 Main Memory 13 Video Subsystems 14 Display section 21 Chipset 22 BIOS memory 31. Embedded Controller (EC) 32 Input section 33 Power supply circuit 40, 40a, 40b SSDs 41 Flash memory 42 Memory Controllers 50, 50a, 50b Data storage units 51 Data storage area 52 ECC storage area 53 Test memory area 54 Timestamp storage area 55 Estimated Model Memory Unit 56 BER storage area 60, 60a, 60b control unit 61 Host I / F Processing Unit 62 Memory I / F Processing Unit 63 Data Management Department 64 ECC Processing Unit 65, 65a, 65b Test Processing Unit 67 Correction Processing Unit 68 Warning Processing Unit 100 Information Processing Devices

Claims

1. A memory drive device having rewritable non-volatile memory, A data storage area comprising the aforementioned non-volatile memory, capable of storing data used for information processing, A test storage area comprising the aforementioned non-volatile memory and storing predetermined test data, A control unit that, when a predetermined data retention period is reached, rewrites the data already stored in the data storage area. Equipped with, The control unit, Based on the date and time information obtained from the host device to which the memory drive device is connected, the power-off period of the host device is calculated, and if the obtained date and time information is accurate and the power-off period exceeds a threshold period, it is determined that the predetermined data retention period has been reached. If the aforementioned date and time information is inaccurate, it is determined that the predetermined data retention period has been reached based on an index value related to a storage failure in the test storage area where the predetermined test data is pre-stored. Memory drive device.

2. The control unit, Based on the first date and time information, which is the date and time information obtained when the above-level device is started up and obtained from the BIOS (Basic Input Output System) of the above-level device, and the second date and time information, which is the date and time information when the memory drive device is powered off, the power off period is calculated. Based on the time relationship between the first date and time information and the second date and time information, it is determined whether the acquired date and time information is accurate. The memory drive device according to claim 1.

3. The aforementioned index value includes the bit error rate when reading the test data from the test storage area. The control unit, If the aforementioned date and time information is inaccurate, the predetermined data retention period is determined based on the bit error rate as the indicator value. The memory drive device according to claim 2.

4. The control unit, If the aforementioned date and time information is accurate, the longer of the first power-off period calculated based on the first date and time information and the second date and time information, and the second power-off period estimated based on the bit error rate, is adopted as the power-off period. If the aforementioned date and time information is inaccurate, the second power outage period shall be adopted as the power outage period. If the power-off period exceeds the threshold period, it is determined that the predetermined data retention period has been reached, and the data already stored in the data storage area is rewritten. The memory drive device according to claim 3.

5. The system includes a warning processing unit that, if the acquired date and time information is accurate, estimates the mean ambient temperature of the host device based on the difference between the first power-off period and the second power-off period, and outputs warning information to the host device if the mean ambient temperature is above a threshold temperature. The memory drive device according to claim 4.

6. The control unit estimates the second power outage period using an estimation model that estimates the power outage period from the bit error rate. The system includes a correction processing unit that corrects the estimation model so that the first and second power-off periods coincide if the difference between the first and second power-off periods is greater than or equal to a certain period. The memory drive device according to claim 4.

7. The control unit, If the aforementioned date and time information is inaccurate, and the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached, the data already stored in the data storage area is rewritten. The memory drive device according to claim 3.

8. The control unit, If the aforementioned date and time information is inaccurate, and the change in the bit error rate reaches a predetermined threshold indicating that the predetermined data retention period has been reached, the data already stored in the data storage area is rewritten. The memory drive device according to claim 3.

9. A memory drive device according to any one of claims 1 to 8, The above-mentioned higher-level device performs information processing using the data stored in the aforementioned memory drive device. Information processing device.

10. A control method for a memory drive device having a rewritable non-volatile memory, a data storage area composed of the non-volatile memory and capable of storing data used for information processing, and a test storage area composed of the non-volatile memory and storing predetermined test data, wherein The control unit, Based on the date and time information obtained from the host device to which the memory drive device is connected, the power-off period of the host device is calculated, and if the obtained date and time information is accurate and the power-off period exceeds a threshold period, it is determined that the predetermined data retention period has been reached. If the aforementioned date and time information is inaccurate, it is determined that the predetermined data retention period has been reached based on an index value related to a storage failure in the test storage area where the predetermined test data is pre-stored. When the predetermined data retention period is reached, the data already stored in the data storage area is rewritten. Control method.

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