Display devices and optical devices

Abstract

We provide display devices and optical devices. [Solution] The present invention relates to a display device and optical device that can improve image quality by minimizing leakage current between adjacent pixels, and includes a substrate (SSUB), a first electrode (AND) on the substrate, a pixel definition film (PDL) disposed on the first electrode and having a trench (TRC), a light-emitting stack (IL) on the first electrode and the pixel definition film, and a dummy electrode (DM) disposed between the substrate and the trench, wherein the voltage applied to the dummy electrode and the voltage applied to the first electrode are different from each other.

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device and optical device that can improve image quality by minimizing leakage current between adjacent pixels. [Background technology]

[0002] A head-mounted display (HMD) is an image display device worn on the user's head in the form of glasses or a helmet, which focuses on the area in front of the user's eyes. Head-mounted displays can realize virtual reality (VR) or augmented reality (AR).

[0003] A head-mounted display magnifies and displays images from a small display device using multiple lenses. Therefore, the display device used in a head-mounted display needs to provide high-resolution images, for example, images with a resolution of 3000 PPI (Pixels Per Inch) or higher. For this purpose, OLEDoS (Organic Light Emitting Diode on Silicon), a high-resolution, small organic light-emitting display device, is used as the display device for head-mounted displays. OLEDoS is a device that displays images by arranging organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which CMOS (Complementary Metal Oxide Semiconductor) is located. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Korean Published Patent No. 10-2022-0049376 [Overview of the project] [Problems that the invention aims to solve]

[0005] The object of the present invention is to provide a display device and an optical device that can improve image quality by minimizing leakage current between adjacent pixels.

[0006] The problems addressed by the present invention are not limited to those described above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention for achieving the above objective includes a substrate, a first electrode on the substrate, a pixel definition film disposed on the first electrode and having a trench, a light-emitting stack on the first electrode and the pixel definition film, and a dummy electrode disposed between the substrate and the trench, wherein the voltage applied to the dummy electrode and the voltage applied to the first electrode are different from each other.

[0008] Furthermore, an optical device according to one embodiment of the present invention for achieving the above objective includes a display device and an optical path conversion member on the display device, the display device including a substrate, a first electrode on the substrate, a pixel definition film disposed on the first electrode and having a trench, a light-emitting stack on the first electrode and the pixel definition film, and a dummy electrode disposed between the substrate and the trench, wherein the voltage applied to the dummy electrode and the voltage applied to the first electrode are different from each other.

[0009] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] According to the display device of one embodiment, the leakage current between adjacent pixels can be minimized to improve the image quality. For example, when the technology of one embodiment of the present invention is adopted, the path of the leakage current between adjacent pixels is changed through the dummy electrodes arranged adjacent to the trenches, so that the leakage current between the adjacent pixels can be minimized.

[0011] Note that the effects obtained from the present invention are not limited to the effects described above, and other effects not mentioned will be clearly understood by those with ordinary knowledge in the technical field to which the present invention belongs from the following description.

Brief Description of the Drawings

[0012] [Figure 1] It is an exploded perspective view showing a display device according to one embodiment. [Figure 2] It is a block diagram showing a display device according to one embodiment. [Figure 3] It is an equivalent circuit diagram of a first sub-pixel according to one embodiment. [Figure 4] It is a layout diagram showing an example of a display panel according to one embodiment. [Figure 5] It is a layout diagram showing an example of the display area of FIG. 4. [Figure 6] It is a layout diagram showing another example of the display area of FIG. 4. [Figure 7] It is a cross-sectional view showing an example of a display panel cut along I1-I1' of FIG. 5. [Figure 8] It is a cross-sectional view showing an example of the A1 area of FIG. 7 in detail. [Figure 9] It is a cross-sectional view showing an example of the A2 area of FIG. 7 in detail. [Figure 10] It is a cross-sectional view of a display device according to another embodiment. [Figure 11] It is a cross-sectional view of a display device according to another embodiment. [Figure 12] It is a diagram for explaining the planar shape of the dummy electrode of FIG. 11. [Figure 13]It is a cross-sectional view of a display device according to another embodiment. [Figure 14] It is a cross-sectional view of a display device according to another embodiment. [Figure 15] It is a diagram for explaining the planar shape of the dummy electrode in FIG. 14. [Figure 16] It is a perspective view showing a head-mounted display device according to an embodiment. [Figure 17] It is an exploded perspective view showing an example of the head-mounted display device in FIG. 16. [Figure 18] It is a perspective view showing a head-mounted display device according to an embodiment.

Embodiments for Carrying Out the Invention

[0013] The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. These embodiments are merely provided to complete the disclosure of the present invention and to fully inform those with ordinary knowledge in the technical field to which the present invention belongs of the scope of the invention. The present invention is defined only by the scope of the claims.

[0014] When an element or layer is referred to as “on” another element or layer, it includes all cases where another layer or element is interposed immediately above or in the middle of the other element. The same reference numerals throughout the specification refer to the same components. The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for explaining the embodiments are exemplary, so the present invention is not limited to the matters shown in the drawings.

[0015] While terms such as "first," "second," etc., are used to describe a variety of components, these components are, of course, not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component mentioned below may, of course, be the second component within the technical concept of the present invention.

[0016] The features of each of the various embodiments of the present invention can be combined or linked together, either partially or entirely, enabling a wide range of technical interlocking and driving processes. Each embodiment can be implemented independently of the others or in conjunction with them.

[0017] The following describes specific embodiments with reference to the attached drawings.

[0018] Figure 1 is an exploded perspective view showing a display device according to one embodiment. Figure 2 is a block diagram of the display device according to one embodiment.

[0019] Referring to Figures 1 and 2, the display device 10 according to one embodiment is a device that displays videos and still images. The display device 10 according to one embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, PMPs (Portable Multimedia Players), navigation systems, and UMPCs (Ultra Mobile PCs). For example, the display device 10 according to one embodiment can be applied to televisions, laptop computers, monitors, billboards, or displays for the Internet of Things (IoT). Alternatively, the display device 10 according to one embodiment can be applied to smartwatches, watch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0020] A display device 10 according to one embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0021] The display panel 100 has a planar shape similar to a rectangle. For example, the display panel 100 may have a planar shape similar to a rectangle, with a short side in a first direction DR1 and a long side in a second direction DR2 that intersects with the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be formed as a rounded or right angle with a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangle, but can be formed into a variety of shapes such as other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments of this specification are not limited thereto.

[0022] The display panel 100 includes multiple pixels PX, multiple scan lines SL, multiple light emission control lines EL, and multiple data lines DL, a scan drive unit 610, a light emission drive unit 620, and a data drive unit 700. The display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images, as shown in Figure 2.

[0023] Multiple pixels PX are arranged in the display area DAA. Multiple pixels PX can be arranged in a matrix in the first direction DR1 and the second direction DR2. Multiple scan lines SL and multiple light emission control lines EL extend in the first direction DR1 and are located in the second direction DR2. Multiple data lines DL extend in the second direction DR2 and are located in the first direction DR1.

[0024] Multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple light emission control lines EL include multiple first light emission control lines ECL1 and multiple second light emission control lines ECL2.

[0025] Multiple pixels PX include multiple sub-pixels SP1, SP2, SP3. Multiple sub-pixels SP1, SP2, SP3 include multiple pixel transistors as shown in Figure 3, and the multiple pixel transistors are formed by a semiconductor process and arranged on a semiconductor substrate (SSUB in Figure 7). For example, the multiple pixel transistors of the data driving unit 700 are formed of CMOS (Complementary Metal Oxide Semiconductor), but the embodiments described herein are not limited to this.

[0026] Each of the multiple sub-pixels SP1, SP2, and SP3 may be connected to one write scan line GWL, one control scan line GCL, one bias scan line GBL, and one first light emission control line ECL1, one second light emission control line ECL2, and one data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 may receive a data voltage from the data line DL in response to the write scan signal from the write scan line GWL, and emit light from the light-emitting element in response to the data voltage.

[0027] The scan drive unit 610, the light emission drive unit 620, and the data drive unit 700 are located in the non-display area NDA.

[0028] The scan drive unit 610 includes a plurality of scan transistors, and the light-emitting drive unit 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors can be formed by a semiconductor process and formed on a semiconductor substrate (SSUB in Figure 7). For example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed using CMOS, but the embodiments herein are not limited thereto.

[0029] The scan drive unit 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal in accordance with the scan timing control signal SCS of the timing control circuit 400 and output it sequentially to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in accordance with the scan timing control signal SCS and output it sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal in accordance with the scan timing control signal SCS and output it sequentially to the bias scan line GBL.

[0030] The light emission drive unit 620 includes a first light emission control drive unit 621 and a second light emission control drive unit 622. Each of the first light emission control drive unit 621 and the second light emission control drive unit 622 can receive a light emission timing control signal ECS from the timing control circuit 400. The first light emission control drive unit 621 can generate a first light emission control signal in response to the light emission timing control signal ECS and output it sequentially to the first light emission control line ECL1. The second light emission control drive unit 622 can generate a second light emission control signal in response to the light emission timing control signal ECS and output it sequentially to the second light emission control line ECL2.

[0031] The data drive unit 700 includes a plurality of data transistors, which are formed by a semiconductor process and can be formed on a semiconductor substrate (SSUB in Figure 7). For example, the plurality of data transistors are formed by CMOS, but the embodiments herein are not limited thereto.

[0032] The data drive unit 700 can receive digital video data DATA and data timing control signal DCS as inputs from the timing control circuit 400. The data drive unit 700 converts the digital video data DATA into analog data voltage according to the data timing control signal DCS and outputs it to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan drive unit 610, and data voltage is supplied to the selected sub-pixels SP1, SP2, and SP3.

[0033] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 is positioned on one side of the display panel 100, for example, on the back. The heat dissipation layer 200 plays a role in releasing heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0034] The circuit board 300 may be electrically connected to a plurality of first pads (PD1 in Figure 4) of the first pad portion (PDA1 in Figure 4) of the display panel 100 using a conductive adhesive, such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film made of a flexible material. Figure 1 shows an example of the circuit board 300 unfolded, but the circuit board 300 can be bent. In this case, one end of the circuit board 300 may be positioned on the back of the display panel 100 and / or on the back of the heat dissipation layer 200. The other end of the circuit board 300 may be connected to a plurality of first pads (PD1 in Figure 4) of the first pad portion (PDA1 in Figure 4) of the display panel 100 using a conductive adhesive. One end of the circuit board 300 may be the end opposite to the other end of the circuit board 300.

[0035] The timing control circuit 400 receives digital video data and timing signals from an external source. The timing control circuit 400 can generate a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signals. The timing control circuit 400 can output the scan timing control signal SCS to the scan drive unit 610 and the light emission timing control signal ECS to the light emission drive unit 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data drive unit 700.

[0036] The power supply circuit 500 can generate multiple panel drive voltages depending on the external power supply voltage. For example, the power supply circuit 500 can generate a first drive voltage VSS, a second drive voltage VDD, and a third drive voltage VINT and supply them to the display panel 100. The first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT will be described later with reference to Figure 3.

[0037] The timing control circuit 400 and the power supply circuit 500 are each formed as integrated circuits (ICs) and are attached to one side of the circuit board 300. In this case, the scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. In addition, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0038] Alternatively, the timing control circuit 400 and the power supply circuit 500, respectively, are located in the non-display area NDA of the display panel 100, similar to the scan drive unit 610, the light emission drive unit 620, and the data drive unit 700. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each of the power supply circuits 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed by a semiconductor process and formed on a semiconductor substrate (SSUB in Figure 7). For example, the plurality of timing transistors and the plurality of power transistors can be formed in CMOS, but the embodiments herein are not limited thereto. The timing control circuit 400 and the power supply circuit 500 can be located between the data drive unit 700 and the first pad unit (PDA1 in Figure 4).

[0039] Figure 3 is an equivalent circuit diagram of the first subpixel according to one embodiment.

[0040] Referring to Figure 3, the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first light emission control line ECL1, the second light emission control line ECL2, and the data line DL. The first sub-pixel SP1 may also be connected to the first drive voltage line VSL to which the first drive voltage VSS corresponding to a low potential voltage is applied, the second drive voltage line VDL to which the second drive voltage VDD corresponding to a high potential voltage is applied, and the third drive voltage line VIL to which the third drive voltage VINT corresponding to the initialization voltage is applied.

[0041] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element (LE), a first capacitor CP1, and a second capacitor CP2.

[0042] The light-emitting element LE emits light in response to the drive current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE is proportional to the drive current Ids. The first electrode of the light-emitting element LE may be the anode electrode, and the second electrode may be the cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes, but the embodiments herein are not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes, in which case the light-emitting element LE may be a micro light-emitting diode.

[0043] The first transistor T1 may be a drive transistor that controls the source-drain current (Ids, hereinafter referred to as "drive current") flowing between the source electrode and the drain electrode in accordance with the voltage applied to the gate electrode.

[0044] The second transistor T2 is positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL, connecting one electrode of the first capacitor CP1 to the data line DL. As a result, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0045] The third transistor T3 is positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by the write control signal of the control scan line GCL, connecting the first node N1 to the second node N2. This allows the first transistor T1 to behave like a diode when its gate electrode and source electrode are connected.

[0046] A fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first light emission control signal of the first light emission control line ECL1, connecting the second node N2 to the third node N3. As a result, the drive current of the first transistor T1 is supplied to the light-emitting element LE.

[0047] The fifth transistor T5 is positioned between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL, connecting the third node N3 to the third drive voltage line VIL. This allows the third drive voltage VINT of the third drive voltage line VIL to be applied to the first electrode of the light-emitting element LE.

[0048] The sixth transistor T6 is positioned between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second light emission control signal of the second light emission control line ECL2, connecting the source electrode of the first transistor T1 to the second drive voltage line VDL. As a result, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0049] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0050] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a p-type MOSFET, but the embodiments herein are not limited to this. Each of the first to sixth transistors T1 to T6 may be an n-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be p-type MOSFETs, and the remaining transistors may each be an n-type MOSFET.

[0051] Figure 3 shows an example where the first sub-pixel SP1 includes six transistors T1-T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to that shown in Figure 3. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to those shown in Figure 3.

[0052] Furthermore, the equivalent circuit diagrams of the second subpixel SP2 and the third subpixel SP3 may be substantially identical to the equivalent circuit diagram of the first subpixel SP1, which was explained with reference to Figure 3. Therefore, the explanation of the equivalent circuit diagrams of the second subpixel SP2 and the third subpixel SP3 is omitted in this specification.

[0053] Figure 4 is a layout diagram showing an example of a display panel according to one embodiment.

[0054] Referring to Figure 4, the display area DAA of the display panel 100 according to one embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one embodiment includes a scan drive unit 610, a light emission drive unit 620, a data drive unit 700, a first distribution circuit 710, a second distribution circuit 720, a first pad unit PDA1, and a second pad unit PDA2.

[0055] The scan drive unit 610 is located on the first side of the display area DAA, and the light emission drive unit 620 is located on the second side of the display area DAA. For example, the scan drive unit 610 is located on one side of the first direction DR1 of the display area DAA, and the light emission drive unit 620 is located on the other side of the first direction DR1 of the display area DAA. However, the embodiments described herein are not limited thereto, and the scan drive unit 610 and the light emission drive unit 620 can also be located on both the first and second sides of the display area DAA.

[0056] The first pad section PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 via a conductive adhesive member. The first pad section PDA1 is located on the third side of the display area DAA. For example, the first pad section PDA1 may be located on one side of the display area DAA in the second direction DR2. The first pad section PDA1 may be located outside the data drive unit 700 in the second direction DR2.

[0057] The second pad section PDA2 may include a plurality of second pads PD2 that correspond to test pads for checking whether the display panel 100 is functioning correctly. The plurality of second pads PD2 may be connected to a fixture or probe pins during the testing process, or to a test circuit board. The test circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0058] The second pad unit PDA2 is located on the fourth side of the display area DAA. For example, the second pad unit PDA2 may be located on the other side of the second direction DR2 of the display area DAA. The second pad unit PDA2 may be located outside the second distribution circuit 720 in the second direction DR2.

[0059] The first distribution circuit 710 distributes the data voltage applied via the first pad unit PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied via one first pad PD1 of the first pad unit PDA1 to P (P is a positive integer of 2 or more) data lines DL, thereby reducing the number of multiple first pads PD1. The first distribution circuit 710 is located on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be located on one side of the second direction DR2 of the display area DAA.

[0060] The second distribution circuit 720 distributes the signal applied via the second pad unit PDA2 to the scan drive unit 610, the light emission drive unit 620, and the data line DL. The second pad unit PDA2 and the second distribution circuit 720 may be configured to inspect the operation of each pixel PX of the display area DAA. The second distribution circuit 720 is located on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be located on the other side of the second direction DR2 of the display area DAA.

[0061] The cathode connection area CCA may be the region where the second electrode (CAT in Figure 7) of the display element layer (EML in Figure 7) is connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection area CCA is located outside at least one side of the display area DA. For example, the cathode connection area CCA may be located outside at least one side of the display area DA, such as the left, right, top, and bottom. Alternatively, the cathode connection area CCA may be positioned to surround the display area DA, as shown in Figure 4, in order to minimize deviations in the first drive voltage VSS due to voltage drop (IR drop) or voltage rise (IR rising) of the second electrode CAT in the display area DA.

[0062] Figure 5 is a layout diagram showing an example of the display area in Figure 4. Figure 6 is a layout diagram showing yet another example of the display area in Figure 4.

[0063] Referring to Figures 5 and 6, each of the multiple pixels PX includes a first light-emitting region EA1, which is the light-emitting region of the first subpixel SP1; a second light-emitting region EA2, which is the light-emitting region of the second subpixel SP2; and a third light-emitting region EA3, which is the light-emitting region of the third subpixel SP3.

[0064] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a quadrilateral or hexagonal planar shape as shown in Figures 5 and 6, but the embodiments herein are not limited thereto. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a planar shape other than a quadrilateral or hexagon, such as a circle, an ellipse, or an irregular shape.

[0065] As shown in Figure 5, in each of the multiple pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent in the first direction DR1. Also, the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent in the first direction DR1. Furthermore, the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent in the second direction DR2. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may differ.

[0066] Alternatively, as shown in Figure 6, the light-emitting regions EA1, EA2, EA3, and EA4 can have a hexagonal planar shape. In this case, the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent in the first direction DR1, and the second light-emitting region EA2 and the fourth light-emitting region EA4 are adjacent in the second direction DR2. Furthermore, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent in the first diagonal direction DD1, and the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent in the second diagonal direction DD2. Also, the first light-emitting region EA1 and the fourth light-emitting region EA4 are adjacent in the second diagonal direction DD2, and the third light-emitting region EA3 and the fourth light-emitting region EA4 are adjacent in the first diagonal direction DD1. The first diagonal direction DD1 is the direction between the first direction DR1 and the second direction DR2, and refers to a direction inclined at 45 degrees with respect to the first direction DR1 and the second direction DR2, while the second diagonal direction DD2 may be a direction perpendicular to the first diagonal direction DD1.

[0067] The first subpixel SP1 may emit the first light, the second subpixel SP2 may emit the second light, and the third subpixel SP3 may emit the third light. Here, the first light may be light in the blue wavelength band, the second light in the green wavelength band, and the third light in the red wavelength band. For example, the blue wavelength band refers to the wavelength band in which the main peak wavelength of the light is approximately 370 nm to 460 nm, the green wavelength band refers to the wavelength band in which the main peak wavelength of the light is approximately 480 nm to 560 nm, and the red wavelength band refers to the wavelength band in which the main peak wavelength of the light is approximately 600 nm to 750 nm.

[0068] As shown in Figure 5, each of the multiple pixels PX may contain three light-emitting regions EA1, EA2, and EA3, or as shown in Figure 6, it may contain four light-emitting regions EA1, EA2, EA3, and EA4. In this case, the fourth light-emitting region EA4 can emit the same second light as the second light-emitting region EA2, but the embodiments herein are not limited to this.

[0069] The light-emitting regions of multiple pixels PX can be arranged in a stripe structure where the light-emitting regions are aligned in the first direction DR1, a PenTile® structure where the light-emitting regions EA1, EA2, EA3, and EA4 are arranged in a rhombus shape as shown in Figure 6, or a hexagonal structure where the light-emitting regions are arranged in a hexagonal shape.

[0070] Figure 7 is a cross-sectional view showing an example of a display panel cut along the line I1-I1' in Figure 5.

[0071] Referring to Figure 7, the display panel 100 includes a semiconductor backplane SBP, an luminescent backplane EBP, a display element layer EML, a encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0072] The semiconductor backplane SBP includes a semiconductor substrate SSUB containing multiple pixel transistors PTR, multiple semiconductor insulating films covering the multiple pixel transistors PTR, and multiple contact terminals CTE that are electrically connected to each of the multiple pixel transistors PTR. The multiple pixel transistors PTR may be the first to sixth transistors T1 to T6 as described with reference to Figure 4.

[0073] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a type 1 impurity. Multiple well regions WA are arranged on the upper surface of the semiconductor substrate SSUB. Multiple well regions WA may be regions doped with a type 2 impurity. The type 2 impurity is different from the type 1 impurity described above. For example, if the type 1 impurity is a p-type impurity, the type 2 impurity may be an n-type impurity. Or, if the type 1 impurity is an n-type impurity, the type 2 impurity may be a p-type impurity.

[0074] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode, and a channel region CH located between the source region SA and the drain region DA.

[0075] A lower insulating film BINS is placed between the gate electrode GE and the well region WA. Side insulating films SINS are placed on the sides of the gate electrode GE. The side insulating films SINS are placed on top of the lower insulating film BINS.

[0076] The source region SA and drain region DA may each be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH may overlap with the gate electrode GE in the third direction DR3. The source region SA is located on one side of the gate electrode GE, and the drain region DA is located on the other side of the gate electrode GE.

[0077] Each of the multiple well regions WA further includes a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may have a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may have a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2 increase the distance between the source region SA and the drain region DA, which may increase the length of each channel region CH of the pixel transistor PTR.

[0078] The first semiconductor insulating film SINS1 is placed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 is placed on the first semiconductor insulating film SINS1.

[0079] Multiple contact terminals CTE are arranged on a second semiconductor insulating film SINS2. Each of the multiple contact terminals CTE may be connected to one of the gate electrode GE, source region SA, and drain region DA of a pixel transistor PTR via a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The multiple contact terminals CTE are made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0080] A third semiconductor insulating film SINS3 is placed on the side surface of each of the multiple contact terminals CTE. The upper surface of each of the multiple contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3.

[0081] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 is made of silicon dioxide (SiCN) or silicon oxide (SiO2). xThe embodiment described herein is formed by an inorganic film of the ) system, but is not limited thereto.

[0082] Semiconductor substrates (SSUBs) can be replaced with glass substrates or polymer resin substrates such as polyimide. In this case, thin-film transistors may be placed on the glass or polymer resin substrate. Glass substrates are rigid substrates that cannot be bent, while polymer resin substrates can be flexible substrates that can be bent or curved.

[0083] The light-emitting element backplane EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. Furthermore, the light-emitting element backplane EBP includes a plurality of insulating films INS1 to INS9 arranged between the first to eighth conductive layers ML1 to ML8.

[0084] The first to eighth insulating films INS1 to INS8 serve to insulate the first to eighth conductive layers ML1 to ML8. The first to eighth conductive layers ML1 to ML8 connect multiple contact terminals CTE exposed on the semiconductor backplane SBP to realize the circuit of the first subpixel SP1 shown in Figure 4.

[0085] For example, the semiconductor backplane SBP only has the first to sixth transistors T1 to T6 formed on it, and the connections between the first to sixth transistors T1 to T6, and between the first capacitor CP1 and the second capacitor CP2, are made via the first to eighth conductive layers ML1 to ML8. In addition, the connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE are also made via the first to eighth conductive layers ML1 to ML8.

[0086] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are made of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are made of one of the following materials, or an alloy containing one of the following: copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The first to eighth vias VA1 to VA8 are made of substantially the same material. The first to eighth insulating films INS1 to INS8 are made of silicon oxide (SiO x The embodiment described herein is formed by an inorganic film of the ) system, but is not limited thereto.

[0087] The ninth insulating film INS9 is placed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 is made of silicon oxide (SiO2). x The embodiment described herein is formed by an inorganic film of the ) system, but is not limited thereto.

[0088] Each of the ninth vias VA9 can be connected to the eighth conductive layer ML8, which is exposed through the ninth insulating film INS9. The ninth vias VA9 consist of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0089] The display element layer (EML) is positioned on the light-emitting element backplane (EBP). The display element layer (EML) may include tenth and eleventh insulating films (INS10, INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel definition film (PDL), a plurality of trenches (TRC), and a plurality of dummy electrodes (DM).

[0090] A reflective electrode RL is placed on the ninth insulating film INS9. The reflective electrode RL may include at least one reflective electrode RL1, RL2, RL3, RL4. For example, the reflective electrode RL may include the first to fourth reflective electrodes RL1, RL2, RL3, RL4 as shown in Figure 7.

[0091] The first reflective electrode RL1 is located on the ninth interlayer insulating film INS9 and may be connected to the ninth via VA9. Each of the second reflective electrodes RL2 is located on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 is located on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 is located on its corresponding third reflective electrode RL3.

[0092] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4.

[0093] The first reflector electrode RL1 is made of one of the following or an alloy containing one of the following: copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflector electrode RL1 may contain titanium nitride (TiN), the second reflector electrode RL2 may contain aluminum (Al), the third reflector electrode RL3 may contain titanium nitride (TiN), and the fourth reflector electrode RL4 may contain titanium (Ti).

[0094] The tenth interlayer insulating film INS10 is placed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 is placed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 may be a film for flattening the step caused by the reflective electrodes RL. The eleventh interlayer insulating film INS11 is placed on the tenth interlayer insulating film INS10 and the reflective electrodes RL.

[0095] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 are made of silicon oxide (SiO x The embodiment described herein is formed by an inorganic film of the ) system, but is not limited thereto.

[0096] The 11th interlayer insulating film INS11 may be an optical auxiliary layer for adjusting the resonance distance of light emitted from the light emission stack IL in at least one of the first subpixel SP1, second subpixel SP2, and third subpixel SP3. The thickness of the 11th interlayer insulating film INS11 may differ in the first subpixel SP1, second subpixel SP2, and third subpixel SP3. That is, the thickness of the 11th interlayer insulating film INS11 can be set in each of the first subpixel SP1, second subpixel SP2, and third subpixel SP3 to adjust the distance from the reflective electrode RL to the second electrode CAT according to the main wavelength of light emitted from each of the first subpixel SP1, second subpixel SP2, and third subpixel SP3.

[0097] For example, as shown in Figure 7, the thickness of the 11th interlayer insulating film INS11 in the first subpixel SP1 may be greater than the thickness of the 11th interlayer insulating film INS11 in the second subpixel SP2, and the thickness of the 11th interlayer insulating film INS11 in the second subpixel SP2 may be greater than the thickness of the 11th interlayer insulating film INS11 in the third subpixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first subpixel SP1 may be greater than the distance between the first electrode AND and the reflective electrode RL in the second subpixel SP2. Also, the distance between the first electrode AND and the reflective electrode RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode RL in the third subpixel SP3.

[0098] Each of the 10th vias VA10 may be connected to a 4th reflective electrode RL4 exposed through the 11th interlayer insulating film INS11. The 10th vias VA10 are made of one or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the 10th via VA10 in the first subpixel SP1 (height in the third direction DR3) may be greater than the thickness of the 10th via VA10 in the second subpixel SP2, and the thickness of the 10th via VA10 in the second subpixel SP2 may be greater than the thickness of the 10th via VA10 in the third subpixel SP3.

[0099] Each first electrode AND of the light-emitting element LE is located on the 11th interlayer insulating film INS11 and may be connected to the 10th via VA10. Each first electrode AND of the light-emitting element LE may be connected to the drain region DA or source region SA of the pixel transistor PTR via the 10th via VA10, the reflective electrode RL, the first to 9th vias VA1 to VA9, the first to 8th conductive layers ML1 to ML8, and the contact terminal CTE. Each first electrode AND of the light-emitting element LE is made of one or an alloy containing any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, each first electrode AND of the light-emitting element LE may be titanium nitride (TiN).

[0100] The pixel definition film PDL is positioned over a portion of the first electrode AND of each light-emitting element LE. The pixel definition film PDL may cover the edges of each first electrode AND of the light-emitting element LE. The pixel definition film PDL demarcates the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be a region where the light-emitting element LE, including the first electrode AND, the light-emitting stack IL, and the second electrode CAT, is positioned.

[0101] The first light-emitting region EA1 can be defined as the region in the first subpixel SP1 where the first electrode AND, light-emitting stack IL, and second electrode CAT are sequentially stacked to emit light. The second light-emitting region EA2 can be defined as the region in the second subpixel SP2 where the first electrode AND, light-emitting stack IL, and second electrode CAT are sequentially stacked to emit light. The third light-emitting region EA3 can be defined as the region in the third subpixel SP3 where the first electrode AND, light-emitting stack IL, and second electrode CAT are sequentially stacked to emit light.

[0102] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 is positioned on the edge of each first electrode AND of the light-emitting element LE, the second pixel definition film PDL2 is positioned on the first pixel definition film PDL1, and the third pixel definition film PDL3 is positioned on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are made of silicon oxide (SiO2). x It is formed from an inorganic film of the ) type. Alternatively, the first pixel definition film PDL1 and the third pixel definition film PDL3 are silicon nitride (SiN x While the first pixel is formed from an inorganic film of the ) system, the second pixel definition film PDL2 is formed from silicon oxide (SiO2). x It can be formed from an inorganic film of the ) system. The thickness of the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can each be approximately 500 Å.

[0103] To prevent the first encapsulating inorganic film TFE1 from being fragmented by step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a stepped cross-sectional structure. Step coverage refers to the ratio of the degree to which the thin film is covered on inclined areas to the degree to which it is covered on flat areas. In other words, step coverage, also called step coverage, is the ratio of the deposited film thickness at the bottom and top of the step on the substrate, and is the ratio of the film thickness at the thinnest part to the film thickness at the flat part. The lower the step coverage, the higher the possibility that the thin film will be fragmented at the inclined parts.

[0104] Each of the multiple trenches TRC may penetrate the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. In each of the multiple trenches TRC, at least a portion of the 11th interlayer insulating film INS11 may have a recessed shape.

[0105] At least one trench TRC is placed between adjacent subpixels SP1, SP2, and SP3. Figure 7 shows an example in which two trench TRCs are placed between adjacent subpixels SP1, SP2, and SP3, but the embodiments described herein are not limited to this.

[0106] As shown in Figure 5 or Figure 6, the trench TRC may have the shape of a closed curve surrounding the light-emitting region in a plan view. For example, a plurality of trench TRCs may include a trench TRC surrounding a first light-emitting region EA1, a trench TRC surrounding a second light-emitting region EA2, and a trench TRC surrounding a third light-emitting region EA3.

[0107] The light-emitting stack IL may include multiple stack layers IL1, IL2, and IL3. Figure 7 shows an example in which the light-emitting stack IL has a 3-tandem structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the embodiments described herein are not limited to this. For example, the light-emitting stack IL may have a 2-tandem structure including two stack layers.

[0108] In a 3-tandem structure, the light-emitting stack IL can have a tandem structure including multiple stack layers IL1, IL2, and IL3 that emit different light from each other. For example, the light-emitting stack IL may include a first stack layer IL1 that emits first light, a second stack layer IL2 that emits second light, and a third stack layer IL3 that emits third light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be stacked sequentially.

[0109] The first stack layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer that emits first light, and a first electron transport layer are sequentially stacked. The second stack layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer that emits second light, and a second electron transport layer are sequentially stacked. The third stack layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits third light, and a third electron transport layer are sequentially stacked.

[0110] Between the first stack layer IL1 and the second stack layer IL2, a first charge generation layer is positioned to supply charge to the second stack layer IL2 and electrons to the first stack layer IL1. The first charge generation layer may include an n-type charge generation layer that supplies electrons to the first stack layer IL1 and a p-type charge generation layer that supplies holes to the second stack layer IL2. The n-type charge generation layer may include a metallic dopant.

[0111] A second charge generation layer is positioned between the second stack layer IL2 and the third stack layer IL3 to supply charge to the third stack layer IL3 and electrons to the second stack layer IL2. The second charge generation layer may include an n-type charge generation layer that supplies electrons to the second stack layer IL2 and a p-type charge generation layer that supplies holes to the third stack layer IL3.

[0112] The first stack layer IL1 is placed on the first electrode AND and the pixel definition film PDL, and in each trench TRC, the residual film RINS (Figure 8) placed at the bottom of the trench TRC may be made of the same material as the first stack layer IL1. The first stack layer IL1 may be divided between adjacent subpixels SP1, SP2, and SP3 by the trench TRC. The second stack layer IL2 is placed on the first stack layer IL1. The second stack layer IL2 may be divided between adjacent subpixels SP1, SP2, and SP3 by the trench TRC. A cavity ES (Figure 8) or empty space is placed between the residual film RINS and the second stack layer IL2 in the trench TRC. The third stack layer IL3 is placed on the second stack layer IL2. The third stack layer IL3 may not be divided by the trench TRC and may be placed so as to cover the second stack layer IL2 in each trench TRC.

[0113] In a 3-tandem structure, each of the multiple trenches (TRCs) can be a structure for separating the first to third hole transport layers, the first charge generation layer, and the second charge generation layer of the first to third stack layers IL1, IL2, IL3 of the display element layer (EML) between adjacent sub-pixels SP1, SP2, SP3. In a 2-tandem structure, each of the multiple trenches (TRCs) can be a structure for separating the charge generation layer from the lower stack layer, positioned between the lower and upper stack layers.

[0114] To stably separate the first and second stack layers IL1 and IL2 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3, the height of each of the multiple trenches TRC may be greater than the height of the pixel definition film PDL. The height of each of the multiple trenches TRC refers to the length of each of the multiple trenches TRC in the third direction DR3. The height of the pixel definition film PDL refers to the length of the pixel definition film PDL in the third direction DR3. Other structures may exist instead of trenches TRC to separate the hole transport layer and charge generation layer of the light emission stack IL of the display element layer EML between adjacent subpixels SP1, SP2, and SP3. For example, a reverse tapered partition may be placed on the pixel definition film PDL instead of trenches TRC.

[0115] Furthermore, Figure 7 shows an example in which the light-emitting stack IL is placed in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, but the embodiments described herein are not limited to this. For example, instead of the light-emitting stack IL, the first light-emitting layer may be placed in the first light-emitting region EA1 and not in the second and third light-emitting regions EA2 and EA3. Alternatively, the second light-emitting layer may be placed in the second light-emitting region EA2 and not in the first and third light-emitting regions EA1 and EA3. Also, the third light-emitting layer may be placed in the third light-emitting region EA3 and not in the first and second light-emitting regions EA1 and EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0116] The second electrode CAT is disposed on the light-emitting stack IL. The second electrode CAT is disposed on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can be formed of a transparent conductive material (TCO, Transparent Conductive Material) such as ITO or IZO that transmits light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the light extraction efficiency is increased in each of the first to third sub-pixels SP1, SP2, SP3 by a micro cavity.

[0117] The encapsulation layer TFE is disposed on the display element layer EML. The encapsulation layer TFE can include at least one inorganic film TFE1, TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the first encapsulation inorganic film TFE1 is disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 is disposed on the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be formed of a multilayer film in which one or more inorganic films of silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), and aluminum oxide (AlO x ) are alternately laminated.

[0118] Furthermore, the sealing layer TFE may include at least one organic film TFE2 to protect the display element layer EML from foreign matter such as dust. For example, the sealing organic film TFE2 is placed between the first sealing inorganic film TFE1 and the second sealing inorganic film TFE3. The sealing organic film TFE2 may be a monomer. Alternatively, the sealing organic film TFE2 may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0119] The adhesive layer ADL may be a layer for bonding the sealing layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. Furthermore, the adhesive layer ADL may be a transparent adhesive member, such as a transparent adhesive or transparent adhesive resin.

[0120] The optical layer (OPL) includes multiple color filters CF1, CF2, CF3, multiple lenses (LNS), and a filling layer (FIL). The multiple color filters CF1, CF2, CF3 may include first to third color filters CF1, CF2, CF3. The first to third color filters CF1, CF2, CF3 are placed on the adhesive layer (ADL).

[0121] The first color filter CF1 may overlap with the first light-emitting region EA1 of the first subpixel SP1 in a planar view. The first color filter CF1 can transmit light of the first color, i.e., light in the blue wavelength band. The blue wavelength band is generally 370 nm to 460 nm. Therefore, the first color filter CF1 can transmit light of the first color among the light emitted by the first light-emitting region EA1.

[0122] The second color filter CF2 may overlap with the second light-emitting region EA2 of the second subpixel SP2 in a planar view. The second color filter CF2 can transmit light of the second color, i.e., light in the green wavelength band. The green wavelength band is generally 480 nm to 560 nm. Therefore, the second color filter CF2 can transmit light of the second color among the light emitted by the second light-emitting region EA2.

[0123] The third color filter CF3 may overlap with the third light-emitting region EA3 of the third subpixel SP3 in a planar view. The third color filter CF3 can transmit light of the third color, i.e., light in the red wavelength band. The blue wavelength band is generally 600nm to 750nm. Therefore, the third color filter CF3 can transmit light of the third color among the light emitted by the third light-emitting region EA3.

[0124] Each of the multiple lens LNS is positioned on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lens LNS may be a structure for increasing the proportion of light directed toward the front of the display device 10. Each of the multiple lens LNS may have a cross-sectional shape that is convex in the upward direction.

[0125] The packing layer FIL is placed on multiple lens LNS. The packing layer FIL can have a predetermined refractive index at the interface between the multiple lens LNS and the packing layer FIL, allowing light to propagate in a third direction DR3. The packing layer FIL may also be a planarization layer. The packing layer FIL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0126] The cover layer (CVL) is placed on the packing layer (FIL). The cover layer (CVL) can be a glass substrate or a polymer resin such as resin. If the cover layer (CVL) is a glass substrate, it can adhere to the packing layer (FIL). In this case, the packing layer (FIL) can serve as an adhesive for the cover layer (CVL). If the cover layer (CVL) is a glass substrate, it can serve as a sealing substrate. If the cover layer (CVL) is a polymer resin such as resin, it can be directly applied onto the packing layer (FIL).

[0127] The polarizer is placed on one surface of the cover layer (CVL). The polarizer may be a structure to prevent a decrease in visibility due to external light reflection. The polarizer may include a linear polarizer and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter-wave plate), but the embodiments herein are not limited thereto. However, if visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizer may be omitted.

[0128] Figure 8 is a cross-sectional view showing a detailed example of area A1 in Figure 7.

[0129] Referring to Figure 8, a trench TRC can be a structure for separating the charge generation layer between the first stack layer IL1 and the second stack layer IL2 of the light-emitting stack IL. A trench TRC can be defined as a hole that penetrates the pixel-defining film PDL and is further recessed in part of the 11th insulating film INS11. A trench TRC can be formed in an exposure process using argon fluoride (ArF) as the photoresist.

[0130] A trench TRC may include an entrance ENT, a side wall SW, and a bottom surface FS.

[0131] The entrance ENT of the trench TRC may be the open area at the top of the trench TRC defined by the third pixel defining film PDL3. The entrance ENT of the trench TRC may be covered by an emission stack IL. For example, a first stack layer IL1 and a second stack layer IL2 may be sequentially arranged at the edge of the entrance ENT of the trench TRC. The entrance ENT of the trench TRC that is exposed and not covered by the first stack layer IL1 and the second stack layer IL2 may be covered by a third stack layer IL3.

[0132] The sidewall SW of the trench TRC may be the side surface connecting the inlet ENT and the bottom surface FS of the trench TRC. The sidewall SW of the trench TRC is defined by the 11th insulating film INS11 and the pixel definition film PDL. The length of the sidewall SW of the trench TRC defined by the 11th insulating film INS11 may be greater than the length of the sidewall SW of the trench TRC defined by the pixel definition film PDL.

[0133] The bottom surface FS of the trench TRC may be a closed area at the bottom of the trench TRC defined by the 11th insulating film INS11. A residual stack layer RIL, made of the same material as the first stack layer IL1, may be placed on the bottom surface FS of the trench TRC.

[0134] The trench height Htrc can be defined as the maximum distance from the bottom surface FS of the trench TRC to the entrance ENT of the trench TRC in the third direction DR3. The trench height Htrc is preferably approximately 6,000 Å to 10,000 Å in order to separate the first and second stack layers IL1, IL2, the first charge generation layer, and the second charge generation layer in each trench TRC. In this case, the height of the pixel definition film PDL may be approximately 1,500 Å. For example, the sum of the thicknesses of the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be less than or equal to 1 / 4 of the trench height Htrc.

[0135] Furthermore, in order to separate the first and second stack layers IL1, IL2, the first charge generation layer, and the second charge generation layer in each trench TRC, the angle (θent1) between the tangent TL of the side wall SW of the trench TRC at the entrance ENT of the trench TRC and the upper surface of the third pixel defining film PDL3 is 80° or more and may be 90° or less. As a result, the maximum width Wsw1 at the center of the side wall SW of the trench TRC in one direction, for example in a plane including the first direction DR1 and the second direction DR2, may be greater than the width Went1 of the entrance ENT in one direction and the width Wfs1 of the bottom surface FS in one direction. That is, each trench TRC may have a vase-shaped cross-section.

[0136] Furthermore, in order to separate the first and second stack layers IL1 and IL2, the first charge generation layer, and the second charge generation layer in each trench TRC, the width Went1 of the trench TRC entrance ENT may be approximately greater than 100 nm and less than 130 nm. Also, the width Wfs1 of the bottom surface of the trench TRC in one direction may be smaller than the width Went1 of the trench TRC entrance ENT in one direction.

[0137] The first stack layer IL1 and the second stack layer IL2 may be positioned sequentially at the edges of each entrance ENT of the trench TRC. The first stack layer IL1 may be positioned more adjacent to the edge of each entrance ENT of the trench TRC than the second stack layer IL2. The third stack layer IL3 may be positioned to cover the remaining portion of each entrance ENT of the trench TRC that is not covered by the first stack layer IL1 and the second stack layer IL2.

[0138] According to one embodiment, the sealing layer TFE includes not only inorganic and organic films, but also transparent conductive oxides (e.g., IZO) and aluminum oxide (AlO xIt may further contain, for example, Al2O3. Therefore, the moisture-preventing function and sealing force of the sealing layer TFE can be improved. In particular, since the display device 10 including a trench TRC may have a structure that is vulnerable to moisture permeation from the outside through cavities (ES; for example, micro-sized cavities) generated by the trench TRC, the sealing layer TFE of one embodiment can prevent moisture permeation through such cavities ES.

[0139] Figure 9 is a detailed cross-sectional view showing an example of area A2 in Figure 7.

[0140] The dummy electrode DM is positioned between the substrate (e.g., semiconductor substrate SSUB) and the trench TRC of the pixel definition film PDL. For example, the dummy electrode DM may be positioned on the ninth insulating film INS9 so as to overlap with the trench TRC in a plan view (on a plane). The dummy electrode DM may include at least one or more dummy electrodes DM. For example, the dummy electrode DM may include, but is not limited to, a first dummy electrode DM1, a second dummy electrode DM2, a third dummy electrode DM3, and a fourth dummy electrode DM4 in the example of Figure 7.

[0141] The first dummy electrode DM1 is placed on the ninth interlayer insulating film INS9. The second dummy electrode DM2 is placed on the first dummy electrode DM1. The third dummy electrode DM3 is placed on the second dummy electrode DM2. The fourth dummy electrode DM4 is placed on the third dummy electrode DM3.

[0142] Adjacent dummy electrodes in the third direction DR3 can be connected to each other. For example, adjacent dummy electrodes can be in contact (or in direct contact) with each other. Specifically, the first dummy electrode DM1 and the second dummy electrode DM2 can be in contact (or in direct contact) with each other, the second dummy electrode DM2 and the third dummy electrode DM3 can be in contact (or in direct contact) with each other, and the third dummy electrode DM3 and the fourth dummy electrode DM4 can be in contact (or in direct contact) with each other.

[0143] The thickness of the second dummy electrode DM2 may be greater than the thickness of the first dummy electrode DM1, the third dummy electrode DM3, and the fourth dummy electrode DM4. Here, the thickness can be the size in the third direction DR3.

[0144] The dummy electrode DM and the trench TRC may be separated from each other by a predetermined distance. For example, the top surface TS of the dummy electrode DM and the bottom surface FS of the trench TRC may be separated from each other by a predetermined distance. Specifically, the top surface TS of the fourth dummy electrode DM4, which is placed on the uppermost layer of the dummy electrode DM, and the bottom surface FS of the trench TRC may be separated from each other by a predetermined distance. In this case, the 11th insulating film INS11 is placed between the dummy electrode DM and the trench TRC. For example, the 11th insulating film INS11 can be placed between the top surface TS of the dummy electrode DM and the bottom surface FS of the trench TRC.

[0145] As shown in Figure 8, when the residual film RINS is placed on the bottom surface FS of the trench TRC, the dummy electrode DM may face the residual film RINS. For example, the dummy electrode DM may overlap with the residual film RINS in the trench TRC in the third direction DR3. In this case, the dummy electrode DM and the residual film RINS may be separated from each other by a predetermined distance.

[0146] The first dummy electrode DM1 is made of one or an alloy containing any one of the following: copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first dummy electrode DM1 may contain titanium nitride (TiN), the second dummy electrode DM2 may contain aluminum (Al), the third dummy electrode DM3 may contain titanium nitride (TiN), and the fourth dummy electrode DM4 may contain titanium (Ti).

[0147] The dummy electrode DM is placed on the same layer as the aforementioned reflective electrode RL. For example, the dummy electrode DM and the reflective electrode RL may be placed on the aforementioned ninth insulating film INS9.

[0148] The first dummy electrode DM1 may be placed on the same layer as the first reflective electrode RL1, the second dummy electrode DM2 may be placed on the same layer as the second reflective electrode RL2, the third dummy electrode DM3 may be placed on the same layer as the third reflective electrode RL3, and the fourth dummy electrode DM4 may be placed on the same layer as the fourth reflective electrode RL4.

[0149] The first dummy electrode DM1 and the first reflective electrode RL1 may be made of the same material, the second dummy electrode DM2 and the second reflective electrode RL2 may be made of the same material, the third dummy electrode DM3 and the third reflective electrode RL3 may be made of the same material, and the fourth dummy electrode DM4 and the fourth reflective electrode RL4 may be made of the same material.

[0150] The first dummy electrode DM1 and the first reflective electrode RL1 can be formed together in the same process, the second dummy electrode DM2 and the second reflective electrode RL2 can be formed together in the same process, the third dummy electrode DM3 and the third reflective electrode RL3 can be formed together in the same process, and the fourth dummy electrode DM4 and the fourth reflective electrode RL4 can be formed together in the same process.

[0151] In a plan view, the dummy electrode DM may overlap with the trench TRC. For example, the dummy electrode DM may overlap with the trench TRC in the third direction DR3. The dummy electrode DM is positioned between the ninth insulating film INS9 and the trench TRC. The top surface TS of the dummy electrode DM may face the bottom surface FS of the trench TRC. For example, the top surface TS of the fourth dummy electrode DM4, positioned on the uppermost layer of the dummy electrode DM, may face the bottom surface FS of the trench TRC. In the example shown in Figure 9, the width of the trench TRC and the width of the dummy electrode DM may be approximately the same in the planar direction including the first direction DR1 and the second direction DR2. Therefore, in the example shown in Figure 9, the positions of the edges of the trench TRC and the edges of the dummy electrode DM are approximately the same. Furthermore, if leakage current flows easily through the dummy electrode DM, the trench TRC and the dummy electrode DM do not need to completely overlap in a planar view, and the widths of the trench TRC and the dummy electrode DM do not need to be approximately the same.

[0152] The dummy electrode DM may have the shape of a closed curve surrounding the light-emitting region in a plan view, as shown in Figure 5 or Figure 6. For example, a plurality of dummy electrodes DM may include a dummy electrode DM surrounding a first light-emitting region EA1, a dummy electrode DM surrounding a second light-emitting region EA2, and a dummy electrode DM surrounding a third light-emitting region EA3. Each of the plurality of dummy electrodes DM may include a first dummy electrode DM1, a second dummy electrode DM2, a third dummy electrode DM3, and a fourth dummy electrode DM4 stacked along the third direction DR3 as described above.

[0153] When viewed from above, the dummy electrode DM is positioned along the trench TRC. When viewed from above, the dummy electrode DM and the trench TRC can have the same shape. For example, when viewed from above, the dummy electrode DM and the trench TRC can each have the shape of a closed curve enclosing the light-emitting region.

[0154] A power supply (e.g., a constant power supply) can be applied to the dummy electrode DM. Here, the power supply may include at least one of voltage (e.g., a constant voltage) and current (a constant current). For this purpose, for example, the dummy electrode DM may be connected to a power supply circuit 500. According to one embodiment, at least one of the multiple dummy electrodes DM1, DM2, DM3, DM4 included in a single dummy electrode DM may be connected to the power supply circuit 500. As another example, the dummy electrode DM may be connected to ground. For example, at least one of the multiple dummy electrodes DM1, DM2, DM3, DM4 included in a single dummy electrode DM may be connected to ground.

[0155] The voltage applied to the dummy electrode DM may be less than the voltage applied to the first electrode AND. In such a case, the dummy electrode DM may be connected to ground.

[0156] In another embodiment, the voltage applied to the dummy electrode DM may be the same as the first drive voltage VSS described above. In this case, the dummy electrode DM may be connected to the first drive voltage line VSL.

[0157] In another embodiment, the voltage applied to the dummy electrode DM may be the same as the third drive voltage VINT described above. In this case, the dummy electrode DM may be connected to the third drive voltage line VIL.

[0158] According to one embodiment, the dummy electrode DM is positioned adjacent to the trench TRC. This minimizes the leakage current between adjacent subpixels (e.g., lateral leakage current). This will be explained in detail below.

[0159] As mentioned above, the light-emitting stack (IL; for example, the charge generation layer of the light-emitting stack IL) may be divided by trenches TRC, thereby blocking the path of leakage current between adjacent subpixels (for example, the first subpixel SP1 containing the first light-emitting region EA1 and the second subpixel SP2 containing the second light-emitting region EA2). However, if the width of the trench TRC (width along the plane containing the first direction DR1 and the second direction DR2) is small, leakage current may occur between adjacent subpixels through the divided light-emitting stack IL. To suppress this problem, as mentioned above, the height Htrc, angle θent1, maximum width Wsw1, width Went1, width Wfs1, etc. of the trench TRC should be appropriately designed. In addition, the height of the pixel-defining film PDL, the height of the first and second stack layers IL1 and IL2, the height of the 11th insulating film INS11, etc., which may be related to the shape and various lengths of the trench TRC, also need to be designed so that the light-emitting stack (IL; for example, the charge generation layer of the light-emitting stack IL) can be divided by the trench TRC. According to one embodiment, the path of leakage current due to the divided light-emitting stack IL can be altered by the dummy electrode DM. For example, leakage current between adjacent subpixels can flow more through the dummy electrode DM, which has relatively low resistance on the trench TRC. In other words, the electric field generated around the dummy electrode DM when power is applied can cause charge (e.g., leakage current charge) from the light-emitting stack (IL; e.g., divided charge generation layer) on the trench TRC to flow to the dummy electrode DM via the pixel-defining film PDL and the 11th insulating film INS11. In this way, the electric field from the dummy electrode DM collects charge on the leakage current path, thereby minimizing the leakage current between adjacent subpixels. Consequently, color mixing between adjacent subpixels can be prevented, improving the image quality of the display device 10. As mentioned above, the voltage applied to the dummy electrode DM is different from the voltage applied to the first electrode (anode electrode) AND of the light-emitting element LE. For example, the voltage applied to the dummy electrode DM can be made smaller than the voltage applied to the first electrode AND. This also causes the leakage current between adjacent subpixels to flow more easily to the dummy electrode DM side rather than the first electrode AND side, thus minimizing the leakage current between adjacent subpixels.

[0160] Figure 10 is a cross-sectional view of the display device 10 according to another embodiment. For example, Figure 10 may be a cross-sectional view showing in detail another example of area A2 in Figure 7.

[0161] The display device 10 in Figure 10 differs from the display device 10 in Figure 9 in terms of the shape of the trench TRC; therefore, the following explanation will focus on these differences.

[0162] As shown in Figure 10, the trench TRC can be connected to a dummy electrode DM. For example, the trench TRC and the dummy electrode DM can be in contact with each other. Therefore, the bottom surface FS of the trench TRC can be substantially the top surface TS of the dummy electrode DM. In other words, the top surface TS of the dummy electrode DM can define the bottom surface FS of the trench TRC. For example, the top surface of the fourth dummy electrode DM4, which is located on the uppermost layer of the dummy electrode DM, can be the bottom surface FS of the trench TRC.

[0163] In Figure 10, the dummy electrode DM can be used as an etching stop film that defines the depth of the trench TRC (for example, the size in the reverse direction of the third direction DR3 (hereinafter referred to as the third reverse direction)). For example, after forming the dummy electrode DM, the trench TRC is formed by etching (for example, dry etching) the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. In this case, the etching of the aforementioned pixel definition films PDL1, PDL2, and PDL3 can be stopped by the dummy electrode DM containing a metallic material.

[0164] As shown in Figure 8, when the residual film RINS is positioned on the bottom surface FS of the trench TRC, the dummy electrode DM may face the residual film RINS. For example, the dummy electrode DM may overlap with the residual film RINS in the trench TRC in the third direction DR3. In this case, the dummy electrode DM and the residual film RINS may be in contact (or in direct contact) with each other.

[0165] Figure 11 is a cross-sectional view of the display device 10 according to another embodiment. For example, Figure 11 is a cross-sectional view showing in detail another example of area A2 in Figure 7. Figure 12 is a diagram illustrating the planar shape of the dummy electrode DM in Figure 11.

[0166] The display devices 10 in Figures 11 and 12 differ from the display device 10 in Figure 9 in the shape of the dummy electrode DM; therefore, the following explanation will focus on these differences.

[0167] As shown in Figure 11, the dummy electrode DM can overlap with multiple adjacent trenches TRC in a plan view. For example, one dummy electrode DM can overlap with two adjacent trenches TRC in a third direction DR3. Specifically, both side edges of the dummy electrode DM can overlap with the bottom surfaces FS of the two trenches TRC. In other words, both side edges of the dummy electrode DM, excluding the center of the top surface TS, can overlap with the bottom surfaces FS of the two trenches TRC. The center of the dummy electrode DM does not overlap with the trenches TRC. Therefore, in Figure 9, multiple dummy electrodes DM are arranged to correspond to multiple trenches TRC, whereas in Figure 11, one dummy electrode DM is arranged to correspond to multiple trenches TRC. In other words, it is not necessary to place a dummy electrode DM for each of the multiple trenches TRC, and a dummy electrode DM may be placed in common for multiple trenches TRC. In the example shown in Figure 11, the sum of the widths of the two trenches TRC and the width between the two trenches TRC in the planar direction including the first direction DR1 and the second direction DR2 may be approximately the same as the width of the dummy electrode DM. Therefore, in the example shown in Figure 11, the position of the edge of one trench TRC and the position of one edge of the dummy electrode DM are approximately the same, and the position of the edge of the other trench TRC and the position of the other edge of the dummy electrode DM are approximately the same. Furthermore, if leakage current flows easily through the dummy electrode DM, the trenches TRC and the dummy electrode DM do not need to completely overlap in a planar view, and the sum of the widths of multiple trenches TRC and the width between multiple trenches TRC does not need to be approximately the same as the width of the dummy electrode DM.

[0168] The dummy electrode DM and the two trenches TRC may be separated from each other by a predetermined distance. For example, the top surface TS of the dummy electrode DM and the bottom surfaces FS of the two trenches TRC may be separated from each other by a predetermined distance. Specifically, the top surface TS of the fourth dummy electrode DM4, which is located on the uppermost layer of the dummy electrode DM, and the bottom surfaces FS of the two trenches TRC may be separated from each other by a predetermined distance.

[0169] As shown in Figure 12, in a plan view, the dummy electrode DM can surround the trench TRC. In this case, the edge of the dummy electrode DM may overlap with the trench TRC. However, in a plan view, the center of the dummy electrode DM may not overlap with the trench TRC and may be positioned between adjacent trenches TRC.

[0170] As shown in Figure 12, in plan view, the dummy electrode DM may have through holes. The region enclosed by the through holes of the dummy electrode DM may overlap with the light-emitting region. A tenth insulating film INS10 may be present inside each through hole. For example, the dummy electrode DM may include a first through hole PH1, a second through hole PH2, and a third through hole PH3 that penetrate the dummy electrode DM in a third direction DR3. The region enclosed by the first through hole PH1 may overlap with the first light-emitting region EA1, the region enclosed by the second through hole PH2 may overlap with the second light-emitting region EA2, and the region enclosed by the third through hole PH3 may overlap with the third light-emitting region EA3. According to one embodiment, in plan view, the first through hole PH1 may enclose the first light-emitting region EA1, the second through hole PH2 may enclose the second light-emitting region EA2, and the third through hole PH3 may enclose the third light-emitting region EA3. According to one embodiment, when viewed from above, the size of the region surrounded by the first through-hole PH1 may be larger than the size of the first light-emitting region EA1, the size of the region surrounded by the second through-hole PH2 may be larger than the size of the second light-emitting region EA2, and the size of the region surrounded by the third through-hole PH3 may be larger than the size of the third light-emitting region EA3.

[0171] As shown in Figure 8, when residual film RINS is placed on the bottom surface FS of each trench TRC, the dummy electrode DM may face the residual film RINS. For example, the dummy electrode DM may overlap with the residual film RINS in the trench TRC in the third direction DR3. In this case, the dummy electrode DM and the residual film RINS may be separated from each other by a predetermined distance.

[0172] Figure 13 is a cross-sectional view of the display device 10 according to another embodiment. For example, Figure 13 may be a cross-sectional view showing in detail another example of area A2 in Figure 7.

[0173] The display device 10 in Figure 13 differs from the display device 10 in Figure 11 in the shape of the dummy electrode DM, so the following explanation will focus on these differences.

[0174] As shown in Figure 13, adjacent trenches TRC can be connected to dummy electrodes DM. For example, trenches TRC and dummy electrodes DM can be in contact with each other. Therefore, each bottom surface FS of a trench TRC can be substantially the top surface TS of a dummy electrode DM. In other words, the top surface TS of a dummy electrode DM can define each bottom surface FS of a trench TRC. For example, the top surface of a fourth dummy electrode DM4, located on the uppermost layer of dummy electrode DM, can be each bottom surface FS of a trench TRC.

[0175] In Figure 13, the dummy electrode DM can be used as an etching stop film that defines each depth of the trench TRC (e.g., the size in the third reverse direction). For example, after forming the dummy electrode DM, the trench TRC is formed by etching (e.g., dry etching) the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. In this process, the etching of the aforementioned pixel definition films PDL1, PDL2, and PDL3 can be stopped by the dummy electrode DM containing a metallic material.

[0176] As shown in Figure 8, when residual film RINS is placed on the bottom surface FS of each trench TRC, the dummy electrode DM may face the residual film RINS. For example, the dummy electrode DM may overlap with the residual film RINS in the trench TRC in the third direction DR3. In this case, the dummy electrode DM and the residual film RINS may be in contact (or in direct contact) with each other.

[0177] Furthermore, the plan view of the display device 10 in Figure 13 may be substantially identical to that of Figure 12 mentioned above. In other words, the planar shape of the dummy electrode DM in Figure 13 and the planar shape of the trench TRC in Figure 13 may be identical to the planar shape of the dummy electrode DM in Figure 12 and the planar shape of the trench TRC in Figure 12, respectively.

[0178] Figure 14 is a cross-sectional view of the display device 10 according to another embodiment. For example, Figure 14 may be a cross-sectional view showing in detail another example of the A2 region of Figure 7. Figure 15 is a diagram illustrating the planar shape of the dummy electrode DM of Figure 14.

[0179] The display devices 10 in Figures 14 and 15 differ from the display device 10 in Figure 9 in the shape of the dummy electrode DM; therefore, the following explanation will focus on these differences.

[0180] As shown in Figure 14, in a plan view, the dummy electrode DM does not overlap with the trench TRC. For example, the dummy electrode DM does not overlap with the trench TRC in the third direction DR3. Instead, the dummy electrode DM may overlap with the pixel defining film PDL and the 11th insulating film INS11 that define its trench TRC. Specifically, the dummy electrode DM is located between two trenches TRC. Even if the dummy electrode DM does not overlap with the trench TRC in this way, it is sufficient if it is designed so that leakage current flows easily through the dummy electrode DM. Furthermore, unlike the configuration shown in Figure 14 where two trenches are provided, only one trench TRC may be provided, and the dummy electrode DM may be formed offset from this trench TRC in a plan view so as not to overlap it.

[0181] As shown in Figure 15, in a plan view, the dummy electrode DM is positioned between adjacent trenches TRC.

[0182] As shown in Figure 15, in a plan view, the dummy electrode DM can surround the trench TRC.

[0183] As shown in Figure 15, in plan view, the dummy electrode DM may have through holes. The region surrounded by the through holes of the dummy electrode DM may overlap with the light-emitting region. A tenth insulating film INS10 may be present inside each through hole. For example, the dummy electrode DM may include a first through hole PH1, a second through hole PH2, and a third through hole PH3 that penetrate the dummy electrode DM in a third direction DR3. The region surrounded by the first through hole PH1 may overlap with the first light-emitting region EA1, the region surrounded by the second through hole PH2 may overlap with the second light-emitting region EA2, and the region surrounded by the third through hole PH3 may overlap with the third light-emitting region EA3. According to one embodiment, in plan view, the region surrounded by the first through hole PH1 may surround the first light-emitting region EA1, the region surrounded by the second through hole PH2 may surround the second light-emitting region EA2, and the region surrounded by the third through hole PH3 may surround the third light-emitting region EA3. According to one embodiment, when viewed from above, the size of the region surrounded by the first through-hole PH1 may be larger than the size of the first light-emitting region EA1, the size of the region surrounded by the second through-hole PH2 may be larger than the size of the second light-emitting region EA2, and the size of the region surrounded by the third through-hole PH3 may be larger than the size of the third light-emitting region EA3.

[0184] As shown in Figure 8, residual film RINS may be placed on the bottom surface FS of each trench TRC. In the example in Figure 14, the dummy electrode DM does not face the residual film RINS on the bottom surface FS of each trench TRC. For example, the dummy electrode DM may not overlap with the residual film RINS in the trench TRC in the third direction DR3, but may overlap with the tenth insulating film INS10. In this case, the dummy electrode DM and the residual film RINS may be separated from each other by a predetermined distance.

[0185] Figure 16 is a perspective view showing a head-mounted display device according to one embodiment. Figure 17 is an exploded perspective view showing an example of the head-mounted display device of Figure 16.

[0186] Referring to Figures 16 and 17, a head-mounted display device 1000 according to one embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head mounting band 1300, a middle frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0187] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Since the first display device 10_1 and the second display device 10_2 are substantially the same as the display device 10 described with reference to Figures 1 to 15, a description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0188] The first optical member 1510 is positioned between the first display device 10_1 and the first eyepiece lens 1210. The second optical member 1520 is positioned between the second display device 10_2 and the second eyepiece lens 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0189] The middle frame 1400 is positioned between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 serves to support and secure the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0190] The control circuit board 1600 is positioned between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 converts an externally input video source into digital video data DATA and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0191] The control circuit board 1600 transmits digital video data corresponding to the left eye image optimized for the user's left eye to the first display device 10_1, and digital video data corresponding to the right eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data to both the first display device 10_1 and the second display device 10_2.

[0192] The display device housing 1100 houses the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is positioned to cover one open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 in which the user's left eye is positioned and a second eyepiece 1220 in which the user's right eye is positioned. Figures 16 and 17 show an example in which the first eyepiece 1210 and the second eyepiece 1220 are positioned separately, but the embodiments herein are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be integrated.

[0193] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical element 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical element 1520. Therefore, the user can view the image of the first display device 10_1, magnified as a virtual image by the first optical element 1510, through the first eyepiece 1210, and the image of the second display device 10_2, magnified as a virtual image by the second optical element 1520, through the second eyepiece 1220.

[0194] The head mounting band 1300 secures the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned for the user's left and right eyes, respectively. If the display device housing 1100 is lightweight and compact, the head-mounted display device 1000 may be equipped with a spectacle frame instead of the head mounting band 1300, as shown in Figure 18.

[0195] In addition, the head-mounted display device 1000 may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving video sources. The external connection port may be a USB (universe serial bus) terminal, a DisplayPort, or an HDMI® (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth® module.

[0196] Figure 18 is a perspective view showing a head-mounted display device according to one embodiment.

[0197] Referring to Figure 18, one embodiment of the head-mounted display device 1000_1 may be a glasses-type display device in which the display device housing 1200_1 is lightweight and compact. One embodiment of the head-mounted display device 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040, 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0198] The display device housing 1200_1 may include a display device 10_3, an optical element 1060, and an optical path conversion element 1070. The image displayed on the display device 10_3 is augmented by the optical element 1060, and the optical path is converted by the optical path conversion element 1070 and provided to the user's right eye via the right eye lens 1020. This allows the user to view an augmented reality image that combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0199] Figure 18 shows an example in which the display device housing 1200_1 is located at the right end of the support frame 1030, but the embodiments herein are not limited to this. For example, the display device housing 1200_1 can be located at the left end of the support frame 1030, in which case the image from the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 can be located at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0200] A person with ordinary skill in the art to which this specification belongs will understand that this specification can be implemented in other specific forms without altering its technical idea or essential features. Therefore, the embodiments described above should be understood to be illustrative and not restrictive in all respects. The scope of this specification is indicated not by the above detailed description but by the claims set forth below, and all modifications or alterations derived from the meaning and scope of the claims and the concept of equivalents thereof should be construed as being included within the scope of this specification.

[0201] This specification and its drawings disclose preferred embodiments thereof, and specific terms are used, but these are merely general terms used to facilitate the explanation of the technical content of this specification and to aid in the understanding of the invention, and do not limit the scope of this specification. It will be obvious to a person ordinary skill in the art to which this specification belongs that, in addition to the embodiments disclosed herein, other modifications based on the technical idea of ​​this specification can be carried out. [Explanation of symbols]

[0202] DA display area DM dummy electrode DM1 First dummy electrode DM2 Second Dummy Electrode DM3 Third Dummy Electrode DM4 4th dummy electrode PDL Pixel Definition Film PDL1 First Pixel Definition Film PDL2 Second Pixel Defining Artery PDL3 Third Pixel Definition Layer RL reflective electrode RL1 1st reflective electrode RL2 2nd reflective electrode RL3 3rd reflective electrode RL4 4th reflective electrode CAT 2nd electrode TFE1 1st sealing inorganic membrane TFE2 sealing organic film DR3 3rd direction AND 1st electrode VA9 (9th Via) VA10 (Via 10) INS9 9th Insulating Film INS10 10th Insulating Film INS11 11th Insulating Film IL Emission Stack IL1 First Stack Layer IL2 Second Stack Layer IL3 3rd Stack Layer TRC Trench EA1 First emission region EA2 Second emission region TS FS bottom

Claims

1. circuit board and The first electrode on the substrate, A pixel definition film having a trench is placed on the first electrode, The first electrode and the light-emitting stack on the pixel-defining film, Includes a dummy electrode positioned between the substrate and the trench, A display device in which the voltage applied to the dummy electrode and the voltage applied to the first electrode are different from each other.

2. The display device according to claim 1, wherein the voltage applied to the dummy electrode is smaller than the voltage applied to the first electrode.

3. The display device according to claim 1, wherein the dummy electrode is connected to ground.

4. The display device according to claim 1, wherein the dummy electrode overlaps the trench.

5. The display device according to claim 1, further comprising an insulating film between the dummy electrode and the trench.

6. The display device according to claim 1, wherein the dummy electrode and the trench are separated from each other.

7. The display device according to claim 1, wherein the dummy electrode and the trench are connected to each other.

8. The display device according to claim 7, wherein the upper surface of the dummy electrode defines the bottom surface of the trench.

9. The display device according to claim 1, wherein the dummy electrode is arranged along the trench.

10. The pixel definition film has a plurality of trenches surrounding different light-emitting regions. The display device according to claim 1, wherein the dummy electrode overlaps with a plurality of adjacent trenches.

11. The display device according to claim 10, wherein the edge of the dummy electrode overlaps with a plurality of adjacent trenches.

12. The display device according to claim 11, wherein the central part of the dummy electrode overlaps with the pixel definition film between a plurality of adjacent trenches.

13. The display device according to claim 10, wherein the dummy electrode does not overlap with the trench.

14. The display device according to claim 13, wherein the dummy electrode overlaps with the pixel definition film.

15. The pixel definition film has a plurality of trenches surrounding different light-emitting regions. The display device according to claim 1, wherein the dummy electrode overlaps with the pixel definition film between a plurality of adjacent trenches.

16. The display device according to claim 1, wherein, when viewed from above, the dummy electrode surrounds the light-emitting region defined by the pixel-defining film.

17. The display device according to claim 16, wherein, when viewed from above, the dummy electrode has a through hole surrounding the light-emitting region.

18. The display device according to claim 1, wherein the dummy electrodes include a plurality of dummy electrodes arranged between the substrate and the trench, along a direction from the substrate toward the trench.

19. The dummy electrode is, The first dummy electrode on the substrate, The second dummy electrode on the first dummy electrode, A third dummy electrode on the preceding second dummy electrode, The display device according to claim 18, further comprising a fourth dummy electrode on the third dummy electrode.

20. The display device according to claim 1, further comprising a reflective electrode connected to the first electrode.

21. The display device according to claim 20, wherein the dummy electrode is arranged on the same layer as the reflective electrode.

22. The display device according to claim 20, wherein the dummy electrode is made of the same material as the reflective electrode.

23. Display device and Including an optical path conversion member on the display device, The aforementioned display device is circuit board and The first electrode on the substrate, A pixel definition film having a trench is placed on the first electrode, The first electrode and the light-emitting stack on the pixel-defining film, Includes a dummy electrode positioned between the substrate and the trench, An optical device in which the voltage applied to the dummy electrode and the voltage applied to the first electrode are different from each other.

24. The optical apparatus according to claim 23, wherein the voltage applied to the dummy electrode is smaller than the voltage applied to the first electrode.

25. The optical apparatus according to claim 23, wherein the dummy electrode is connected to ground.

26. The optical apparatus according to claim 23, wherein the dummy electrode overlaps the trench.

27. The optical apparatus according to claim 23, further comprising an insulating film between the dummy electrode and the trench.

28. The optical apparatus according to claim 23, wherein the dummy electrode and the trench are separated from each other.

29. The optical apparatus according to claim 23, wherein the dummy electrode and the trench are connected to each other.

30. The optical apparatus according to claim 29, wherein the upper surface of the dummy electrode defines the bottom surface of the trench.

31. The optical apparatus according to claim 23, wherein the dummy electrode is arranged along the trench.

32. The pixel definition film has a plurality of trenches surrounding different light-emitting regions. The optical apparatus according to claim 23, wherein the dummy electrode overlaps with a plurality of adjacent trenches.

33. The optical apparatus according to claim 32, wherein the edge of the dummy electrode overlaps with a plurality of adjacent trenches.

34. The optical apparatus according to claim 33, wherein the central part of the dummy electrode overlaps with the pixel-defining film between a plurality of adjacent trenches.

35. The optical apparatus according to claim 32, wherein the dummy electrode does not overlap with the trench.

36. The optical apparatus according to claim 35, wherein the dummy electrode overlaps with the pixel defining film.

Images