Programmable controller redundancy system and recording method for said redundancy system

Abstract

This invention provides a method for efficiently managing data changes in data memory by integrating equivalent processing and recording functions in a PLC redundancy system. [Solution] The PLC redundancy system comprises a master and a slave. The master and slave each comprise CPU modules 30a and 30b and a database module 31a. The contents of the data memory 11 rewritten by CPU module 30a are stored in a ring buffer 12, and communication data 13 is created from the ring buffer 12 and sent to CPU module 30b and the database module. CPU module 30b normally rewrites the data memory 22 based on the received communication data 13. The database module records the changes in the data memory 11 in a time-series database 45 based on the received communication data 13.

Description

Technical Field

[0001] The present invention relates to a technique for recording time-series information of a memory during equivalent processing between a master and a slave in a system in which a programmable controller (hereinafter, PLC) is duplicated as a master-slave.

Background Art

[0002] In a PLC, data obtained as a result of calculations or received through communication is stored on a memory (data memory) used by a user. Particularly, in a duplicated PLC system, the data memories are made equivalent between the master and the slave (see Patent Document 1). That is, during normal operation, the data in the data memory of the master is transmitted to the slave, and the slave makes the received data equivalent to its own data memory.

[0003] In this case, as shown in Patent Document 2, if the master transmits only the area of the data memory in which data has been rewritten by arithmetic processing or communication processing that operates at a set cycle to the slave, efficient equivalence of the data memory can be achieved.

[0004] Based on FIG. 5, the data structure used for equivalence of the data memory will be described. In FIG. 5, 10 indicates the master PLC, and 20 indicates the slave PLC.

[0005] (1) Data Memory 11 of Master 10 The master 10 performs read / write access to the data memory 11 and executes arithmetic processing and communication processing. The basic operation of the H / W (hardware) circuit when performing an arithmetic operation is to read data from the address of the data memory specified in the application, execute an arithmetic operation using the data, and write the data of the arithmetic result to the data memory 11.

[0006] (2) Ring Buffer 12 of Master 10 The ring buffer 12 of the master 10 is used as a memory area on the ring and is used as an area to store address data and rewritten data. To manage the ring buffer 12, the ring buffer 12 has both an address pointer to which data is written and an address pointer for sending data.

[0007] The destination address pointer indicates the address to which the address data and the rewritten data will be written, and is updated to the next address after the writing is completed by the hardware circuit. The address pointer for transmitting data indicates the starting address of the data portion 13b of the communication data 13, and is updated to the next address after the data portion 13b of the communication data 13 is created by the hardware circuit.

[0008] (3) Communication data 13 Communication data 13 is data for performing communication compliant with well-known local area network standards such as "Ethernet (registered trademark)," and has a header section 13a and a data section 13b. The data section 13b has a communication sequence number 13c, equivalent data (data rewritten with address data) 13d, and a communication sequence number inversion value 13e. The communication data is transmitted from the master 10 to the slave 20.

[0009] (4) Data memory 22 of slave 20 Slave 20 uses data memory 22 to perform arithmetic and communication processing. The basic operation of the hardware circuit when performing calculations is to read data from the address of data memory 22 specified by the application, perform calculations using that data, and write the calculation result data to data memory 22.

[0010] Furthermore, as shown in Figure 6, the slave 20 performs data equivalent processing after receiving the communication data 13, once the arithmetic and communication processing is completed and it transitions to normal operation. That is, it expands the address data rewritten by the master 10 into the data memory 22 based on the equivalent data 13d of the communication data 13 received by the H / W circuit. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 04-49402 [Patent Document 2] Japanese Patent Publication No. 2019-117482 [Overview of the project] [Problems that the invention aims to solve]

[0012] In recent years, the recording function of PLCs, which records calculation results and data received through communication processing, has been attracting attention.

[0013] This recording function records changes (rewrites / updates) in the user's data memory 11 in chronological order on the database. However, the data structure and timing of the equivalent processing shown in Figures 1 and 2 alone are insufficient to achieve an efficient recording function, and each of these needs to be reviewed.

[0014] This invention was made to solve the problems of the conventional system, and aims to propose a method for efficiently recording and managing data changes in data memory by integrating equivalent processing and recording functions of a PLC redundancy system. [Means for solving the problem]

[0015] (1) One aspect of the present invention is: A system of programmable controllers (hereinafter referred to as PLCs) with a master and slave configuration, The aforementioned master is CPU module and Database module, Equipped with, The CPU module and the slave are, It is equipped with a data memory that can be rewritten during arithmetic and communication processing, The CPU module includes a ring buffer for storing the content of the rewrite of the data memory during normal operation excluding the arithmetic processing and the communication processing, creates communication data from the stored data in the ring buffer, and transmits the created communication data to the slave and the database module, The slave rewrites its own data memory during normal times based on the received communication data and executes equivalent processing, while The database module is characterized by recording the changes in the data memory in a database in chronological order based on the received communication data and performing recording processing.

[0016] (2) Another aspect of the present invention is duplicated into a master and a slave, The master includes a CPU module, a database module, and The CPU module and the slave include a data memory in which data is rewritten during arithmetic processing and communication processing, The CPU module is a recording method executed by a dual system of a programmable controller (hereinafter referred to as PLC) including a ring buffer for storing the rewrite content of the data memory, wherein the CPU module creates communication data from the stored data in the ring buffer during normal times excluding the arithmetic processing and the communication processing, and transmits the created communication data to the slave and the database module; the slave rewrites its own data memory during normal times based on the received communication data and executes equivalent processing; The database module records in a database the changes in the data memory of the CPU module over time based on the received communication data and performs a recording process.

Advantages of the Invention

[0017] According to the present invention, by integrating the equivalent processing and recording function of the PLC dualization system, it becomes possible to efficiently record and manage the data changes in the data memory.

Brief Description of the Drawings

[0018] [Figure 1] Configuration diagram of a PLC dualization system according to an embodiment of the present invention. [Figure 2] Block diagram of the same CPU module and database module. [Figure 3] Explanatory diagram showing the same data equivalence processing and recording function. [Figure 4] Timing diagram of the same data equivalence processing and recording function. [Figure 5] Explanatory diagram showing the data equivalence processing of a conventional PLC dualization system. [Figure 6] Timing diagram of the same data equivalence processing.

Modes for Carrying Out the Invention

[0019] Hereinafter, a PLC dualization system according to an embodiment of the present invention will be described. This system is dualized into a master PLC and a slave PLC, and realizes equivalent processing and a recording function as a single entity. The same components as those in FIGS. 5 and 6 will be described using the same reference numerals.

[0020] ≪Example of System Configuration≫ Reference numeral 1 in FIG. 1 shows an example of the configuration of the PLC dualization system. This system 1 includes a master 10 and a slave 20, and both 10 and 20 are each provided with a CPU module 30 and a database module 31.

[0021] Specifically, 30a and 31a in Figure 1 represent the CPU module 30 and database module 31 of the master 10, while 30b and 31b represent the CPU module 30 and database module 31 of the slave 20.

[0022] Here, the equivalent processing of System 1 is performed between CPU modules 30a and 30b, while the recording function is performed between CPU module 30a and database module 31a.

[0023] Here, CPU modules 30a and 30b are connected via a redundant cable (such as an Ethernet cable) 40a, enabling communication between them. Additionally, CPU modules 30a and 30b are connected to database modules 31a and 31b via a LAN cable 40b, enabling communication between them.

[0024] As shown in Figure 2, CPU modules 30a and 30b implement a CPU 32, data memories 11 and 22, and a communication unit 33. However, the ring buffer 12 in Figure 2 only needs to be implemented in CPU module 30a, and 33a in the same figure represents the communication unit 33 implemented in CPU module 30a, while 33b represents the communication unit 33 implemented in CPU module 30b.

[0025] On the other hand, database modules 31a and 31b implement storage (HDD, SSD, etc.) 34 and a communication unit 35. In Figure 2, 35a represents the communication unit 35 implemented in database module 31a, and 35b represents the communication unit 35 implemented in database module 31b.

[0026] ≪Data Structure≫ The data structures for the equivalence processing and recording functions are explained based on Figure 3. Here, the data structure for the equivalence processing is basically the same as the conventional example in Figure 5.

[0027] <Data structure for equivalent processing> (1) Data memory 11 of CPU module 30a The CPU 32 of the CPU module 30a performs calculations and communication processing by writing to the data memory 11. The basic operation of the hardware circuit when performing calculations is to read data from the data memory address specified by the application, perform calculations using that data, and write the calculation result data to the data memory 11.

[0028] (2) Ring buffer 12 of CPU module 30a The ring buffer 12 of the CPU module 30a is used as a memory area on the ring and is used as an area to store address data and rewrite data. To manage the ring buffer 12, the ring buffer 12 has both an address pointer to which data is written and an address pointer for sending data.

[0029] The destination address pointer indicates the address to which the address data and the rewritten data will be written, and is updated to the next address after the writing is completed by the hardware circuit. The address pointer for transmitting data indicates the starting address of the data portion 13b of the communication data 13, and is updated to the next address after the data portion 13b of the communication data 13 is created by the hardware circuit.

[0030] (3) Communication data 13 Communication data 13 is data for performing communication compliant with well-known local area network standards such as "Ethernet (registered trademark)," and has a header section 13a and a data section 13b. This communication data 13 has a communication sequence number 13c, equivalent data (data rewritten with address data) 13d, and a communication sequence number inversion value 13e. This communication data 13 is transmitted from communication unit 33a to communication unit 33b and communication unit 35a.

[0031] (4) Data memory 22 of CPU module 30b The CPU 32 of the CPU module 30b performs arithmetic and communication processing using the data memory 22. The basic operation of the hardware circuit when performing calculations is to read data from the address of the data memory 22 specified by the application, perform calculations using that data, and write the calculation result data to the data memory 22.

[0032] As shown in Figure 4, the CPU module 30b performs data equivalence processing after receiving the communication data 13, once the arithmetic and communication processing is completed and it transitions to normal operation. That is, the communication unit 33b's hardware circuit expands the data of the address rewritten by the master 10 into the data memory 22 based on the equivalent data 13d of the communication data 13 received by the communication unit 33b.

[0033] <Recording function> (1) Time-series database 45 of database module 31a The storage 34 of the database module 31a contains the time-series database 45 shown in Figure 3.

[0034] In other words, when the communication unit 35a receives the communication data 13, the database module 31a records the address data and data of the data memory 11, which have been rewritten by the CPU module 30a based on the equivalent data 13d of the communication data 13, in the time-series database 45 at a time-based interval. The date and time recorded here is not the date and time when the data memory 11 was rewritten, but the date and time recorded in the time-series database 45.

[0035] (2) Scheduling Based on Figure 4, the scheduling of the recording function of the PLC redundancy system 1 will be explained.

[0036] First, the CPU module 30a performs arithmetic processing, communication processing, and data equivalence processing for each event cycle. Furthermore, during normal operation after arithmetic and communication processing, the communication unit 33a sends communication data 13 to the communication unit 33b of the CPU module 30b via Ethernet communication or similar means. Similarly, the communication unit 33a sends the communication data 13 to the communication unit 35a of the database module 31a as data for the time-series database.

[0037] Next, the CPU module 30b performs arithmetic and communication processing at each event cycle. When the communication unit 33b receives communication data 13 via Ethernet or other means, it performs equivalent processing of the data memory 22 using equivalent data 13d of the communication data 13 during normal operation.

[0038] Then, when the communication unit 35a receives the communication data 13, the database module 31a records the data in the time-series database 45 using the equivalent data 13d of the communication data 13, and executes the recording function.

[0039] ≪Processing≫ The operation processing steps (S01 to S07) of the PLC redundancy system 1 will be explained based on Figure 3.

[0040] S01, S02: The CPU 32 and communication unit 33a of the CPU module 30a perform write access to their own data memory 11 during arithmetic processing and communication processing, and rewrite the data in the data memory 11 as shown in rewrites 1 to 5 (S01). At this time, for each rewrite 1 to 5, the address data at the time of the write access and the rewritten data are saved in their own ring buffer 12 (S02). This saving function is implemented by the hardware circuit.

[0041] S03: The CPU 32 of the CPU module 30a transitions to normal operation once the arithmetic and communication processing is complete. In this normal operation, the hardware circuit creates communication data 13 from the address data 1-5 that were rewritten and stored in the ring buffer 12 in S02. The hardware circuit sets the "communication sequence number" 13c at the beginning of the data section 13b of the communication data 13, and the "communication sequence number inversion value" 13e at the end.

[0042] S04: Once the CPU 32 of CPU module 30a has finished creating the communication data 13, the hardware circuit of the communication unit 33a transmits the communication data 13 to the hardware circuit of the communication unit 33b of CPU module 30b using Ethernet communication or similar methods. This communication is called redundant communication.

[0043] S05: Once the CPU 32 of CPU module 30a has finished creating the communication data 13, the hardware circuit of the communication unit 33a transmits the communication data 13 to the hardware circuit of the communication unit 35a of database module 31a using Ethernet communication or similar. This communication is called database communication. Note that the order in which the redundant communication in S04 and the database communication in S05 are performed does not matter.

[0044] S06: The CPU module 30b receives the communication data 13 at the communication unit 33b. Here, after the calculation and communication processing is completed and the system transitions to normal operation, the hardware circuit checks whether the "transmission serial number" 13c and the "transmission serial number inverted value" 13e of the communication data 13 match.

[0045] If the verification confirms a match, the address data for rewriting 1-5 and the rewritten data are obtained from the equivalent data 13d of the communication data 13, and the corresponding data at the corresponding address in the data memory 22 is rewritten (data equivalence processing).

[0046] S07: After receiving the communication data 13 at the communication unit 35a, the database module 31a checks whether the "transmission serial number" 13c and the "transmission serial number inverted value" 13e of the communication data 13 match using the hardware circuit.

[0047] If the verification confirms a match, the address data for rewriting 1 to 5 and the rewritten data are obtained from the equivalent data 13d of the communication data 13, and the date and time are recorded sequentially in the time-series database 45 for each obtained address data and rewritten data (recording function).

[0048] Thus, according to the PLC redundancy system 1, the data for equivalent processing of the CPU module 30b, i.e., the equivalent data 13d of the communication data 13, is used as data for the time-series database. This integrates data equivalent processing and recording functions, enabling efficient use of data and achieving a faster and more efficient recording function. In this respect, it becomes possible to construct a system that streamlines the equivalent processing of the data memory 11 and the recording and management of data changes.

[0049] It should be noted that the present invention is not limited to the embodiments described above, and can be implemented with modifications within the scope of each claim. For example, if equivalent data 13d can be used as data for the time-series database 45, the communication data 13 may have a different data configuration. [Explanation of Symbols]

[0050] 1…PLC Redundancy System 10…Master 11,22…Data memory 12... Ring buffer 13…Communication data 13a...Communication data, header 13b...Communication data, data section 13c...Communication data, data section, communication serial number 13d... Communication data, data section, equivalent data 13e...Communication data, data section, transmission serial number inverted value 20...Slave 30a, 30b…CPU module 31a, 31b… Database Modules 32…CPU 33a, 33b...CPU module, communication unit 34…Storage 35a, 35b... Database module, communications unit 40a…Dual-duplication cable 40b…LAN cable 45…Time-series database

Claims

1. A system of programmable controllers (hereinafter referred to as PLCs) with duplicate master and slave configurations, The aforementioned master is CPU module and Database module, Equipped with, The CPU module and the slave are, It is equipped with a data memory that can be rewritten during arithmetic and communication processing, The CPU module is The system includes a ring buffer that stores the contents of the data memory during normal operation, excluding the aforementioned calculation and communication processing. Communication data is created from the data stored in the ring buffer, and the created communication data is transmitted to the slave and the database module. The aforementioned slave is Based on the received communication data, the data memory is rewritten during normal operation to perform equivalent processing, The aforementioned database module is Based on the received communication data, the changes in the data memory are recorded in a database in chronological order and recorded. A PLC redundancy system characterized by the following features.

2. The CPU module and the database module are connected via a cable to enable communication. The PLC redundancy system according to claim 1, characterized in that it is a dual-use system for a PLC.

3. It is duplicated as a master and a slave. The aforementioned master is CPU module and Database module, Equipped with, The CPU module and the slave are, It is equipped with a data memory that can be rewritten during arithmetic and communication processing, The CPU module is A recording method to be performed by a redundant system of a programmable controller (hereinafter referred to as PLC) equipped with a ring buffer for storing the rewritten contents of the data memory, The CPU module, during normal operation excluding the calculation and communication processing, creates communication data from the data stored in the ring buffer and transmits the created communication data to the slave and the database module. The steps include: the slave rewriting its own data memory based on the received communication data and performing equivalent processing during normal operation; The database module performs a recording process by recording the changes in the CPU module's data memory in a time-series database based on the received communication data. A recording method for a PLC redundancy system, characterized by having the following:

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