Control method for storage device and flash memory

Abstract

This invention provides a storage device and a control method for flash memory that improve data reliability. [Solution] In the storage device, the controller performs an all-scan process on all data stored in the flash memory at startup. The controller also performs a refresh on the blocks containing data that have been detected as degraded by the all-scan process, and then performs a Manual-BKOSP process that sequentially detects degradation in all blocks constituting the flash memory and refreshes the blocks in which degradation has been detected.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for controlling a flash memory.

Background Art

[0002] In recent years, NAND-type flash memories have become widespread.

[0003] The charge amount of the memory cells constituting the above-described NAND-type flash memory is discharged over time, and the reliability of data deteriorates. For this reason, conventionally, a refresh that writes data before the data lifetime and retains the charge amount of the memory cells has been executed (Patent Document 1).

[0004] The above-described refresh is performed by sequentially patrolling all pages constituting the flash memory to detect deterioration, and is performed on a block including a page in which deterioration is detected by the patrol. One patrol is performed on only a part of the flash memory. Since data read and write operations are stopped during patrol and refresh, the patrol and refresh frequencies cannot be increased arbitrarily. For this reason, it takes time to perform refresh on all blocks, and the refresh of deteriorated cells is not executed within the data lifetime, resulting in a problem that the reliability of data deteriorates.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory device and a method for controlling a flash memory that improve the reliability of data. [Means for solving the problem]

[0007] To achieve the aforementioned objectives, the memory device according to the present invention is characterized by the following: A storage device comprising a flash memory consisting of multiple blocks and a controller for controlling the flash memory, The aforementioned controller, A first degradation detection unit performs degradation detection on all data stored in the flash memory at startup, The flash memory includes a refresh unit that, after performing a refresh on the block containing the data for which degradation has been detected by the first degradation detection unit, sequentially detects degradation in all the blocks constituting the flash memory and performs a refresh on the blocks for which degradation has been detected. It is a memory device.

[0008] Furthermore, in order to achieve the aforementioned objectives, the flash memory control method according to the present invention is characterized by the following: In a flash memory control method that controls flash memory consisting of multiple blocks, A first degradation detection step is performed to detect degradation in all data stored in the flash memory at startup, After performing a refresh on the block containing the data in which degradation was detected in the first degradation detection step, a refresh step is performed in which degradation is detected sequentially for all the blocks constituting the flash memory, and the blocks in which degradation was detected are refreshed. It is a method for controlling flash memory. [Effects of the Invention]

[0009] The control method for the storage device and flash memory according to the present invention has the effect of improving data reliability.

[0010] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a block diagram showing the configuration of the eMMC as a storage device according to the present invention. [Figure 2] Figure 2 is a block diagram showing the configuration of the flash memory shown in Figure 1. [Figure 3] Figure 3 is a flowchart illustrating the refresh control processing procedure performed by the controller shown in Figure 1. [Figure 4] Figure 4 is a flowchart illustrating the details of the all-scan process shown in Figure 3. [Figure 5] Figure 5 is an explanatory diagram illustrating the all-scan process shown in Figure 3. [Figure 6] Figure 6 is a flowchart illustrating the details of the Manual-BKOPS process shown in Figure 3. [Figure 7] Figure 7 is an explanatory diagram illustrating the patrol sequence shown in Figure 3. [Modes for carrying out the invention]

[0012] Specific embodiments of the present invention will be described below with reference to the figures.

[0013] The eMMC (embedded Multi Media Card) 1, acting as a storage device, is connected to the host device 10 in a communicative manner, and data is read / written according to instructions from the host device 10.

[0014] As shown in FIG. 1, the eMMC 1 includes a NAND flash memory 2, a controller 3, an external I / F (interface) 4, and a RAM (Random Access Memory) 5.

[0015] The configuration of the flash memory 2 will be described with reference to FIG. 2. FIG. 2 shows a configuration example of the flash memory 2 of, for example, 8 gigabytes. As shown in the figure, the flash memory 2 is composed of pages, blocks, and planes. A page is composed of a plurality of memory cells. A page is the minimum unit of read / write operations and the execution unit of the patrol scan described later.

[0016] A block is composed of a plurality of pages. In the example shown in FIG. 2, one block is composed of 256 pages. A block is the execution unit of the refresh described later. A plane is composed of a plurality of blocks. In the example shown in FIG. 2, two planes are provided, each composed of 934 blocks.

[0017] The controller 3 is composed of a computer that operates according to a program. The controller 3 is connected to the flash memory 2 and controls the flash memory 2. The control of the flash memory 2 includes, in addition to the control of data writing and data reading, the initialization, patrol, and refresh control of the flash memory.

[0018] In addition, the controller 3 performs error correction processing. In the error correction processing, the controller 3 performs error correction coding, for example, by adding redundant bits to the data to be written, and writes this coded data to the flash memory 2. The controller 3 reads the coded data read from the flash memory 2 and performs error correction processing by performing decoding. In this error correction processing, the number of bit errors corrected for each data is calculated.

[0019] External I / F4 is an interface unit connected to the host device 10 that enables communication between the host device 10 and the eMMC1.

[0020] Next, the operation of the eMMC1 with the above configuration will be explained with reference to Figure 3. First, when power is turned on to the eMMC1 and it starts up, the controller 3 starts the refresh control process shown in Figure 3. After startup, in the fresh control process, the controller 3 initializes the flash memory 2 (S1). Next, the controller 3 functions as the first degradation detection unit and performs an all-scan process (S2).

[0021] The details of the all-scan process will be explained with reference to Figure 4. In the all-scan process, the controller 3 scans the flash memory 2 (S21). In S21, the controller 3 reads all the data written to the flash memory 2 and performs error correction processing on all the data read. In the error correction process, the controller 3 calculates the number of bit errors corrected for the data read.

[0022] Controller 3 determines whether or not degraded data has been detected as a result of the scan (S22). In S22, Controller 3 detects data with a bit error count exceeding a threshold as degraded data. If degraded data is detected (Y in S22), Controller 3 writes the block containing the page where the detected degraded data is stored to the refresh management table (S23).

[0023] Furthermore, after setting BKOPS-STATUS to 0x03 (S23), controller 3 terminates the all-scan process. Note that the refresh management table and BKOPS-STATUS are stored in the system area of ​​flash memory 2. The system area is not subject to patrol or refresh processing. Conversely, if no degraded data is detected (N in S22), controller 3 immediately terminates the all-scan process.

[0024] Normally, data is not written to the entire area of ​​flash memory 2. For example, as shown in Figure 5, when data is written to the pages indicated by the diagonal lines, the controller 3 performs error correction processing on the data stored in the diagonal lines.

[0025] Returning to Figure 3, after completing the all-scan process, the controller 3 functions as a read unit and performs data read / write operations according to commands from the host device 10 (S3). In S3, if the controller 3 performs a data read operation, it performs error correction processing on the read data and transmits the error-corrected data to the host device 10. The controller 3 also functions as a second degradation detection unit and detects degradation of the read data if the number of error bits corrected by the error correction process exceeds a threshold. The controller 3 writes the block containing the data in which degradation was detected to the refresh management table and sets BKOPS-STATUS to 0x03.

[0026] When the host device 10 determines that the conditions for executing Manual-BKOSP processing, which does not affect data reading / writing, are met, it issues a CMD6 (refresh command) and sends it to the controller 3. The controller 3 returns to S3 while it has not received a CMD6 (N in S4). When the controller 3 receives a CMD6 (Y in S4), it functions as a refresh unit and executes Manual-BKOSP processing (S5).

[0027] The details of the Manual-BKOSP process will be explained with reference to Figure 6. In the Manual-BKOSP process, controller 3 determines whether BKOPS-STATU is 0x03 or not (S51). If BKOPS-STATU is 0x03 (Y in S51), controller 3 determines whether the refresh of all blocks written to the refresh management table has been completed or not (S52).

[0028] If the refresh of all blocks written to the refresh management table has not been completed (N in S52), controller 3 will refresh the blocks that have not been refreshed (S53) and then terminate the Manual-BKOSP process. In S53, controller 3 will also remove the blocks that have been refreshed from the refresh management table.

[0029] If the refresh of all blocks written to the refresh management table is complete (Y in S52), controller 3 resets the value of BKOPS-STATUS to 0x00 (S54) and then terminates the Manual-BKOSP process.

[0030] If BKOPS-STATU is 0x00 (N in S51), controller 3 performs a patrol to detect memory cell degradation (S55). At this time, controller 3 performs the patrol sequentially, for example, from page 0 of the first block 0 to page 255 of the last block 1987, as shown by the arrows in Figure 7. In one Manual-BKOSP process, controller 3 performs a patrol of a predetermined area (for example, 64 pages). If the patrol is interrupted, it will resume from where it was interrupted in the next Manual-BKOSP process.

[0031] Next, if controller 3 detects a degraded memory cell as a result of its patrol (Y in S56), it writes the block containing the page where the detected degraded memory cell is stored to the refresh management table (S57). Controller 3 also sets BKOPS-STATUS to 0x03 (S57).

[0032] Subsequently, controller 3 refreshes the blocks written to the refresh management table (S58) and then terminates the Manual-BKOSP process. In S58, controller 3 removes the refreshed blocks from the refresh management table. If controller 3 does not detect any degraded memory cells as a result of its patrol (N in S56), it immediately terminates the Manual-BKOSP process.

[0033] Returning to Figure 3, after the Manual-BKOSP process is completed, if the wake-up condition is met (Y in S6), the controller 3 returns to S3. If the wake-up condition is not met (N in S6), the controller 3 determines whether the number of CMD6 issuances has exceeded XX (S7).

[0034] If the number of CMD6 issuances does not exceed XX (N in S7), controller 3 returns to S4. If the number of CMD6 issuances exceeds XX (Y in S7), controller 3 determines that it has performed a patrol using Manual-BKOSP processing on the entire area of ​​flash memory 2 and terminates processing.

[0035] According to the embodiment described above, the controller 3 performs an all-scan process at startup. Furthermore, in the Manual-BKOSP process, after refreshing the blocks containing data that have been detected as degraded by the all-scan process, degradation is detected sequentially for all blocks of the flash memory 2, and the blocks in which degradation is detected are refreshed. This improves data reliability.

[0036] Let's explain in detail why the reliability of the above data is improved. First, let's consider the conventional Manual-BKOSP process, which patrols all blocks and performs a refresh on blocks containing degraded memory cells where degradation is detected during the patrol. Let's assume that 64 pages are checked per patrol in the Manual-BKOSP process. The number of patrols required to check the entire 8GB is 7952 (= 508928 pages ÷ 64).

[0037] In the worst-case scenario, if a degraded memory cell exists on the last page of the memory area (page 255 of block 1987), it will not be detected until 7952 patrols have been performed. If patrols are performed 100 times per day, it would take 79.5 days even if patrols were performed daily. If the frequency of patrols decreases, it will take even longer to detect the degraded memory cell. As a result, the degradation of the degraded memory cell will progress further, worsening the reliability of the data.

[0038] In this embodiment, an all-scan process is performed at startup, and blocks containing data in which degradation is detected during the all-scan process can be refreshed preferentially. Therefore, degraded data containing degraded cells can be detected and refreshed at an earlier stage than before after startup, thereby improving data reliability.

[0039] According to the embodiment described above, the controller 3 performs error correction processing on the data read during the all-scan process, and detects data where the number of bit errors corrected by the error correction process exceeds a threshold as degraded data. This allows the block containing the degraded data to be refreshed before the number of error bits that can be corrected by the error correction process is exceeded, thereby further improving the reliability of the data.

[0040] According to the embodiment described above, the controller 3 uses error correction processing performed during normal read operations in accordance with commands from the host device 10 to detect degradation of read data and prioritize refreshing it. As a result, degradation of read data can be detected even during normal operation, allowing for earlier detection and refreshing of degraded data, thereby further improving data reliability.

[0041] According to the embodiment described above, the controller 3 executes Manual-BKOSP processing in response to the issuance of CMD6 from the host device 10. This allows the refresh to be performed according to the timing from the host device 10, and the refresh can be performed at a timing that does not affect the read / write operations of the host device 10.

[0042] It should be noted that the present invention is not limited to the embodiments described above, and various modifications can be adopted within the scope of the present invention. For example, the present invention is not limited to the embodiments described above, and can be modified, improved, etc. as appropriate. Furthermore, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited as long as they can achieve the present invention.

[0043] According to the embodiment described above, manual-BKOSP processing was performed to refresh in response to the issuance of CMD6 from the host device 10, but this is not the only option. For example, if the controller 3 has not accessed the host device 10 for a predetermined period of time, it may perform auto-BKOSP processing to automatically perform a patrol refresh.

[0044] Herein, the features of the embodiments of the storage device and flash memory control method according to the present invention described above are briefly summarized and listed below in [1] to [5].

[0045] [1] A storage device (1) comprising a flash memory (2) consisting of multiple blocks and a controller (3) that controls the flash memory (2), The aforementioned controller (3) A first degradation detection unit (3) performs degradation detection on all data stored in the flash memory (2) at startup, The flash memory (2) includes a refresh unit (3) that, after performing a refresh on the block containing the data for which degradation has been detected by the first degradation detection unit (3), sequentially detects degradation in all the blocks constituting the flash memory (2) and performs a refresh on the blocks for which degradation has been detected. Storage device (1).

[0046] According to the storage device (1) with the configuration described in [1] above, degraded data including degraded cells can be detected and refreshed at an early stage after startup, thereby improving data reliability.

[0047] [2] In the memory device (1) described in [1], The first degradation detection unit (3) performs error correction processing on the read data and detects the data where the number of bit errors corrected by the error correction processing exceeds a threshold as degraded data. Storage device (1).

[0048] According to the storage device (1) with the configuration described in [2] above, a block containing degraded data can be refreshed before the number of error bits that can be corrected by the error correction process is exceeded, thereby further improving the reliability of the data.

[0049] [3] In the memory device (1) described in [1], The aforementioned controller (3) A reading unit (3) reads the data in the flash memory (2) according to a command from the host device (10), performs error correction processing on the read data, and transmits the error-corrected data to the host device (10), The system includes a second degradation detection unit (3) which detects the data as degraded data if the number of bit errors corrected by the error correction process performed by the reading unit (3) exceeds a threshold, The refresh unit (3) performs a refresh of the block containing the data for which degradation has been detected by the first degradation detection unit (3) and the second degradation detection unit (3), then sequentially detects degradation in all the blocks constituting the flash memory (2), and performs a refresh of the blocks for which degradation has been detected. Storage device (1).

[0050] According to the storage device (1) with the configuration described in [3] above, degradation of read data can be detected even during normal operation, allowing for earlier detection and refresh of degraded data, thereby further improving data reliability.

[0051] [4] In the memory device (1) described in [1], When the refresh unit (3) receives a refresh command from the host device (10), it performs the refresh. Storage device (1).

[0052] According to the storage device (1) in the configuration described in [4] above, a refresh can be performed at a timing determined by the host device (10), and the refresh can be performed at a timing that does not affect the read / write operations of the host device (10).

[0053] [5] In a flash memory control method for controlling a flash memory (2) consisting of multiple blocks, A first degradation detection step is performed to detect degradation of all data stored in the flash memory (2) at startup, After performing a refresh on the block containing the data in which degradation was detected in the first degradation detection step, a refresh step is performed in which degradation is detected sequentially for all the blocks constituting the flash memory (2), and the blocks in which degradation was detected are refreshed. A method for controlling flash memory.

[0054] According to the flash memory control method of the configuration described in [5] above, degraded data, including degraded cells, can be detected and refreshed at an early stage after startup, thereby improving data reliability. [Explanation of Symbols]

[0055] 1 eMMC (storage device) 2 Flash memory 3. Controller (First degradation detection unit, refresh unit) 10 Host device

Claims

1. A storage device comprising a flash memory consisting of multiple blocks and a controller for controlling the flash memory, The aforementioned controller, A first degradation detection unit performs degradation detection on all data stored in the flash memory at startup, The flash memory includes a refresh unit that, after performing a refresh on the block containing the data for which degradation has been detected by the first degradation detection unit, sequentially detects degradation in all the blocks constituting the flash memory and performs a refresh on the blocks for which degradation has been detected. storage device.

2. In the storage device described in claim 1, The first degradation detection unit performs error correction processing on the read data and detects the data where the number of bit errors corrected by the error correction processing exceeds a threshold as degraded data. storage device.

3. In the storage device described in claim 1, The aforementioned controller, A reading unit that reads the data in the flash memory according to a command from the host device, performs error correction processing on the read data, and transmits the error-corrected data to the host device, The system includes a second degradation detection unit that detects the data as degraded data if the number of bit errors corrected by the error correction process performed by the reading unit exceeds a threshold, The refresh unit, after performing a refresh on the block containing the data for which degradation has been detected by the first degradation detection unit and the second degradation detection unit, sequentially detects degradation in all the blocks constituting the flash memory and performs a refresh on the blocks for which degradation has been detected. storage device.

4. In the storage device described in claim 1, The refresh unit, upon receiving a refresh command from the host device, executes the refresh. storage device.

5. In a flash memory control method that controls flash memory consisting of multiple blocks, A first degradation detection step is performed to detect degradation in all data stored in the flash memory at startup, After performing a refresh on the block containing the data in which degradation was detected in the first degradation detection step, a refresh step is performed in which degradation is detected sequentially for all the blocks constituting the flash memory, and the blocks in which degradation was detected are refreshed. A method for controlling flash memory.

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