Method for recommending optimal applied voltage for data extraction of NAND flash memory

Abstract

The present invention relates to a method for recommending an optimal applied voltage for data extraction of a NAND flash memory. The method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one aspect of the present invention comprises: an initial data extraction step of applying a preset initial applied voltage to an input pin of a NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; a per-voltage data extraction step of applying a plurality of voltages, obtained by repeatedly increasing or decreasing the initial applied voltage by a predetermined voltage, to the input pin of the NAND flash memory, each at different time points, and extracting, for each voltage, data having the same logical address as the logical address of the data extracted in the initial data extraction step; and a step of recommending an optimal applied voltage on the basis of binary data generated by performing an XOR operation between data having the same logical address extracted according to different applied voltages.

Description

Recommendation Method for Optimal Applied Voltage for Data Extraction from NAND Flash Memory

[0001] The present invention relates to a technology that recommends an optimal applied voltage to extract data from a NAND flash memory.

[0002] Flash memory is a semiconductor memory that can read and write data using electrical signals and retains stored data even after the power is cut off. It has the characteristic that while reading and writing are possible in specific units within the memory, erasing must be done in block units, so an area that has been written once must be erased before it can be written again.

[0003] These flash memories can be broadly classified into the parallel NOR method and the serial NAND method. Among these, while the NAND method has slower data read speeds compared to the NOR method, it offers faster write and erase speeds because the memory blocks are divided into multiple pages, and it also boasts superior integration density per unit compared to NOR; for these reasons, it is primarily used in SSDs (Solid State Drives) and USB memory devices.

[0004] Storage devices equipped with NAND flash memory are configured such that the NAND flash memory and controller are separated into individual chips and integrated onto a single board. In the event of physical damage or failure to the device, the memory chip corresponding to the NAND flash memory is detached from the device board and installed in a recovery device equipped with a data recovery program. Data recovery is then performed by reconstructing the dumped data using the memory chip's parameter data through the recovery program.

[0005] However, even if a data recovery program is used, accessing the data area of ​​the memory chip requires that the controller controlling the memory operation of the memory chip be functioning normally.

[0006] Therefore, if a problem occurs with the controller itself and it does not operate normally, there is a problem in that it is difficult to recover data from the memory chip, and there is also a problem in that it is difficult to determine the appropriate power voltage value to extract data from the NAND flash memory.

[0007] The objective of the present invention is to solve the above problem by providing a method for recommending an optimal applied voltage for data extraction of a NAND flash memory, which can recommend an optimal applied voltage suitable for applying a power supply voltage to the NAND flash memory when attempting recovery through a data recovery program due to physical damage or failure of the controller of the NAND flash memory.

[0008] Another objective of the present invention is to provide a method for recommending an optimal applied voltage for data extraction of a NAND flash memory, which can recommend an optimal applied voltage through a comparison between data extracted for each different applied voltage and a match rate with an error correction code.

[0009] The objectives of the present invention are not limited to those mentioned above, and other unmentioned objectives will be clearly understood from the description below.

[0010] A method for recommending an optimal applied voltage for data extraction in a NAND flash memory according to one aspect of the present invention relates to a method performed by a computing device, wherein the NAND flash memory has a data area (DA) and a spare area (SA) containing an error correction code (ECC) for each page, and comprises: an initial data extraction step of applying an initial applied voltage having a preset voltage level to an input pin of the NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; a voltage-specific data extraction step of applying a plurality of voltages according to a plurality of voltage levels by repeatedly adding or subtracting a predetermined voltage from the initial applied voltage at different times to the input pin of the NAND flash memory, and extracting data having the same logical address as the data extracted in the initial data extraction step for each voltage; and a step of recommending an optimal applied voltage by selecting one of the initial applied voltage and the plurality of voltages based on binary data generated by performing an XOR operation between data having the same logical address extracted according to different applied voltages.

[0011] According to the present invention, when physical damage or failure occurs to the controller of a NAND flash memory and recovery is attempted through a data recovery program, it is possible to recommend an optimal applied voltage for applying a power supply voltage suitable for the NAND flash memory.

[0012] FIG. 1 is a flowchart illustrating a method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to an embodiment of the present invention.

[0013] FIG. 2 is a block diagram of a computing device in which the optimal applied voltage recommendation method for data extraction of a NAND flash memory of the present invention is performed.

[0014] A method for recommending an optimal applied voltage for data extraction in a NAND flash memory according to one aspect of the present invention relates to a method performed by a computing device, wherein the NAND flash memory has a data area (DA) and a spare area (SA) containing an error correction code (ECC) for each page, and comprises: an initial data extraction step of applying an initial applied voltage having a preset voltage level to an input pin of the NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; a voltage-specific data extraction step of applying a plurality of voltages according to a plurality of voltage levels by repeatedly adding or subtracting a predetermined voltage from the initial applied voltage at different times to the input pin of the NAND flash memory, and extracting data having the same logical address as the data extracted in the initial data extraction step for each voltage; and a step of recommending an optimal applied voltage by selecting one of the initial applied voltage and the plurality of voltages based on binary data generated by performing an XOR operation between data having the same logical address extracted according to different applied voltages.

[0015] The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the claims. Meanwhile, the terms used in this specification are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text.

[0016]

[0017] Referring to FIG. 2, a computing device (10) for performing an optimal applied voltage recommendation method for data extraction of a NAND flash memory may include an input / output interface (11), a communication interface (12), a memory (13), and a processor (14) connected to each other via a bus (BUS).

[0018] The input / output interface (11) is connected to an input / output device for receiving user input or outputting data processing results, and can receive user input or output data processing results through the input / output device.

[0019] The input / output interface (11) may be connected to the NAND flash memory (93) to read or write data to the NAND flash memory, and may be configured to apply a voltage set by the processor (14) to the NAND flash memory. Additionally, the input / output interface (11) may be connected to a power supply unit (80) required for voltage application to provide power to the NAND flash memory.

[0020] Input / output devices may include a mouse, keyboard, display, touch display, etc., but are not limited to these.

[0021] The communication interface (12) communicates with an external computing device through a network and can receive input from a user or output data processing results to the user through the external computing device.

[0022] The memory (13) includes a computer-readable recording medium and may store an operating system and pre-configured instructions.

[0023] The processor (14) can execute instructions stored in memory (13) as it performs basic arithmetic, logic, and input / output operations. The processor (14) may control the input / output interface (11) to apply voltage for driving the NAND flash memory.

[0024] Additionally, the processor (14) may output a control command to control the voltage of the power output from an external power supply (80).

[0025] Each step of the method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one embodiment of the present invention may be implemented as computer instructions that perform specified functions by being loaded into a processor or memory of a computing device capable of data processing (e.g., a general-purpose computer, a special-purpose computer, a portable notebook computer, a tablet computer, or other computing device).

[0026]

[0027] Standards related to NAND flash memory include JEDEC and ONFI. Here, JEDEC, specifically JESD230, is a standard that defines the basic specifications, instructions, and operating methods of NAND flash memory. ONFI (Open NAND Flash Interface) is an interface standard that ensures compatibility between NAND flash memory devices.

[0028] Since the standards and manufacturers related to NAND flash memory applied to each NAND flash memory differ, when attempting to recover data using a data recovery program due to physical damage or failure of the NAND flash memory controller, it is necessary to apply a power voltage suitable for the NAND flash memory.

[0029] However, since it is not easy to identify the standard and manufacturer applied to the NAND flash memory based solely on the appearance or shape of the NAND flash memory, the optimal application voltage recommendation method for data extraction of a NAND flash memory according to one embodiment of the present invention provides a method for recommending an optimal application voltage based on the data status and the match rate with the error correction code for each application voltage of the NAND flash memory.

[0030] A method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one embodiment of the present invention may be applicable to a NAND flash memory having a data area (DA) and a spare area (SA) containing an error correction code (ECC) for each page.

[0031]

[0032] In a NAND flash memory having a data area (DA) and a spare area (SA) containing an error correction code (ECC) for each page, the processor (14) applies an initial applied voltage having a preset voltage level to the input pin of the NAND flash memory (S101).

[0033] The ONFI standard and the JEDEC standard specify 1.2V, 1.8V, and 3.3V, respectively, as voltages for driving NAND flash memory. Considering the ONFI standard and the JEDEC standard, it is desirable to select an initial applied voltage within the voltage range of 1.2V to 3.3V.

[0034] After the initial applied voltage is applied, the processor (14) extracts data contained in the NAND flash memory and stores the logical address of the extracted data (S103).

[0035] The processor (14) applies multiple voltages corresponding to multiple voltage levels, which are repeatedly increased or decreased by a predetermined voltage (e.g., 0.05V) from the initial applied voltage, to the input pins of the NAND flash memory at different times, and extracts data having the same logical address as the data extracted in the initial data extraction step for each voltage (S105).

[0036] In the case of NAND flash memory, it may include an Error Correction Code (ECC) to correct errors, and it is possible to correct the binary data values ​​of erroneous bits into correct binary data values ​​based on a predetermined error correction algorithm and the error correction code.

[0037] The processor (14) calculates the error correction code matching ratios for each voltage by calculating the ratio of the number of bits that match the error correction code to the total number of bits for each of the data extracted in the initial data extraction step and the data extracted in the voltage-specific data extraction step (S107).

[0038] The processor (14) may input data from the data area and an error correction code into a predetermined error correction algorithm according to the type of NAND flash memory, obtain a binary code corresponding to a bit in which an error is detected or not detected through the error correction algorithm, and calculate the ratio of the number of bits in which the error correction code is correct to the total number of bits.

[0039] The processor (14) recommends an optimal application voltage by selecting one of the initial application voltage and a plurality of voltages based on the ratio of the number of bits whose bit value is 1 to the total number of bits of binary data generated by performing an XOR operation between data having the same logical address extracted according to different application voltages (S109).

[0040] Ideally, data with the same logical address extracted from a single NAND flash memory will yield identical binary data bit by bit.

[0041] However, if a voltage unsuitable for NAND flash memory is applied as a power source, the extracted data may have the same logical address but with a different voltage of the applied power source, resulting in bit-by-bit binary data output.

[0042] In a method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one embodiment of the present invention, different voltages are applied to the NAND flash memory, and the data extracted from the NAND flash memory for each different voltage is compared or the degree of error is determined to recommend an optimal applied voltage.

[0043] The processor (14) may recommend an optimal applied voltage based on the bitwise value or the match ratio of the error correction code resulting from performing an XOR operation between data having the same logical address extracted according to different applied voltages.

[0044] When an XOR operation is performed, the difference between data with the same logical address extracted for each different voltage can be identified.

[0045] When there is no difference between the data, it can be assumed that the data being compared match each other and that there are likely no errors between them, so it may be reasonable to recommend the voltage level used to extract these data as the optimal applied voltage.

[0046] In addition, in the case of data where there are differences between the data but the match rate of the error correction code is the highest, it can be considered that a voltage level of critical significance has been applied, and thus it may be considered to recommend it as the optimal applied voltage.

[0047] Accordingly, the processor (14) may recommend an optimal application voltage by selecting one of a plurality of voltages and an initial application voltage corresponding to the case where the ratio of the number of bits corresponding to a bit value of 1 to the total number of bits of binary data generated by performing an XOR operation between data having the same logical address extracted according to different application voltages is 0.

[0048] Additionally, the processor (14) may recommend the voltage applied when extracting data with the highest matching ratio of the single error correction code as the optimal applied voltage, such that the ratio of the number of bits corresponding to a bit value of 1 to the total number of bits of binary data generated by performing an XOR operation is not 0.

[0049]

[0050] According to the present invention, there is an advantage in that when attempting to recover data through a data recovery program due to physical damage or failure occurring in the controller of the NAND flash memory according to the aforementioned steps, an optimal applied voltage suitable for applying a power supply voltage to the NAND flash memory can be recommended.

[0051]

[0052] A person skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the claims and their equivalents should be interpreted as being included within the scope of the present invention.

[0053] The present invention relates to a technology that recommends an optimal applied voltage to extract data from a NAND flash memory.

Claims

1. A method performed by a computing device, wherein in a NAND flash memory having a data area (DA) and a spare area (SA) containing an error correction code (ECC) for each page, an initial data extraction step of applying an initial applied voltage having a preset voltage level to an input pin of the NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; A voltage-specific data extraction step for applying multiple voltages corresponding to multiple voltage levels, which are repeatedly increased or decreased by a predetermined amount from the initial applied voltage, to the input pins of the NAND flash memory at different times, and extracting data having the same logical address as the data extracted in the initial data extraction step for each voltage; and A step of recommending an optimal application voltage by selecting one of the initial application voltage and the plurality of voltages based on binary data generated by performing an XOR operation between data having the same logical address extracted according to different application voltages; A method for recommending an optimal applied voltage for data extraction of a NAND flash memory including 2. In paragraph 1, after the voltage-specific data extraction step and before the recommended step, A method for recommending an optimal applied voltage for data extraction of a NAND flash memory, further comprising the step of calculating, for each of the data extracted in the initial data extraction step and the data extracted in the voltage-specific data extraction step, the ratio of the number of bits where the error correction code matches the total number of bits, and calculating the matching ratios of the error correction codes for each voltage.

3. In paragraph 2, the recommended step above is, A step of recommending an optimal application voltage by selecting one of the initial application voltage and the plurality of voltages based on the ratio of the number of bits with a bit-by-bit value of 1 to the total number of bits of binary data generated by performing an XOR operation between data having the same logical address extracted according to different application voltages. Method for recommending optimal applied voltage for data extraction of NAND flash memory.

4. In paragraph 2, the recommended step above is, A step that recommends the applied voltage as the optimal applied voltage when extracting data in which the ratio of the number of bits with a bit value of 1 to the total number of bits of binary data generated by the XOR operation is non-zero and the matching rate of the binary error correction code is the highest. Method for recommending optimal applied voltage for data extraction of NAND flash memory.

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