Switching circuits, power converters, and inverters

Abstract

Provided are a switching circuit, a power conversion device, and an inverter that can balance voltages in each device while preventing complication due to an increase in components of a circuit. 【Solution means】According to one embodiment, the switching circuit includes n (n is an integer of 2 or more) switching elements connected in series. Further, the switching circuit includes n - 1 capacitors Ca k (k is an integer satisfying 2 ≤ k ≤ n) connected between the gates and drains of the switching elements. Further, the n - 1 capacitors Ca k each have different capacitance values. Further, the n - 1 capacitors Ca k are respectively provided in the 2nd to nth switching elements among the 1st to nth switching elements counted from the low potential side.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a switching circuit, a power converter, and an inverter. [Background technology]

[0002] In recent years, power MOSFETs used in power conversion devices and inverters for electric vehicles, power equipment, elevators, and railways, etc., have been required to achieve both voltage withstand capability of several hundred volts or more and high-frequency switching.

[0003] Generally, devices with a voltage rating approximately twice the power supply voltage are selected. However, increasing the voltage rating leads to problems such as increased cost, increased resistance loss, or decreased availability. Furthermore, power MOSFETs with kV-class voltage ratings primarily use SiC as the material, which is expected to further increase costs.

[0004] On the other hand, when multiple devices are connected in series and the voltage is shared among them, the voltage applied to each individual device decreases. Therefore, connecting low-voltage devices in series can be more cost-effective than using a single high-voltage device.

[0005] When using multiple devices connected in series, it is desirable to equalize the voltage distributed among each device during turn-off. This helps to avoid damage to specific devices caused by excessive voltage being applied to them. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Patent No. 3772534 specification [Non-patent literature]

[0007] [Non-Patent Document 1] A. Marzoughi et al, “Dynamic Voltage Balancing Method for Fast Switching SiC MOSFETs with High dv / dt Rates”, 2017 IEEE Southern Power Electronics Conference (SPEC).

Summary of the Invention

Problems to be Solved by the Invention

[0008] In the above-described circuit, at the turn-off of each device, the drain voltage of each device is detected, and a delay circuit that adjusts the delay time of the gate signal is provided to control the gate signal of each element to equalize the shared voltage. The time that needs to be corrected varies for each device, and a voltage detection circuit and a correction circuit are required independently for each device. Also, as the number of devices connected in series increases, not only do the components increase, but a control circuit for adjusting the gate signal and determining the value of the current injected into the gate is also required, leading to circuit complexity and cost increase.

[0009] Also, in the technology using feedback control, when a sudden deviation occurs in the shared voltage due to fluctuations in the load current or the like during the driving of the device, it is difficult to immediately return the voltage to equilibrium. For example, the imbalance in the shared voltage continues for several cycles to several tens of cycles.

[0010] Therefore, embodiments of the present invention provide a switching circuit, a power conversion device, and an inverter that can balance the voltage in each device while preventing complexity due to an increase in circuit components.

Means for Solving the Problems

[0011] According to one embodiment, the switching circuit includes n (n is an integer greater than or equal to 2) switching elements connected in series. Further, the switching circuit includes n - 1 capacitors Ca connected between the gates and drains of the switching elements k(where k is an integer satisfying 2 ≤ k ≤ n). Also, the n - 1 capacitances Ca k have different capacitance values. Also, the n - 1 capacitances Ca k are respectively provided in the 2nd to nth switching elements among the 1st to nth switching elements counted from the low - potential side.

Brief Description of the Drawings

[0012] [Figure 1] It is a schematic configuration diagram of an inverter in the first embodiment. [Figure 2] It is a schematic configuration diagram of a switching control circuit in the first embodiment. [Figure 3] It is a diagram for explaining an example of deriving capacitance Ca in the first embodiment. [Figure 4] It is another schematic configuration diagram of a switching control circuit in the first embodiment. [Figure 5] It is an example of setting capacitance Ca in the first embodiment. [Figure 6] It is a comparison diagram of the sharing voltage during turn - off in a switching control circuit in the first embodiment. [Figure 7] It shows the analysis result of the relationship between the value of capacitance Ca and the magnitude of voltage variation of the switching element in the first embodiment, with the result normalized. [Figure 8] It shows the analysis result of the relationship between the power - supply voltage Vdc and the magnitude of voltage variation of the switching element in the first embodiment. [Figure 9] It is a schematic configuration diagram of a switching control circuit in the second embodiment. [Figure 10] It is an example of a surge - suppression circuit in this embodiment. [Figure 11] It is a schematic configuration diagram of a switching control circuit in the third embodiment. [Figure 12] It is a schematic configuration diagram of a switching control circuit in the fourth embodiment.

Modes for Carrying Out the Invention

[0013] (First Embodiment) Embodiments of this disclosure will be described below with reference to the drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed descriptions are omitted as appropriate.

[0014] Furthermore, in this disclosure, the terms "greater than or equal to" and "less than or equal to" may be interpreted as "greater than" and "less than" as appropriate.

[0015] Furthermore, in the following embodiments, the high-voltage side of the circuit will be referred to as the upper stage, and the low-potential side will be referred to as the lower stage.

[0016] Figure 1 is a schematic diagram of the inverter 100 in the first embodiment.

[0017] The inverter 100 comprises multiple switching control circuits 1, a controller 30, and multiple loads 50. Figure 1 shows an example of a three-phase AC inverter 100. The inverter 100 uses two switching control circuits 1 to form one phase arm pair, and further uses three sets of these to operate a three-phase load. Each switching control circuit 1 operates in response to a control signal such as a PWM (Pulse Width Modulation) signal output from the controller 30 to perform power conversion and supply power to the load 50.

[0018] Furthermore, the circuit, which includes two switching control circuits 1 that are controlled by the controller 30 and constitute an arm pair, is also called a power converter. The following will mainly describe the configuration of the switching control circuits 1.

[0019] Figure 2 is a schematic diagram of the switching control circuit 1 in the first embodiment.

[0020] The switching control circuit 1 includes multiple switching elements 10, multiple gate control circuits 12, a load 50, and an additional capacitance Ca. Furthermore, parasitic capacitances of the substrate and the gate control circuit 12 exist between the gate and ground of each switching element 10; these parasitic capacitances are collectively referred to as the parasitic capacitance Cp. In this diagram, the parasitic capacitance of the lower switching element 10 is denoted as Cp1, and the parasitic capacitance of the upper switching element 10 is denoted as Cp2. In the following, the switching elements 10, capacitance Ca, and parasitic capacitance Cp will also be referred to as the switching circuit. The switching element 10 is an example of a device. As will be explained in detail later, the effect of parasitic capacitance Cp1 is minimal compared to parasitic capacitance Cp2; therefore, capacitance Ca is not present in the lower switching element 10.

[0021] The switching control circuit 1 is controlled by a control signal such as a PWN signal output from the controller 30, which controls the gate control circuit 12. The switching element 10 operates with its gate controlled by a gate control signal output from the gate control circuit 12. In this embodiment, in order to reduce losses by reducing the total on-resistance, the switching control circuit 1 has multiple low-voltage switching elements 10 connected in series instead of having one high-voltage switching element 10 in the circuit. This figure shows an example of a switching control circuit 1 with two switching elements 10 connected in series, but the number of elements in series is not limited to this and can be any number depending on the voltage rating required for the circuit design and the cost of implementation. The voltage rating of each switching element 10 can also be any value.

[0022] When using low-voltage switching elements 10 in a high-voltage system, it is desirable for each switching element 10 to share the drain-source voltage equally during turn-off. That is, if the drain-source voltage of the lower switching element 10 is Vds1, the drain-source voltage of the upper switching element 10 is Vds2, and the power supply voltage is Vdc, it is desirable that Vds1 = Vds2 = Vdc / 2. However, due to variations in parameters (such as the capacitance between terminals Cgd, Cgs, or Cds, which will be described later) and the influence of parasitic capacitance Cp, the voltage is distributed unevenly to each switching element 10.

[0023] When the switching element 10 is ON, the voltage value is small, so the voltage balance between elements does not pose a major problem. However, when two switching elements 10 are driven simultaneously, a mismatch in gate current occurs due to the charging and discharging of their parasitic capacitances Cp. This causes variations in turn-off times, resulting in uneven voltages Vds1 and Vds2 applied when each switching element 10 has completed its turn-off.

[0024] Due to the difference between voltages Vds1 and Vds2, a large voltage may be applied to one switching element 10, especially the switching element 10 closer to the power supply voltage. If the voltage rating of the switching element 10 is lower than the power supply voltage, the element will be destroyed if the entire voltage is applied to one switching element 10.

[0025] In this embodiment, the switching control circuit 1 is equipped with an additional capacitance Ca between the gate and drain of all switching elements 10 except for the lowest-most switching element 10 among the switching elements 10 connected in series, in order to maintain the voltage balance of each switching element 10. The capacitance Ca is, for example, a capacitor.

[0026] This eliminates the uneven distribution of voltage caused by differences in charging and discharging currents to parasitic capacitances, etc., and equalizes the drain-source voltage of each switching element 10.

[0027] In this embodiment, the switching control circuit 1 is provided with an additional capacitance Ca between the gate and drain of all switching elements 10 except for the lowest-most switching element 10 among the multiple switching elements 10 connected in series. This is intended for cases where Cp is sufficiently small and negligible compared to the capacitance value originally present between the gate and source inside the switching element 10. If Cp cannot be considered sufficiently small compared to the capacitance inside the element, or if there is a large variation in the capacitance inside the device among the multiple switching elements 10 and this needs to be corrected, a capacitance Ca1 may be added to the switching element 10 on the lowest potential side.

[0028] Figure 3 illustrates an example of deriving the capacity Ca in the first embodiment.

[0029] Figure 3(A) shows the equivalent circuit of two MOSFETs, Figure 3(B) shows a circuit approximating Figure 3(A), and Figure 3(C) shows a simplified circuit of Figure 3(B).

[0030] Figure 3 shows an example of two MOSFETs (shown as MOS1 on the lower side and MOS2 on the upper side) connected in series, including a switching element 10. This will be used to explain how to calculate the capacitance Ca. The MOSFET has parameter capacitances Cds, Cgd, and Cgs between its terminals, and these components along with the parasitic capacitance Cp are extracted and shown as an equivalent circuit.

[0031] In Figure 3(A), capacitance Cgs is in the nF class, and capacitance Cgd is approximately 10pF, so the effect of Cgs, which is sufficiently large, can be ignored. Furthermore, the parasitic capacitance Cp of the bottommost MOS1 is located in parallel with capacitance Cgs and can therefore be ignored. Also, the parasitic capacitance Cp of the upper stage can be considered to be in parallel with the capacitance component Cgd of the lower stage.

[0032] Figure 3(B) shows a circuit approximating Figure 3(A). In MOS1, the capacitance Cgd approximated by the above description is shown as capacitance Cgd1, and the capacitance Cds is shown as capacitance Cds1. Similarly, in MOS2, the capacitance Cgd approximated by the above description is shown as capacitance Cgd2, the capacitance Cds is shown as capacitance Cds2, and the parasitic capacitance Cp is shown as parasitic capacitance Cp2. Parasitic capacitance Cp2 can be considered to be in parallel with capacitance Cgd1 in the lower stage. Also, in Figure 3(B), the drain-source voltage of MOS1 is shown as Vds1, and the drain-source voltage of MOS2 is shown as Vds2.

[0033] Figure 3(C) shows a circuit that is a simplified version of Figure 3(B). In this figure, as described above, the parasitic capacitance Cp2 on the upper side is shown in parallel with the capacitance component Cgd on the lower side. In the lower MOS1 and MOS2, for example, if the value of capacitance Cds1 is 100pF, the value of capacitance Cgd1 is 8pF, the value of capacitance Cds2 is 100pF, the value of capacitance Cgd2 is 8pF, and the value of capacitance Cp1 is 25pF, then by adding capacitance Ca of 25pF in parallel with capacitance Cgd1, the combined capacitances of MOS1 and MOS2 become equal.

[0034] As shown in this diagram, by adding the necessary capacitance Ca to the upper MOSFET, the circuit configuration does not become complex, and it is also less susceptible to the influence of other parasitic capacitances.

[0035] Figure 4 is another schematic diagram of the switching control circuit 1 in the first embodiment.

[0036] Unlike Figure 1, this figure shows an example in which n switching elements 10 (where n is an integer greater than or equal to 2) are connected in series in the switching control circuit 1. Furthermore, the switching circuit 11 has n-1 capacitors Ca, each connected to the 2nd to nth switching elements 10, counting from the lowest potential side. The capacitance values ​​of each capacitor Ca are also different.

[0037] Ideally, when n switching elements 10 are connected in series, for the m-th (m is an integer satisfying 1 <= m <= n) switching element 10 counted from the lower side, the Ca to be set m The value of is determined in order from the low potential side according to the parasitic capacitance Cp generated between the gate and the ground of each switching element 10 m The voltage between the parasitic capacitance Cp and the ground increases towards the upper side. Therefore, the capacitance Ca set for the upper switching element 10 m The larger the value. In this embodiment, it will be described that the addition of the capacitance Ca1 to the switching element 10 on the lowest potential side is unnecessary.

[0038] In this figure, the ideal capacitance value to be added to the second switching element 10 counted from the low potential side, corresponding to the capacitance Ca2, is the same as the parasitic capacitance Cp2 generated between the gate and the ground of this switching element 10.

[0039] Next, the value of the capacitance Ca3 to be added to the third switching element 10 counted from the low potential side is the value of Cp2, which is the capacitance value added to the second switching element 10, plus twice the value of the parasitic capacitance Cp3 generated between the gate and the ground of the third switching element 10.

[0040] Subsequently, the value of the capacitance Ca4 to be added to the fourth switching element 10 counted from the low potential side is the value of Cp2 + 2Cp3, which is the capacitance value added to the third switching element 10, plus three times the value of the parasitic capacitance Cp4 generated between the gate and the ground of the fourth switching element 10. Thus, the value of the capacitance Ca added to the switching element 10 is set according to the parasitic capacitance Cp existing in this switching element 10.

[0041] This operation is repeatedly performed up to the switching element 10 connected to the highest potential side. Generally speaking, for an integer k (2 <= k <= n), among the first to n-th switching elements 10, the capacitance Ca added between the gate and the drain of the k-th switching element 10 counted from the low potential side kThe value of k is the sum of the capacitance values of the capacitors Ca added to the switching elements 10 from the second to the (k - 1)-th counting from the low potential side, and the parasitic capacitance Cp between the gate and the low potential wiring in the k-th switching element 10 k added by multiplying it by (k - 1). Therefore, the value of Ca k increases as the value of k increases from the low potential side to the high potential side. The value of Ca added at the k-th position is expressed by the formula (1). The addition of Ca1 is optional. When Ca1 is not added, set Ca1 = 0. Ca k = Ca (k-1) +(k - 1)Cp k (1)

[0042] Figure 5 shows an example of setting the capacitance Ca in the first embodiment.

[0043] Figure 5(A) shows an example where the parasitic capacitance Cp in each switching element 10 has the same value, and Figure 5(B) shows an example where the parasitic capacitance Cp in each switching element 10 has different values. Also, Figure 5(C) is a diagram showing the calculation method of the capacitance value of the capacitance Ca in each switching element 10.

[0044] Figure 5(A) shows the values of the capacitance Ca in each switching element 10 when n = 4. In this example, it is assumed that the values of the parasitic capacitance Cp of each switching element 10 are all the same. Also, it is assumed that the capacitance Cp1 is not added.

[0045] Referring to Figures 5(A) and 5(C) to derive the capacitance Ca, the capacitance Ca2 is Ca2 = Cp2. Here, since Cp2 = 10, the capacitance Ca2 is 10 pF. Also, the capacitance Ca3 is Ca3 = 2Cp3 + Cp2. Here, since Cp2 = Cp3 = 10, the capacitance Ca3 is 30 pF. Also, the capacitance Ca4 is Ca4 = 3Cp4 + 2Cp3 + Cp2. Here, since Cp2 = Cp3 = Cp4 = 10, the capacitance Ca4 is 60 pF.

[0046] Figure 5(B) shows the capacitance Ca values ​​for each switching element 10 when n=4. In this example, it is assumed that the parasitic capacitance Cp of each switching element 10 is all different. Also, capacitance Cp1 is not added.

[0047] Referring to Figures 5(B) and 5(C) together, the capacitance Ca is derived as follows: Since Cp2 = 10, the capacitance Ca2 is 10 pF. Also, since Cp2 = 10 and Cp3 = 15, the capacitance Ca3 is 40 pF. Furthermore, since Cp2 = 10, Cp3 = 15 and Cp4 = 20, the capacitance Ca4 is 100 pF.

[0048] Figure 6 is a comparison diagram of the voltage distribution during turn-off in the switching control circuit 1 in the first embodiment.

[0049] Figure 6(A) shows an example of the voltage distribution when capacitance Ca is not added to the switching control circuit 1, and Figure 6(B) shows an example of the voltage distribution when capacitance Ca is added to the switching control circuit 1.

[0050] Furthermore, in Figure 6, for the sake of simplicity, an example is shown in which two switching elements 10 are connected in series in the switching control circuit 1, similar to Figure 1. In the figure, the horizontal axis represents time, and the vertical axis represents the drain-source voltage of each switching element 10.

[0051] As shown in Figure 6(A), when capacitance Ca is not added to the switching control circuit 1, a variation occurs between the voltage Vds1 of the lower switching element 10 and the voltage Vds2 of the upper switching element 10. On the other hand, as shown in Figure 6(B), when capacitance Ca is added to the switching control circuit 1, the variation between the voltage Vds1 of the lower switching element 10 and the voltage Vds2 of the upper switching element 10 is eliminated, and the voltage is distributed evenly.

[0052] Figure 7 shows the normalized analysis results regarding the relationship between the capacitance value Ca and the magnitude of voltage variation of the switching element in the first embodiment.

[0053] The capacitance value derived in equation (1) assumes that the switching element 10 operates as an ideal element. In reality, due to the non-ideal nature of the switching element 10 and the influence of parasitic capacitance (not shown), the distribution voltage may not perfectly match between each switching element 10. Therefore, the value of capacitance Ca may be set within a certain range according to the value derived in equation (1) above. Compared to not adding capacitance Ca, the voltage balance can be improved by setting the value of capacitance Ca within a certain range.

[0054] In Figure 7, the horizontal axis shows the set capacitance Ca value as a ratio, with the capacitance Ca value derived from equation (1) set to 1. The vertical axis shows the difference between the drain-source voltage Vds of the switching element 10 with the maximum voltage share among the series-connected switching elements 10 and the reference value of the voltage share, with the drain-source voltage Vds value when capacitance Ca is not added set to 1.

[0055] In the analysis, the reference value for the voltage distribution is the value of Vds when the voltage distribution of all switching elements 10 is the same, that is, when the number of elements in series is n, the value obtained by dividing the power supply voltage into n equal parts. Also, when n is 3 or more, the capacitance Ca of each of the n-1 elements is considered. k The values ​​are set so that they are in the same proportion to the values ​​derived from equation (1).

[0056] Figure 7 shows that when the value of capacitance Ca matches the value derived from equation (1), there is no variation in the drain-source voltage Vds of each switching element 10, and they are all uniform. Although the value of capacitance Ca to be added will differ depending on the parasitic capacitance Cp of the element, twice the value obtained from equation (1) is used for capacitance Ca. k When set to this value, it can be seen that it is equivalent to the variation in the drain-source voltage Vds of each switching element 10 when no capacitance Ca is added.

[0057] Therefore, assuming a typical device, setting the value of the additional capacitance Ca within ±80% (0.2 to 1.8 times) of the value derived by equation (1) can be said to reduce the variation in the drain-source voltage Vds of each element by more than 20% compared to when no capacitance Ca is added, regardless of the parasitic capacitance Cp that occurs between the gate and ground.

[0058] Figure 8 shows the results of an analysis of the relationship between the power supply voltage Vdc and the magnitude of voltage variation of the switching element 10 in the first embodiment.

[0059] This figure shows the results of an analysis of the ratio between the power supply voltage Vdc and the magnitude of variation in the drain-source voltage Vds of each switching element 10, when the capacitance Ca added to each switching element 10 is set to the value derived from equation (1). The horizontal axis shows the power supply voltage Vdc, and the vertical axis shows the variation in the drain-source voltage Vds of each switching element 10 as a percentage of the power supply voltage Vdc.

[0060] As shown in Figure 8, regardless of the value of the power supply voltage Vdc, the variation in the drain-source voltage Vds of each switching element 10 is less than 4%. In particular, when the voltage is 100V or higher, the variation is less than 0.5%. Therefore, the switching control circuit 1 in this embodiment enables voltage balancing regardless of the value of the power supply voltage Vdc.

[0061] According to this embodiment, the switching control circuit 1 connects an additional capacitance Ca between the gate and drain of the switching elements 10, excluding the switching element 10 connected to the lowest stage. This allows for a low-cost and simple configuration in the switching control circuit 1, which connects multiple low-voltage devices in series, by adding only one capacitance per switching element 10, and enabling voltage balancing during the turn-off of each switching element 10. Furthermore, since only one capacitance is added to each switching element 10, the amount of parameter adjustment required for control can be reduced.

[0062] Furthermore, according to this embodiment, the switching control circuit 1, with the configuration described above, has little effect on the deviation of the voltage distribution of each switching element 10 even when the power supply voltage Vdc or load current fluctuates. Therefore, for example, by operating the system so that the voltage distribution of the switching elements 10 is balanced at low voltage, and then increasing the voltage to the operating voltage to drive the switching elements 10, the amount of parameter adjustment required is reduced, and the risk of damage to the switching elements 10 due to mismatch in voltage distribution at high voltage is mitigated.

[0063] (Second Embodiment) Figure 9 is a schematic diagram of the switching control circuit 1 in the second embodiment.

[0064] This figure shows an example in which n switching elements 10 are connected in series in the switching control circuit 1, and a surge suppression circuit 13 is connected in parallel to both ends of the multiple switching elements 10 connected in series. In this embodiment, the parts that differ from the first embodiment will be mainly described, and the parts that are the same will be omitted from the explanation.

[0065] When the circuit described in the above-mentioned embodiment is mounted on a circuit board, parasitic inductance components may be generated on the wiring, potentially causing voltage and current surges and ringing during switching. For example, if the amplitude of the surge current is large, even if the voltage distribution of each switching element 10 is equal, these elements may be damaged.

[0066] In this embodiment, a surge suppression circuit 13 is connected between the drain terminal of the uppermost switching element 10 and the low-potential wiring in order to cancel out voltage and current surges caused by parasitic inductance in the drain and source wiring of each switching element 10.

[0067] Figure 10 shows an example of the surge suppression circuit 13 in this embodiment.

[0068] Figure 10(A) shows an example of an RC snubber circuit as a surge suppression circuit 13, Figure 10(B) shows an example of an RCD snubber circuit as a surge suppression circuit 13, and Figure 10(C) shows an example of a TVS diode as a surge suppression circuit 13.

[0069] Figure 10(A) shows an example of an RC snubber circuit as a surge suppression circuit 13. The RC snubber circuit is equipped with a snubber resistor Rsnb and a snubber capacitance Csnb. It suppresses spike voltages by mitigating voltage and current surges generated by parasitic inductance, etc., with the snubber capacitance Csnb and converting them into heat with the snubber resistor Rsnb.

[0070] Figure 10(B) shows an example of an RCD snubber circuit as a surge suppression circuit 13. The RCD snubber circuit includes a snubber resistor Rsnb, a snubber capacitance Csnb, and a snubber diode Dsnb. Unlike the RC snubber circuit, the addition of the snubber diode Dsnb allows for a larger snubber resistance value.

[0071] Figure 10(C) shows an example of a surge suppression circuit 13 using a TVS diode. The TVS diode turns on when a surge voltage occurs, and clamps the overvoltage by dissipating the surge current on the TVS diode side.

[0072] The surge suppression circuit 13 is not limited to the example described in this embodiment, and various circuits for suppressing voltage and current surges may be employed.

[0073] According to this embodiment, the switching control circuit 1 includes a surge suppression circuit 13. This allows the switching control circuit 1 to suppress the effects of parasitic inductance in the main circuit loop. For example, even if voltage and current surges occur during switching, it is possible to prevent damage to the switching element 10.

[0074] (Third embodiment) Figure 11 is a schematic diagram of the switching control circuit 1 in the third embodiment.

[0075] This figure shows an example in which n switching elements 10 are connected in series in the switching control circuit 1, and a capacitance Cgs' is connected between the gate and source of each switching element 10. In this embodiment, the parts that differ from the first embodiment will be mainly described, and the parts that are similar will be omitted from the explanation.

[0076] Unlike the example described above, in order to cancel out voltage and current surges caused by parasitic inductance in the gate wiring of the switching element 10, a capacitance Cgs' is connected between the gate and source of each switching element 10. In this embodiment, a capacitance Cgs' is connected between the gate and source of n switching elements 10. Furthermore, in this embodiment, in order to cancel out surges, the capacitance value of the capacitance Cgs' is set to the same value for all switching elements 10.

[0077] Generally, since the drain and source wiring of each switching element 10 and the gate wiring are independent, surge countermeasures are implemented individually. Therefore, in addition to the surge countermeasures for parasitic inductance generated at the gate of each switching element 10 described in this embodiment, the surge suppression circuit 13 described in the second embodiment may also be used in combination. This makes it possible to cancel out voltage and current surges associated with parasitic inductance generated in the drain and source wiring of the switching element 10.

[0078] According to this embodiment, the switching control circuit 1 is provided with a capacitance Cgs' between the gate and source of each switching element 10. This allows the switching control circuit 1 to suppress the effects of parasitic inductance in the gate loop to which the gate control circuit 12 is connected. For example, even if voltage and current surges occur during switching, the voltage balance can be maintained, preventing damage to the switching element 10.

[0079] (Fourth Embodiment) Figure 12 is a schematic diagram of the switching control circuit 1 in the fourth embodiment.

[0080] This figure shows an example in which n switching elements 10 are connected in series in the switching control circuit 1. Furthermore, a capacitance Cg is connected between the gates and low-potential wiring of the 2nd to nth switching elements 10, counting from the low-potential side. In this embodiment, the parts that differ from the first embodiment will be mainly described, and the parts that are similar will be omitted from the explanation.

[0081] As described above, a parasitic capacitance Cp exists between the gate and the low-potential wiring of each switching element 10. In order to determine the value of the capacitance Ca, it is desirable to specify the exact value of the parasitic capacitance Cp in advance. However, it may be difficult to specify the exact value of the parasitic capacitance Cp at the design stage. Therefore, in the present embodiment, a capacitance Cg with a known value and sufficiently larger than the parasitic capacitance Cp is added between the gate and the low-potential wiring of each switching element 10. Instead of the parasitic capacitance Cp, the calculation of the capacitance Ca is performed by replacing it with the value of the capacitance Cg which is a known value.

[0082] For an integer k (2 ≤ k ≤ n), the capacitance Cg connected to the k-th switching element 10 counted from the low-potential side is defined as capacitance Cg k as described above. Similar to the above-described embodiment, the value of the capacitance Ca k to be added between the gate and the drain of the k-th switching element 10 counted from the low-potential side is the sum of the capacitance values of the capacitances Ca added to the switching elements 10 from the 2nd to the (k - 1)-th counted from the low-potential side, and the value obtained by multiplying the capacitance Cg k of the k-th switching element 10 by (k - 1). The value of Ca k to be added at the k-th position is represented by Equation (2). Here, the value of the capacitance Cg k is sufficiently larger than the value of the corresponding parasitic capacitance Cp k . Ca k = Ca (k-1) + (k - 1)Cg k (2)

[0083] Also, similar to the above-described embodiment, assuming a general device, if the value of the added capacitance Ca is set within the range of ±80% (0.2 to 1.8 times) of the value derived from Equation (2), regardless of the parasitic capacitance Cp generated between the gate and the ground, the variation in the drain-source voltage Vds in each element can be suppressed by 20% or more compared to the case where the capacitance Ca is not added.

[0084] According to this embodiment, the switching control circuit 1 includes a capacitor Cg between the gate of each switching element 10 and the low potential wiring. Thereby, even when the value of the parasitic capacitance Cp cannot be accurately specified, the capacitance between the gate and the ground can be visualized, and the capacitance Ca can be accurately estimated at the design stage.

[0085] The technology described in the above embodiment can be widely applied to a circuit in which the switching elements 10 are connected in series. Compared with a single switching element 10, a high voltage can be applied to the circuit by using the switching circuit described in this embodiment. Therefore, for example, in addition to the above-described power conversion device and inverter 100, it can be used in a wide variety of power electronics circuits. Further, this technology can also be used by being incorporated into a gate drive IC (Integrated Circuit), an IPM (Intelligent Power Module), or the like. <0000​​​​​​​​​​​​​​​​​​​​​​​​ Switching circuit.

[0089] (2) n-1 units of the aforementioned capacity Ca k This refers to the parasitic capacitance Cp present between the gate and the low-potential wiring of each of the 2nd to nth switching elements. k A switching circuit as described in (1), wherein the capacitance value is set according to the value.

[0090] (3) n-1 units of the aforementioned capacity Ca k This refers to the switching circuit described in (1) to (2), which is set so that the capacitance value increases from the low potential side to the high potential side.

[0091] (4) The aforementioned capacity Ca k The capacity value is Ca k =Ca (k-1) +(k-1)Cp k The switching circuits described in (2) and (3) are set according to the values ​​derived by the above.

[0092] (5) n-1 units of the aforementioned capacity Ca k The switching circuit described in (4), wherein the capacitance value is set within the range of 0.2 to 1.8 times the derived value.

[0093] (6) The switching circuit according to (1) to (5), further comprising a surge suppression circuit connected to the drain terminal of the switching element on the highest potential side among the 1st to nth switching elements and to a low potential wiring.

[0094] (7) The switching circuit according to (1) to (6), further comprising n capacitors Cgs' connected between the gate and source of each of the 1st to nth switching elements.

[0095] (8) The switching circuit described in (7), wherein each of the n capacitors Cgs' is set to the same value.

[0096] (9) n-1 capacitors Cg connected between the gate and low-potential wiring of the switching element k Furthermore, n-1 units of the aforementioned capacity Cg k This is provided in the 2nd to nth switching elements among the 1st to nth switching elements counting from the low-potential side, The switching circuits described in (1) to (8).

[0097] (10) The aforementioned capacity Cg k The capacity value is the capacity Cg k The parasitic capacitance Cp of the switching element provided k A switching circuit described in (9) that is greater than the value of (9).

[0098] (11) n-1 units of the aforementioned capacity Ca k The capacity value is Ca k =Ca (k-1) +(k-1)Cg k The switching circuit described in (10), which is set according to the value derived by (10).

[0099] (12) n-1 units of the aforementioned capacity Ca k The switching circuit described in (11), wherein the capacitance value is set within the range of 0.2 to 1.8 times the derived value.

[0100] (13) The switching circuit according to (1) to (12), further comprising a capacitance Ca1 connected between the gate and drain of the first switching element counting from the low-potential side.

[0101] (14) A power converter comprising two switching circuits that constitute an arm pair and are controlled by a controller, The switching circuit is n switching elements (n is an integer of 2 or more) connected in series, n - 1 capacitors Ca connected between the gates and drains of the switching elements k (k is an integer satisfying 2 <= k <= n), and the n - 1 capacitors Ca k are each of different capacitance values, among the 1st to nth switching elements counted from the low - potential side, provided in the 2nd to nth switching elements respectively, a power conversion device. [[ID=I7]]

[0102] (15) an inverter including three sets of power conversion devices controlled by a controller and including two switching circuits constituting an arm pair, each of the switching circuits n switching elements (n is an integer of 2 or more) connected in series, n - 1 capacitors Ca connected between the gates and drains of the switching elements k (k is an integer satisfying 2 <= k <= n), and the n - I capacitors Ca k are each of different capacitance values, among the 1st to nth switching elements counted from the low - potential side, provided in the 2nd to nth switching elements respectively, an inverter.

Explanation of Signs

[0103] 1: Switching control circuit, 10: Switching element, 11: Switching circuit, 12: Gate control circuit, 13: Surge suppression circuit, 30: Controller, 50: Load, 100: Inverter

Claims

1. n switching elements (where n is an integer greater than or equal to 2) connected in series, n-1 capacitors Ca connected between the gate and drain of the switching element ｋ (where k is an integer satisfying 2 = < k = < n) n-1 of the aforementioned capacities Ca ｋ teeth, Each has a different capacity value, Among the 1st to nth switching elements, counting from the low-potential side, the 2nd to nth switching elements are each provided with: Switching circuit.

2. n-1 of the aforementioned capacities Ca ｋ This refers to the parasitic capacitance Cp present between the gate and the low-potential wiring of each of the 2nd to nth switching elements. ｋ A switching circuit according to claim 1, wherein the capacitance value is set according to the value.

3. n-1 of the aforementioned capacities Ca ｋ The switching circuit according to claim 1, wherein the capacitance value is set to increase from the low potential side to the high potential side.

4. The capacity Ca ｋ has a capacity value of Ca ｋ = Ca （ｋ－１） + (k - 1)Cp ｋ The switching circuit according to claim 2, which is set according to the value derived by the above formula.

5. n-1 of the aforementioned capacities Ca ｋ The switching circuit according to claim 4, wherein the capacitance value is set in the range of 0.2 to 1.8 times the derived value.

6. The switching circuit according to claim 1, further comprising a surge suppression circuit connected to the drain terminal of the switching element on the highest potential side among the 1st to nth switching elements, and to a low-potential wiring.

7. The switching circuit according to claim 1, further comprising n capacitors Cgs' connected between the gate and source of each of the 1st to nth switching elements.

8. The switching circuit according to claim 7, wherein each of the n capacitors Cgs' is set to the same value.

9. n-1 capacitors Cg connected between the gate and low-potential wiring of the switching element. ｋ Furthermore, n-1 of the aforementioned capacities Cg ｋ This is provided in the 2nd to nth switching elements among the 1st to nth switching elements counting from the low-potential side, The switching circuit according to claim 2.

10. The aforementioned volume Cg ｋ The capacity value is the capacity Cg ｋ The parasitic capacitance Cp of the switching element provided ｋ A switching circuit according to claim 9, wherein the value is greater than the value of the switching circuit according to claim 9.

11. n-1 of the aforementioned capacities Ca ｋ The capacity value is Ca ｋ = Ca （ｋ－１） + (k-1)Cg ｋ A switching circuit according to claim 10, which is set according to a value derived by

12. n-1 of the aforementioned capacities Ca ｋ The switching circuit according to claim 11, wherein the capacitance value is set in the range of 0.2 to 1.8 times the derived value.

13. Capacitor Ca connected between the gate and drain of the first switching element counting from the low-potential side 1 The switching circuit according to claim 1, further comprising:

14. A power converter comprising two switching circuits that constitute an arm pair and are controlled by a controller, The aforementioned switching circuit is n switching elements (where n is an integer greater than or equal to 2) connected in series, n-1 capacitors Ca connected between the gate and drain of the switching element ｋ (where k is an integer satisfying 2 = < k = < n) n-1 of the aforementioned capacities Ca ｋ teeth, Each has a different capacity value, Among the 1st to nth switching elements, counting from the low-potential side, the 2nd to nth switching elements are each provided with: Power converter.

15. An inverter comprising three sets of power converters, each containing two switching circuits that form an arm pair and are controlled by a controller, Each of the aforementioned switching circuits is, n switching elements (where n is an integer greater than or equal to 2) connected in series, n-1 capacitors Ca connected between the gate and drain of the switching element ｋ (where k is an integer satisfying 2 = < k = < n) n-1 of the aforementioned capacities Ca ｋ teeth, Each has a different capacity value, Among the 1st to nth switching elements, counting from the low-potential side, the 2nd to nth switching elements are each provided with: Inverter.

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