Memory device

Abstract

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment comprises a memory cell in which a first conductive layer, a switching layer, a third conductive layer, a resistance-changing layer, and a second conductive layer are stacked in this order. The switching layer includes a two-dimensional crystal. The first conductive layer or the second conductive layer includes a two-dimensional crystal. When the memory cell is in a low-resistance state, as the absolute value of the voltage is increased, it exhibits a nonlinear current-voltage characteristic in which the current rises at a specific first threshold voltage, and as the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, it exhibits a current-voltage characteristic in which the current falls at a voltage with an absolute value smaller than the first threshold voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] As a large-capacity nonvolatile memory device, there is a cross-point type two-terminal memory device. The cross-point type two-terminal memory device is easy to miniaturize and highly integrate memory cells.

[0003] Memory cells of the cross-point type two-terminal memory device have, for example, a resistance change element and a switching element. By having a switching element in the memory cell, the current flowing through memory cells other than the selected memory cell is suppressed.

[0004] The switching element is required to have excellent characteristics such as a low leakage current, a high on-current, and high reliability.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a memory device having a switching element with excellent characteristics.

Means for Solving the Problems

[0007] The memory device of the embodiment includes a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a switching layer provided between the first conductive layer and the third conductive layer, and a resistance change layer provided between the third conductive layer and the second conductive layer, and comprises a memory cell in which the electrical resistance changes when a predetermined voltage is applied, and which can take on a low resistance state and a high resistance state in which the electrical resistance is higher than the electrical resistance of the low resistance state, and the switching layer is made of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, disele The conductive layer comprises at least one first compound selected from the group consisting of rhenium ditelluride and rhenium ditelluride, and at least one of the first conductive layer and the third conductive layer comprises at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite, and when the memory cell is in the low-resistance state, when a voltage is applied between the first conductive layer and the second conductive layer, it exhibits a nonlinear current-voltage characteristic in which the current rises at a first threshold voltage as the absolute value of the voltage is increased, and when the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, it exhibits a current-voltage characteristic in which the current falls at a first voltage with an absolute value smaller than the first threshold voltage. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram of the storage device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 3] A diagram illustrating the current-voltage characteristics of the memory device according to the first embodiment. [Figure 4] A schematic cross-sectional view of a memory cell of a first modified memory device according to the first embodiment. [Figure 5] A schematic cross-sectional view of a memory cell of a second modified memory device according to the first embodiment. [Figure 6] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 7] A diagram illustrating the current-voltage characteristics of the memory device according to the second embodiment. [Figure 8] A schematic cross-sectional view of the memory cell of the first modified memory device of the second embodiment. [Figure 9] A schematic cross-sectional view of a memory cell of a second modified memory device according to the second embodiment. [Figure 10] A schematic cross-sectional view of a memory cell of the third embodiment of the storage device. [Figure 11] A schematic cross-sectional view of the memory cell of the fourth embodiment of the storage device. [Figure 12] A diagram illustrating the current-voltage characteristics of the memory device according to the fourth embodiment. [Figure 13] A schematic cross-sectional view of a memory cell of a modified memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described will be omitted from the description as appropriate.

[0010] Qualitative and quantitative analyses of the chemical composition constituting the memory device described herein can be performed, for example, by Rutherford backscattering spectroscopy (RBS), secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS). Furthermore, a transmission electron microscope (TEM) can be used, for example, to measure the thickness of the components constituting the memory device, the distance between components, etc. Furthermore, for the identification, abundance, bonding state, local structure (interatomic distance, coordination number), and chemical state of the constituent materials of the memory device, for example, scanning transmission electron microscopes (STEM), X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), or EELS can be used. In addition, for the measurement of the band gap of the constituent materials of the memory device, for example, EELS can be used.

[0011] In this specification, "two-dimensional crystal" means a structure in which atoms or molecules are arranged periodically in a two-dimensional plane. It is possible to stack single layers of "two-dimensional crystals" bonded together by von der Waals forces to form a three-dimensional structure.

[0012] (First embodiment) The memory device according to the first embodiment includes a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a switching layer provided between the first conductive layer and the third conductive layer, and a resistance change layer provided between the third conductive layer and the second conductive layer. The memory device includes a memory cell whose electrical resistance changes upon application of a predetermined voltage and can take a low resistance state and a high resistance state having an electrical resistance higher than that of the low resistance state. The switching layer includes at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenide, and rhenium ditelluride. At least one of the first conductive layer and the third conductive layer includes at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenide, tantalum disulfide, tantalum diselenide, niobium disulfide, niobium diselenide, hafnium disulfide, and hafnium diselenide, graphene, or graphite. When the memory cell is in the low resistance state, when a voltage is applied between the first conductive layer and the second conductive layer, as the absolute value of the voltage is increased, a non-linear current-voltage characteristic is exhibited in which the current rises at a first threshold voltage, and as the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, a current-voltage characteristic is exhibited in which the current falls at a first voltage having an absolute value smaller than the first threshold voltage.

[0013] Further, the memory device according to the first embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect the plurality of first wirings. The memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0014] FIG. 1 is a block diagram of the memory device according to the first embodiment.

[0015] The memory cell array 100 of the memory device according to the first embodiment includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 that intersect the word lines 102 via an insulating layer on a semiconductor substrate 101. The bit lines 103 are provided, for example, above the word lines 102. Further, around the memory cell array 100, a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided as peripheral circuits.

[0016] The word line 102 is an example of the first wiring. Also, the bit line 103 is an example of the second wiring.

[0017] A plurality of memory cells MC are provided in a region where the word line 102 and the bit line 103 intersect. The memory device according to the first embodiment is a two-terminal magnetoresistive memory having a cross-point structure.

[0018] The plurality of word lines 102 are each connected to the first control circuit 104. Also, the plurality of bit lines 103 are each connected to the second control circuit 105. The sense circuit 106 is connected to the first control circuit 104 and the second control circuit 105.

[0019] The first control circuit 104 and the second control circuit 105 have functions, for example, of selecting a desired memory cell MC, writing data to the memory cell MC, reading data from the memory cell MC, erasing data from the memory cell MC, and the like. When reading data, the data of the memory cell MC is read as the amount of current flowing between the word line 102 and the bit line 103 or as a potential change in the bit line 103. The sense circuit 106 has a function of determining the amount of current or the potential change and determining the polarity of the data. For example, it determines "0" and "1" of the data.

[0020] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are configured, for example, by an electronic circuit using semiconductor devices formed on the semiconductor substrate 101.

[0021] Figure 2 is a schematic cross-sectional view of a memory cell of the first embodiment of the storage device. Figure 2 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0022] As shown in Figure 2, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The resistive switching layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0023] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0024] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0025] The electrical resistance of a memory cell (MC) changes when a predetermined voltage is applied. This change in electrical resistance allows the memory cell (MC) to exist in either a low-resistance state or a high-resistance state. The electrical resistance in the high-resistance state is higher than that in the low-resistance state.

[0026] The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the direction from the lower electrode 10 to the upper electrode 20 is, for example, 0.5 nm or more and 50 nm or less.

[0027] The switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. The switching layer 40 has the function of suppressing leakage current flowing to non-selected cells. In the memory cell MC, the switching layer 40 functions as a so-called selector.

[0028] The switching layer 40 contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride.

[0029] Molybdenum disulfide can be written as MoS2. Molybdenum diselenium can be written as MoSe2. Molybdenum ditelluride can be written as MoTe2. Tungsten disulfide can be written as WS2. Tungsten diselenium can be written as WSe2. Indium selenide can be written as InSe. Gallium sulfide can be written as GaS. Gallium selenide can be written as GaSe. Gallium telluride can be written as GaTe. Germanium sulfide can be written as GeS. Germanium selenide can be written as GeSe. Germanium telluride can be written as GeTe. Silicon sulfide can be written as SiS. Silicon selenide can be written as SiSe. Silicon telluride can be written as SiTe. Tin sulfide can be written as SnS. Tin selenide can be written as SnSe. Tin telluride can be written as SnTe. Rhenium disulfide can be written as ReS2. Rhenium diselenium can be written as ReSe2. Rhenium ditelluride can be written as ReT2.

[0030] The switching layer 40 includes a two-dimensional crystal. The switching layer 40 is composed of, for example, a single layer of two-dimensional crystal or multiple layers of two-dimensional crystal.

[0031] The switching layer 40 includes a crystal of space group P63 / mmc, a crystal of space group Pnma62, or a crystal of space group P-1. The crystals of space group P63 / mmc, space group Pnma62, and space group P-1 are two-dimensional crystals.

[0032] The first compound contained in the switching layer 40 is a two-dimensional crystal. The space group of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, and gallium telluride is P63 / mmc. The space group of germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, and tin telluride is Pnma62. The space group of rhenium disulfide, rhenium diselenium, and rhenium ditelluride is P-1.

[0033] The first compound is a chalcogenide. The first compound is a semiconductor. The first compound has the property that its band gap changes when a voltage is applied. The first compound has the property that as a voltage is applied, its band gap decreases and its electrical resistance decreases.

[0034] The lower electrode 10 is connected to the word line 102. The lower electrode 10 may also be part of the word line 102. The lower electrode 10 is in contact with, for example, the switching layer 40.

[0035] The upper electrode 20 is connected to the bit line 103. The upper electrode 20 may also be part of the bit line 103. The upper electrode 20 is in contact with, for example, the resistance change layer 50.

[0036] The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is in contact with, for example, the switching layer 40 and the resistance layer 50.

[0037] At least one of the lower electrode 10 and the intermediate electrode 30 contains at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite.

[0038] The lower electrode 10 includes, for example, at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite.

[0039] Tungsten ditelluride can be written as WTe2. Titanium disulfide can be written as TiS2. Titanium diselenium can be written as TiSe2. Tantalum disulfide can be written as TaS2. Tantalum diselenium can be written as TaSe2. Niobium disulfide can be written as NbS2. Niobium diselenium can be written as NbSe2. Hafnium disulfide can be written as HfS2. Hafnium diselenium can be written as HfSe2.

[0040] The lower electrode 10 includes, for example, a two-dimensional crystal. The lower electrode 10 is composed of, for example, a single layer of two-dimensional crystal or multiple layers of two-dimensional crystal. The surface of the lower electrode 10 on the side of the switching layer 40 is, for example, a two-dimensional crystal.

[0041] The second compound, graphene, and graphite contained in the lower electrode 10 are two-dimensional crystals.

[0042] The intermediate electrode 30 includes, for example, at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, and hafnium disulfide, graphene, or graphite.

[0043] The intermediate electrode 30 includes, for example, a two-dimensional crystal. The intermediate electrode 30 is composed of, for example, a single layer of two-dimensional crystal or multiple layers of two-dimensional crystal. The surface of the intermediate electrode 30 on the switching layer 40 side is, for example, a two-dimensional crystal.

[0044] The second compound, graphene, and graphite contained in the intermediate electrode 30 are two-dimensional crystals.

[0045] The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of graphite, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0046] Furthermore, it is acceptable for only one of the lower electrode 10 and the intermediate electrode 30 to contain the second compound, graphene, or graphite.

[0047] If the intermediate electrode 30 contains a second compound, graphene, or graphite, the lower electrode 10 contains, for example, at least one substance selected from the group consisting of graphite, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0048] If the lower electrode 10 contains a second compound, graphene, or graphite, the intermediate electrode 30 contains, for example, at least one substance selected from the group consisting of graphite, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0049] When forming a two-dimensional crystal switching layer 40 on the lower electrode 10 of the two-dimensional crystal, for example, a dry transfer method is used to suppress bubble formation at the interface between the lower electrode 10 and the switching layer 40. Similarly, when forming a two-dimensional crystal intermediate electrode 30 on the switching layer 40 of the two-dimensional crystal, for example, a dry transfer method is used to suppress bubble formation at the interface between the switching layer 40 and the intermediate electrode 30. By using a dry transfer method that suppresses bubble formation at the interface, the interface between the lower electrode 10 and the switching layer 40 and the interface between the switching layer 40 and the intermediate electrode 30 can be cleaned.

[0050] The resistive change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistive change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistive change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

[0051] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0052] The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change with respect to a predetermined writing voltage, and the magnetization direction is fixed in a specific direction.

[0053] The tunnel layer 52 is an insulator. Electrons pass through the tunnel layer 52 by the tunneling effect.

[0054] The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes in response to a predetermined writing voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and flowing a current between the intermediate electrode 30 and the upper electrode 20.

[0055] By changing the magnetization direction of the free layer 53, the electrical resistance of the resistance-changing layer 50 changes. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high-resistance state is achieved where current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low-resistance state is achieved where current is easy to flow. Note that the arrangement of the fixed layer 51 and the free layer 53 can be reversed. In other words, the layers may be stacked in the order of intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20.

[0056] When the resistive transition layer 50 is in a low-resistance state, the memory cell MC is in a low-resistance state. Conversely, when the resistive transition layer 50 is in a high-resistance state, the memory cell MC is in a high-resistance state.

[0057] Figure 3 is an explanatory diagram of the current-voltage characteristics of the memory device according to the first embodiment. The horizontal axis represents the voltage applied between the lower electrode 10 and the upper electrode 20 of the memory cell MC, and the vertical axis represents the current flowing between the lower electrode 10 and the upper electrode 20 of the memory cell MC. The vertical axis is, for example, on a logarithmic scale.

[0058] The following explanation will use the case where a positive voltage is applied to the lower electrode 10 by the upper electrode 20 as an example. There is also the case where a negative voltage is applied to the lower electrode 10 by the upper electrode 20. When a negative voltage is applied to the lower electrode 10 by the upper electrode 20, the direction of the arrow on the horizontal axis in Figure 3 will indicate the direction in which the negative value increases. In both the case where a positive voltage is applied to the lower electrode 10 by the upper electrode 20 and the case where a negative voltage is applied to the lower electrode 10 by the upper electrode 20, the direction of the arrow in Figure 3 is the direction in which the absolute value of the applied voltage increases.

[0059] In Figure 3, the solid line shows the current-voltage characteristics when the memory cell MC is in a low-resistance state. The dotted line in Figure 3 shows the current-voltage characteristics when the memory cell MC is in a high-resistance state. In Figure 3, the arrows along the current-voltage characteristics indicate the direction of the voltage sweep.

[0060] First, we will explain the current-voltage characteristics when the memory cell MC is in a low-resistance state. As the applied voltage is increased, the current rises at a first threshold voltage (Vth1 in Figure 3), exhibiting a nonlinear current-voltage characteristic. Subsequently, as the voltage is decreased from a voltage exceeding the first threshold voltage Vth1 (Vx in Figure 3), the current falls at a first voltage lower than the first threshold voltage (V1 in Figure 3). In other words, when the memory cell MC is in a low-resistance state, the current-voltage characteristics of the memory cell MC exhibit hysteresis. The first voltage V1 is, for example, between 0.1 and 0.9 times the first threshold voltage Vth1.

[0061] Next, we will explain the current-voltage characteristics when the memory cell MC is in a high-resistance state. As the applied voltage is increased, the current rises at a specific second threshold voltage (Vth2 in Figure 3), exhibiting a nonlinear current-voltage characteristic. Subsequently, as the voltage is decreased from a voltage exceeding the second threshold voltage Vth2 (Vx in Figure 3), the current falls at a second voltage lower than the second threshold voltage (V2 in Figure 3). In other words, when the memory cell MC is in a high-resistance state, the current-voltage characteristics of the memory cell MC exhibit hysteresis. The second voltage V2 is, for example, between 0.1 and 0.9 times the second threshold voltage Vth2.

[0062] The second threshold voltage Vth2 and the first threshold voltage Vth1 are, for example, approximately the same magnitude. Also, the second voltage V2 is, for example, greater than the first voltage V1.

[0063] For example, the high-resistance state of the resistive switching layer 50 is defined as data "1," and the low-resistance state is defined as data "0." The memory cell MC can maintain different resistance states, enabling it to store 1-bit data of "0" and "1."

[0064] When reading data from a memory cell MC, for example, the read voltage Vread is set to a voltage higher than the first threshold voltage Vth1 and the second threshold voltage Vth2. If the memory cell MC is in a low-resistance state, the first read current Iread1 flows. If the memory cell MC is in a high-resistance state, the second read current Iread2 flows. The first read current Iread1 is greater than the second read current Iread2. For example, by detecting the magnitude of the read current when the read voltage Vread is applied to the memory cell MC, it is possible to determine the data written to the memory cell MC.

[0065] Next, the operation and effects of the storage device according to the first embodiment will be described.

[0066] As shown in Figure 1, the memory device of the first embodiment has multiple memory cells MC in the region where the word line 102 and the bit line 103 intersect. For example, when one of the multiple memory cells MC is selected for a read operation, it is necessary to suppress the leakage current flowing to the unselected cells other than the selected cell. This is because if the leakage current flowing to the unselected cells becomes large, for example, data read errors may occur or the power consumption of the memory device may increase.

[0067] As shown in Figure 3, the memory cell MC of the first embodiment has a nonlinear current-voltage characteristic in which the current rises sharply at a first threshold voltage when in a low-resistance state. Furthermore, when in a high-resistance state, it has a nonlinear current-voltage characteristic in which the current rises sharply at a second threshold voltage. Therefore, the memory device of the first embodiment can suppress leakage current flowing to non-selected cells, where the voltage applied between the electrodes is smaller than that of selected cells. Thus, for example, a memory device can be realized in which read operations are stable and power consumption is reduced.

[0068] Furthermore, the reason why the memory cell MC has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage is because the switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

[0069] The switching layer 40 of the memory device in the first embodiment includes a two-dimensional crystal having a stable and flat two-dimensional structure. By including a two-dimensional crystal having a stable and flat two-dimensional structure in the switching layer 40, a switching layer 40 with small variation in characteristics and excellent endurance characteristics can be realized. Therefore, a memory device with small variation in characteristics and high reliability can be realized.

[0070] Furthermore, in the memory cell MC of the first embodiment, when in a low-resistance state, the current-voltage characteristics exhibit hysteresis, as shown in Figure 3. The presence of hysteresis in the current-voltage characteristics increases the current flowing through the memory cell MC after the voltage applied to the memory cell MC exceeds the first threshold voltage Vth1, compared to the case without hysteresis.

[0071] Furthermore, the reason why the current-voltage characteristics of the memory cell MC in the low-resistance state exhibit hysteresis is because the current-voltage characteristics of the switching layer 40 exhibit hysteresis. The hysteresis in the current-voltage characteristics of the switching layer 40 increases the current after exceeding the threshold voltage of the switching layer 40, improving the ON / OFF ratio of the switching layer 40. This improved ON / OFF ratio of the switching layer 40 enables the realization of a memory device with, for example, more stable read operations and reduced power consumption.

[0072] As described above, the two-dimensional crystalline switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage, and the current-voltage characteristic exhibits hysteresis. This is thought to be due to the selection of a first compound as the two-dimensional crystal for the switching layer 40, which has a smaller band gap when a voltage is applied, the use of a two-dimensional crystal for the electrode in contact with the switching layer 40, and the creation of a clean interface between the two-dimensional crystals of the switching layer 40 and the electrode. The clean interface between the switching layer 40 and the electrode is thought to be due to the use of a dry transfer method that suppresses bubble formation at the interface during the formation of the switching layer 40 and the electrode.

[0073] According to the first embodiment, a memory device is realized that has stable operating characteristics, reduced power consumption, and improved reliability.

[0074] From the viewpoint of achieving miniaturization of memory devices, the thickness of the switching layer 40 in the direction from the lower electrode 10 to the upper electrode 20 is preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0075] Furthermore, from the viewpoint of increasing the hysteresis of the switching layer 40 and improving the ON / OFF ratio, the first voltage V1 is preferably 0.9 times or less, more preferably 0.8 times or less, and even more preferably 0.7 times or less of the first threshold voltage Vth1.

[0076] (First variation) The first modified memory device of the first embodiment includes a first conductive layer, a second conductive layer, a switching layer provided between the first and second conductive layers, and a resistance-changing layer provided between the switching layer and the second conductive layer, and comprises a memory cell whose electrical resistance changes when a predetermined voltage is applied, and which can take on a low-resistance state and a high-resistance state in which the electrical resistance is higher than that of the low-resistance state. The first modified memory device differs from the memory device of the first embodiment in that it does not include a third conductive layer. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0077] Figure 4 is a schematic cross-sectional view of a memory cell of a first modified memory device of the first embodiment. Figure 4 corresponds to Figure 2 of the first embodiment.

[0078] The first modified memory cell MC, as shown in Figure 4, comprises a lower electrode 10, an upper electrode 20, a switching layer 40, and a resistive switching layer 50. The resistive switching layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0079] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0080] The switching layer 40 and the resistive switching layer 50 are in contact.

[0081] The switching layer 40 contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride.

[0082] The lower electrode 10 includes at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite.

[0083] According to the first modification of the first embodiment of the storage device, a storage device is realized that, similar to the first embodiment, has stable operating characteristics, reduced power consumption, and improved reliability.

[0084] (Second variation) The memory device of the second modification of the first embodiment differs from the memory device of the first embodiment in that the memory cell further includes a current suppression layer comprising at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0085] Figure 5 is a schematic cross-sectional view of a memory cell of a second modified storage device of the first embodiment. Figure 5 corresponds to Figure 2 of the first embodiment.

[0086] As shown in Figure 5, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive switching layer 50, and a current suppression layer 70. The resistive switching layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0087] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0088] The current suppression layer 70 is provided, for example, between the lower electrode 10 and the upper electrode 20. The current suppression layer 70 is provided, for example, between the resistance change layer 50 and the upper electrode 20, as shown in Figure 5.

[0089] Furthermore, the current suppression layer 70 is not limited to being located between the resistance change layer 50 and the upper electrode 20. For example, the current suppression layer 70 may be located between the lower electrode 10 and the switching layer 40, between the switching layer 40 and the intermediate electrode 30, or between the intermediate electrode 30 and the resistance change layer 50. Also, the current suppression layer 70 may be located on the opposite side of the lower electrode 10 from the switching layer 40, or on the opposite side of the upper electrode 20 from the resistance change layer 50. In addition, the current suppression layer 70 may be located at multiple positions.

[0090] The thickness of the current suppression layer 70 in the direction from the lower electrode 10 to the upper electrode 20 is, for example, 0.2 nm or more and 2 nm or less.

[0091] The current suppression layer 70 contains at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride.

[0092] According to the second modification of the first embodiment, a storage device is realized that, like the first embodiment, has stable operating characteristics, reduced power consumption, and improved reliability. Furthermore, according to the second modification of the first embodiment, the current suppression layer 70 suppresses the flow of large currents to the memory cell MC. Therefore, for example, a storage device with high destruction resistance is realized.

[0093] As described above, according to the first embodiment and its modifications, a memory device is realized that has a switching element with excellent characteristics, stable operating characteristics, reduced power consumption, and improved reliability.

[0094] (Second embodiment) The storage device of the second embodiment differs from the storage device of the first embodiment in that it is a resistive random-access memory (ReRAM). Some parts of the description that overlap with the first embodiment will be omitted below.

[0095] Figure 6 is a schematic cross-sectional view of a memory cell of the second embodiment of the storage device. Figure 6 shows a cross-section of a single memory cell MC, for example, indicated by a dotted circle, in the memory cell array 100 of Figure 1. Figure 6 corresponds to Figure 2 of the first embodiment.

[0096] As shown in Figure 6, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50. The resistive switching layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0097] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0098] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0099] The configuration of the switching layer 40, the lower electrode 10, the upper electrode 20, and the intermediate electrode 30 is the same as that of the memory device in the first embodiment.

[0100] The resistance-changing layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0101] The high-resistance layer 50x is, for example, a metal oxide. The high-resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0102] The low-resistance layer 50y is, for example, a metal oxide. The low-resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0103] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0104] By applying a voltage to the resistance-changing layer 50, the resistance-changing layer 50 changes from a high-resistance state to a low-resistance state, or from a low-resistance state to a high-resistance state. The application of voltage to the resistance-changing layer 50 causes oxygen ions to move between the high-resistance layer 50x and the low-resistance layer 50y, changing the amount of oxygen vacancies in the low-resistance layer 50y. The conductivity of the resistance-changing layer 50 changes in accordance with the amount of oxygen vacancies in the low-resistance layer 50y. The low-resistance layer 50y is a so-called vacancy-modulated conductive oxide.

[0105] For example, a high-resistance state is defined as data "1," and a low-resistance state as data "0." The memory cell MC can then store 1-bit data, either "0" or "1."

[0106] Figure 7 is an explanatory diagram of the current-voltage characteristics of the memory device in the second embodiment. Figure 7 corresponds to Figure 3 of the first embodiment.

[0107] In Figure 7, the solid line shows the current-voltage characteristics when the memory cell MC is in a low-resistance state. The dotted line in Figure 7 shows the current-voltage characteristics when the memory cell MC is in a high-resistance state. In Figure 7, the arrows along the current-voltage characteristics indicate the direction of the voltage sweep.

[0108] First, we will explain the current-voltage characteristics when the memory cell MC is in a low-resistance state. As the applied voltage is increased, the current rises at a first threshold voltage (Vth1 in Figure 7), exhibiting a nonlinear current-voltage characteristic. Subsequently, as the voltage is decreased from a voltage exceeding the first threshold voltage Vth1 (Vx in Figure 7), the current falls at a first voltage lower than the first threshold voltage (V1 in Figure 7). In other words, when the memory cell MC is in a low-resistance state, the current-voltage characteristics of the memory cell MC exhibit hysteresis. The first voltage V1 is, for example, between 0.1 and 0.9 times the first threshold voltage Vth1.

[0109] Next, we will explain the current-voltage characteristics when the memory cell MC is in a high-resistance state. As the applied voltage is increased, the current rises at a second threshold voltage (Vth2 in Figure 7), exhibiting a nonlinear current-voltage characteristic. Subsequently, as the voltage is decreased from a voltage exceeding the second threshold voltage Vth2 (Vx in Figure 7), the current falls at a second voltage lower than the second threshold voltage (V2 in Figure 7). In other words, when the memory cell MC is in a high-resistance state, the current-voltage characteristics of the memory cell MC exhibit hysteresis. The second voltage V2 is, for example, between 0.1 and 0.9 times the second threshold voltage Vth2.

[0110] The second threshold voltage Vth2 is, for example, greater than the first threshold voltage Vth1. Also, the second voltage V2 is, for example, of about the same magnitude as the first voltage V1.

[0111] For example, the high-resistance state of the resistive switching layer 50 is defined as data "1," and the low-resistance state is defined as data "0." The memory cell MC can maintain different resistance states, enabling it to store 1-bit data of "0" and "1."

[0112] When reading data from a memory cell MC, for example, the voltage between a first threshold voltage Vth1 and a second threshold voltage Vth2 is set as the read voltage Vread. If the memory cell MC is in a low-resistance state, a first read current Iread1 flows. If the memory cell MC is in a high-resistance state, a second read current Iread2 flows. The first read current Iread1 is greater than the second read current Iread2. By detecting the magnitude of the read current when the read voltage Vread is applied to the memory cell MC, it is possible to determine the data written to the memory cell MC.

[0113] The difference in electrical resistance between the low-resistance state and the high-resistance state of the resistive transition layer 50 of the resistive transition memory in the second embodiment is extremely large compared to the difference in electrical resistance between the low-resistance state and the high-resistance state of the resistive transition layer 50 of the magnetoresistive memory in the first embodiment. Therefore, the difference between the first read current Iread1 and the second read current Iread2 of the memory cell MC of the resistive transition memory is extremely large compared to the difference between the first read current Iread1 and the second read current Iread2 of the memory cell MC of the magnetoresistive memory.

[0114] Furthermore, in resistive random-access memory, the current flowing at a voltage below the first threshold voltage Vth1 in the high-resistance state is extremely small compared to the current flowing at a voltage below the first threshold voltage Vth1 in the low-resistance state.

[0115] According to the second embodiment, a storage device is realized that, similar to the first embodiment, has stable operating characteristics, reduced power consumption, and improved reliability.

[0116] (First variation) The first modified storage device of the second embodiment differs from the storage device of the second embodiment in that it does not include a third conductive layer. Hereafter, some descriptions that overlap with the second embodiment may be omitted.

[0117] Figure 8 is a schematic cross-sectional view of the memory cell of the first modified storage device in the second embodiment. Figure 8 corresponds to Figure 6 of the second embodiment.

[0118] The first modified memory cell MC, as shown in Figure 8, comprises a lower electrode 10, an upper electrode 20, a switching layer 40, and a resistive switching layer 50. The resistive switching layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0119] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0120] The switching layer 40 and the resistive switching layer 50 are in contact.

[0121] The switching layer 40 contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride.

[0122] The lower electrode 10 includes at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite.

[0123] According to the first modification of the second embodiment, a storage device is realized that, similar to the second embodiment, has stable operating characteristics, reduced power consumption, and improved reliability.

[0124] (Second variation) The second modified memory device of the second embodiment differs from the memory device of the second embodiment in that the memory cell further includes a current suppression layer comprising at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride. Hereafter, some descriptions that overlap with the second embodiment may be omitted.

[0125] Figure 9 is a schematic cross-sectional view of a memory cell of a second modified memory device of the second embodiment. Figure 9 corresponds to Figure 6 of the second embodiment.

[0126] As shown in Figure 9, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive switching layer 50, and a current suppression layer 70. The resistive switching layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0127] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0128] The current suppression layer 70 is provided, for example, between the lower electrode 10 and the upper electrode 20. The current suppression layer 70 is provided, for example, between the resistance change layer 50 and the upper electrode 20, as shown in Figure 9.

[0129] Furthermore, the current suppression layer 70 is not limited to being located between the resistance change layer 50 and the upper electrode 20. For example, the current suppression layer 70 may be located between the lower electrode 10 and the switching layer 40, between the switching layer 40 and the intermediate electrode 30, or between the intermediate electrode 30 and the resistance change layer 50. Also, the current suppression layer 70 may be located on the opposite side of the lower electrode 10 from the switching layer 40, or on the opposite side of the upper electrode 20 from the resistance change layer 50. In addition, the current suppression layer 70 may be located at multiple positions.

[0130] The thickness of the current suppression layer 70 in the direction from the lower electrode 10 to the upper electrode 20 is, for example, 0.2 nm or more and 2 nm or less.

[0131] The current suppression layer 70 contains at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride.

[0132] According to the second modified memory device of the second embodiment, a memory device with stable operating characteristics, reduced power consumption, and improved reliability is realized, similar to the second embodiment. Furthermore, according to the second modified memory device of the second embodiment, the current suppression layer 70 suppresses the flow of large currents to the memory cell MC. Therefore, for example, a memory device with high destruction resistance is realized.

[0133] As described above, according to the second embodiment and its modifications, a memory device is realized that has a switching element with excellent characteristics, stable operating characteristics, reduced power consumption, and improved reliability.

[0134] (Third embodiment) The storage device of the third embodiment differs from the storage device of the second embodiment in that it is a Phase Change Memory (PCM). Some parts of the description that overlap with the second embodiment will be omitted below.

[0135] Figure 10 is a schematic cross-sectional view of a memory cell of the third embodiment of the storage device. Figure 10 shows a cross-section of a single memory cell MC, for example, indicated by a dotted circle, in the memory cell array 100 of Figure 1. Figure 10 corresponds to Figure 6 of the second embodiment.

[0136] As shown in Figure 10, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistive switching layer 50.

[0137] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0138] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0139] The configuration of the switching layer 40, the lower electrode 10, the upper electrode 20, and the intermediate electrode 30 is the same as that of the storage device in the second embodiment.

[0140] The resistive layer 50 is, for example, a chalcogenide. The resistive layer 50 includes, for example, germanium (Ge), antimony (Sb), and tellurium (Te).

[0141] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0142] By applying a voltage to the resistive layer 50, the resistive layer 50 changes from a high-resistance state to a low-resistance state, or from a low-resistance state to a high-resistance state. The application of voltage to the resistive layer 50 causes the resistive layer 50 to transition between a crystalline state and an amorphous state. For example, the crystalline state becomes the low-resistance state of the memory cell MC, and the amorphous state becomes the high-resistance state of the memory cell MC.

[0143] For example, a high-resistance state is defined as data "1," and a low-resistance state as data "0." The memory cell MC can then store 1-bit data, either "0" or "1."

[0144] The current-voltage characteristics of the memory device of the third embodiment are similar to, for example, the current-voltage characteristics of the memory device of the second embodiment shown in Figure 7.

[0145] As described above, according to the third embodiment, a memory device is realized that has a switching element with excellent characteristics, stable operating characteristics, reduced power consumption, and improved reliability.

[0146] (Fourth embodiment) The memory device of the fourth embodiment includes a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer, and comprises a memory cell whose electrical resistance changes when a predetermined voltage is applied, and which can take on a low-resistance state and a high-resistance state in which the electrical resistance is higher than that of the low-resistance state. The memory layer contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride. At least one of the first conductive layer and the second conductive layer contains at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite. When the memory cell is in a low-resistance state and a voltage is applied between the first conductive layer and the second conductive layer, the current-voltage characteristics are observed such that as the absolute value of the voltage is increased, the current rises at a first threshold voltage, and as the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, the current-voltage characteristics are observed such that the current falls at a first voltage with an absolute value smaller than the first threshold voltage.

[0147] Furthermore, the storage device of the fourth embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0148] The storage device of the fourth embodiment differs from the storage device of the first embodiment in that the memory cell does not include a third conductive layer and a resistive switching layer, and instead includes a memory layer with a configuration similar to the switching layer of the first embodiment. The following description will omit some parts that overlap with the first embodiment.

[0149] Figure 11 is a schematic cross-sectional view of a memory cell of a storage device according to the fourth embodiment. Figure 11 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0150] As shown in Figure 11, the memory cell MC comprises a lower electrode 10, an upper electrode 20, and a memory layer 60.

[0151] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0152] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function to store information.

[0153] The memory layer 60 has the same configuration as the switching layer 40 in the first embodiment.

[0154] The configuration of the lower electrode 10 and the upper electrode 20 is the same as that of the lower electrode 10 and the intermediate electrode 30 of the storage device in the first embodiment.

[0155] The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. Furthermore, the memory layer 60 has a characteristic in which the threshold voltage changes when a predetermined voltage is applied. The memory layer 60 also has a characteristic in which the electrical resistance changes when a predetermined voltage is applied.

[0156] The memory layer 60 has a function to suppress the increase in leakage current flowing to non-selected cells. Furthermore, the memory layer 60 has a function to store data by changing resistance. The memory layer 60 alone realizes both the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment.

[0157] At least one of the lower electrode 10 and the intermediate electrode 30 contains at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite.

[0158] Figure 12 is an explanatory diagram of the current-voltage characteristics of the memory device according to the fourth embodiment. Figure 12 corresponds to Figure 7 of the second embodiment.

[0159] In Figure 12, the solid line shows the current-voltage characteristics when the memory cell MC is in a low-resistance state. The dotted line in Figure 12 shows the current-voltage characteristics when the memory cell MC is in a high-resistance state. In Figure 12, the arrows along the current-voltage characteristics indicate the direction of the voltage sweep.

[0160] First, we will explain the current-voltage characteristics when the memory cell MC is in a low-resistance state. As the applied voltage is increased, the current rises at a first threshold voltage (Vth1 in Figure 12), exhibiting a nonlinear current-voltage characteristic. Subsequently, as the voltage is decreased from a voltage exceeding the first threshold voltage Vth1 (Vx in Figure 12), the current falls at a first voltage lower than the first threshold voltage (V1 in Figure 12). In other words, when the memory cell MC is in a low-resistance state, the current-voltage characteristics of the memory cell MC exhibit hysteresis. The first voltage V1 is, for example, between 0.1 and 0.9 times the first threshold voltage Vth1.

[0161] Next, we will explain the current-voltage characteristics when the memory cell MC is in a high-resistance state. As the applied voltage is increased, the current rises at a second threshold voltage (Vth2 in Figure 12), exhibiting a nonlinear current-voltage characteristic. Subsequently, as the voltage is decreased from a voltage exceeding the second threshold voltage Vth2 (Vx in Figure 12), the current falls at a second voltage lower than the second threshold voltage Vth2 (V2 in Figure 12). In other words, when the memory cell MC is in a high-resistance state, the current-voltage characteristics of the memory cell MC exhibit hysteresis. The second voltage V2 is, for example, between 0.1 and 0.9 times the second threshold voltage Vth2.

[0162] The second threshold voltage Vth2 is, for example, greater than the first threshold voltage Vth1. Also, the second voltage V2 is, for example, of about the same magnitude as the first voltage V1.

[0163] For example, a high-resistance state in a memory cell (MC) is defined as data "1," and a low-resistance state as data "0." By maintaining different resistance states, the memory cell (MC) can store 1-bit data, either "0" or "1."

[0164] When reading data from a memory cell MC, for example, the voltage between a first threshold voltage Vth1 and a second threshold voltage Vth2 is set as the read voltage Vread. If the memory cell MC is in a low-resistance state, a first read current Iread1 flows. If the memory cell MC is in a high-resistance state, a second read current Iread2 flows. The first read current Iread1 is greater than the second read current Iread2. By detecting the magnitude of the read current when the read voltage Vread is applied to the memory cell MC, it is possible to determine the data written to the memory cell MC.

[0165] According to the fourth embodiment, a storage device is realized that, similar to the first and second embodiments, has stable operating characteristics, reduced power consumption, and improved reliability.

[0166] (modified version) The modified memory device of the fourth embodiment differs from the memory device of the fourth embodiment in that the memory cell further includes a current suppression layer comprising at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride. Hereafter, some descriptions that overlap with the fourth embodiment may be omitted.

[0167] Figure 13 is a schematic cross-sectional view of a memory cell of a modified memory device according to the fourth embodiment. Figure 13 corresponds to Figure 11 of the fourth embodiment.

[0168] As shown in Figure 13, the memory cell MC comprises a lower electrode 10, an upper electrode 20, a memory layer 60, and a current suppression layer 70.

[0169] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0170] The current suppression layer 70 is provided, for example, between the lower electrode 10 and the upper electrode 20. The current suppression layer 70 is provided, for example, between the memory layer 60 and the upper electrode 20, as shown in Figure 13.

[0171] Furthermore, the current suppression layer 70 is not limited to being located between the memory layer 60 and the upper electrode 20. For example, the current suppression layer 70 may be located between the lower electrode 10 and the memory layer 60. Alternatively, the current suppression layer 70 may be located on the side of the lower electrode 10 opposite to the memory layer 60, or on the side of the upper electrode 20 opposite to the memory layer 60. In addition, the current suppression layer 70 may be located at multiple positions.

[0172] The thickness of the current suppression layer 70 in the direction from the lower electrode 10 to the upper electrode 20 is, for example, 0.2 nm or more and 2 nm or less.

[0173] The current suppression layer 70 contains at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride.

[0174] In the modified memory device of the fourth embodiment, the current suppression layer 70 suppresses the flow of large currents to the memory cell MC. Therefore, for example, a memory device with high destruction resistance can be realized.

[0175] As described above, according to the fourth embodiment and its modifications, a memory device is realized that has a switching element with excellent characteristics, stable operating characteristics, reduced power consumption, and improved reliability.

[0176] In the first embodiment, a magnetoresistive memory was described as a two-terminal storage device; in the second embodiment, a resistive random-access memory was described as a two-terminal storage device; and in the third embodiment, a phase-change memory was described as a two-terminal storage device. However, the present invention can be applied to other two-terminal storage devices. For example, the present invention can be applied to ferroelectric random-access memory (FeRAM).

[0177] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0178] 10 Lower electrode (first conductive layer) 20 Upper electrode (second conductive layer) 30 Intermediate electrode (third conductive layer) 40 Switching Layer 50 Resistivity change layer 60 memory layers 70 Current suppression layer 102 Word line (first wiring) 103-bit line (second wiring) MC memory cell

Claims

1. A first conductive layer and A second conductive layer, A third conductive layer is provided between the first conductive layer and the second conductive layer, A switching layer provided between the first conductive layer and the third conductive layer, A memory cell is provided which includes a resistance-changing layer provided between the third conductive layer and the second conductive layer, wherein the electrical resistance changes when a predetermined voltage is applied, and the memory cell can take on a low-resistance state and a high-resistance state in which the electrical resistance is higher than that of the low-resistance state. The switching layer contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride. The conductive layer of the first conductive layer and the third conductive layer comprises at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite. A memory device in which, when the memory cell is in the low-resistance state, a voltage is applied between the first conductive layer and the second conductive layer, and as the absolute value of the voltage is increased, the memory device exhibits a nonlinear current-voltage characteristic in which the current rises at a first threshold voltage, and as the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, the memory device exhibits a current-voltage characteristic in which the current falls at a first voltage with an absolute value smaller than the first threshold voltage.

2. The storage device according to claim 1, wherein the switching layer includes a crystal of space group P63 / mmc, a crystal of space group Pnma62, or a crystal of space group P-1.

3. The memory device according to claim 1, wherein the thickness of the switching layer in the direction from the first conductive layer toward the second conductive layer is 0.5 nm or more and 50 nm or less.

4. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 1, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

5. The storage device according to claim 1, wherein the resistance change layer includes a magnetic tunnel junction.

6. The memory device according to claim 1, further comprising a current-suppressing layer containing at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride.

7. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 1, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

8. A first conductive layer and A second conductive layer, A switching layer provided between the first conductive layer and the second conductive layer, A memory cell comprising a resistance-changing layer provided between the switching layer and the second conductive layer, wherein the electrical resistance changes upon application of a predetermined voltage, and the memory cell can take on a low-resistance state and a high-resistance state in which the electrical resistance is higher than that of the low-resistance state. The switching layer contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride. The first conductive layer comprises at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite. A memory device in which, when the memory cell is in the low-resistance state, a voltage is applied between the first conductive layer and the second conductive layer, and as the absolute value of the voltage is increased, the memory device exhibits a nonlinear current-voltage characteristic in which the current rises at a first threshold voltage, and as the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, the memory device exhibits a current-voltage characteristic in which the current falls at a first voltage with an absolute value smaller than the first threshold voltage.

9. The storage device according to claim 8, wherein the switching layer includes a crystal of space group P63 / mmc, a crystal of space group Pnma62, or a crystal of space group P-1.

10. The memory device according to claim 8, wherein the thickness of the switching layer in the direction from the first conductive layer to the second conductive layer is 0.5 nm or more and 50 nm or less.

11. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 8, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

12. The storage device according to claim 8, wherein the resistance change layer includes a magnetic tunnel junction.

13. The memory device according to claim 8, further comprising a current-suppressing layer containing at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride.

14. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 8, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

15. A first conductive layer and A second conductive layer, A memory cell is provided, comprising: a memory layer provided between the first conductive layer and the second conductive layer, having the characteristic that the threshold voltage at which current rises changes when a predetermined voltage is applied; and capable of taking on a low-resistance state and a high-resistance state in which the electrical resistance is higher than that of the low-resistance state. The memory layer contains at least one first compound selected from the group consisting of molybdenum disulfide, molybdenum diselenium, molybdenum ditelluride, tungsten disulfide, tungsten diselenium, indium selenide, gallium sulfide, gallium selenide, gallium telluride, germanium sulfide, germanium selenide, germanium telluride, silicon sulfide, silicon selenide, silicon telluride, tin sulfide, tin selenide, tin telluride, rhenium disulfide, rhenium diselenium, and rhenium ditelluride. The conductive layer of the first conductive layer and the second conductive layer comprises at least one second compound selected from the group consisting of tungsten ditelluride, titanium disulfide, titanium diselenium, tantalum disulfide, tantalum diselenium, niobium disulfide, niobium diselenium, hafnium disulfide, and hafnium diselenium, graphene, or graphite. A memory device in which, when the memory cell is in the low-resistance state, a voltage is applied between the first conductive layer and the second conductive layer, and as the absolute value of the voltage is increased, the memory device exhibits a nonlinear current-voltage characteristic in which the current rises at a first threshold voltage, and as the absolute value of the voltage is decreased from a voltage exceeding the first threshold voltage, the memory device exhibits a current-voltage characteristic in which the current falls at a first voltage with an absolute value smaller than the first threshold voltage.

16. The memory device according to claim 15, wherein the memory layer includes a crystal of space group P63 / mmc, a crystal of space group Pnma62, or a crystal of space group P-1.

17. The memory device according to claim 15, wherein the thickness of the memory layer in the direction from the first conductive layer toward the second conductive layer is 0.5 nm or more and 50 nm or less.

18. The memory device according to claim 15, further comprising a current-suppressing layer containing at least one compound selected from the group consisting of aluminum oxide, boron nitride, silicon oxide, aluminum nitride, and silicon nitride.

19. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 15, wherein the memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

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