Performance improvement through cycling-aware adaptive program voltage tuning

Abstract

The present invention provides a memory device, a controller, and a method. [Solution] The memory device 100 includes one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuit includes a plurality of sense blocks SB1 to SBp and reads or programs pages of memory cells in parallel. The controller 122 is included in the same memory device as one or more memory dies (e.g., a removable storage card). Commands and data are transferred between the host 140 and the controller via a data bus 120 and between the controller and one or more memory dies via lines 118.

Description

[Technical Field]

[0001] This technology relates to the operation of memory devices. [Background technology]

[0002] Semiconductor memory devices or equipment are widely used in a variety of electronic devices, including laptops, digital audio players, digital cameras, mobile phones, video game consoles, scientific instruments, industrial robots, medical electronics, solid-state drives, automotive electronics, Internet of Things (IoT) devices, and Universal Serial Bus (USB) devices. Semiconductor memory includes both non-volatile and volatile memory. Non-volatile memory retains stored information without requiring an external power source. Examples of non-volatile memory include flash memory (e.g., NAND and NOR flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0003] A memory device can be coupled to one or more hosts, and one or more interfaces are used to access the memory device. In addition, memory devices are often managed by a controller, which, among several roles, is configured to interface between the host and the memory device.

[0004] To improve performance, some memory devices utilize device modes such as smart verification (SV) to reduce program time. Smart verification can improve the program speed during programming of subsequent strings by obtaining the acquired program voltage from a sampling string. However, program and erase cycles can cause performance degradation that is not fully accounted for by smart verification. Therefore, improved non-volatile memory devices and operating methods are needed. [Overview of the project]

[0005] This section provides a general overview of this disclosure and does not constitute a comprehensive disclosure of its entire scope or all of its features and benefits.

[0006] The purpose of this disclosure is to provide a memory device and a method for operating the memory device that address and overcome the above-mentioned shortcomings.

[0007] Accordingly, one aspect of the present disclosure is to provide a memory device including a memory cell connected to one of a plurality of word lines. The memory cell is located within a memory hole and is configured to hold a threshold voltage corresponding to one of a plurality of data states. The memory hole is organized into rows, which are grouped into a plurality of strings. The plurality of strings each include a plurality of blocks. A control means is configured to obtain a smart verification program voltage by programming a memory cell connected to one of the plurality of word lines and associated with one of the plurality of strings in a smart verification operation which includes a plurality of smart verification loops beginning with an initial program voltage, the initial program voltage being adjusted based on the cycling conditions of the memory cell. The control means is also configured to use the smart verification program voltage, based on the adjusted initial program voltage, to program at least some of the memory cells connected to the plurality of word lines in a program operation.

[0008] In another aspect of the present disclosure, a controller is also provided that communicates with a memory device including a memory cell connected to one of a plurality of word lines. The memory cell is located within a memory hole and is configured to hold a threshold voltage corresponding to one of a plurality of data states. The memory hole is organized into rows, which are grouped into a plurality of strings. The plurality of strings each include a plurality of blocks. The controller is configured to instruct the memory device to obtain a smart verification program voltage by programming a memory cell connected to one of the plurality of word lines and associated with one of the plurality of strings in a smart verification operation which includes a plurality of smart verification loops beginning with an initial program voltage, the initial program voltage being adjusted based on the cycling conditions of the memory cell. The controller is further configured to instruct the memory device to program at least some of the memory cells connected to the plurality of word lines in a program operation using the smart verification program voltage based on the adjusted initial program voltage.

[0009] An additional aspect of the present disclosure provides a method for operating a memory device. The memory device includes memory cells connected to one of a plurality of word lines. The memory cells are located within memory holes and are configured to hold threshold voltages corresponding to one of a plurality of data states. The memory holes are organized into rows, which are grouped into a plurality of strings. The plurality of strings each include a plurality of blocks. The method includes the step of obtaining a smart verification program voltage by programming a memory cell connected to one of the plurality of word lines and associated with one of the plurality of strings in a smart verification operation which includes a plurality of smart verification loops beginning with an initial program voltage, the initial program voltage being adjusted based on the cycling conditions of the memory cells. The method also includes the step of programming at least some of the memory cells connected to the plurality of word lines using the smart verification program voltage based on the adjusted initial program voltage in a program operation.

[0010] Further areas of applicability will become apparent from the descriptions provided herein. The descriptions and specific examples in this summary are for illustrative purposes only and do not limit the scope of this disclosure. [Brief explanation of the drawing]

[0011] The drawings described herein are for illustrative purposes only of selected embodiments and do not represent all possible implementations, nor are they intended to limit the scope of this disclosure. [Figure 1A] This is a block diagram of an exemplary memory device according to an aspect of the present disclosure. [Figure 1B] This is a block diagram of an exemplary control circuit comprising a programming circuit, a counting circuit, and a determination circuit according to an aspect of the present disclosure. [Figure 2] Figure 1A shows a block of memory cells in an exemplary two-dimensional configuration of the memory array according to an aspect of this disclosure. [Figure 3A] An exemplary cross-sectional view of a floating gate memory cell in a NAND string according to an aspect of this disclosure is shown. [Figure 3B] A cross-sectional view of the structure of Figure 3A along line 329 is shown according to an aspect of this disclosure. [Figure 4A] An exemplary cross-sectional view of a charge trap memory cell in a NAND string according to an aspect of this disclosure is shown. [Figure 4B] A cross-sectional view of the structure of Figure 4A along line 429 is shown according to an aspect of this disclosure. [Figure 5A] An exemplary block diagram of the sense block SB1 in Figure 1A, according to an aspect of this disclosure, is shown. [Figure 5B] Another exemplary block diagram of the sense block SB1 of Figure 1A, according to an aspect of this disclosure, is shown. [Figure 6A] This is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array shown in Figure 1A, according to an aspect of this disclosure. [Figure 6B] An exemplary cross-sectional view of one portion of the block in Figure 6A, according to an aspect of this disclosure, is shown. [Figure 6C] Shows a plot of the memory hole diameter in the stack of FIG. 6B according to an aspect of the present disclosure. [Figure 6D] Shows an enlarged view of region 622 of the stack of FIG. 6B according to an aspect of the present disclosure. [Figure 7A] Shows a top view of an exemplary word line layer WLL0 of the stack of FIG. 6B according to an aspect of the present disclosure. [Figure 7B] Shows a top view of an exemplary upper dielectric layer DL19 of the stack of FIG. 6B according to an aspect of the present disclosure. [Figure 8A] Shows exemplary NAND strings within sub-blocks SBa to SBd of FIG. 7A according to an aspect of the present disclosure. [Figure 8B] Shows another exemplary view of NAND strings within a sub-block according to an aspect of the present disclosure. [Figure 9] Shows the Vth distribution of memory cells in an exemplary one-pass programming operation using four data states according to an aspect of the present disclosure. [Figure 10] Shows the Vth distribution of memory cells in an exemplary one-pass programming operation having eight data states according to an aspect of the present disclosure. [Figure 11] Shows the Vth distribution of memory cells in an exemplary one-pass programming operation having sixteen data states according to an aspect of the present disclosure. [Figure 12] Is a flowchart of an exemplary programming operation in a memory device according to an aspect of the present disclosure. [Figure 13A] Shows a smart verification algorithm used for triple-level cell (TLC) programming for two different planes of an exemplary memory device according to an aspect of the present disclosure. [Figure 13B] Shows a smart verification algorithm used for triple-level cell (TLC) programming for two different planes of an exemplary memory device according to an aspect of the present disclosure. [Figure 14] Shows an exemplary smart verification operation utilizing word line skip smart verification according to an aspect of the present disclosure. [Figure 15A] This is a plot of threshold voltage distributions in a smart verification loop for exemplary smart verification operation using two different initial program voltage VPGMUs according to an aspect of the present disclosure. [Figure 15B] This is a plot of threshold voltage distributions in a smart verification loop for exemplary smart verification operation using two different initial program voltage VPGMUs according to an aspect of the present disclosure. [Figure 16] The present disclosure describes experimental steps performed to study the periodic behavior of the program time tPROG with respect to the initial program voltage VPGMU arising from the application word line due to smart verification (SV), according to an aspect of this disclosure. [Figure 17] This is a plot of program time tPROG versus various initial program voltage VPGMU offsets against -25 degrees Celsius, showing the results of experiments according to aspects of this disclosure in Figure 16. [Figure 18] An exemplary lookup table, according to an aspect of the present disclosure, includes a plurality of predetermined initial program voltage offsets for one of a plurality of cycling categories. [Figure 19] This is an example showing four blocks of memory cells identified as the same among multiple cycling categories, according to an aspect of this disclosure. [Figure 20] An example of an aspect of this disclosure in which three of the four blocks of a memory cell are identified as the same among multiple cycling categories, and one represents three of the four blocks of a different memory cell. [Figure 21] This disclosure presents two different examples of smart verification without using the cycling-dependent initial program voltage VPGMU tuning described herein (Smart Verification 1 and Smart Verification 2), and a comparison with an example of smart verification using cycling-dependent initial program voltage VPGMU adjustment. [Figure 22]A plot of program time tPROG for probing one of a plurality of strings (i.e., probing WL-STR) and then probing one of a plurality of word lines associated with the programmed word line, according to an aspect of the present disclosure. [Figure 23] A lookup table for static mode is shown, along with a smart verification loop count for the optimal initial program voltage VPGMU relationship that can be used for adaptive mode, according to aspects of this disclosure. [Figure 24] Steps of a method for operating a memory device according to an aspect of this disclosure are shown. [Figure 25] Steps of a method for operating a memory device according to an aspect of this disclosure are shown. [Figure 26] Steps of a method for operating a memory device according to an aspect of this disclosure are shown. [Figure 27] Steps of a method for operating a memory device according to an aspect of this disclosure are shown. [Figure 28] The present disclosure illustrates the steps of an exemplary process for obtaining the optimal initial program voltage (VPGMU) versus smart verification loop relationship.

[0012] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements disclosed in one embodiment are intended to be usefully utilized in other embodiments without specific description. [Modes for carrying out the invention]

[0013] The following description provides details to help you understand this disclosure. In some instances, certain circuits, structures, and techniques are not described or illustrated in detail to avoid obscuring this disclosure.

[0014] Generally, this disclosure relates to a type of non-volatile memory device well suited for use in many applications. The non-volatile memory devices and associated operating methods of this disclosure are described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are provided only to illustrate the concepts, features, advantages, and objectives of the invention with sufficient clarity to enable a person skilled in the art to understand and implement this disclosure. Specifically, the exemplary embodiments are provided so that this disclosure is complete and fully conveys its scope to a person skilled in the art. Numerous specific details, such as examples of specific components, devices, and methods, are described in order to provide a complete understanding of the embodiments of this disclosure. It will be apparent to a person skilled in the art that specific details are not required to be used, that the exemplary embodiments may be embodied in many different forms, and that none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

[0015] In some memory devices or apparatus, memory cells are joined to each other in NAND strings within a block or subblock. Each NAND string comprises several memory cells connected in series between one or more drain-side selected gate SG transistors (SGD transistors) on the drain side of the NAND string connected to bit lines and one or more source-side selected gate SG transistors (SGS transistors) on the source side of the NAND string connected to source lines. Furthermore, the memory cells may be arranged with common control gate lines (e.g., word lines) that function as control gates. The set of word lines extends from the source side of the block to the drain side of the block. Memory cells can also be connected in other types of strings and in other ways.

[0016] In a 3D memory structure, memory cells may be arranged in vertical strings within a stack, the stack comprising alternating conductive and dielectric layers. The conductive layers function as word lines connecting to the memory cells. The memory cells may include data memory cells that are qualified to store user data and dummy or non-data memory cells that are not qualified to store user data.

[0017] Before programming a particular non-volatile memory device, the memory cells are typically erased. In some devices, the erase operation removes electrons from the floating gate of the memory cell being erased, or from the charge trap layer.

[0018] Programming a set of memory cells typically involves applying a series of program voltages to the memory cells after they have been provided in an erased state. Each program voltage is provided in a program loop, also known as a program verification iteration. For example, the program voltage may be applied to a word line connected to the control gate of the memory cell. One approach is to perform incremental step pulse programming, where the program voltage is increased by the step size in each program loop. A verification operation may be performed after each program voltage to determine whether the memory cell has completed programming. Once programming for a memory cell is complete, it may be locked out from further programming while programming continues for other memory cells in subsequent program loops.

[0019] Each memory cell may be associated with a data state according to the write data in the program command. Based on that data state, the memory cell either remains in the erased state or is programmed to a different data state (a programmed data state). For example, a 2-bit memory device has four data states, including the erased state and three higher data states called A, B, and C data states (see Figure 9). A 3-bit memory device has eight data states, including the erased state and seven higher data states called A, B, C, D, E, F, and G data states (see Figure 10). A 4-bit memory device has sixteen data states, including the erased state and fifteen higher data states called Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see Figure 11).

[0020] When a program command is issued, the data to be written is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell should be programmed. Each programmed data state is associated with a verification voltage, and a memory cell with a given data state is considered to have completed programming when the sensing operation determines that its threshold voltage (Vth) is above the associated verification voltage. The sensing operation can determine whether a memory cell has a Vth above the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current flowing through the memory cell. A relatively high current indicates that the memory cell is in a conductive state and Vth is below the control gate voltage. A relatively low current indicates that the memory cell is in a non-conductive state such that Vth is above the control gate voltage.

[0021] The verification voltage used to determine that a memory cell has completed programming is sometimes called the final or lockout verification voltage. In some cases, an additional verification voltage can be used to determine that the memory cell is nearing completion of programming. This additional verification voltage is sometimes called the offset verification voltage and can be lower than the final verification voltage. When a memory cell is nearing completion of programming, the programming speed of the memory cell may be reduced, for example, by increasing the voltage of each bit line during one or more subsequent programming voltages. For example, in Figure 9, a memory cell to be programmed into the A data state can be tested for verification at VvAL, which is the offset verification voltage for the A data state, and VvA, which is the final verification voltage for the A data state. By slowing down the programming speed just before the memory cell completes programming, a narrower Vth distribution can be achieved.

[0022] Smart verification can improve the programming speed during programming of subsequent strings by shortening the program time tProg by obtaining a program voltage or smart verification program voltage VPGM_SV acquired from the sampling string. Referring to Figures 13A and 13B, during triple-level cell (TLC) programming, smart verification is performed on the sampling string (WLn string 0) to obtain the acquired VPGM_SV. The smart verification program voltage VPGM_SV is then used as the initial program voltage VPGM applied to the word line during programming for subsequent strings WLn string 1 / 2 / 3. However, the initial program voltage used to obtain the acquired program or smart verification program voltage may be fixed and not account for degradation due to program and erase cycles.

[0023] Figure 1A is a block diagram of an exemplary memory device or apparatus. The memory device 100 may include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2, ..., SBp (sense circuits) that enable parallel reading or programming of pages of memory cells. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via a line 118.

[0024] The memory structure may be 2D or 3D. The memory structure may comprise one or more arrays of memory cells, including a 3D array. The memory structure may include a monolithic 3D memory structure, in which multiple memory levels are formed on (but not in) a single substrate, such as a wafer, without an intervening substrate. The memory structure may include any type of non-volatile memory monolithically formed at one or more physical levels of an array of memory cells having active regions located on a silicon substrate. The memory structure may also be in a non-volatile memory device having circuits associated with the operation of the memory cells, and the associated circuits may be on or within the substrate.

[0025] The control circuit 110, in cooperation with the read / write circuit 128, performs memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. A storage area 113 may be provided for verifying parameters such as those described herein.

[0026] The on-chip address decoder 114 provides an address interface between the address used by the host or memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word and bit lines during memory operation. It may include drivers for the word lines, SGS and SGD transistors, and source lines. In one approach, the sense block may include a bit line driver. The SGS transistor is a selection gate transistor at the source end of the NAND string, and the SGD transistor is a selection gate transistor at the drain end of the NAND string.

[0027] In some implementations, some of the components can be combined. In various designs, one or more components other than the memory structure 126 (either individually or in combination) can be considered as at least one control circuit configured to perform the operations described herein. For example, the control circuit may include one or a combination of the following: control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sense blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0028] The control circuit may include a programming circuit configured to perform a programming operation on a set of memory cells, the set of memory cells including memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of a plurality of data states. The programming operation includes a plurality of program verification iterations, in which the programming circuit performs programming on one word line and then applies a verification signal to one word line. The control circuit may also include a counting circuit configured to obtain a count of memory cells that have passed the verification test for one data state. The control circuit may also include a determination circuit configured to determine a particular program verification iteration of a plurality of program verification iterations to perform a verification test on another data state for a memory cell assigned to represent another data state, based on the amount by which the count exceeds a threshold.

[0029] For example, Figure 1B is a block diagram of an exemplary control circuit 150 comprising a programming circuit 151, a counting circuit 152, and a determination circuit 153. The programming circuit may include, for example, software, firmware, and / or hardware that implement steps 1200 to 1220 in Figure 12.

[0030] The off-chip controller 122 may include a processor 122c, memory devices such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct some read errors caused when the upper tail of the Vth distribution becomes too high. However, there may be errors that cannot be corrected. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0031] The memory device contains code, such as an instruction set, and the processor is operable to execute the instruction set to provide the functions described herein. Alternatively or additionally, the processor may access code from the memory device 126a of a memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0032] For example, code may be used by the controller to access memory structures for programming, reading, and erasing operations. Code may include boot code and control code (e.g., instruction set). Boot code is software that initializes the controller during the boot or startup process and enables the controller to access memory structures. Code may be used by the controller to control one or more memory structures. When powered on, processor 122c fetches boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers for performing basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input / output ports.

[0033] In general, control codes may include instructions that perform the functions described herein, including steps in the flowcharts further described below, and that provide voltage waveforms, including those further described below.

[0034] In one embodiment, the host is a computing device (e.g., a laptop, desktop, smartphone, tablet, or digital camera) including one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, or solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0035] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0036] Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0037] Memory devices can be formed from any combination of passive and / or active elements. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching memory elements such as antifuse or phase change materials, and optionally steering elements such as diodes or transistors. As a further non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements with charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0038] Multiple memory elements can be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, flash memory devices with a NAND configuration (NAND memory) typically include memory elements connected in series. A NAND string is an example of a set of transistors connected in series, comprising memory cells and SG transistors.

[0039] A NAND memory array may be configured such that the array consists of multiple memory strings, each string comprising multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible (e.g., a NOR memory array). The NAND and NOR memory configurations are examples, and the memory elements may be configured in other ways.

[0040] Semiconductor memory elements arranged within and / or on a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0041] In a two-dimensional memory structure, semiconductor memory elements are arranged at the single-plane or single-memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed, either above or within it, or a carrier substrate to which the memory elements are attached after they have been formed. In non-limiting examples, the substrate may include semiconductors such as silicon.

[0042] Memory elements may be arranged at the single memory device level in an ordered array such as multiple rows and / or columns. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0043] A three-dimensional memory array is an array in which memory elements are arranged to occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, with the z direction substantially perpendicular to the main surface of the substrate and the x and y directions substantially parallel).

[0044] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main surface of the substrate, i.e., extending in the y-direction), each column having multiple memory elements. These columns may be arranged in a two-dimensional configuration, e.g., in the xy-plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertical stack memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0045] As a non-restrictive example, in a three-dimensional NAND memory array, memory elements may be coupled to each other to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled to each other to form a vertical NAND string traversing multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and other strings contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0046] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. Optionally, a monolithic three-dimensional memory array may also have at least one or more memory layers within a single substrate. In non-limiting examples, the substrate may include semiconductors such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, and intervening layers may exist between the memory device levels.

[0047] In this case as well, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0048] Related circuitry is typically required for the operation of memory elements and for communication with them. As a non-limiting example, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This related circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0049] Those skilled in the art will recognize that this art is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but covers all relevant memory structures within the spirit and scope of the art as described herein and understood by those skilled in the art.

[0050] Figure 2 shows a block of memory cells in an exemplary two-dimensional configuration of the memory array 126 of Figure 1A. The memory array can contain many blocks. Each exemplary block 200, 210 contains several NAND strings and their respective bit lines, e.g., BL0, BL1, and so on, which are shared between blocks. Each NAND string is connected at one end to a drain selection gate (SGD), and the control gate of the drain selection gate is connected via a common SGD line. The other end of the NAND strings is connected to a source selection gate, and the source selection gate is connected to a common source line 220. Sixteen word lines, e.g., WL0 to WL15, extend between the source selection gate and the drain selection gate. In some cases, dummy word lines that do not contain user data may be used in the memory array adjacent to the selection gate transistors. Such dummy word lines can shield the edge data word lines from certain edge effects.

[0051] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory. See Figures 3A and 3B. Other types of non-volatile memory can also be used. For example, a charge-trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to non-volatilely store charge. See Figures 4A and 4B. A triple-layer dielectric made of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate on the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a restricted region. This stored charge then causes a detectable change in the threshold voltage of a portion of the cell's channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration in which a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0052] Another approach uses NROM cells. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending across a channel between the source and drain diffusion regions. The charge of one data bit is localized in the dielectric layer adjacent to the drain, and the charge of the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0053] Figure 3A shows a cross-sectional view of an exemplary floating-gate memory cell within a NAND string. The bit line or NAND string direction is on the page, and the word line direction is from left to right. As an example, word line 324 extends across the NAND string, including the respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell is located within a different NAND string. A polyinterdielectric (IPD) layer 328 is also shown. The control gate is part of the word line. A cross-sectional view along line 329 is shown in Figure 3B.

[0054] The control gate encloses the floating gate, increasing the surface contact area between the control gate and the floating gate. This results in higher IPD capacitance and a higher coupling ratio, making programming and erasing easier. However, as NAND memory devices shrink, the spacing between adjacent cells decreases, and therefore there is little space for the control gate and IPD between two adjacent floating gates. As an alternative, flat or planar memory cells have been developed in which the control gate is flat or planar, as shown in Figures 4A and 4B. That is, it does not enclose the floating gate, and the only contact with the charge storage layer is from above. In this case, there is no advantage to having a high floating gate. Instead, the floating gate can be made very thin. Furthermore, charge can be stored using the floating gate, or the charge can be trapped using a thin charge trap layer. This approach can avoid the problem of ballistic electron transport, where electrons can move through the floating gate after tunneling through the tunnel oxide during programming.

[0055] Figure 3B shows a cross-sectional view of the structure of Figure 3A along line 329. The NAND string 330 includes an SGS transistor 331, exemplary memory cells 300, 333, ..., 334 and 335, and an SGD transistor 336. As an example of each memory cell, memory cell 300, consistent with Figure 3A, includes a control gate 302, an IPD layer 328, a floating gate 304, and a tunnel oxide layer 305. The passages in the IPD layers within the SGS and SGD transistors allow the control gate layer and the floating gate layer to communicate. For example, the control gate and floating gate layers may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer can be a stack of nitride (N) and oxide (O), such as in a non-non-on configuration.

[0056] A NAND string can be formed on a substrate comprising a p-type substrate region 355, an n-type well 356, and a p-type well 357. The p-type wells have n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7. A channel voltage Vch can be applied directly to the channel region of the substrate.

[0057] Figure 4A shows a cross-sectional view of an exemplary charge-trapped memory cell within a NAND string. This figure is a word-line oriented view of a memory cell, including a flat control gate and charge-trap region, as a 2D example of a memory cell in the memory cell array 126 of Figure 1A. Charge-trapped memories can be used in NOR and NAND flash memory devices. This technique uses an insulator, such as a SiN film, to store electrons, in contrast to floating-gate MOSFET technology, which uses a conductor, such as doped polycrystalline silicon, to store electrons. As an example, a word line (WL) 424 extends across the NAND string, including the respective channel regions 406, 416, and 426. Part of the word line provides the control gates 402, 412, and 422. Below the word line are the IPD layer 428, charge-trap layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunnel layers 409, 407, and 408. Each charge trap layer extends continuously within its respective NAND string.

[0058] Memory cell 400 includes a control gate 402, a charge trap layer 404, a polysilicon layer 405, and a portion of the channel region 406. Memory cell 410 includes a control gate 412, a charge trap layer 414, a polysilicon layer 415, and a portion of the channel region 416. Memory cell 420 includes a control gate 422, a charge trap layer 421, a polysilicon layer 425, and a portion of the channel region 426.

[0059] Here, a flat control gate is used instead of a control gate that encloses a floating gate. One advantage is that the charge trap layer can be thinner than with a floating gate. In addition, the memory cells can be placed closer to each other.

[0060] Figure 4B shows a cross-sectional view of the structure of Figure 4A along line 429. This figure shows a NAND string 430 having a flat control gate and charge trap layer. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ..., 434 and 435, and an SGD transistor 435.

[0061] A NAND string can be formed on a substrate comprising a p-type substrate region 455, an n-type well 456, and a p-type well 457. The p-type well 457 has n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 formed therein. The channel voltage Vch can be applied directly to the channel region of the substrate. The memory cell 400 includes a charge trap layer 404, a polysilicon layer 405, a tunnel layer 409, and control gates 402 and an IPD layer 428 on top of the channel region 406.

[0062] For example, the control gate layer may be polysilicon, and the tunnel layer may be silicon oxide. The IPD layer can be a stack of high-k dielectrics such as AlOx or HfOx, which helps to increase the coupling ratio between the control gate layer and the charge trap or charge storage layer. The charge trap layer may be, for example, a mixture of silicon nitride and oxide.

[0063] SGD and SGS transistors have the same configuration as memory cells but have longer channel lengths to ensure that current is interrupted in prohibited NAND strings.

[0064] In this example, layers 404, 405, and 409 extend continuously within the NAND string. Alternatively, portions of layers 404, 405, and 409 between control gates 402, 412, and 422 can be removed to expose the top surface of channel 406.

[0065] Figure 5A shows an exemplary block diagram of sense block SB1 of Figure 1A. In one approach, the sense block comprises multiple sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different subsets of bit lines may be sensed using different sense blocks. This allows the processing load associated with the sense circuits to be divided and processed by each processor within each sense block. For example, a sense circuit controller 560 in SB1 can communicate with a set of sense circuits and latches. The sense circuit controller may include a precharge circuit 561 that supplies voltage to each sense circuit to set the precharge voltage. In one possible approach, the voltage is provided independently to each sense circuit, for example, via a database 503 and a local bus such as LBUS1 or LBUS2 in Figure 5B. In another possible approach, a common voltage is supplied simultaneously to each sense circuit, for example, via line 505 in Figure 5B. The sense circuit controller may also include memory 562 and a processor 563. As also mentioned with respect to Figure 2, memory 562 can store code executable by the processor to perform the functions described herein. These functions may include reading latches associated with the sense circuits, setting bit values ​​in the latches, and supplying voltages to set precharge levels in the sense nodes of the sense circuits. Further exemplary details of the sense circuit controller and the sense circuits 550a and 551a are provided below.

[0066] Figure 5B shows another exemplary block diagram of the sense block SB1 of Figure 1A. The sense circuit controller 560 communicates with several sense circuits, including exemplary sense circuits 550a and 551a, also shown in Figure 5A. Sense circuit 550a includes a latch 550b, which includes a trip latch 526, an offset verification latch 527, and a data state latch 528. The sense circuit further includes a voltage clamp 521, such as a transistor, which sets the precharge voltage at the sense node 522. A switch 523 from the sense node to the bit line (BL) selectively allows the sense node to communicate with the bit line 525, for example, by electrically connecting the sense node to the bit line so that the sense node voltage can be attenuated. The bit line 525 is connected to one or more memory cells, such as memory cell MC1. A voltage clamp 524 can set the voltage on the bit line, such as during sensing operation or program voltage. A local bus LBUS1 allows the sense circuit controller to communicate with components within the sense circuits, such as the latch 550b and the voltage clamp, if applicable. To communicate with the sense circuit 550a, the sense circuit controller supplies voltage to transistor 504 via line 502, connecting LBUS1 to the data bus DBUS503. Communication may include sending data to the sense circuit and / or receiving data from the sense circuit.

[0067] The sense circuit controller can communicate with different sense circuits, for example, using a time-division multiplexing scheme. Line 505 can be connected to the voltage clamp in each sense circuit in one approach.

[0068] The sense circuit 551a includes latches 551b, which include a trip latch 546, an offset verification latch 547, and a data state latch 548. A voltage clamp 541 may be used to set the precharge voltage at the sense node 542. A switch 543 from the sense node to the bit line (BL) selectively allows the sense node to communicate with the bit line 545, and a voltage clamp 544 can set the voltage on the bit line. The bit line 545 is connected to one or more memory cells, such as the memory cell MC2. The local bus LBUS2 allows the sense circuit controller to communicate with components in the sense circuit, such as the latches 551b and the voltage clamps, if applicable. To communicate with the sense circuit 551a, the sense circuit controller connects LBUS2 to the DBUS by supplying voltage to transistor 506 via line 501.

[0069] The sense circuit 550a may be a first sense circuit equipped with a first trip latch 526, and the sense circuit 551a may be a second sense circuit equipped with a second trip latch 546.

[0070] Sense circuit 550a is an example of a first sense circuit comprising a first sense node 522, the first sense circuit being associated with a first memory cell MC1 and a first bit line 525. Sense circuit 551a is an example of a second sense circuit comprising a second sense node 542, the second sense circuit being associated with a second memory cell MC2 and a second bit line 545.

[0071] Figure 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of Figure 1A. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 604 having circuits used by the blocks. For example, the circuits may include voltage drivers 605 that can be connected to the control gate layers of the blocks. In one approach, control gate layers at a common height within the blocks are driven in common. The substrate 601 can also carry circuits beneath the blocks, along with one or more lower metal layers patterned into conductive paths for carrying the signals of the circuits. The blocks are formed in the intermediate region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned into conductive paths for carrying the signals of the circuits. Each block contains a stack region of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block has opposing stepped sides with vertical contacts extending upward to the upper metal layer to form connections to the conductive paths. Four blocks are shown as an example, but two or more blocks extending in the x and / or y directions can be used.

[0072] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends into one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends into one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0073] Figure 6B shows an exemplary cross-sectional view of a portion of one of the blocks in Figure 6A. The block includes a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include data word line layers (word lines) WLL0 to WLL10, as well as two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, regions of the stack containing NAND strings NS1 and NS2 are shown. Each NAND string contains memory holes 618 or 619 filled with material that forms memory cells adjacent to the word line. Region 622 of the stack is shown in more detail in Figure 6D.

[0074] The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of the source line SL. NS1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack. Metal-filled slits 617 and 620 may be periodically provided across the stack as interconnections extending through the stack, such as for connecting the source line to a line above the stack. The slits may be used during the formation of the word line and then filled with metal. A portion of the bit line BL0 is also shown. A conductive via 621 connects the drain end 615 to BL0.

[0075] Figure 6C shows a plot of memory hole diameters in the stack of Figure 6B. The vertical axis is aligned with the stack of Figure 6B and shows the width (wMH), e.g., diameter, of memory holes 618 and 619. The word line layers WLL0 to WLL10 in Figure 6A are repeated as an example, at their respective heights z0 to z10 in the stack. In such memory devices, memory holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. The memory holes may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter gradually decreases from the top to the bottom of the memory hole; that is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the selected gate, so that the diameter widens slightly before gradually decreasing from the top to the bottom of the memory hole.

[0076] Due to the non-uniformity of memory hole widths, the programming speed, including the program gradient and erase speed of memory cells, can vary based on the location of the memory cells along the memory holes, for example, based on the height of the memory cells in the stack. Smaller memory hole diameters result in relatively stronger electric fields across the tunnel oxide, thus leading to relatively faster programming and erase speeds. One approach is to define groups of adjacent word lines with similar memory hole diameters (e.g., within a defined range of diameters) and apply an optimized verification scheme to each word line within the group. Different groups may have different optimized verification schemes.

[0077] Figure 6D shows an enlarged view of region 622 of the stack in Figure 6B. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 680, 681 are provided above the dummy memory cells 682, 683 and the data memory cell MC. Several layers can be deposited along the sidewalls (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., pillars formed by the material within the memory hole) may include a charge trap layer or film 663 such as SiN or other nitride, a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / blocking high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate. For example, control gates 690, 691, 692, 693, 694 are provided. In this example, all layers except the metal are provided within the memory hole. In other approaches, some of the layers may be within the control gate layer. Additional pillars may be formed similarly within different memory holes. The pillars can form columnar active regions (AAs) of the NAND string.

[0078] When a memory cell is programmed, electrons accumulate in a portion of the charge trap layer associated with the memory cell. These electrons are drawn from the channel through the tunnel layer into the charge trap layer. The Vth of the memory cell increases proportionally to the amount of accumulated charge. During the erase operation, the electrons return to the channel.

[0079] Each memory hole may be filled with multiple annular layers, including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each memory hole is filled with body material, and the multiple annular layers are located between the core region and the word line in each memory hole.

[0080] Since the channel length is not formed on the substrate, the NAND string can be considered to have a floating body channel. Furthermore, the NAND string is provided by multiple word line layers that are on top of each other in the stack and separated from each other by dielectric layers.

[0081] Figure 7A shows an exemplary top view of the word line layer WLL0 of the stack in Figure 6B. As described above, a 3D memory device can include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for the SG transistors and memory cells. The layer used for the SG transistors is the SG layer, and the layer used for the memory cells is the word line layer. Furthermore, memory holes are formed within the stack and filled with charge trapping material and channel material. As a result, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0082] A block BLK in a 3D memory device can be divided into subblocks, each containing a set of NAND strings with common SGD control lines. For example, refer to the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in subblocks SBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layers within a block can be regionized. Each region resides within its own subblock and can extend between slits periodically formed within the stack for processing the word line layers during the memory device manufacturing process. This processing may include replacing the sacrificial material of the word line layers with metal. Generally, the distance between slits should be relatively small, taking into account the limits of how far the etching solution can move laterally to remove the sacrificial material and how far the metal can move to fill the voids created by the removal of the sacrificial material. For example, the distance between slits may allow for several rows of memory holes between adjacent slits. The layout of memory holes and slits should also take into account the limit on the number of bit lines that can extend across a region while each bit line connects to a different memory cell. After processing the word line layer, the slits can be optionally filled with metal to provide interconnects through the stack.

[0083] This and other diagrams are not necessarily to scale. In reality, the area can be much longer in the x-direction than in the y-direction to accommodate additional memory holes.

[0084] In this example, there are four rows of memory holes between adjacent slits. Here, a row is a group of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are arranged in an alternating pattern to increase the density of memory holes. The word line layer or word line is divided into regions WLL0a, WLL0b, WLL0c, and WLL0d, each connected by a connector 713. One approach is to connect the last region of the word line layer in one block to the first region of the word line layer in the next block. The connector is connected to a voltage driver for the word line layer. Region WLL0a has exemplary memory holes 710 and 711 along line 712. Region WLL0b has exemplary memory holes 714 and 715. Region WLL0c has exemplary memory holes 716 and 717. Region WLL0d has exemplary memory holes 718 and 719. The memory holes are also shown in Figure 7B. Each memory hole can be part of its respective NAND string. For example, memory holes 710, 714, 716, and 718 may be part of NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, respectively.

[0085] Each circle represents a cross-section of a memory hole in the word line layer or SG layer. Illustrative circles shown with dashed lines represent memory cells provided by the material within the memory hole and the adjacent word line layer. For example, memory cells 720 and 721 are in WLL0a, memory cells 724 and 725 are in WLL0b, memory cells 726 and 727 are in WLL0c, and memory cells 728 and 729 are in WLL0d. These memory cells are at a common height in the stack.

[0086] Metal-filled slits 701, 702, 703, and 704 (e.g., metal interconnects) may be positioned adjacent to each other between the edges of regions WLL0a to WLL0d. The metal-filled slits provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line at the top of the stack, which in turn connects to a voltage driver in the peripheral region of the memory device. See also Figure 8A for further details of the subblocks SBa to SBd in Figure 7A.

[0087] Figure 7B shows a top view of the exemplary upper dielectric layer DL19 of the stack in Figure 6B. The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to its respective voltage driver. This allows a set of memory cells within one region of the word line layer to be programmed simultaneously, with each memory cell located within its respective NAND string connected to its respective bit line. A voltage can be set on each bit line to allow or prohibit programming during each program voltage.

[0088] Region DL19a has exemplary memory holes 710 and 711 along line 712a, which coincides with bit line BL0. Several bit lines extend above the memory holes and connect to them as indicated by the “X” symbol. BL0 connects to a set of memory holes including memory holes 711, 715, 717, and 719. In another example, bit line BL1 connects to a set of memory holes including memory holes 710, 714, 716, and 718. Metal-filled slits 701, 702, 703, and 704 from Figure 7A are also shown extending vertically through the stack. The bit lines may be numbered in the order BL0 to BL23 across the DL19 layer in the -x direction.

[0089] Different subsets of bit lines connect to cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 connect to cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 connect to cells in adjacent rows of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 connect to cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 connect to cells in adjacent rows of cells adjacent to the first row at the left edge.

[0090] Figure 8A shows an example of NAND strings within the subblocks SBa to SBd of Figure 7A. The subblocks correspond to the structure in Figure 6B. The conductive layers in the stack are shown on the left for reference. Each subblock contains multiple NAND strings, with one exemplary NAND string shown. For example, SBa contains the exemplary NAND string NS0_SBa, SbB contains the exemplary NAND string NS0_SbB, SBc contains the exemplary NAND string NS0_SBc, and SBd contains the exemplary NAND string NS0_SBd.

[0091] In addition, NS0_SBa includes SGS transistors 800 and 801, dummy memory cells 802 and 803, data memory cells 804, 805, 806, 807, 808, 809, 810, 811, 812, 813 and 814, dummy memory cells 815 and 816, and SGD transistors 817 and 818.

[0092] NS0_SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833 and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0093] NS0_SBc includes SGS transistors 840 and 841, dummy memory cells 842 and 843, data memory cells 844, 845, 846, 847, 848, 849, 850, 851, 852, 853 and 854, dummy memory cells 855 and 856, and SGD transistors 857 and 858.

[0094] NS0_SBd includes SGS transistors 860 and 861, dummy memory cells 862 and 863, data memory cells 864, 865, 866, 867, 868, 869, 870, 871, 872, 873 and 874, dummy memory cells 875 and 876, and SGD transistors 877 and 878.

[0095] Within a given height in a block, the sets of memory cells within each subblock are at a common height. For example, one set of memory cells (including memory cell 804) is among several memory cells formed along tapered memory holes in a stack of alternating conductive and dielectric layers. One set of memory cells is at a specific height z0 in the stack. Another set of memory cells (including memory cell 824) connected to one word line (WLL0) is also at a specific height. Alternatively, another set of memory cells (including memory cell 812) connected to another word line (e.g., WLL8) is at a different height (z8) in the stack.

[0096] Figure 8B shows another exemplary diagram of NAND strings within a subblock. The NAND strings include NS0_SBa, NS0_SbB, NS0_SBc, and NS0_SBd, which in this example have 48 word lines WL0 to WL47. Each subblock comprises a set of NAND strings that extend in the x-direction and have common SGD lines, e.g., SGD0, SGD1, SGD2, or SGD3. In this simplified example, there is only one SGD transistor and one SGS transistor within each NAND string. The NAND strings NS0_SBa, NS0_SbB, NS0_SBc, and NS0_SBd are located within subblocks SBa, SBb, SBc, and SBd, respectively. Furthermore, groups of word lines G0, G1, and G2 are shown as an example.

[0097] In particular, in three-dimensional memory layouts, layers may have different memory hole diameters, so the natural Vth distribution can vary for different word lines within a memory block. Therefore, it is advantageous to perform smart verification operations during programming to determine the optimal program voltage for any given word line and to avoid either under-programming or over-programming.

[0098] Figure 12 is a flowchart illustrating an example of programming operations in a memory device. Step 1200 initiates a programming operation for a set of word lines or at least one word line. Step 1202 initiates the programming operation for the page to be programmed (e.g., word line [WL]). n Select ) and set Vpgm to the specified initial program voltage (Vpgmint). In one example, Vpgmint is 14 volts (14V).

[0099] Step 1204 is WL in programming operation. n Applying Vpgm to at least some of the combined cells and performing validation tests on, for example, one or more data states during WL nExecute a program verification iteration that includes applying a verification signal (e.g., a voltage waveform). The cell WL to which the program verification iteration is applied n is preferably up to a predetermined checkpoint within WL n The predetermined checkpoint is preferably near the minimum state threshold voltage.

[0100] The determination step 1206 determines whether the acquisition of smart verification has been completed, for example, based on the result of the verification test in step 1204. The acquisition may be performed, for example, when all or almost all of the cells of the word line are programmed to a predetermined checkpoint within WLn. If the determination step 1206 is false, in step 1208, Vpgm is incrementally increased (i.e., stepped up) by a voltage step amount in the form of a predetermined delta program voltage (dVpgm), that is, Vpgm is set to Vpgm + dVpgm. In one example, dVpgm is 1 / 2 volt (0.5V). Next, the programming operation returns to step 1204 to perform the next program verification iteration. Each repetition of step 1204 until the determination step 1206 becomes true is one smart verification loop and requires resources from the controller.

[0101] If the determination step 1206 is true (the acquisition of smart verification has been completed), in step 1209, the remaining cells of WL n are programmed using the newly acquired Vpgm as the start program voltage and any known program verification sequence. Next, the determination step 1210 determines whether there is a next word line to be programmed. If the determination step 1210 is false (there is no additional word line to be programmed), the programming operation ends at step 1212. If the determination step 1210 is true, in step 1214, WL n [[ID=十六]]is incrementally advanced to the next word line to be programmed, that is, WL[[ID=十七]] n is set to WL n+1 is set.

[0102] Step 1216 is WL n A programming operation is performed which includes applying Vpgm to the Vpgm. The Vpgm applied in step 1216 is the Vpgm that was ultimately successful in step 1206, and therefore the Vpgm in step 1216 may be greater than or equal to Vpgmint.

[0103] The determination step 1218 determines whether there is another word line to program. If the determination step 1218 is false (there are no additional word lines to program), the programming operation ends in step 1212. If the determination step 1210 is true, in step 1220, WL n It is programmed to progress incrementally to the next word line (WL). n is WL n+1 Once set to (), Vpgm is reset to Vpgmint. The programming operation then returns to the program verification operation of step 1202. In an alternative embodiment, steps 1214, 1216, and 1218 may be repeated one or more times so that two or more word lines are programmed using Vpgm before returning to the program verification operation of step 1202.

[0104] The following table shows 10 example word lines (WL1~WL) 10 Figure 12 shows an exemplary plot illustrating the programming behavior applied to ).

[0105] [Table 1]

[0106] In the example above, the cumulative number of smart verification loops that must be completed to successfully program these 10 word lines is reduced compared to other known programming operations that utilize smart verification to minimize underprogramming and overprogramming. In other words, the programming operation optimizes the time to obtain the optimal programming voltage. Thus, both the overall performance and durability of the memory device are improved.

[0107] As mentioned above, smart verification can help reduce program time. Specifically, smart verification improves the program speed during programming of subsequent strings by obtaining an acquired program voltage or smart verification program voltage VPGM_SV from a sampling string. Figures 13A and 13B show smart verification algorithms used for triple-level cell (TLC) programming for two different planes of an exemplary memory device. In Figure 13A, the smart verification program voltage VPGM_SV for plane 0 WLn str0 is obtained in three smart verification loops. In Figure 13B, the smart verification program voltage VPGM_SV for plane 1 WLn str0 is obtained in four smart verification loops. During TLC programming, smart verification is performed on the sampling string (WLn string 0) and the smart verification program voltage VPGM_SV is obtained. The obtained smart verification program voltage VPGM_SV is then used as the initial program voltage VPGM for several subsequent strings (WLn string 1 / 2 / 3). In multiplane mode, smart verification can employ the minimum smart verification program voltage VPGM_SV obtained (based on the minimum number of smart verification loops). Furthermore, the program time tProg (i.e., the time required for program operation) can be further reduced by using word line skip smart verification mode. Figure 14 shows an exemplary smart verification operation utilizing word line skip smart verification. As shown, smart verification is performed on WL2n string 0, and the resulting smart verification program voltage VPGM_SV is applied to WL2n strings 1 / 2 / 3 and W2n+1 strings 0 / 1 / 2 / 3. Furthermore, to further reduce the program time tProg, smart verification on WL4n string 0 can also be used, which is used on WL4n strings 1 / 2 / 3 and WL4n+1 / 2 / 3 strings 0 / 1 / 2 / 3.

[0108] Referring back to FIGS. 13A and 13B, one exemplary smart verification operation for plane 0 WLn str0 and plane 1 WLn str0 is shown. In this example, plane 0 obtains the smart verification program voltage VPGM_SV_PB0 with 3 SV loops, and the plane 1 smart verification program voltage VPGM_SV_PB1 is obtained with 4 SV loops (VPGM_SV_PB0 < VPGM_SV_PB1). In single plane mode, the smart verification program voltage VPGM_SV_PB0 and the smart verification program voltage VPGM_SV_PB1 are adopted as the start program voltage VPGM for plane 0 WLn str1 / 2 / 3 and plane 1 WLn str1 / 2 / 3, respectively. For multi-plane mode with one smart verification algorithm, the smart verification is first performed independently for each plane WLn str0, and then, to avoid over-programming, the minimum smart verification program voltage VPGM_SV obtained (based on the minimum SV loop on each plane) is adopted as the final start program voltage VPGM for subsequent strings. Thus, the minimum smart verification program voltage VPGM_SV can be applied to both plane 0 and plane 1 under multi-plane operation.

[0109] As described above, the initial program voltage used to acquire the acquired program or smart verification program voltage (e.g., the initial program voltage (Vpgmint) described with reference to Figure 12 above, VPGMU in Figures 13A and 13B) is fixed and does not need to be considered for degradation due to program and erase cycles. More specifically, with a fixed program voltage (VPGM or VPGMU) for the smart verification (SV) acquired word line, program performance degrades significantly through cycling due to the phase shift of the program time tPROG relative to the initial program voltage VPGMU due to cycling from the application word line. Figures 15A and 15B are plots of the threshold voltage distribution in the smart verification loop of an exemplary smart verification operation using two different initial program voltages VPGMU (VPGMU' in Figure 15B is slightly smaller than VPGMU in Figure 15A). As shown in Figure 15A, a lower program voltage VPGM can result in a longer program time tPROG for the application word line. Similarly, as shown in Figure 15B, a higher program voltage VPGM can result in a shorter program time tPROG for the application word line. Figure 16 shows the steps of an experiment performed to study the periodic behavior of program time tPROG with respect to the initial program voltage VPGMU arising from application word lines due to smart verification (SV). The experiment was conducted to investigate ways to improve program time tPROG. For each memory device or apparatus in the experiment, 40 blocks (12 edge / 16 intermediate / 12 inside), and all word lines and strings for each block, pass through the process shown in Figure 16. Program time tPROG is measured at fresh, early life (BOL) (0.3K erase / program (E / P) cycles), mid-life (MOL) (1.5KE / P cycles), and end-of-life (EOL) (3.0KE / P cycles). Figure 17 is a plot of program time tPROG versus various initial program voltage VPGMU offsets against -25 degrees Celsius, showing the results of the experiment in Figure 16.As shown, a periodic program time tPROG is observed with respect to the initial program voltage VPGMU. The variation in program time tPROG due to the initial program voltage VPGMU is most pronounced at low temperatures (e.g., -25 degrees Celsius). Therefore, a finer-grained optimal opportunity exists for the periodic program time tPROG with respect to the initial program voltage VPGMU. Through cycling, the periodic program time tPROG with respect to the initial program voltage VPGMU at all temperatures consistently shifts towards lower initial program voltage VPGMU (faster program speeds with cycling for typical bits) and higher program time tPROG (slower program speeds with a wider natural threshold voltage Vt distribution and cycling for slower bits) (in the direction of the arrows below the plot). Tuning the cycling-dependent initial program voltage VPGMU is desirable, as it can reduce the degradation of program time tPROG caused by cycling (e.g., degradation from fresh to EOL at room temperature). It can also be demonstrated that the same optimal initial program voltage VPGMU exists for a given cycling condition across all measured blocks, or at least across blocks within the same block zone (inner / middle / edge). Furthermore, the same cycling dependence of program time tPROG on the initial program voltage VPGMU valley shift is observed across all word lines.

[0110] Accordingly, this specification describes a memory device (e.g., memory device 100 in Figure 1A) that includes a memory cell (e.g., data memory cell MC in Figure 6D) connected to one of a plurality of word lines (e.g., data word line layer (word line)), (WLL0-WLL10 in Figure 6B or WLL10 in Figure 6D). The memory cell is located within a memory hole (e.g., memory holes 618 and 619 in Figure 6B) and is configured to hold a threshold voltage Vt or Vth corresponding to one of a plurality of memory or data states (Figures 9-11). The memory holes are organized into rows grouped into a plurality of strings (e.g., subblocks SBa-SBd in Figure 7A). Each of the plurality of strings includes a plurality of blocks (e.g., blocks BLK0, BLK1, BLK2, BLK3 in Figure 6A). The memory device also includes one or any combination of control circuits or means (e.g., control circuit 110, decoder 124 / 132, sense blocks SB1, SB2, ..., SBp, read / write circuit 128, controller 122 in Figure 1A, control circuit 150 in Figure 1B, and / or sense circuit controller 560 in Figure 5A). The control means is connected to one of a plurality of word lines and configured to acquire the smart verification program voltage (e.g., Vpgm newly acquired as the start program voltage in step 1209 of Figure 12 above) by programming a memory cell associated with one of a plurality of strings in a smart verification operation which includes a plurality of smart verification loops starting with an initial program voltage VPGMU (e.g., the initial program voltage (Vpgmint) described with reference to Figure 12 above or VPGMU in Figures 13A and 13B). The initial program voltage VPGMU is adjusted based on the cycling conditions of the memory cell. The control means is also configured to program at least some of the memory cells connected to multiple word lines in the programmed operation using a smart verification programmed voltage based on a regulated initial programmed voltage VPGMU.The purpose of adjusting the initial program voltage VPGMU in this way is to minimize the degradation of program performance through cycling due to the phase shift between the program time tPROG and the initial program voltage VPGMU caused by cycling, by applying a program voltage that is adapted to the cycling conditions.

[0111] As explained above, multiple blocks may comprise multiple planes. Therefore, the programming operation may be a multiplane programming operation. The cycling conditions for each of the multiple blocks can be classified into multiple cycling categories, including, in increasing amounts of program and erase cycles for the memory cells of one of the multiple blocks, a fresh block in which the memory cells of one of the multiple blocks have not been programmed and erased; an early-life (BOL) block in which the memory cells of one of the multiple blocks have been programmed and erased less than a first predetermined amount (e.g., 300 erase / program (E / P) cycles); a mid-life (MOL) block in which the memory cells of one of the multiple blocks have been programmed and erased less than a second predetermined amount (e.g., 1500 erase / program (E / P) cycles); and an end-of-life (EOL) block in which the memory cells of one of the multiple blocks have been programmed and erased less than a third predetermined amount (e.g., 3000 erase / program (E / P) cycles). Accordingly, according to one aspect of the “static mode”, the control means is further configured to identify one of a plurality of cycling categories for one of a plurality of blocks in each of a plurality of planes programmed in multiplane programming operation. The control means is further configured to select one of a plurality of predetermined initial program voltage offsets based on one of a plurality of cycling categories identified for one of the plurality of blocks, which minimizes the change in program time caused by one of a plurality of predetermined initial program voltage offsets, and to adjust the initial program voltage VPGMU using one of a plurality of predetermined initial program voltage offsets. Figure 18 is an exemplary lookup table containing a plurality of predetermined initial program voltage offsets for one of a plurality of cycling categories. Such a lookup table may be used to determine the initial program voltage VPGMU offset based on the change in program time ΔtPROG(μs) compared with fresh with 0 DAC offset.It should be understood that a finer cycling category is intended instead of Fresh / BOL / MOL / EOL. Figure 19 is an example showing four blocks of memory cells identified as the same among multiple cycling categories. In other words, all four blocks programmed simultaneously are MOL, and according to the lookup table in Figure 18, the initial program voltage VPGMU should be set to a -2 DAC offset. By assuming the same cycling conditions for all blocks programmed, cycling-dependent initial program voltage VPGMU tuning selects an initial program voltage VPGMU DAC offset that yields the shortest program time tPROG corresponding to the cycling conditions. The lookup table can be predetermined through memory wafer-level characterization, for example, by being stored on the NAND chip or specified in the system firmware. Therefore, in static mode, cycling-dependent initial program voltage VPGMU tuning can be performed according to a predetermined lookup table, for example, by selecting an initial program voltage VPGMU DAC offset that yields the shortest program time tPROG corresponding to the cycling conditions (fresh / BOL / MOL / EOL) from most blocks (at least two planes in the case of 4 planes) during multiplane programming. Such an approach works because, for wear leveling, in a typical use case, all or most of the blocks being programmed simultaneously should have the same cycling conditions. In many memory devices, the cycling conditions for each block are readily available from a system perspective and can be used to set the initial program voltage VPGMU accordingly.

[0112] In the rare case of a 2:2 cycling condition for blocks (assuming four planes), the memory device can select an initial program voltage VPGMU that provides the minimum average program time tPROG increase. Figure 20 shows an example where three of the four blocks of the memory cell are identified as the same of the multiple cycling categories, and one is different. Thus, in more detail, according to a further aspect for static modes, the control means is further configured to identify one of the multiple cycling categories for one of the multiple blocks in each of the multiple planes being programmed in multiplane programming operation. Furthermore, the control means is configured to determine whether half of the total number of multiple blocks are identified as the first cycling category of the multiple cycling categories, and the remainder of the total number of multiple blocks are identified as the second cycling category of the multiple cycling categories (e.g., 2:2 for four planes). The control means is further configured to select one of a plurality of predetermined initial program voltage offsets that minimizes the change in program time due to one of a plurality of predetermined initial program voltage offsets relative to the average of one of the plurality of cycling categories identified for one of the plurality of blocks, based on one of a plurality of cycling categories identified for one of the plurality of blocks, and to adjust the initial program voltage VPGMU using one of the predetermined initial program voltage offsets in response to determining that half of the total number of blocks are identified as a first cycling category among the plurality of cycling categories and the remainder of the total number of blocks are identified as a second cycling category among the plurality of cycling categories.The control means is also configured to select one of a plurality of predetermined initial program voltage offsets that minimizes the change in program time for most of the blocks based on one of a plurality of cycling categories identified for one of the plurality of blocks, and to adjust the initial program voltage VPGMU using one of the plurality of predetermined initial program voltage offsets in response to not determining that half of the total number of blocks are identified as the first cycling category of the plurality of cycling categories and the remainder of the total number of blocks are identified as the second cycling category of the plurality of cycling categories. Thus, in the example of Figure 20, assuming that one BOL block and three MOL blocks are programmed simultaneously, the initial program voltage VPGMU should be set to a -2 DAC offset.

[0113] Through cycling, the programming speed for a typical bit becomes faster, which results in fewer smart verification loops for acquired word lines and a lower optimal initial program voltage VPGMU for application word lines, in terms of program time tPROG. Therefore, it is reasonable to assume a positive correlation between the number of smart verification loops and the optimal initial program voltage VPGMU. Thus, according to another embodiment, for one option of the "adaptive mode", "Option 1", the control means is further configured to identify the number of probing smart verification loops among the multiple smart verification loops required to complete programming of the memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed during smart verification operation. The control means identifies the optimal initial program voltage VPGMU for each of the multiple blocks being programmed according to a predetermined optimal initial program voltage VPGMU and smart verification loop relationships taking cycling conditions into account. The control means is also configured to select one of a plurality of predetermined initial program voltage offsets (e.g., using a lookup table) based on the optimal initial program voltage VPGMU for each of the plurality of blocks identified for one of the plurality of blocks that is closest to the average of the optimal initial program voltage VPGMU for all of the plurality of blocks being programmed, and to adjust the initial program voltage VPGMU using one of the plurality of predetermined initial program voltage offsets. Thus, in adaptive mode, the smart verification (SV) loop count of one early SV acquisition ("probing") word line and string WL-STR (e.g., WL 4-STR 0) from the programmed block is used to dynamically adjust the initial program voltage VPGMU according to a pre-characterized optimal initial program voltage VPGMU vs smart verification loop count relationship. The program voltage delta or step size DVPGM for that particular smart verification acquisition word line and string WL-STR needs to be reasonably small to provide sufficient resolution.The incorporation of loop count information may already be done for other aspects of programming in some memory devices. Alternatively, applying a customized program voltage step size DVPGM to specific acquisition word lines and strings WL-STR is feasible from both a design and system perspective. A lookup table mapping smart verification loop counts to the optimal initial program voltage VPGMU may be stored on-chip (e.g., in a ROM fuse) or specified within the system firmware.

[0114] The program operation can begin by programming the memory cell of a first word line among a plurality of word lines, continue by programming the memory cells of other word lines among the plurality of word lines, and end by programming the memory cell of the last word line among the plurality of word lines. Thus, according to one embodiment, the word line to be probed among the plurality of word lines is selected as one of the plurality of word lines that includes or is within a predetermined probing word line limit of the first word line among the plurality of word lines (for example, relatively close to the first word line among the plurality of word lines).

[0115] In another embodiment, the cycling condition may include write-erase cycle counts of program and erase cycles previously experienced by a memory cell among multiple blocks. Thus, in "Option 2," another option of the adaptive mode, the control means may be further configured to identify write-erase cycle counts for each of the multiple blocks being programmed. In addition, the control means is configured to determine whether the write-erase cycle count for any one of the multiple blocks is equal to a predetermined write-erase cycle checkpoint threshold (e.g., every 100 cycles). The control means is also configured, in response to determining that the write-erase cycle count for any one of the multiple blocks is not equal to a predetermined write-erase cycle checkpoint threshold, to continue using the smart verification program voltage at a predetermined write-erase cycle checkpoint threshold previously used. In response to determining that the write-erase cycle count for any one of the multiple blocks is equal to a predetermined write-erase cycle checkpoint threshold, the control means may be further configured, during smart verification operation, to identify the probing smart verification loop count among multiple smart verification loops necessary to complete programming of a memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed. The control means also identifies an optimal initial program voltage VPGMU for each of the multiple blocks being programmed, according to a predetermined optimal initial program voltage VPGMU and a smart verification loop relationship that takes cycling conditions into account. The control means is also configured to select one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage VPGMU for each of the multiple blocks identified for the block whose average is closest to the optimal initial program voltage VPGMU for all of the multiple blocks being programmed, and to adjust the initial program voltage VPGMU using one of the plurality of predetermined initial program voltage offsets.Therefore, in adaptive mode, adaptive initial program voltage VPGMU tuning is performed according to the optimal initial program voltage VPGMU vs. smart-verified SV loop count relationship by using the smart-verified SV loop count obtained from the initial acquired word lines and strings WL-STR (e.g., WL4-STR0) together with a program voltage step size DVPGM that is much smaller than the normal (base) program voltage step size DVPGM used by all remaining (acquired or applied) word lines and strings WL-STR. This operation is an adaptive version of cycling-dependent initial program voltage VPGMU tuning, as in static mode, and provides more block-level flexibility and adaptability for adjusting the initial program voltage VPGMU using cycling for program time tPROG improvement, with the downside being a slight program time tPROG penalty from probing word lines and strings WL-STR.

[0116] Figure 21 shows a comparison between two different examples of smart verification without cycling-dependent initial program voltage VPGMU tuning (smart verification 1 and smart verification 2) and an example of smart verification with cycling-dependent initial program voltage VPGMU tuning as described herein. Figure 22 is a plot of program time tPROG for probing one of several word lines, associated with the one of several strings being probed (i.e., probing WL-STR) and the word line subsequently programmed. As shown, the adaptive mode program time tPROG for the probing word line and string WL-STR increases with the use of a small program voltage step size DVPGM. However, since there is only one probing word line and string WL-STR, the program time tPROG penalty from the probing word line and string WL-STR themselves should be minimal, and a net program time tPROG benefit is still obtained. Figure 23 shows a lookup table for static mode, along with smart verification loop counts for the optimal initial program voltage VPGMU relationship that can be used for adaptive mode. Therefore, the static mode assumes that the initial program voltage VPGMU is optimized during development (D / S) of a fresh block and can be used as a reference when a lookup table is generated. Compared to the static mode, in addition to block-level suitability for cycling-dependent VPGMU tuning, the adaptive mode offers another inherent advantage: a self-correction mechanism for initial program voltage VPGMU adjustment (even for fresh blocks) when the developed initial program voltage VPGMU is suboptimal for fresh conditions, which ensures the optimality of the adaptively tuned initial program voltage VPGMU.

[0117] Figures 24 to 27 illustrate the steps of how to operate a memory device. As described above, a memory device (e.g., memory device 100 in Figure 1A) includes memory cells (e.g., data memory cells MC in Figure 6D) connected to one of several word lines (e.g., data word line layers (word lines) WLL0-WLL10 in Figure 6B or WLL10 in Figure 6D). The memory cells are located within memory holes (e.g., memory holes 618 and 619 in Figure 6B) and are configured to hold threshold voltages Vt or Vth corresponding to one of several memory or data states (Figures 9 to 11). The memory holes are organized into rows grouped into several strings (e.g., subblocks SBa to SBd in Figure 7A). Each of the several strings includes several blocks (e.g., blocks BLK0, BLK1, BLK2, BLK3 in Figure 6A). Referring first to Figure 24, the method includes a step 2400 in which a smart verification operation includes multiple smart verification loops beginning with an initial program voltage VPGMU (e.g., the initial program voltage (Vpgmint) described with reference to Figure 12 above, or the VPGMU in Figures 13A and 13B), and in which a smart verification operation includes a memory cell connected to one of multiple word lines and associated with one of multiple strings, thereby obtaining a smart verification program voltage (e.g., the newly obtained Vpgm as the start program voltage in step 1209 of Figure 12 above). Here again, the initial program voltage VPGMU is adjusted based on the cycling conditions of the memory cell. The method also includes a step in the program operation to program at least some of the memory cells connected to multiple word lines using the smart verification program voltage based on the adjusted initial program voltage VPGMU.

[0118] In this case as well, multiple blocks can include multiple planes. Therefore, the program operation can be a multiplane programming operation. As described above, the cycling conditions for each of the multiple blocks may be classified into multiple cycling categories, with increasing program and erase cycles for one of the memory cells in the multiple blocks, including: fresh blocks where one of the memory cells in the multiple blocks has not been programmed and erased; early-life (BOL) blocks where one of the memory cells in the multiple blocks has been programmed and erased fewer than a first predetermined amount (e.g., 300 erase / program (E / P) cycles); mid-life (MOL) blocks where one of the memory cells in the multiple blocks has been programmed and erased fewer than a second predetermined amount (e.g., 1500 erase / program (E / P) cycles); and end-of-life (EOL) blocks where one of the memory cells in the multiple blocks has been programmed and erased fewer than a third predetermined amount (e.g., 3000 erase / program (E / P) cycles). Accordingly, according to one embodiment, particularly with reference to Figure 25, in a “static mode”, the method further includes step 2500 of identifying one of a plurality of cycling categories for one of a plurality of blocks in each of a plurality of planes programmed in multiplane programming operation. The method also includes step 2502 of selecting one of a plurality of predetermined initial program voltage offsets based on one of a plurality of cycling categories identified for one of the plurality of blocks, and adjusting the initial program voltage VPGMU using one of the plurality of predetermined initial program voltage offsets, which minimizes the change in program time caused by one of a plurality of predetermined initial program voltage offsets.

[0119] As described above, in the rare case of two cycling conditions versus two cycling conditions for a block (assuming four planes), the memory device can select an initial program voltage VPGMU that results in an average increase in the minimum program time tPROG. Thus, according to a further embodiment, particularly with reference to Figure 26, in the case of static mode, the method further includes step 2600 of identifying one of a plurality of cycling categories for one of a plurality of blocks in each of the plurality of planes being programmed in multiplane programming operation. Next, 2602 determines whether half of the total number of the plurality of blocks is identified as a first cycling category of the plurality of cycling categories, and the remainder of the total number of blocks is identified as a second cycling category of the plurality of cycling categories. Furthermore, the method includes the steps of: selecting one of a plurality of predetermined initial program voltage offsets based on one of a plurality of cycling categories identified for one of a plurality of blocks, such that the change in program time due to one of a plurality of predetermined initial program voltage offsets is minimized for the average of one of a plurality of cycling categories identified for one of a plurality of blocks; and adjusting the initial program voltage VPGMU using one of a plurality of predetermined initial program voltage offsets (e.g., using a lookup table) in response to determining that half of the total number of blocks is identified as a first cycling category and the remainder of the total number of blocks is identified as a second cycling category.The method also includes the steps of: selecting one of a plurality of predetermined initial program voltage offsets based on one of a plurality of cycling categories identified for one of a plurality of blocks, such that the change in program time due to one of a plurality of predetermined initial program voltage offsets for most of the plurality of blocks; and adjusting the initial program voltage VPGMU using one of the plurality of predetermined initial program voltage offsets (e.g., using a lookup table) in response to not determining that half of the total number of blocks are identified as a first cycling category and the remainder of the total number of blocks are identified as a second cycling category.

[0120] Again, through cycling, the programming speed for a typical bit becomes faster, which results in fewer smart verification loops for the acquired word line and a lower optimal initial program voltage VPGMU for the application word line, in terms of program time tPROG. Thus, for one option, “Option 1” of “Adaptive Mode,” referring to Figure 27, the method further includes step 2700 identifying the probing smart verification loop count of multiple smart verification loops required to complete programming of the memory cell connected to one of multiple word lines to be probed and associated with one of multiple strings to be probed during smart verification operation. The method proceeds to 2702, identifying the optimal initial program voltage VPGMU for each of multiple blocks being programmed according to a predetermined optimal initial program voltage VPGMU and smart verification loop relationships that take cycling conditions into account. The method also includes the steps of: selecting one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage VPGMU for each of the plurality of blocks identified for one of the plurality of blocks which is closest to the average of the optimal initial program voltage VPGMU for all of the plurality of blocks being programmed; and adjusting the initial program voltage VPGMU using one of the plurality of predetermined initial program voltage offsets.

[0121] As described above, the program operation can begin by programming the memory cell of a first word line among multiple word lines, continue by programming the memory cells of other word lines among multiple word lines, and end by programming the memory cell of the last word line among multiple word lines. Accordingly, according to one embodiment, the word line to be probed among multiple word lines is selected as one of multiple word lines that includes or is within a predetermined probing word line limit of the first word line among multiple word lines (for example, relatively close to the first word line among multiple word lines).

[0122] In this case as well, according to another embodiment, the cycling condition may include write-erase cycle counts of program and erase cycles previously experienced by one of the multiple blocks of memory cells. Thus, in "Option 2," another option of the adaptive mode, the method further includes step 2706 of identifying write-erase cycle counts for each of the multiple blocks being programmed. Next, it determines whether the write-erase cycle count of any one of the multiple blocks is equal to a predetermined write-erase cycle checkpoint threshold (2708). The method also includes step 2710 of continuing to use the smart verification program voltage at a predetermined write-erase cycle checkpoint threshold previously used, in response to determining that the write-erase cycle count for any one of the multiple blocks is not equal to a predetermined write-erase cycle checkpoint threshold. In response to determining that the write-erase cycle count for any one of the multiple blocks is equal to a predetermined write-erase cycle checkpoint threshold, the method includes step 2712 of identifying the probing smart verification loop count of multiple smart verification loops required to complete programming of the memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed during the smart verification operation. The method follows step 2714, which identifies a predetermined optimal initial program voltage VPGMU for each of several blocks to be programmed according to a smart verification loop relationship and a predetermined optimal initial program voltage VPGMU that takes cycling conditions into account. The next step 2716 of the method is to select one of several predetermined initial program voltage offsets based on the optimal initial program voltage VPGMU for each of the several blocks identified for one of the several blocks that is closest to the average of the optimal initial program voltage VPGMU for all of the several blocks being programmed, and to adjust the initial program voltage VPGMU using one of the several predetermined initial program voltage offsets.Wafer-level pre-characterization of the optimal initial program voltage (VPGMU) versus smart verification loop count or relationship can be performed. Such a mapping relationship establishes a self-correction mechanism, as the optimal initial program voltage (VPGMU) for a fresh block is not bound to the initial program voltage (VPGMU) determined during development. Figure 28 shows the steps of an exemplary process for obtaining the optimal initial program voltage (VPGMU) versus smart verification loop relationship (e.g., the bottom of Figure 23).

[0123] The memory device and operating method disclosed herein offer numerous advantages. For example, the memory device and operating method disclosed herein apply a program voltage adapted to the cycling conditions, thereby achieving a significant program performance gain for the cycled block.

[0124] Clearly, modifications to those described and illustrated herein can be made without departing from the scope defined in the appended claims. The foregoing description of embodiments is provided for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are not limited in general to that particular embodiment, but are interchangeable and can be used in selected embodiments, even if not specifically illustrated or described, where applicable. The same may be modified in many ways. Such modifications should not be considered departures from the disclosure, and all such modifications are intended to be within the scope of the disclosure.

[0125] Various terms are used to refer to specific system components. Different companies may refer to components by different names, and this document is not intended to distinguish components that have different names but the same function. In the following description and claims, the terms “including” and “comprising” are used in an open-ended manner and should therefore be interpreted as “including, but not limited to…”. Also, the term “to combine” is intended to mean either an indirect or direct connection. Thus, when a first device combines with a second device, the connection may be a direct connection or an indirect connection via other devices and connections.

[0126] In addition, when a layer or element is referred to as being "on top" of another layer or substrate, it may be directly on top of the other layer of the substrate, or there may be an intervening layer. Furthermore, when a layer is referred to as being "below" another layer, it will be understood that it may be directly underneath, or there may be one or more intervening layers. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0127] As described herein, a controller includes individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), processors with control software, field-programmable gate arrays (FPGAs), or combinations thereof.

Claims

1. A memory device, A memory cell connected to one of a plurality of word lines, located within a memory hole, and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the memory hole is organized into rows grouped within a plurality of strings, and each of the plurality of strings comprises a plurality of blocks, A control means, In a smart verification operation including multiple smart verification loops beginning with an initial program voltage, the smart verification program voltage is obtained by programming the memory cell connected to one of the multiple word lines and associated with one of the multiple strings, wherein the initial program voltage is adjusted based on the cycling conditions of the memory cell. A memory device comprising: control means configured to program at least some of the memory cells connected to the plurality of word lines in a program operation using the smart verification program voltage based on the adjusted initial program voltage.

2. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the cycling conditions for each of the plurality of blocks are classified into a plurality of cycling categories, including, as the magnitude of the program and erase cycles of one of the plurality of blocks increases, a fresh block in which one of the plurality of blocks has not been programmed and erased; an early-life block in which one of the plurality of blocks has been programmed and erased fewer than a first predetermined amount; a mid-life block in which one of the plurality of blocks has been programmed and erased fewer than a second predetermined amount; and an end-of-life block in which one of the plurality of blocks has been programmed and erased fewer than a third predetermined amount, and the control means is, In the multiplane programming operation, one of the cycling categories for one of the blocks in each of the multiple planes that are programmed, The memory device according to claim 1, further configured to: select one of a plurality of predetermined initial program voltage offsets based on the cycling category identified for one of the plurality of blocks; select one of the plurality of predetermined initial program voltage offsets that minimizes the change in program time; and adjust the initial program voltage using one of the plurality of predetermined initial program voltage offsets.

3. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the cycling conditions for each of the plurality of blocks are classified into a plurality of cycling categories, including, as the magnitude of the program and erase cycles of one of the plurality of blocks increases, a fresh block in which one of the plurality of blocks has not been programmed and erased; an early-life block in which one of the plurality of blocks has been programmed and erased fewer than a first predetermined amount; a mid-life block in which one of the plurality of blocks has been programmed and erased fewer than a second predetermined amount; and an end-of-life block in which one of the plurality of blocks has been programmed and erased fewer than a third predetermined amount, and the control means is, In the multiplane programming operation, one of the cycling categories for one of the blocks in each of the multiple planes that are programmed, To determine whether half of the total number of the aforementioned multiple blocks is identified as a first cycling category among the aforementioned multiple cycling categories, and whether the remaining number of the aforementioned multiple blocks is identified as a second cycling category among the aforementioned multiple cycling categories, Minimizing the change in program time due to one of the plurality of predetermined initial program voltage offsets for the average of one of the plurality of cycling categories identified for one of the plurality of blocks, selecting one of the plurality of predetermined initial program voltage offsets based on one of the plurality of cycling categories identified for one of the plurality of blocks, and adjusting the initial program voltage using one of the predetermined initial program voltage offsets in response to determining that half of the total number of the plurality of blocks are identified as the first cycling category and the remainder of the total number of blocks are identified as the second cycling category. The memory device according to claim 1, further configured to minimize the change in program time due to one of the plurality of predetermined initial program voltage offsets for most of the plurality of blocks, by selecting one of the plurality of predetermined initial program voltage offsets based on one of the plurality of cycling categories identified for one of the plurality of blocks, and adjusting the initial program voltage using one of the plurality of predetermined initial program voltage offsets in response to not determining that half of the total number of blocks are identified as a first cycling category and the remainder of the total number of blocks are identified as a second cycling category.

4. The aforementioned plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the control means is During the smart verification operation, identify the probing smart verification loop count among the multiple smart verification loops necessary to complete the programming of the memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed, Identifying the optimal initial program voltage for each of the plurality of blocks programmed according to a predetermined optimal initial program voltage and a smart verification loop relationship that takes the cycling conditions into account, The memory device according to claim 1, further configured to select one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage for each of the plurality of blocks identified for that block, which is closest to the average of the optimal initial program voltages for all of the plurality of blocks that are programmed, and to adjust the initial program voltage using the one of the plurality of predetermined initial program voltage offsets.

5. The memory device according to claim 4, wherein the program operation begins by programming a memory cell of a first word line among the plurality of word lines, continues by programming memory cells of other word lines among the plurality of word lines, and ends by programming a memory cell of the last word line among the plurality of word lines, and the one of the plurality of word lines to be probed is selected as one of the plurality of word lines that includes or is within a predetermined probing word line limit of the first word line among the plurality of word lines.

6. The plurality of blocks comprises a plurality of planes, the program operation is a multiplane programming operation, the cycling condition includes a write-erase cycle count of program cycles and erase cycles previously experienced by one of the plurality of blocks' memory cells, and the control means is Identifying the write-erase cycle count for each of the programmed blocks, Determining whether the write-erase cycle count for any one of the aforementioned multiple blocks is equal to a predetermined write-erase cycle checkpoint threshold, The memory device according to claim 1, further configured to continue using the smart verification program voltage at the predetermined write-erase cycle checkpoint threshold in response to determining that the write-erase cycle count for any one of the plurality of blocks is not equal to a predetermined write-erase cycle checkpoint threshold previously used.

7. The control means, in response to determining that the write-erase cycle count for any one of the plurality of blocks is equal to the predetermined write-erase cycle checkpoint threshold, During the smart verification operation, identify the probing smart verification loop count among the multiple smart verification loops necessary to complete the programming of the memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed, Identifying the optimal initial program voltage for each of the plurality of blocks programmed according to a predetermined optimal initial program voltage and a smart verification loop relationship that takes the cycling conditions into account, The memory device according to claim 6, further configured to select one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage for each of the plurality of blocks identified for that block, which is closest to the average of the optimal initial program voltages for all of the plurality of blocks that are programmed, and to adjust the initial program voltage using the one of the plurality of predetermined initial program voltage offsets.

8. A controller for communicating with a memory device, which includes a memory cell connected to one of a plurality of word lines, located within a memory hole, and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the memory hole is organized into rows grouped into a plurality of strings, each of the plurality of strings includes a plurality of blocks, and the controller In a smart verification operation that includes multiple smart verification loops beginning with an initial program voltage, the memory device is instructed to obtain the smart verification program voltage by programming the memory cell connected to one of the multiple word lines and associated with one of the multiple strings, and the initial program voltage is adjusted based on the cycling conditions of the memory cell. A controller configured to, in program operation, instruct the memory device to program at least some of the memory cells connected to the plurality of word lines using the smart verification program voltage based on the adjusted initial program voltage.

9. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the cycling conditions for each of the plurality of blocks are classified into a plurality of cycling categories, including, as the magnitude of the program and erase cycles of one of the plurality of blocks' memory cells increases, a fresh block in which one of the plurality of blocks' memory cells has not been programmed and erased; an early-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a first predetermined amount; a mid-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a second predetermined amount; and an end-of-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a third predetermined amount, and the controller, The memory device is instructed to identify one of the multiple cycling categories for one of the multiple blocks in each of the multiple planes programmed in the multiplane programming operation, The controller according to claim 8, further configured to: select one of a plurality of predetermined initial program voltage offsets based on the cycling category identified for the block among the plurality of blocks; select one of the plurality of predetermined initial program voltage offsets that minimizes the change in program time; and adjust the initial program voltage using one of the plurality of predetermined initial program voltage offsets.

10. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the cycling conditions for each of the plurality of blocks are classified into a plurality of cycling categories, including, as the magnitude of the program and erase cycles of one of the plurality of blocks' memory cells increases, a fresh block in which one of the plurality of blocks' memory cells has not been programmed and erased; an early-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a first predetermined amount; a mid-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a second predetermined amount; and an end-of-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a third predetermined amount, and the controller, The memory device is instructed to identify one of the multiple cycling categories for one of the multiple blocks in each of the multiple planes programmed in the multiplane programming operation, The memory device is instructed to determine whether half of the total number of blocks is identified as a first cycling category among the multiple cycling categories, and whether the remaining number of blocks is identified as a second cycling category among the multiple cycling categories. Minimizing the change in program time due to one of the plurality of predetermined initial program voltage offsets for the average of one of the plurality of cycling categories identified for one of the plurality of blocks, selecting one of the plurality of predetermined initial program voltage offsets based on one of the plurality of cycling categories identified for one of the plurality of blocks, and adjusting the initial program voltage using one of the predetermined initial program voltage offsets in response to determining that half of the total number of the plurality of blocks are identified as the first cycling category and the remainder of the total number of blocks are identified as the second cycling category. The controller according to claim 8, further configured to minimize the change in program time due to one of the plurality of predetermined initial program voltage offsets for most of the plurality of blocks, by selecting one of the plurality of predetermined initial program voltage offsets based on one of the plurality of cycling categories identified for one of the plurality of blocks, and adjusting the initial program voltage using one of the plurality of predetermined initial program voltage offsets in response to not determining that half of the total number of the plurality of blocks are identified as a first cycling category and the remainder of the total number of blocks are identified as a second cycling category.

11. The aforementioned multiple blocks include multiple planes, the program operation is a multiplane programming operation, and the controller is During the smart verification operation, the memory device is instructed to identify the probing smart verification loop count among the multiple smart verification loops necessary to complete the programming of the memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed. The memory device is instructed to identify the optimal initial program voltage for each of the plurality of programmed blocks according to a predetermined optimal initial program voltage and a smart verification loop relationship that takes into account the cycling conditions. The controller according to claim 8, further configured to select one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage for each of the plurality of blocks identified for that block, which is closest to the average of the optimal initial program voltages for all of the plurality of blocks that are programmed, and to adjust the initial program voltage using the one of the plurality of predetermined initial program voltage offsets.

12. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, the cycling condition includes a write-erase cycle count of program cycles and erase cycles previously experienced by one of the plurality of blocks' memory cells, and the controller, Identifying the write-erase cycle count for each of the programmed blocks, Determining whether the write-erase cycle count for any one of the aforementioned multiple blocks is equal to a predetermined write-erase cycle checkpoint threshold, The controller according to claim 8, further configured to instruct the memory device to continue using the smart verification program voltage at the predetermined write-erase cycle checkpoint threshold in response to determining that the write-erase cycle count for any one of the plurality of blocks is not equal to a predetermined write-erase cycle checkpoint threshold previously used.

13. The controller, in response to determining that the write-erase cycle count for any one of the plurality of blocks is equal to the predetermined write-erase cycle checkpoint threshold, During the smart verification operation, the memory device is instructed to identify the probing smart verification loop count among the multiple smart verification loops necessary to complete the programming of the memory cell connected to one of the multiple word lines being probed and associated with one of the multiple strings being probed. The memory device is instructed to identify the optimal initial program voltage for each of the plurality of programmed blocks according to a predetermined optimal initial program voltage and a smart verification loop relationship that takes into account the cycling conditions. The controller according to claim 12, further configured to select one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage for each of the plurality of blocks identified for that block, which is closest to the average of the optimal initial program voltages for all of the plurality of blocks that are programmed, and to adjust the initial program voltage using the one of the plurality of predetermined initial program voltage offsets.

14. A method for operating a memory device including a memory cell connected to one of a plurality of word lines, located in a memory hole, and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the memory hole is organized into rows grouped into a plurality of strings, and each of the plurality of strings includes a plurality of blocks, and the method A smart verification operation including a plurality of smart verification loops beginning with an initial program voltage, comprising the steps of obtaining a smart verification program voltage by programming the memory cell connected to one of the plurality of word lines and associated with one of the plurality of strings, wherein the initial program voltage is adjusted based on the cycling conditions of the memory cell; A method comprising the step of programming at least some of the memory cells connected to the plurality of word lines in a program operation using the smart verification program voltage based on the adjusted initial program voltage.

15. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the cycling conditions for each of the plurality of blocks are classified into a plurality of cycling categories, including, as the magnitude of the program and erase cycles of one of the plurality of blocks' memory cells increases, a fresh block in which one of the plurality of blocks' memory cells has not been programmed and erased; an early-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a first predetermined amount; a mid-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a second predetermined amount; and an end-of-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a third predetermined amount, and the method is, The multiplane programming operation includes the step of identifying one of the multiple cycling categories for one of the multiple blocks in each of the multiple planes that are programmed, The method of claim 14, further comprising the steps of: selecting one of a plurality of predetermined initial program voltage offsets based on the cycling category of a plurality of cycling categories identified for the block of the plurality of blocks; selecting one of the plurality of predetermined initial program voltage offsets that minimizes the change in program time; and adjusting the initial program voltage using one of the plurality of predetermined initial program voltage offsets.

16. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the cycling conditions for each of the plurality of blocks are classified into a plurality of cycling categories, including, as the magnitude of the program and erase cycles of one of the plurality of blocks' memory cells increases, a fresh block in which one of the plurality of blocks' memory cells has not been programmed and erased; an early-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a first predetermined amount; a mid-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a second predetermined amount; and an end-of-life block in which one of the plurality of blocks' memory cells has been programmed and erased fewer than a third predetermined amount, and the method is, The multiplane programming operation includes the step of identifying one of the multiple cycling categories for one of the multiple blocks in each of the multiple planes that are programmed, The steps include determining whether half of the total number of blocks is identified as a first cycling category among the multiple cycling categories, and whether the remaining number of blocks is identified as a second cycling category among the multiple cycling categories, A step of selecting one of a plurality of predetermined initial program voltage offsets that minimizes the change in program time due to one of a plurality of predetermined initial program voltage offsets relative to the average of one of the plurality of cycling categories identified for one of the plurality of blocks, and adjusting the initial program voltage using one of the predetermined initial program voltage offsets in response to the determination that half of the total number of blocks are identified as the cycling category and the remainder of the total number of blocks are identified as the second cycling category. The method of claim 14, further comprising the steps of: selecting one of a plurality of predetermined initial program voltage offsets based on one of a plurality of cycling categories identified for one of the plurality of blocks, in order to minimize the change in program time due to one of a plurality of predetermined initial program voltage offsets for most of the plurality of blocks; and adjusting the initial program voltage using one of the plurality of predetermined initial program voltage offsets in response to not determining that half of the total number of the plurality of blocks are identified as a first cycling category and the remainder of the total number of blocks are identified as a second cycling category.

17. The aforementioned plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, and the method is During the smart verification operation, the steps include identifying the probing smart verification loop count among the plurality of smart verification loops necessary to complete the programming of the memory cell connected to one of the plurality of word lines being probed and associated with one of the plurality of strings being probed, A step of identifying an optimal initial program voltage for each of the plurality of blocks programmed according to a predetermined optimal initial program voltage and a smart verification loop relationship that takes into account the cycling conditions, The method of claim 14, further comprising the steps of selecting one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage for each of the plurality of blocks identified for the block which is closest to the average of the optimal initial program voltages for all of the plurality of blocks that are programmed, and adjusting the initial program voltage using one of the plurality of predetermined initial program voltage offsets.

18. The method according to claim 17, wherein the program operation begins by programming a memory cell of a first word line among the plurality of word lines, continues by programming memory cells of other word lines among the plurality of word lines, and ends by programming a memory cell of the last word line among the plurality of word lines, and the one of the plurality of word lines to be probed is selected as one of the plurality of word lines that includes or is within a predetermined probing word line limit of the first word line among the plurality of word lines.

19. The plurality of blocks include a plurality of planes, the program operation is a multiplane programming operation, the cycling condition includes a write-erase cycle count of program cycles and erase cycles previously experienced by one of the plurality of blocks' memory cells, and the method is A step of identifying the write-erase cycle count for each of the plurality of programmed blocks, The steps include determining whether the write-erase cycle count for any one of the plurality of blocks is equal to a predetermined write-erase cycle checkpoint threshold, The method according to claim 14, further comprising the step of continuing to use the smart verification program voltage at the predetermined write-erase cycle checkpoint threshold in response to determining that the write-erase cycle count for any one of the plurality of blocks is not equal to a predetermined write-erase cycle checkpoint threshold previously used.

20. A method according to claim 19, wherein, in response to determining that the write-erase cycle count for any one of the plurality of blocks is equal to the predetermined write-erase cycle checkpoint threshold, During the smart verification operation, the steps include identifying the probing smart verification loop count among the plurality of smart verification loops necessary to complete the programming of the memory cell connected to one of the plurality of word lines being probed and associated with one of the plurality of strings being probed, A step of identifying an optimal initial program voltage for each of the plurality of blocks programmed according to a predetermined optimal initial program voltage and a smart verification loop relationship that takes into account the cycling conditions, The method of claim 19, further comprising the steps of selecting one of a plurality of predetermined initial program voltage offsets based on the optimal initial program voltage for each of the plurality of blocks identified for the block which is closest to the average of the optimal initial program voltages for all of the plurality of blocks that are programmed, and adjusting the initial program voltage using one of the plurality of predetermined initial program voltage offsets.

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