Read offset compensation in memory device read operations

Abstract

This provides read offset compensation for memory device read operations. [Solution] A memory controller coupled to a memory device including an array of memory cells, wherein each memory cell corresponds to 2 bits of data N It is set to one of the states, where N is an integer greater than 1, and the array of memory cells is divided into one or more units. The memory controller is coupled to the memory device, and when an instruction is executed, 2 N The system is configured to obtain from the memory device the number P of memory cells in one of a group of units that are in one or more programmed states, calculate a compensated read voltage with an offset from the default read voltage based on the number P, and provide the memory device with the compensated read voltage for a read operation performed on a selected memory cell in one of the group of units.

Description

[Technical Field]

[0001] This disclosure relates to a memory device and its operation. [Background technology]

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory allows for various operations such as reading, programming (writing), and erasing. In the case of NAND flash memory, erasing can be performed at the block level, while programming or reading operations can be performed at the page level. [Overview of the project] [Means for solving the problem]

[0003] In one embodiment, the memory system includes a memory device and a memory controller. The memory device includes an array of memory cells and peripheral circuits. Each memory cell corresponds to one N-bit data. N The memory array is configured to be set to one of the states, where N is an integer greater than 1, and the array of memory cells is divided into one or more units. Peripheral circuits are coupled to the memory cells and are configured to perform read operations on selected memory cells within one of the multiple units. A memory controller is coupled to the memory device and is configured to control the memory device to perform read operations using a compensated read voltage with an offset from the default read voltage by sending instructions to the peripheral circuits. The offset is 2 N It correlates with the number P of memory cells in a unit that are in one or more programmed states.

[0004] In some implementations, the offset is associated with a unit and is updated after the number of memory cells P within that unit changes.

[0005] In some implementations, the offset is updated periodically.

[0006] In some implementations, the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0007] In some implementations, the number P is obtained through a verification read operation configured to count the number P of memory cells within the unit.

[0008] In some implementations, the memory controller is 2 N The system is configured to select one or more programmed states and determine the verification voltage used in the verification readout operation based on a default range of threshold voltages corresponding to the selected one or more states. The verification voltage is equal to the minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0009] In some implementations, 2 N The number of selected programmed states is 1, and the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of the memory cell corresponding to the non-selected state among the states.

[0010] In some implementations, the peripheral circuitry includes a word line driver configured to apply a verification voltage to at least some of the memory cells in the unit via the word line.

[0011] In some implementations, the memory controller includes a digital signal processor configured to count a number P after a verification voltage has been applied to at least some of the memory cells in the unit.

[0012] In some implementations, each unit of one or more units contains one or more pages, and the validation read operation is performed on one or more selected pages from the one or more pages, and the number of P is 2 N This is the average number of memory cells in one or more selected pages that are in one or more programmed states.

[0013] In some implementations, the controller includes a processor configured to retrieve the offset through a lookup operation by looking up an offset corresponding to a number P and a first mapping table between the offset and the number P.

[0014] In some implementations, the memory controller includes a first register configured to store a first mapping table.

[0015] In some implementations, the memory controller includes a digital signal processor configured to calculate the numerical difference ΔP between a number P and a default number P', where the default number P' is set after the program operation is complete. N This is the number of memory cells in a unit that are in one or more programmed states.

[0016] In some implementations, the memory controller includes a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the numerical difference ΔP and a second mapping table between the offset and the numerical difference ΔP.

[0017] In some implementations, the memory controller includes a second register configured to store a second mapping table.

[0018] In some implementations, the memory controller includes a third register configured to store a default number P'.

[0019] In some implementations, the processor is configured to adjust an offset for memory cells within a unit based on a default threshold voltage of the memory cells.

[0020] In some implementations, an adjusted offset for memory cells within a unit has a positive correlation with a default threshold voltage of the memory cells.

[0021] In some implementations, the memory controller includes a fourth register configured to store an offset obtained by the processor.

[0022] In some implementations, the processor is configured to obtain an offset from the fourth register and calculate a compensated read voltage by adding the offset to a default read voltage.

[0023] In another aspect, the memory controller is coupled to a memory device that includes an array of memory cells, each memory cell is set to one of two states corresponding to N-bit data, where N is an integer greater than 1, and the array of memory cells is divided into one or more units. The memory controller is coupled to the memory device and, upon execution of an instruction, obtains the number P of memory cells within one unit of one or more units of the memory device that are in one or more programmed states of the two states, calculates a compensated read voltage having an offset from a default read voltage based on the number P, and provides the compensated read voltage for a read operation to be performed on a selected memory cell of the memory cells within one unit of the one or more units to the memory device. N In another aspect, the memory controller is coupled to a memory device that includes an array of memory cells, each memory cell is set to one of two states corresponding to N-bit data, where N is an integer greater than 1, and the array of memory cells is divided into one or more units. The memory controller is coupled to the memory device and, upon execution of an instruction, obtains the number P of memory cells within one unit of one or more units of the memory device that are in one or more programmed states of the two states, calculates a compensated read voltage having an offset from a default read voltage based on the number P, and provides the compensated read voltage for a read operation to be performed on a selected memory cell of the memory cells within one unit of the one or more units to the memory device. N In another aspect, the memory controller is coupled to a memory device that includes an array of memory cells, each memory cell is set to one of two states corresponding to N-bit data, where N is an integer greater than 1, and the array of memory cells is divided into one or more units. The memory controller is coupled to the memory device and, upon execution of an instruction, obtains the number P of memory cells within one unit of one or more units of the memory device that are in one or more programmed states of the two states, calculates a compensated read voltage having an offset from a default read voltage based on the number P, and provides the compensated read voltage for a read operation to be performed on a selected memory cell of the memory cells within one unit of the one or more units to the memory device.

[0024] In some implementations, the offset is associated with a unit and is updated after the number P of memory cells within the unit is changed.

[0025] In some implementations, the offset is updated periodically. In some implementations, the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0026] In some implementations, the memory controller includes a processor configured to control the memory device to count the number P of memory cells in a unit by performing a verifying read operation.

[0027] In some implementations, the processor is 2 N The system is configured to select one or more programmed states from among the states and to determine a verification voltage used in the verification read operation based on a default range of threshold voltages corresponding to the selected one or more states, wherein the verification voltage is equal to the minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0028] In some implementations, 2 N The number of selected programmed states is 1, and the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of the memory cell corresponding to the non-selected state among the states.

[0029] In some implementations, the memory controller includes a digital signal processor configured to count a number P after a verification voltage has been applied to at least some of the memory cells in the unit.

[0030] In some implementations, each unit of one or more units contains one or more pages, and the validation read operation is performed on one or more selected pages from the one or more pages, and the number of P is 2 N This is the average number of memory cells in one or more selected pages that are in one or more programmed states.

[0031] Some implementations include a processor configured to obtain the offset through a lookup operation by looking up an offset corresponding to a number P and a first mapping table between the offset and the number P.

[0032] In some implementations, the memory controller includes a first register configured to store a first mapping table.

[0033] In some implementations, the memory controller includes a digital signal processor configured to calculate the numerical difference ΔP between a number P and a default number P', where the default number P' is set after the program operation is complete. N This is the number of memory cells in a unit that are in one or more programmed states.

[0034] In some implementations, the memory controller includes a processor configured to retrieve the offset through a lookup operation by looking up the offset corresponding to the numerical difference ΔP and a second mapping table between the offset and the numerical difference ΔP.

[0035] In some implementations, the memory controller includes a second register configured to store a second mapping table.

[0036] In some implementations, the memory controller includes a third register configured to store a default number P'.

[0037] In some implementations, the processor is configured to adjust the offset for memory cells within a unit based on the default threshold voltage of the memory cells.

[0038] In some implementations, the adjusted offset of memory cells within a unit is positively correlated with the default threshold voltage of the memory cells.

[0039] In some implementations, the memory controller includes a fourth register configured to store the offset obtained by the processor.

[0040] In some implementations, the processor is configured to obtain an offset from a fourth register and calculate a compensated read voltage by adding that offset to the default read voltage.

[0041] In yet another embodiment, the memory device includes an array of memory cells and peripheral circuits. Each memory cell corresponds to 2 bits of data. N It is configured to be set to one of the states, where N is an integer greater than 1, and the array of memory cells is divided into one or more units. Peripheral circuits are coupled to the memory cells and configured to perform read operations on selected memory cells in one of the units, using a compensated read voltage with an offset from the default read voltage. The offset is 2 N It correlates with the number P of memory cells in a unit that are in one or more programmed states.

[0042] In some implementations, the offset is associated with a unit and is updated after the number of memory cells P within that unit changes.

[0043] In some implementations, the offset is updated periodically.

[0044] In some implementations, the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0045] In some implementations, the number P is obtained through a verification read operation configured to count the number P of memory cells within the unit.

[0046] In some implementations, the peripheral circuitry is 2 N The system is configured to select one or more programmed states and determine the verification voltage used in the verification readout operation based on a default range of threshold voltages corresponding to the selected states. The verification voltage is equal to the minimum threshold voltage of the default range of threshold voltages corresponding to the selected states.

[0047] In some implementations, 2 N The number of selected programmed states is 1, and the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of the memory cell corresponding to the unselected state.

[0048] In some implementations, the peripheral circuitry includes a word line driver configured to apply a verification voltage to at least some of the memory cells in the unit via the word line.

[0049] In some implementations, the peripheral circuitry includes a computer configured to calculate a number P after a verification voltage has been applied to at least some of the memory cells within the unit.

[0050] In some implementations, each unit of one or more units contains one or more pages, and the validation read operation is performed on one or more selected pages from the one or more pages, and the number of P is 2 N This is the average number of memory cells in one or more selected pages that are in one or more programmed states.

[0051] In some implementations, the peripheral circuitry includes control logic configured to retrieve the offset through a lookup operation by looking up an offset corresponding to a number P and a first mapping table between the offset and the number P.

[0052] In some implementations, the peripheral circuitry includes a first register configured to store a first mapping table.

[0053] In some implementations, the peripheral circuitry includes a computer configured to calculate the numerical difference ΔP between a number P and a default number P', where the default number P' is set after the program operation is complete. N This is the number of memory cells in a unit that are in one or more of the program states.

[0054] In some implementations, the control logic is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the numerical difference ΔP, and a second mapping table between the offset and the numerical difference ΔP.

[0055] In some implementations, the peripheral circuitry includes a second register configured to store a second mapping table.

[0056] In some implementations, the peripheral circuitry includes a third register configured to store a default number P'.

[0057] In some implementations, the processor is configured to adjust the offset for memory cells within a unit based on the default threshold voltage of the memory cells.

[0058] In some implementations, the adjusted offset of memory cells within a unit is positively correlated with the default threshold voltage of the memory cells.

[0059] In some implementations, the peripheral circuitry includes a fourth register configured to store the offset obtained by the processor.

[0060] In some implementations, the control logic is configured to obtain an offset from a fourth register and calculate a compensated read voltage by adding that offset to the default read voltage.

[0061] In yet another embodiment, 2 corresponding to one N-bit data N A method for reading a memory device containing an array of memory cells configured to be set to one of the states is disclosed, where N is an integer greater than 1, the array of memory cells is divided into one or more units, and the method is 2 N The process includes the steps of obtaining the number P of memory cells in a unit that are in one or more programmed states, calculating a compensated read voltage having an offset from a default read voltage, and performing a read operation on selected memory cells in the unit using the compensated read voltage.

[0062] In some implementations, after calculating the compensated read voltage, the method further includes updating the offset after the number of memory cells P in the unit has changed.

[0063] In some implementations, the offset is updated periodically.

[0064] In some implementations, the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0065] In some implementations, the number of memory cells P in a unit is calculated by performing a verification read operation.

[0066] In some implementations, the step of performing a verifiable read operation is 2 NThe process includes the steps of selecting one or more programmed states from among the states, and determining a verification voltage to be used in a verification read operation based on a default range of threshold voltages corresponding to the selected one or more states. The verification voltage is equal to the minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0067] In some implementations, 2 N The number of selected programmed states is 1, and the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of the memory cell corresponding to the non-selected state among the states.

[0068] In some implementations, each unit of one or more units contains one or more pages, and the validation read operation is performed on one or more selected pages from the one or more pages, and the number of P is 2 N This is the average number of memory cells in one or more selected pages that are in one or more programmed states.

[0069] In some implementations, calculating a compensated readout voltage with an offset involves looking up an offset corresponding to a number P, and a first mapping table between the offset and the number P.

[0070] In some implementations, the first mapping table is stored in the first register.

[0071] In some implementations, the step of calculating the compensated read voltage with an offset includes the step of calculating the numerical difference ΔP between a number P and a default number P', where the default number P' is set after the program operation is complete. N This is the number of memory cells in a unit that are in one or more programmed states.

[0072] In some implementations, the step of calculating a compensated readout voltage with an offset further includes looking up an offset corresponding to the number difference ΔP, and a second mapping table between the offset and the number difference ΔP.

[0073] In some implementations, the second mapping table is stored in a second register.

[0074] In some implementations, the default number P' is stored in a third register.

[0075] In some implementations, after calculating a compensated read voltage with an offset, the method further includes the step of adjusting the offset based on the default threshold voltage of the memory cell.

[0076] In some implementations, the adjusted offset of memory cells within a unit is positively correlated with the default threshold voltage of the memory cells.

[0077] In some implementations, the method further includes the step of storing the adjusted offset in a fourth register.

[0078] In some implementations, the step of determining the compensated read voltage includes the steps of obtaining an offset from a fourth register and calculating the compensated read voltage by adding the offset to the default read voltage.

[0079] The accompanying drawings incorporated herein and forming part of the specification illustrate aspects of the disclosure and, together with the description thereof, further assist in explaining the disclosure and enabling those skilled in the art to prepare and use the disclosure. [Brief explanation of the drawing]

[0080] [Figure 1] This figure shows the trend of changes in the threshold voltage distribution of a memory device after charge loss, according to several aspects of this disclosure. [Figure 2A] This figure shows the storage time of blocks in a memory device according to some aspects of the present disclosure. [Figure 2B] This figure shows the relationship between storage time and the threshold voltage distribution of a memory device according to several aspects of this disclosure. [Figure 3A] This figure shows the length of time required for a read operation that does not involve error recovery. [Figure 3B] This figure shows the length of time required for a read operation that involves error recovery. [Figure 3C] This figure shows the length of time required by a read operation according to some aspects of this disclosure. [Figure 4] This is a block diagram of a system having a memory device according to some aspects of the present disclosure. [Figure 5A] This figure shows a memory card having a memory device according to some aspects of the present disclosure. [Figure 5B] This figure shows a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. [Figure 6] This is a schematic diagram showing a memory device including peripheral circuits according to some aspects of the present disclosure. [Figure 7] This block diagram shows a memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure. [Figure 8] This is a block diagram showing a memory system including a host, a memory controller, and a memory device, according to some aspects of the present disclosure. [Figure 9A] Block diagram showing a memory controller coupled to a memory cell array according to some aspects of the present disclosure. [Figure 9B] A block diagram showing another memory controller coupled to a memory cell array according to some aspects of the present disclosure. [Figure 10A] This figure shows the relationship between the verification voltage and the threshold voltage distribution, without charge loss. [Figure 10B] This figure shows the relationship between the verification voltage and threshold voltage distribution, including charge loss. [Figure 11] This is a diagram showing the first mapping table. [Figure 12] This figure shows a plot of the programming state offset and the number of memory cells P. [Figure 13] This figure shows a table of offsets for each unit. [Figure 14A] This figure shows the relationship between the verification voltage and the threshold voltage distribution, without charge loss. [Figure 14B] This figure shows the relationship between the verification voltage and threshold voltage distribution, including charge loss. [Figure 15] This is a flowchart of a method for read offset compensation based on the number of memory cells P, according to some aspects of this disclosure. [Modes for carrying out the invention]

[0081] The aspects of this disclosure will be described with reference to the attached drawings.

[0082] In general, terms may be understood at least partially from their usage in context. For example, the term “one or more” as used herein may be used at least partially, depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may be understood, at least partially, depending on the context, to convey a singular or plural usage. Furthermore, the term “based on” is not necessarily intended to convey an exclusive set of factors, but instead may, at least partially, depending on the context, allow for the presence of additional factors that are not necessarily explicitly stated.

[0083] Memory devices such as NAND flash memory devices can increase storage capacity and reduce the cost per bit by utilizing charge capture technology to store one or more bits of information in each memory cell in multiple states. In the program operation of memory devices employing charge capture technology, data can be programmed (written) to multi-level cell (MLC) blocks such as trip-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC), significantly improving programming speed. Referring to Figure 1, the threshold voltage distribution of a block decreases due to charge loss, and memory cells in different programmed states experience different degrees of charge loss. The decrease in threshold voltage distribution causes error bits, and in cases of severe charge loss, it causes read error recovery. A read offset is provided to compensate for charge loss. For example, a first offset is added to the default read voltage to compensate for changes in the threshold voltage distribution. This approach is largely ineffective because charge loss is closely related to the period after data has been written. As shown in Figures 2A and 2B, the durations of the various blocks are not statistically maintained but change dynamically. Therefore, the read offset cannot compensate for the charge loss of all blocks and cannot avoid read errors.

[0084] Figure 3A shows the first period t for reading data from a memory page. R Then, a second period t for transferring data to the memory controller. XER Figure 3B shows the time durations resulting from a normal read operation, including the first period t. R and the second period t XER In addition, there is a third period t for the memory controller and hardware to prepare to try again after a read error. 0V This further includes: The actual time taken by a read operation of a memory block with charge loss is the first period tR , second period t XER , and the third period t 0V The sum of these values ​​can be multiples of each other. Therefore, the efficiency of the memory system will be significantly reduced.

[0085] To address one or more of the aforementioned problems, this disclosure detects the degree of charge loss in each block and generates a specially adjusted read offset to compensate for the default read voltage based on the degree of charge loss, and thus, as shown in Figure 3C, read errors are avoided, the read speed is significantly improved, and the time incurred by the read operation of the memory block is less than a first period t regardless of charge loss. R , second period t XER , and the third time t 0V A solution is introduced that is the sum of the following: By counting the number of memory cells in a programmed state within each block, the degree of charge loss can be detected because the number decreases due to charge loss. Depending on the detected degree of charge loss, the read voltage can be accurately compensated with a customized offset. This solution can detect the charge loss in each block and accurately compensate the read voltage regardless of the cause of the charge loss, i.e., regardless of whether the charge loss is caused by time, temperature, programming, etc. The relationship between the offset and the number of memory cells in a programmed state is pre-calculated and stored as a mapping table, so the offset can be determined immediately after obtaining the number. Because a certain amount of time is required for charge loss to accumulate, the offset is updated periodically rather than being calculated before each read operation in order to balance the efficiency and accuracy of the read operation. The solution of this disclosure reduces the undesirable effects of charge loss at low cost and significantly improves the performance of memory devices and memory systems.

[0086] Figure 4 shows a block diagram of a system 100 having a memory device according to several aspects of the present disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or other suitable electronic device having storage. As shown in Figure 4, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device such as a central processing unit (CPU), or a system-on-chip (SoC) such as an application processor (AP). The host 108 may be configured to send and receive data to and from the memory device 104.

[0087] The memory device 104 may be any memory device as detailed in this disclosure. According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, and laptop computers, and in enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 106 is further configured to handle error correction codes (ECC) with respect to data read from or written to the memory device 104. Any other appropriate functions can also be performed by the memory controller 106, such as formatting the memory device 104.In accordance with some aspects of this disclosure, in some implementations, the memory controller 106 is configured to perform read offset compensation all or part of the time, as described in detail below.

[0088] The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with an external device via at least one of various interface protocols such as the USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0089] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, in the same package such as a universal flash storage (UFS) package or an eMMC package. In other words, the memory system 102 can be implemented and packaged in various types of final electronic products. In one example shown in Figure 5A, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include PC cards (PCMCIA, International Association for Personal Computer Memory Cards), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that connects the memory card 202 to a host (for example, the host 108 in Figure 1). In another example shown in Figure 5B, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD206 may further include an SSD connector 208 that connects the SSD206 to a host (for example, host 108 in Figure 4). In some implementations, the storage capacity and / or operating speed of the SSD206 is greater than that of the memory card 202.

[0090] Figure 6 shows a schematic circuit diagram of a memory device 300 including peripheral circuits according to several embodiments of the present disclosure. The memory device 300 may be an example of the memory device 104 in Figure 4. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, and the memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically on a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be either a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trapping transistor.

[0091] In some implementations, each memory cell 306 is a single-level cell (SLC) capable of storing one bit of data, having two possible memory states. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC can store 2 bits per cell, 3 bits per cell (also called a triple-level cell (TLC)), or 4 bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one embodiment, if each MLC stores 2 bits of data, the MLC can be programmed to assume one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0092] As shown in Figure 6, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 can be configured to activate the selected NAND memory string 308 (a column in the array) during read and program operation. In some implementations, the sources of NAND memory strings 308 within the same block 304 are connected via the same source line (SL) 314, for example, a common SL. In other words, according to some implementations, all NAND memory strings 308 within the same block 304 have an array common source (ACS). The DSG 312 of each NAND memory string 308 is, according to some implementations, connected to a bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselection voltage (e.g., 0V) to each DSG 312 via one or more DSG lines 313, and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a deselection voltage (e.g., 0V) to each SSG 310 via one or more SSG lines 315.

[0093] As shown in Figure 6, a NAND memory string 308 can be organized into multiple blocks 304, each block having a common source line 314 coupled, for example, to ACS. In some implementations, each block 304 is the basic data unit of an erase operation; that is, all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source lines 315 coupled to the selected block 304, as well as to unselected blocks 304 in the same plane as the selected block 304, can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). In some examples, it is understood that the erase operation may be performed at the half-block level, the quarter-block level, or at any appropriate number of blocks or any appropriate portion of a block. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318 that select which rows of memory cells 306 are affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which are the basic data units of program operation. The size of one page 320 in bits may relate to the number of NAND memory strings 308 coupled by word lines 318 in one block 304. For ease of explanation, memory cells 306 in one page 320 may be coupled to the same word line 318, and the terms “page” and “word line” may be used interchangeably in this disclosure. However, it will be understood that in some examples, memory cells 306 in one page 320 may be coupled to multiple word lines 318. Each word line 318 may include multiple control gates (gate electrodes) in each memory cell 306 within each page 320, and gate lines coupling the control gates.

[0094] As shown in Figure 6, the program operation is performed at the page / word line level of each block 304, and is therefore consistent with the scope of this disclosure. The peripheral circuit 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313 to facilitate the operation of the memory cell array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 shows the peripheral circuitry within a memory device 104, which includes a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, control logic 412, registers 414, an interface 416, and a data bus 418. It is understood that in some examples, additional peripheral circuitry not shown in Figure 7 may also be included.

[0095] The page buffer / sensor amplifier 404 can be configured to read and program (write) data to and from the memory cell array 301 according to control signals from the control logic 412. In one example, the page buffer / sensor amplifier 404 can store one page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sensor amplifier 404 can perform a program verification operation to ensure that data has been properly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sensor amplifier 404 can also sense a low-power signal from the bit line 316 representing data bits stored in the memory cell 306 and amplify small voltage swings in read operations to a recognizable logic level. The column decoder / bit line driver 406 can be controlled by the control logic 412 and configured to select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 410.

[0096] The row decoder / word line driver 408 can be configured to be controlled by control logic 412, a select / deselect block 304 of the memory cell array 301, and a select / deselect word line 318 of block 304. The row decoder / word line driver 408 can further be configured to drive the word line 318 using a word line voltage generated from a voltage generator 410. In some implementations, the row decoder / word line driver 408 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 408 is configured to apply a read voltage to the selected word line 318 during read operations on memory cells 306 coupled to the selected word line 318.

[0097] The voltage generator 410 may be controlled by control logic 412 and configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages supplied to the memory cell array 301. The control logic 412 may be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. The registers 415 may be coupled to the control logic 412 and include a status register for storing status information, a command register, and an address register, a command operation code (OP code), as well as command addresses for controlling the operation of each peripheral circuit.

[0098] Interface 416 can be coupled to control logic 412 and function as a control buffer that buffers control commands received from a host (not shown) and relays them to control logic 412, and relays status information received from control logic 412 to the host. Interface 416 can also be coupled to column decoder / bit line driver 406 via data bus 418 and function as a data input / output (I / O) interface and data buffer that can buffer and relay data to and from memory cell array 301.

[0099] Referring to Figure 8, a memory system 500 is provided, including a plurality of memory devices 104 and a memory controller 106, according to several implementations of this disclosure. Each of the memory devices 104 includes an array of memory cells and peripheral circuits, as shown in Figure 7. The memory cells in the memory device 104 are MLCs, and each memory cell corresponds to 2 N bits of data. NIt is configured to be set to one of the states, where N is an integer greater than 1. The array of memory cells is divided into one or more units. A unit can be a physical unit or a logical unit. For example, a unit can be a page or a block based on the physical connections between memory cells. A unit can also be a group of memory cells in different pages or blocks that operate with the same write operation. The number of memory cells in each unit can be the same or different depending on the actual storage needs. In one implementation, the number of memory cells in a unit may be one. The methods of dividing units and the number of memory cells in units described herein are for illustrative purposes only and should not be construed as limiting the disclosure. Peripheral circuits are coupled to the memory cells and configured to perform read operations on selected memory cells in one of the units.

[0100] The memory controller 106 may be coupled to a memory device and configured to execute various interface protocols disclosed herein. As shown in Figure 8, the memory controller 106 may be coupled to one or more memory devices 104 and configured to control the cache programming of the memory devices 104. The memory controller 106 may include various interface layers, including but not limited to a peripheral component interconnect express (PCIe) layer 510, a non-volatile memory express (NVMe) layer 520, and / or a NAND controller interface (NFI) layer 530, for interface with the host 108 and the memory devices 104. The PCIe layer 510 and / or the NVMe layer 520 may be coupled to one or more processing units 540 (e.g., microcontrollers), and the processing units 540 may be configured to implement various memory control functions by executing instructions, for example, in the form of firmware stored in read-only memory (ROM) 550. The processing units 540 may be coupled to a DRAM 570 via a dynamic random access memory (DRAM) controller 560. The DRAM controller 560 may be configured to store and access data stored in the DRAM 570, such as cached new programming data and / or reconstructed current programming data, which are transmitted from the memory device 104 to the memory controller 106 according to various interface protocols disclosed herein. In some examples, it will be understood that the DRAM 570 and the DRAM controller 560 may be omitted. In other words, the memory controller 106 may be a non-DRAM memory controller.

[0101] Figure 9A shows an implementation of the memory controller 106 coupled to the memory cell array 301 via a backend interface 628. The memory controller 106 includes a processor 622 and a digital signal processor (DSP) 624 coupled to the backend interface 628. The processor 622 is configured to control the memory cell array 301 to count a number P of memory cells in a unit by performing a verification read operation. The DSP 624 is configured to count the number P after a verification voltage has been applied to at least some of the memory cells in the unit. The memory controller 106 further includes a register 626 configured to store a first mapping table and offsets. The number P calculated by the DSP 624 can be stored in a register, for example, register 626, and the processor 622 can retrieve the number P from the register. The first mapping table, the number P, and the offsets may be stored in the same register or in different registers, depending on the size of the registers. In the current implementation, the first mapping table is stored in the first register, and the offset is stored in the fourth register.

[0102] In one implementation of this disclosure, the memory controller 106 is configured to control the memory device 104 to perform a read operation using a compensated read voltage having an offset from the default read voltage by transmitting instructions to peripheral circuits. The offset is 2 NThis correlates with the number P of memory cells in a unit that are in one or more programmed states. A TLC unit is used as an example of the current implementation (N=3), and each TLC unit has eight states. Other MLC units, such as QLC units and PLC units, can also be used in this disclosure. In a QLC unit, N=4, the memory cells of the QLC unit have 16 states, of which 15 are programmed states. In a PLC unit, N=5, the memory cells of the QLC unit have 32 states, of which 31 are programmed states. This disclosure can be applied to any MLC unit, regardless of the number of states the unit has.

[0103] Referring to Figure 10A, after data is programmed into the memory device, the number of memory cells in each of the eight states is approximately the same. The default read voltage for memory cells in different states is set to the margin between adjacent states. Taking state L7 as an example, the default read voltage for memory cells in state L7 is below the minimum threshold voltage for memory cells in state L7 and greater than the maximum threshold voltage for memory cells in state L6. Figure 10B shows the threshold voltage distribution within the same unit after a certain period of time in the memory device. As the threshold voltage decreases, the number of memory cells in each of the eight states changes slightly, but the default read voltage for read operations remains at the original level. In situations where the default read voltage is equal to the minimum threshold voltage for memory cells in state L7, read operations complete in the distribution shown in Figure 10A and fail in the distribution shown in Figure 10B. Referring to Figure 3B, if a read operation fails, error recovery is triggered to adjust the read voltage. This process can take time because the degree of threshold voltage decrease differs from unit to unit. The greater the deviation of the threshold voltage from the default read voltage, the longer the error recovery takes. A fixed offset cannot solve this problem.

[0104] To save time spent on error recovery, the charge loss of each memory unit must be accurately compensated. This means that the offset must be specifically adjusted for each unit based on the duration of each read operation after the unit has been programmed. Since charge loss accumulates and changes over time, the offset is updated periodically to accurately compensate for the charge loss. Charge loss is relatively slow compared to the speed and frequency of read operations. For example, the threshold voltage of a memory cell is unaffected up to a certain amount of accumulated lost charge, which can take a month or more. Therefore, it is not necessary to update the offset after every read operation. In this implementation, the offset can be updated periodically after a program operation. In some implementations, the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit. For example, the offset is updated monthly after a write operation.

[0105] The number of memory cells P within the unit is obtained by a verification read operation using a verification voltage. To determine the verification voltage, 2 N One or more programmed states are selected from the available states, and the default range of threshold voltages corresponding to the selected states is extracted. The verification voltage must be equal to the minimum threshold voltage of the default range of threshold voltages corresponding to the selected states, so that minor charge losses can be detected.

[0106] In this implementation, 2 N The number of selected programmed states is 1, i.e., the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2. NThe threshold voltage of the memory cell corresponding to the unselected state is higher than the threshold voltage of the memory cell. Referring to Figures 10A and 10B, eight states can be stored in the TLC unit, where L0 is the erase state and L1 through L7 are seven programmed states. The highest level, L7, is selected, and the corresponding L7 verification voltage is equal to the minimum threshold voltage of L7. In the verification read operation, the verification voltage is applied to at least some of the memory cells in the unit via the word line 318 driven by the word line driver 408. In other MLC units, such as QLC units, 16 states can be stored in the QLC unit, where L0 is the erase state and L1 through L15 are 15 programmed states. The highest level, L15, can be selected, and the corresponding L15 verification voltage is equal to the minimum threshold voltage of L15.

[0107] The principle of the verification read operation is to view the MLC unit as a single-level cell (SLC) unit; that is, memory cells with a threshold voltage higher than the verification voltage enter the first state and receive data "0" as feedback, and memory cells with a threshold voltage lower than the verification voltage enter the second state and receive data "1" as feedback. Assuming an ideal situation with no charge loss in the memory device, the number of memory cells in the first state should not change over time. However, in reality, when charge in memory cells is detrapped, the threshold voltage distribution shifts to the left, as shown in Figure 1. Therefore, when a verification read operation is performed on the memory device, the number of memory cells in the first state decreases. The more charge lost, the fewer memory cells remain in the first state. In this way, the degree of charge loss can be accurately detected, and the offset can be specially adjusted to accurately compensate for the charge loss. The first and second states are distinguished by the verification voltage of the verification read operation. Depending on the setting of the verification voltage, 2 N One or more programmed states can be selected from the available states. Typically, the highest level of memory cell is selected to improve the speed and accuracy of the verification read operation, for example, level 7 for TLC devices and level 15 for QLC devices. Once the verification voltage is determined, it is fixed and does not change in subsequent verification read operations.

[0108] When the L7 verification voltage is applied to the unit immediately after the program operation is completed, the number of memory cells P in state L7 is equal to the default number P'. Because there is a scrambler that randomizes the data pattern in each program operation, the number of memory cells in each of the eight states will be close. For example, an 18 kB NAND page has a total of 18 × 1024 × 8 = 147456 bits, and the number of memory cells in each of the eight states is 147456 / 8 = 18432 bits. For a unit containing 1 page, the number of memory cells in each of the eight states is 18432 × 1 = 18432 bits. For a unit containing 4 pages, the number of memory cells in each of the eight states is 18432 × 4 = 73728 bits. For a unit containing 8 pages, the number of memory cells in each of the eight states is 18432 × 8 = 147456 bits. In this implementation, taking a unit containing 4 pages as an example, immediately after the unit is programmed, the number of memory cells P in state L7 is equal to the default number P' of memory cells in state L7, which is 73728 bits.

[0109] As time passes, more electrons are detrapped on the cells due to charge loss. Therefore, the threshold voltage distribution shifts downward. That is, L7 shifts to the left, and the cell number P decreases. After the L7 verification voltage is applied to at least some of the memory cells in the unit, the number P is counted by the digital signal processor of the memory controller. As shown in Figure 10B, as the threshold voltage distribution shifts to the left, under the same verification voltage, the number P of memory cells in L7 will be less than the default number P'. To address the offset to compensate for charge loss, the processor 622 sends instructions to the memory cell array 301 via the backend interface 628, controlling the memory cell array 301 to count the number P of memory cells in the L7 state by performing a verification read operation. The verification voltage used in the verification read operation is the minimum threshold voltage for memory cells in the L7 state, as verified by the processor 622 as described above.

[0110] After the verification read operation is complete, the DSP624 counts a number P. In one embodiment, the DSP624 is coupled to the page buffer of the memory cell array 301 via the backend interface 628. For memory cells coupled on the same bit line, the number of memory cells and the current generated by each memory cell in the L7 state are stored in register 626, and the total current generated under the verification voltage can be tested by the page buffer, with the number of memory cells in L7 being proportional to the current tested by the page buffer.

[0111] In some implementations, each unit of one or more units contains one or more pages, and the validation read operation is performed on one or more selected pages from the one or more pages, and the number of P is 2 N This is the average number of memory cells in one or more selected pages that are in one or more programmed states. Verification read operations are performed page by page. That is, memory cells driven by the same bit line are verified with the same verification read operation. In the case of a unit containing multiple pages, verification efficiency can be improved by sampling only a portion of the pages rather than the entire set. For example, unit 1 contains 1024 pages written with the same write operation, and performing verification read operations on all 1024 pages would be time-consuming. Since charge loss is strongly related to the time elapsed since the last write operation, pages within the same unit will have a similar amount of charge loss. Therefore, to obtain a number P, it is reasonable to sample a few pages out of 1024. For example, one page is selected to perform a verification read operation. In other implementations, two or more pages can be selected to perform a verification read operation, and to reduce errors, a number P can be obtained by averaging the number of memory cells in the selected state within the selected pages.

[0112] After the number P is confirmed, processor 622 can obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P. The first mapping table can be stored in a first register of register 626. The first mapping table can also be stored in static random access memory (SRAM). Figure 11 shows an example of the first mapping table, where M corresponds to the number P. That is, if P is 2 N If M is the number of memory cells in a unit that are in one or more programmed states, then M is the number of memory cells in the unit, and P is the number of memory cells in the selected page. N If M is the number of memory cells in one or more programmed states, then M is the number of memory cells in the selected pages of the unit. In this implementation, only some, but not all, of the pages in the unit are selected for a verifying read operation, and M is 2 N This is the number of memory cells in a selected page of a unit that is in one or more programmed states. In another implementation, all pages in a unit are selected to perform a verifiable read operation, and M is 2 N This is the number of memory cells in a unit that are in one or more programmed states. In this implementation, M is the number of memory cells in the selected page that are in the L7 state immediately after the selected page is programmed, i.e., 18432. The degree of charge loss is divided into eight stages from D0 to D7 based on the number of P counted by the DSP624. As shown in Figure 11, the number P is 18340, which is less than M,

[0113]

number

[0114] If it is greater than 18340, the degree of charge loss corresponding to D0 is small and there is no need to adjust the default read voltage. The offset should be 0. A few P

[0115]

number

[0116] Smaller

[0117]

number

[0118] If it is a larger 14240, the degree of charge loss corresponding to 14240 is D2, and an offset of -120mV must be applied to the memory cell in the L7 state.

[0119]

number

[0120] Smaller

[0121]

number

[0122] If the value is greater than 3072, the degree of charge loss corresponding to 3072 is D5, and an offset of -300mV must be applied to the memory cell in the L7 state.

[0123]

number

[0124] If the value is smaller, 1120, the degree of charge loss corresponding to 3072 is D7, which means that the charge loss of the unit is too severe to be compensated for, and therefore the data stored in the unit needs to be rearranged.

[0125] For memory cells exhibiting similar charge loss, the higher the threshold voltage of the memory cell, the more severe the threshold drop. Therefore, the offset must be adjusted based on the default threshold voltage of the memory cell, and the adjusted offset of the memory cells within a unit is positively correlated with the default threshold voltage of the memory cell. For example, in the case of a D2 degree charge loss, the offset of a memory cell in the L7 state should be -120mV, the offset of a memory cell in the L4 state should be -60mV, and the offset of a memory cell in the L1 state should be -20mV. Figure 12 shows the relationship between the offset and charge loss of memory cells in different states. For other MLC devices, such as QLC devices, the relationship between the offset and charge loss of memory cells in various states shows a similar trend to that shown in Figure 12.

[0126] After the unit offsets are obtained, they are stored in an index table as shown in Figure 13. Different units have different degrees of charge loss, and therefore different offsets. For example, the degree of charge loss for unit 1 is D0, which means that the memory cells in unit 1 do not experience charge loss, and the offset for each memory cell in unit 1 is 0. The degree of charge loss for unit 2 is D5, which means that the memory cells in unit 2 experience significant, though not fatal, charge loss, and therefore require an offset. Referring to Figure 13, for the memory cells of unit 2, the offset for level 1 memory cells is -130mV, the offset for level 3 memory cells is -200mV, and the offset for level 7 memory cells is -300mV. If the degree of charge loss for a unit is D7, this means that the memory cells in the unit experience significant and fatal charge loss, and it may not be possible to read the data correctly, as in unit 3, and the data in unit 3 needs to be rearranged. The index table in Figure 13 is stored in a register or SRAM and is updated periodically by performing a verification read operation. The system accesses the index table for each read operation to retrieve the corresponding offset, thus avoiding read errors. Therefore, the time required to access the index table becomes negligible, significantly improving the efficiency of the memory device.

[0127] Figure 9B shows another implementation of the present disclosure, in which the numerical difference ΔP between a number P and a default number P' is calculated. The default number P' is 2 after the completion of the program operation. NThis is the number of memory cells in a unit that are in one or more programmed states. As described above, in a unit containing 4 18kB NAND pages, the number of memory cells P in state L7 is equal to the default number P' of memory cells in state L7, which is 73728 bits. In this implementation, the processor 622 is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the difference in the number ΔP, and a second mapping table between the offset and the difference in the number ΔP. The second mapping table is stored in a second register of register 626, and the default number P' is stored in a third register of register 626. The memory controller 106 further includes a computer 629 coupled to the processor 622 and the DSP 624. The computer 629 is configured to calculate the difference in the number ΔP based on the default number P' stored in the third register and the number P obtained by the DSP 624. The difference in the number ΔP is then sent to the processor 622, and the offset is determined based on the difference in the number ΔP and the second mapping table. The numerical difference ΔP used in this implementation has the same function as the number P in the implementation described above, that is, it reflects the charge loss due to the change in the numerical value under the selected conditions. Although the approaches to calculating the numerical difference ΔP and the number P are different, both can be implemented in multiple ways. The implementation described above is illustrative and should not be construed as limiting this disclosure.

[0128] Figures 14A and 14B illustrate several implementations of this disclosure in which four programmed states are selected instead of one to reflect a change in the number P. The verification voltage is set as the minimum threshold voltage of the memory cells in all states from L4 to L7, i.e., the minimum threshold voltage of the memory cell in state L4. The memory cells from state L4 to L7 are in the first state, and when the verification voltage is applied, the data "0" is fed back. As the threshold voltage distribution shifts due to charge loss, the number P of the memory cells decreases under the verification voltage, as shown in Figure 14B. Thus, the offset can be specially adjusted based on the number P. The verification read operation is the same as described above and will not be repeated here.

[0129] The memory system of this disclosure can detect the exact degree of charge loss and can specially adjust the offset to compensate for charge loss during read operations. Therefore, error recovery is avoided, and the time required for each read operation is significantly reduced. The performance of the memory system is greatly improved.

[0130] Figures 9A and 9B show different implementation configurations of the memory controller 106 coupled to the memory cell array 301, as shown in Figure 7. Each memory cell corresponds to 2 N bits of data. N It is set to one of the states, where N is an integer greater than 1, and the array of memory cells is divided into one or more units.

[0131] In Figure 9A, the memory controller 106 is coupled to the memory device to address the aforementioned problem. The memory controller 106 is coupled to the memory cell array 301, and when it executes an instruction, it receives 2 from the memory cell array 301. NThe memory controller is configured to obtain the number P of memory cells in one of a plurality of units that are in one or more programmed states, calculate a compensated read voltage with an offset from the default read voltage based on the number P, and provide the memory device with the compensated read voltage for a read operation performed on a selected memory cell in one of the plurality of units. Referring to Figure 9A, the memory controller 106 includes a processor 622 and a DSP 624 coupled to a backend interface 628. The processor 622 is configured to control the memory cell array 301 to count the number P of memory cells in a unit by performing a verification read operation. The DSP 624 is configured to count the number P after a verification voltage has been applied to at least some of the memory cells in the unit. The memory controller 106 further includes a register 626 configured to store a first mapping table and an offset. The first mapping table and the offset can be stored in the same register or in different registers, depending on the size of the register. In this implementation, the first mapping table is stored in a first register and the offset is stored in a fourth register. In Figure 9B, the memory controller further includes a computer 629 coupled to processor 622 and DSP 624. The numerical difference ΔP is then sent to processor 622, and an offset is determined based on the numerical difference ΔP and a second mapping table. The numerical difference ΔP used in this implementation has the same function as the number P in the implementation described above, that is, it reflects the charge loss due to the change in the numerical value in the selected state.

[0132] Figure 9B shows another implementation of the present disclosure, in which the numerical difference ΔP between a number P and a default number P' is calculated. The default number P' is calculated after the program operation is complete. NThis is the number of memory cells in a unit that are in one or more programmed states. The processor 622 is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the difference in numbers ΔP and a second mapping table between the offset and the difference in numbers ΔP. ​​The second mapping table is stored in a second register of register 626, and the default number P' is stored in a third register of register 626. The memory controller 106 further includes a computer 629 coupled to the processor 622 and the DSP 624. The computer 629 is configured to calculate the difference in numbers ΔP based on the default number P' stored in the third register and the number P obtained by the DSP 624. The difference in numbers ΔP is then sent to the processor 622, and the offset is determined based on the difference in numbers ΔP and the second mapping table. The difference in numbers ΔP used in this implementation has the same function as the number P in the implementation described above, i.e., it reflects the charge loss due to the change in the number in the selected state. The approaches to calculating the difference in numbers ΔP and the number P are different, but both can be implemented in multiple ways. The implementations described above are illustrative and should not be construed as limiting the scope of this disclosure.

[0133] In some implementations of this disclosure, an offset that can accurately compensate for charge loss may be provided by the memory device without the involvement of a memory controller. As shown in Figure 7, the memory device 104 includes an array of memory cells 301 and peripheral circuits 302. Each memory cell corresponds to one N-bit data. N The array of memory cells 301 is configured to be set to one of the states, where N is an integer greater than 1, and the array of memory cells 301 is divided into one or more units. Peripheral circuits 302 are coupled to the memory cells and configured to perform read operations on selected memory cells among the memory cells of the unit using a compensated read voltage with an offset from the default read voltage. The offset is 2 N It correlates with the number P of memory cells in a unit that are in one or more programmed states.

[0134] Taking a TLC device as an example, as shown in Figures 10A and 10B, the TLC unit can store eight states, with L0 being the erase state and L1 through L7 being the seven program states. In this implementation, 2 N The number of selected programmed states is one, i.e., the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2 N The threshold voltage for the memory cell corresponding to the unselected state is higher. The highest level, L7, is selected, and the corresponding L7 verification voltage becomes equal to the minimum threshold voltage for L7. In a verification read operation, the verification voltage is applied to at least some of the memory cells in the unit via word line 318, driven by word line driver 408. When the L7 verification voltage is applied to the unit immediately after the program operation is completed, the number of memory cells P in the L7 state becomes equal to the default number P'. Because there is a scrambler that randomizes the data pattern in each program operation, the number of memory cells in each of the eight states will be close. For example, an 18kB NAND page has a total of 18 × 1024 × 8 = 147456 bits, and the number of memory cells in each of the eight states is 147456 / 8 = 18432 bits. For a unit containing 1 page, the number of memory cells in each of the eight states is 18432 × 1 = 18432 bits. For a unit containing 4 pages, the number of memory cells in each of the eight states is 18432 × 4 = 73728 bits. For a unit containing 8 pages, the number of memory cells in each of the 8 states is 18432 × 8 = 147456 bits. In this embodiment, taking a unit containing 4 pages as an example, immediately after the unit is programmed, the number of memory cells P in state L7 is equal to the default number P' for state L7 memory cells, which is 73728 bits.

[0135] As time passes, more electrons are detrapped on the cells due to charge loss. Therefore, the threshold voltage distribution shifts downward, i.e., L7 shifts to the left, and the cell number P decreases. After the L7 verification voltage is applied to at least some of the memory cells in the unit, the number P is counted by the computer of the peripheral circuit 302. As shown in Figure 10B, as the threshold voltage distribution shifts to the left, under the same verification voltage, the number P of memory cells in L7 will be less than the default number P'. To address the offset in order to compensate for charge loss, the control logic 412 sends an instruction to the memory cell array 301, controlling it to count the number P of memory cells in the L7 state by performing a verification read operation. The verification voltage used in the verification read operation is verified by the control logic 412 as described above, i.e., the minimum threshold voltage for memory cells in the L7 state.

[0136] After the verification read operation is complete, the page buffer counts a number P. For memory cells coupled on the same bit line, the number of memory cells and the current generated by each memory cell in the L7 state are stored in register 414, and the total current generated under the verification voltage can be tested by the page buffer, and the number of memory cells in L7 is proportional to the current tested by the page buffer. In some implementations, each unit of one or more units contains one or more pages, and the verification read operation is performed on one or more selected pages from the one or more pages, and the number P is 2 NThis is the average number of memory cells in one or more selected pages that are in one or more programmed states. Verification read operations are performed page by page, meaning that memory cells driven by the same bit line are verified with the same verification read operation. For units containing multiple pages, verification efficiency is improved by sampling only a portion of the pages rather than the entire set. For example, unit 1 contains 1024 pages written with the same write operation, and performing verification read operations on all 1024 pages would be time-consuming. Since charge loss is strongly related to the time elapsed since the last write operation, pages within the same unit will have a similar amount of charge loss. Therefore, to obtain a number P, it is reasonable to sample a few pages out of 1024. For example, one page is selected to perform a verification read operation. In other implementations, two or more pages can be selected to perform a verification read operation, and to reduce errors, a number P can be obtained by averaging the number of memory cells in the selected state within the selected pages.

[0137] After the number P is confirmed, the control logic 412 can obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P. The first mapping table is stored in the first register of register 414. Figure 11 shows an example of the first mapping table, where M is 2 N This is the number of memory cells in one of several units that are in one or more programmed states. In this implementation, M is the number of memory cells in a unit that is in the L7 state immediately after the unit is programmed, i.e., 18432. The degree of charge loss is divided into eight stages from D0 to D7 based on the number P counted by the page buffer. As shown in Figure 11, if the number P is smaller than M...

[0138]

number

[0139] If it is a larger 18340, the degree of charge loss corresponding to the 18340 is D0, which is small, and there is no need to adjust the default read voltage, and the offset should be 0.

[0140]

number

[0141] Smaller

[0142]

number

[0143] If it is a larger 14240, the degree of charge loss corresponding to 14240 is D2, and an offset of -120mV must be applied to the memory cell in the L7 state.

[0144]

number

[0145] Smaller

[0146]

number

[0147] If the value is greater than 3072, the degree of charge loss corresponding to 3072 is D5, and an offset of -300mV must be applied to the memory cell in the L7 state.

[0148]

number

[0149] For the smaller 1120, the degree of charge loss corresponding to 3072 is D7, which means that the charge loss of the unit is too severe to be compensated for, and therefore the data stored in the unit needs to be rearranged.

[0150] For memory cells exhibiting similar charge loss, the higher the threshold voltage of the memory cell, the more severe the threshold drop. Therefore, the offset must be adjusted based on the default threshold voltage of the memory cell, and the adjusted offset of the memory cells within a unit is positively correlated with the default threshold voltage of the memory cell. For example, for a charge loss of approximately D2, the offset of a memory cell in the L7 state should be -120mV, the offset of a memory cell in the L4 state should be -60mV, and the offset of a memory cell in the L1 state should be -20mV. Figure 12 shows the relationship between the offset and the charge loss of memory cells in various states. For other MLC devices, such as QLC devices, the relationship between the offset and the charge loss of memory cells in various states shows a similar trend to that shown in Figure 12.

[0151] After the unit offsets are obtained, they are stored in an index table as shown in Figure 13. Different units have different degrees of charge loss, and therefore different offsets. For example, the degree of charge loss for unit 1 is D0, which means that the memory cells in unit 1 experience no charge loss, and the offset for each memory cell in unit 1 is 0. A degree of charge loss for unit 2 is D5, which means that the memory cells in unit 2 experience significant, though not fatal, charge loss, and require an offset. Referring to Figure 13, for the memory cells in unit 2, the offset for level 1 memory cells is -130mV, the offset for level 3 memory cells is -200mV, and the offset for level 7 memory cells is -300mV. If the degree of charge loss for a unit is D7, this means that the memory cells in the unit experience significant and fatal charge loss, and it may not be possible to read the data correctly, as in unit 3, and the data in unit 3 needs to be rearranged. The index table in Figure 13 is stored in a register or SRAM and is updated periodically by performing a verification read operation. By accessing the index table for each read operation to obtain the corresponding offset, read errors are avoided, and therefore the time required to access the index table becomes negligible, significantly improving the efficiency of the memory device.

[0152] In another implementation of this disclosure, the numerical difference ΔP between a number P and a default number P' is calculated. The default number P' is calculated after the program execution is complete. NThis is the number of memory cells in a unit that is in one or more programmed states. As described above, in a unit containing 4 18kB NAND pages, the number of memory cells P in state L7 is equal to the default number P' of memory cells in state L7, i.e., 73728 bits. In this implementation, the control logic 412 is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP. The second mapping table is stored in a second register of register 414, and the default number P' is stored in a third register of register 414. The control logic 412 further includes a computer configured to calculate the number difference ΔP based on the default number P' stored in the third register and the obtained number P. The offset is then determined using the number difference ΔP and the second mapping table. The number difference ΔP used in this implementation has the same function as the number P in the implementation described above, i.e., it reflects the charge loss due to the change in the numerical value in the selected state. While the approaches to calculating the difference ΔP and the number P differ, both can be implemented in multiple ways. The implementations described above are illustrative and should not be construed as limiting the scope of this disclosure.

[0153] Figure 15 shows a flowchart of a method 1500 for operating a memory device according to several aspects of this disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 104. Memory device 104 corresponds to 2 N-bit data. NMethod 1500 includes an array of memory cells 301 configured to be set to one of the states, where N is an integer greater than 1, and the array of memory cells 301 is divided into one or more units. Method 1500 may be implemented by peripheral circuits 302 such as a row decoder / word line driver 408, a voltage generator 410, control logic 412, and registers 414. Method 1500 may be implemented by a memory controller 106 such as a processor 622, a DSP 624, and registers 626. The operations shown in Method 1500 may not be exhaustive, and it should be understood that other operations may also be performed before, after, or between any of the illustrated operations. Furthermore, some operations may be performed simultaneously, or in an order different from the order shown in Figure 15.

[0154] Referring to Figure 15, Method 1500 begins with Operation 1502, 2 N The number P of memory cells in the unit that are in one or more programmed states is obtained. Taking a TLC device as an example, referring to Figures 10A and 10B, eight states can be stored in the TLC unit, with L0 being the erase state and L1 to L7 being the seven programmed states. In this implementation, 2 N The number of selected programmed states is 1, i.e., the minimum threshold voltage in the default range of threshold voltages corresponding to the selected state is 2. NThe threshold voltage for the memory cell corresponding to the unselected state is higher. The highest level, L7, is selected, and the corresponding L7 verification voltage becomes equal to the minimum threshold voltage for L7. In a verification read operation, the verification voltage is applied to at least some of the memory cells in the unit via word line 318, driven by word line driver 408. When the L7 verification voltage is applied to the unit immediately after the program operation is completed, the number of memory cells P in the L7 state becomes equal to the default number P'. Because there is a scrambler that randomizes the data pattern in each program operation, the number of memory cells in each of the eight states will be close. For example, an 18kB NAND page has a total of 18 × 1024 × 8 = 147456 bits, and the number of memory cells in each of the eight states is 147456 / 8 = 18432 bits. For a unit containing 1 page, the number of memory cells in each of the eight states is 18432 × 1 = 18432 bits. For a unit containing 4 pages, the number of memory cells in each of the eight states is 18432 × 4 = 73728 bits. For a unit containing 8 pages, the number of memory cells in each of the 8 states is 18432 × 8 = 147456 bits. In this implementation, taking a unit containing 4 pages as an example, immediately after the unit is programmed, the number of memory cells P in state L7 is equal to the default number P' of memory cells in state L7, which is 73728 bits.

[0155] Over time, charge loss causes more electrons to be detrapped on the cell. Consequently, the threshold voltage distribution shifts downward, i.e., L7 shifts to the left, and the cell number P decreases. The number P is counted after the L7 verification voltage is applied to at least some of the memory cells in the unit. As shown in Figure 10B, as the threshold voltage distribution shifts to the left, under the same verification voltage, the number P of memory cells in L7 will be less than the default number P'. To address the offset and compensate for charge loss, a verification read operation is performed. The verification voltage used in the verification read operation is verified as described above, i.e., the minimum threshold voltage of memory cells in the L7 state.

[0156] Once the verification read operation is complete, the page buffer counts a number P. For memory cells coupled on the same bit line, the number of memory cells and the current generated by each memory cell in the L7 state are stored in a register. The total current generated under the verification voltage can be tested in the page buffer, and the number of memory cells in L7 is proportional to the current tested in the page buffer. In some implementations, each unit of one or more units contains one or more pages, and the verification read operation is performed on one or more selected pages from the one or more pages, and the number P is 2 N This is the average number of memory cells in one or more selected pages that are in one or more programmed states. Verification read operations are performed page by page, meaning that memory cells driven by the same bit line are verified with the same verification read operation. For units containing multiple pages, verification efficiency is improved by sampling only a portion of the pages rather than the entire set. For example, unit 1 contains 1024 pages written with the same write operation, and performing verification read operations on all 1024 pages would be time-consuming. Since charge loss is strongly related to the time elapsed since the last write operation, pages within the same unit will have a similar amount of charge loss. Therefore, to obtain a number P, it is reasonable to sample a few pages out of 1024. For example, one page is selected to perform a verification read operation. In other implementations, two or more pages can be selected to perform a verification read operation, and to reduce errors, a number P can be obtained by averaging the number of memory cells in the selected state within the selected pages.

[0157] Method 1500 proceeds to operation 1504 as shown in Figure 15, where a compensated read voltage with an offset from the default read voltage is obtained. After the number P is confirmed, the offset is obtained through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P. The first mapping table is stored in a first register of the registers. Figure 11 shows an example of the first mapping table, where M corresponds to the number P. That is, if P is 2 N If M is the number of memory cells in a unit that is in one or more programmed states, then M is the number of memory cells in the unit and P is 2 N If M is the number of memory cells in a selected page that are in one or more programmed states, then M is the number of memory cells in the selected page of the unit. In this implementation, only some, but not all, of the pages in the unit are selected to perform a verifying read operation, then M is 2 N This is the number of memory cells in a selected page within one of several units that are in one or more programmed states. In another implementation, all pages within a unit are selected to perform a verifiable read operation, and M is 2 N This is the number of memory cells in a unit that are in one or more programmed states. In this implementation, M is the number of memory cells in the selected page that are in the L7 state immediately after the selected page is programmed, i.e., 18432. The degree of charge loss is divided into eight stages from D0 to D7 based on the number of P counted by the page buffer. As shown in Figure 11, if the number P is smaller than M...

[0158]

number

[0159] If it is a larger 18340, the degree of charge loss corresponding to the 18340 is D0, which is small and does not require adjustment of the default read voltage and the offset should be 0.

[0160]

number

[0161] Smaller

[0162]

number

[0163] If it is a larger 14240, the degree of charge loss corresponding to 14240 is D2, and an offset of -120mV must be applied to the memory cell in the L7 state.

[0164]

number

[0165] Smaller

[0166]

number

[0167] If the value is greater than 3072, the degree of charge loss corresponding to 3072 is D5, and an offset of -300mV must be applied to the memory cell in the L7 state.

[0168]

number

[0169] If the value is smaller, 1120, the degree of charge loss corresponding to 3072 is D7, which means that the charge loss of the unit is too severe to be compensated for, and therefore the data stored in the unit needs to be rearranged.

[0170] For memory cells exhibiting similar charge loss, the higher the threshold voltage of the memory cell, the more severe the threshold drop. Therefore, the offset must be adjusted based on the default threshold voltage of the memory cell, and the adjusted offset of the memory cells within a unit is positively correlated with the default threshold voltage of the memory cell. For example, for a charge loss of approximately D2, the offset of a memory cell in the L7 state should be -120mV, the offset of a memory cell in the L4 state should be -60mV, and the offset of a memory cell in the L1 state should be -20mV. Figure 12 shows the relationship between the offset and the charge loss of memory cells in various states. For other MLC devices, such as QLC devices, the relationship between the offset and charge loss of memory cells in various states shows a similar trend to that shown in Figure 12.

[0171] In another implementation of this disclosure, the numerical difference ΔP between a number P and a default number P' is calculated. The default number P' is calculated after the program execution is complete. NThis is the number of memory cells in a unit that are in one or more programmed states. As described above, in a unit containing 4 18kB NAND pages, the number of memory cells P in state L7 is equal to the default number P' of memory cells in state L7, which is 73728 bits. In this implementation, the offset is obtained through a lookup operation by looking up the offset corresponding to the difference in numbers ΔP and a second mapping table between the offset and the difference in numbers ΔP. ​​The second mapping table is stored in a second register of several registers, and the default number P' is stored in a third register of several registers. Next, the difference in numbers ΔP is calculated based on the default number P' stored in the third register and the obtained number P. Then, the difference in numbers ΔP is used to determine the offset based on the difference in numbers ΔP and the second mapping table. The difference in numbers ΔP used in this implementation has the same function as number P in the implementation described above, that is, it reflects the charge loss due to the change in numbers in the selected state. The approaches to calculating the difference in numbers ΔP and number P are different, but both can be implemented in multiple ways. The implementations described above are illustrative and should not be construed as limiting the scope of this disclosure.

[0172] Method 1500 proceeds to operation 1506, as shown in Figure 15, in which a read operation is performed on a selected memory cell among the memory cells in the unit using a compensated read voltage.

[0173] By treating MLC units as single-level cell (SLC) units and performing a verification read operation to confirm the actual charge loss of a particular unit, this disclosure allows for the confirmation of a customized offset to compensate for the default read voltage of a read operation. Error recovery is avoided, and the time required for each read operation is significantly reduced. The performance of the memory system is greatly improved.

[0174] The foregoing descriptions relating to specific implementations can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to be equivalent in meaning and scope to the disclosed implementations, based on the teachings and guidance presented herein.

[0175] The scope and breadth of this disclosure should not be limited by any of the embodiments described above, but should be defined solely in accordance with the following claims and their equivalents.

[0176] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with the scope of this disclosure.

[0177] [1] A memory system, An array of memory cells, where each memory cell corresponds to 2 bits of data. N A memory cell array configured to be set to one of the states, where N is an integer greater than 1, and the memory cell array is divided into one or more units, A peripheral circuit coupled to the memory cell and configured to perform a read operation on a selected memory cell within one of the plurality of units, A memory device including, A memory controller coupled to the memory device and configured to control the memory device to perform the read operation using a compensated read voltage having an offset from the default read voltage by transmitting commands to the peripheral circuitry, Equipped with, The offset is the 2 NThe number P of memory cells in the unit that are in one or more programmed states is correlated with the number of such memory cells. Memory system. [2] The memory system according to [1], wherein the offset is associated with the unit and updated after the number P of memory cells in the unit changes. [3] The memory system described in [2], wherein the offset is updated periodically. [4] The memory system according to [3], wherein the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit. [5] The memory system according to [1], wherein the number P is obtained through a verification read operation configured to count the number P of a memory cell in the unit. [6] The memory controller, The above 2 N Select one or more programmed states from the available states. Based on the default range of threshold voltages corresponding to the selected one or more states, the verification voltage used in the verification readout operation is determined. It is configured in such a way, The verification voltage is equal to the minimum threshold voltage of the default range of the threshold voltages corresponding to the selected one or more states. The memory system described in [5]. [7] The above 2 N The number of the selected one or more programmed states is 1. The minimum threshold voltage of the default range of the threshold voltage corresponding to the selected state is the 2 N Higher than the threshold voltage of the memory cell corresponding to the non-selected state among the states, The memory system described in [6]. [8] The memory system according to [6], further comprising a word line driver configured to apply the verification voltage to at least a portion of the memory cells in the unit via a word line, the peripheral circuit. [9] The memory system according to [8], wherein the memory controller comprises a digital signal processor configured to count the number P after the verification voltage has been applied to at least a portion of the memory cells in the unit.

[10] Each unit of the one or more units includes one or more pages, the verification read operation is performed on one or more selected pages from the one or more pages, and the number P is the 2 N The memory system according to [5], wherein the average number of memory cells in one or more selected pages is in one or more programmed states.

[11] The memory system according to [1], comprising a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P.

[12] The memory system according to

[11] , wherein the memory controller comprises a first register configured to store the first mapping table.

[13] The memory controller includes a digital signal processor configured to calculate the numerical difference ΔP between the number P and a default number P', wherein the default number P' is determined after the program operation is complete. N The memory system according to [1], wherein the number of memory cells in the unit is in one or more programmed states among the states.

[14] The memory system according to

[13] , comprising a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the difference ΔP of the number and a second mapping table between the offset and the difference ΔP of the number.

[15] The memory system according to

[14] , wherein the memory controller comprises a second register configured to store the second mapping table.

[16] The memory system according to

[14] , wherein the memory controller comprises a third register configured to store the default number P'.

[17] The memory system according to any one of

[11] to

[16] , wherein the processor is configured to adjust the offset for memory cells in the unit based on a default threshold voltage of the memory cells.

[18] The memory system according to

[17] , wherein the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell.

[19] The memory system according to

[11] or

[14] , wherein the memory controller comprises a fourth register configured to store the offset obtained by the processor.

[20] The memory system according to

[19] , wherein the processor is configured to obtain the offset from a fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

[21] A memory controller coupled to a memory device having an array of memory cells, wherein each memory cell corresponds to 2 bits of data N It is set to one of the states, N is an integer greater than 1, the array of memory cells is divided into one or more units, and the memory controller is coupled to the memory device. When executing an instruction, From the memory device, the 2 N Obtain the number of memory cells P in one of the plurality of units that are in one or more programmed states, Based on the aforementioned number P, a compensated read voltage with an offset from the default read voltage is calculated. The memory device is provided with the compensated read voltage for a read operation performed on a selected memory cell among the memory cells in one of the plurality of units. It is structured in such a way. Memory controller.

[22] The memory controller according to

[21] , wherein the offset is associated with the unit and updated after the number P of memory cells in the unit is changed.

[23] The memory controller described in

[22] , wherein the offset is updated periodically.

[24] The memory controller according to

[23] , wherein the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[25] The memory controller according to

[21] , further comprising a processor configured to control the memory device to count the number P of memory cells in the unit by performing a verification read operation.

[26] The processor The above 2 N Select one or more programmed states from the available states. Based on the default range of threshold voltages corresponding to the selected one or more states, the verification voltage used in the verification readout operation is determined. It is configured in such a way, The verification voltage is equal to the minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states. The memory controller described in

[25] .

[27] The above 2 N The number of the selected one or more programmed states is 1. The minimum threshold voltage of the default range of the threshold voltage corresponding to the selected state is the 2 N Higher than the threshold voltage of the memory cell corresponding to the non-selected state among the states, The memory controller described in

[26] .

[28] The memory controller according to

[27] , further comprising a digital signal processor configured to count the number P after the verification voltage has been applied to at least a portion of the memory cells in the unit.

[29] Each unit of the one or more units includes one or more pages, the verification read operation is performed on one or more selected pages from the one or more pages, and the number P is the 2 N The memory system according to

[25] , wherein the average number of memory cells in one or more selected pages is in one or more programmed states.

[30] The memory controller according to

[21] , comprising a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P.

[31] The memory controller according to

[30] , further comprising a first register configured to store the first mapping table.

[32] The memory controller includes a digital signal processor configured to calculate the numerical difference ΔP between the number P and a default number P', wherein the default number P' is determined after the program operation is complete. N The memory controller according to

[21] , wherein the number of memory cells in the unit is in one or more programmed states among the states.

[33] The memory controller according to

[32] , comprising a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the difference ΔP of the number and a second mapping table between the offset and the difference ΔP of the number.

[34] The memory controller according to

[33] , further comprising a second register configured to store the second mapping table.

[35] The memory controller according to

[33] , further comprising a third register configured to store the default number P'.

[36] The memory controller according to

[30] or

[33] , wherein the processor is configured to adjust the offset for memory cells in the unit based on a default threshold voltage of the memory cells.

[37] The memory controller according to

[36] , wherein the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell.

[38] The memory controller according to

[30] or

[33] , further comprising a fourth register configured to store the offset obtained by the processor.

[39] The memory controller according to

[38] , wherein the processor is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

[40] A memory device, An array of memory cells, where each memory cell corresponds to 2 bits of data. N A memory cell array configured to be set to one of the states, where N is an integer greater than 1, and the memory cell array is divided into one or more units, A peripheral circuit coupled to the memory cell and configured to perform a read operation on a selected memory cell among the memory cells in one of the plurality of units using a compensated read voltage having an offset from the default read voltage, Equipped with, The offset is the 2 N The number P of memory cells in the unit that are in one or more programmed states is correlated with the number of such memory cells. Memory device.

[41] The memory device according to

[40] , wherein the offset is associated with the unit and updated after the number P of memory cells in the unit changes.

[42] The memory device according to

[41] , wherein the offset is updated periodically.

[43] The memory device according to

[42] , wherein an update period is not more than a minimum interval between two adjacent programming operations executed on the unit.

[44] The memory device according to

[40] , wherein the number P is obtained through a verification read operation configured to count the number P of memory cells in the unit.

[45] The peripheral circuit selects one or more programmed states of the two N states, and determines a verification voltage used in the verification read operation based on a default range of threshold voltages corresponding to the selected one or more states, and is configured such that the verification voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states, The memory device according to

[44] .

[46] The number of the selected one or more programmed states of the two N is 1, and the minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is higher than a threshold voltage of a memory cell corresponding to a non - selected state of the two N states, The memory device according to

[45] .

[47] The memory device according to

[45] , wherein the peripheral circuit includes a word - line driver configured to apply the verification voltage to at least a part of the memory cells in the unit via a word line.

[48] The memory device according to

[47] , wherein the peripheral circuit includes a computer configured to calculate the number P after the verification voltage is applied to at least a part of the memory cells in the unit.

[49] Each unit of the one or more units includes one or more pages, the verification read operation is performed on one or more selected pages of the one or more pages, and the number P is the two NThe average number of memory cells in one or more selected pages that are in one or more programmed states, The memory device described in

[44] .

[50] The memory device according to

[40] , wherein the peripheral circuit is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P.

[51] The memory device according to

[50] , wherein the peripheral circuit comprises a first register configured to store the first mapping table.

[52] The peripheral circuit includes a computer configured to calculate the difference ΔP between the number P and a default number P', and the default number P' is determined after the program operation is completed. N The memory device according to

[50] , wherein the number of memory cells in the unit is in one or more programmed states among the states.

[53] The memory device according to

[52] , wherein the control logic is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the difference ΔP of the numbers and a second mapping table between the offset and the difference ΔP of the numbers.

[54] The memory device according to

[53] , wherein the peripheral circuit comprises a second register configured to store the second mapping table.

[55] The memory device according to

[53] , wherein the peripheral circuit comprises a third register configured to store the default number P'.

[56] The memory device according to

[50] or

[53] , wherein the control logic is configured to adjust the offset for memory cells in the unit based on a default threshold voltage of the memory cells.

[57] The memory device according to

[56] , wherein the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell.

[58] The memory device according to

[50] or

[53] , wherein the peripheral circuit comprises a fourth register configured to store the offset obtained by the control logic.

[59] The memory device according to

[58] , wherein the control logic is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

[60] 2 corresponding to one N-bit data N A method for reading a memory device comprising an array of memory cells configured to be set to one of the states, wherein N is an integer greater than 1, and the array of memory cells is divided into one or more units, and the method The above 2 N A step of obtaining the number P of memory cells in a unit that are in one or more programmed states, A step of calculating a compensated read voltage with an offset from the default read voltage, The steps include: performing a read operation on a selected memory cell among the memory cells in the unit using the compensated read voltage; Methods that include...

[61] The method of

[60] , further comprising the step of updating the offset after the number of memory cells P in the unit has been changed, after calculating the compensated read voltage.

[62] The method according to

[61] , wherein the offset is updated periodically.

[63] The method according to

[62] , wherein the update cycle is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[64] The method according to

[60] , wherein the number P of memory cells in the unit is calculated by performing a verification read operation. The step of performing the verification read operation includes selecting one or more programmed states out of the two N states; and determining a verification voltage to be used in the verification read operation based on a default range of threshold voltages corresponding to the selected one or more states, and the verification voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states, the method according to

[64] .

[66] The number of the selected one or more programmed states of the two N is 1, and the minimum threshold voltage of the default range of the threshold voltage corresponding to the selected state is higher than the threshold voltage of a memory cell corresponding to a non-selected state among the two N states, the method according to

[65] .

[67] Each unit of the one or more units includes one or more pages, the verification read operation is performed on one or more selected pages among the one or more pages, and the number P is an average number of memory cells in the one or more selected pages in one or more programmed states among the two N states, the method according to

[64] .

[68] The step of calculating the compensated read voltage having the offset includes looking up an offset corresponding to the number P and a first mapping table between the offset and the number P, the method according to

[66] . ​​​​The method according to

[66] , wherein the number of memory cells in the unit is in one or more programmed states among the states.

[71] The method according to

[70] , wherein the step of calculating the compensated read voltage having the offset further includes the step of looking up the offset corresponding to the difference ΔP of the numbers, and a second mapping table between the offset and the difference ΔP of the numbers.

[72] The method according to

[71] , wherein the second mapping table is stored in a second register.

[73] The method according to

[71] , wherein the default number P' is stored in a third register.

[74] The method according to

[67] or

[71] , further comprising the step of calculating the compensated read voltage having the offset and then adjusting the offset based on a default threshold voltage of the memory cell.

[75] The method of

[74] wherein the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell.

[76] The method according to

[74] , comprising the step of storing the adjusted offset in a fourth register.

[77] The step of determining the compensated read voltage is: The steps include obtaining the offset from the fourth register and A step of calculating the compensated read voltage by adding the offset to the default read voltage, The method described in

[76] , including the method described in

[76] . [Explanation of Symbols]

[0178] 100 Systems 104 Memory Devices 106 Memory Controller 108 hosts 202 memory card 204 Memory card connector 206 SSD 208 SSD connectors 300 Memory device 301 Memory cell array 302 Peripheral circuit 304 Block 306 Memory cell 308 NAND memory string 310 SSG 312 DSG 313 DSG line 314 Source line 315 SSG line 316 Bit line 318 Word line 320 Page 404 Page buffer / sense amplifier 406 Column decoder / bit line driver 408 Row decoder / word line driver 410 Voltage generator 412 Control logic 414 Register 416 Interface 418 Data bus 500 Memory system 510 Peripheral Component Interconnect Express (PCIe) layer [ 520 Non-Volatile Memory Express (NVMe) layer 530 NAND Controller Interface (NFI) layer 540 Processing unit 550 Read Only Memory (ROM) 560 DRAM controller 570 Dynamic Random Access Memory (DRAM) 622 Processor 624 Digital Signal Processor (DSP) 626 Register 628 Back-end interface 629 Computer

Claims

1. It is a memory system, An array of memory cells divided into one or more units, wherein each memory cell in one unit stores N bits of data, and the two corresponding to the N bits of data Ｎ An array of memory cells configured to be set to one of the states, where N is an integer greater than 1. A memory device including, The memory device is coupled to the aforementioned memory device, Controlling the memory device to perform a verifier read operation with a single voltage in at least a portion of the memory cells within a single unit; Determining a voltage offset based on a predetermined relationship between the result of the verification read operation and the value of the voltage offset, wherein the result of the verification read operation determines a number P of memory cells in at least a portion of the memory cells in one unit, the number of which has a threshold voltage equal to or less than the single voltage; and Controlling the memory device to perform a read operation using a compensated read voltage determined based on the voltage offset by sending a command to the memory device; A memory controller configured to perform the following actions: A memory system equipped with the following features.

2. The memory system according to claim 1, wherein each of the one or more units has a corresponding voltage offset.

3. The memory system according to claim 1, wherein the memory controller is configured to control the memory device to periodically perform the verification read operation with the single voltage in order to update the voltage offset.

4. The above 2 Ｎ The state is distinguished by the (N-1) level readout voltage. The memory system according to claim 2, wherein the memory controller is configured to determine a voltage offset corresponding to each level of read voltage based on the pre-set relationship between the result of the verification read operation and the value of the voltage offset.

5. The memory system according to claim 4, wherein the single voltage is one of the (N-1) level read voltages.

6. The memory system according to claim 5, wherein the single voltage is the highest voltage in the (N-1) level read voltage.

7. Each of the one or more units mentioned above includes one or more pages, The verification read operation is performed on one or more selected pages from the one or more pages. The memory system according to claim 1, wherein the number P is the average number of memory cells in one or more selected pages whose threshold voltage is greater than or equal to the single voltage, or less than the single voltage.

8. The aforementioned memory controller The voltage offset is determined based on a first mapping table that includes a mapping relationship between the value of the number P and the voltage offset value. The memory system according to claim 1, configured as described above.

9. The memory controller is configured to calculate a numerical difference ΔP between the number P and a default number P', wherein the default number P' is equal to the number of memory cells, at least a portion of the memory cells in one unit, whose threshold voltage is greater than or equal to the single voltage, or less than the single voltage, after the program operation is completed, according to claim 1.

10. The memory system according to claim 9, wherein the memory controller is configured to determine the voltage offset based on a second mapping table which includes a mapping relationship between the number difference ΔP and the voltage offset value.

11. A method for reading a memory device including an array of memory cells divided into one or more units, wherein each memory cell in one unit stores N bits of data, and the N bits of data correspond to 2 Ｎ It is configured to be set to one of the states, where N is an integer greater than 1, and the method is A step of performing a verification read operation at a single voltage in at least a portion of the memory cells within a unit, A step of determining a voltage offset based on a predetermined relationship between the result of the verification read operation and a voltage offset value, wherein the result of the verification read operation includes a number P of memory cells, at least a portion of the memory cells in one unit, whose threshold voltage is greater than or equal to the single voltage, or less than the single voltage. The steps include: performing a read operation in the memory device using a compensated read voltage determined based on the voltage offset; Methods that include...

12. The method according to claim 11, wherein each of the one or more units has a corresponding voltage offset.

13. The method according to claim 11, wherein the verification readout operation at the single voltage is performed periodically to update the voltage offset.

14. The above 2 Ｎ The state is distinguished by the (N-1) level readout voltage. The aforementioned method, The step of determining the voltage offset corresponding to each level's read voltage based on the pre-set relationship between the result of the verification read operation and the voltage offset value. The method according to claim 12, including the method described in claim 12.

15. The method according to claim 11, wherein the single voltage is one of the (N-1) level readout voltages.

16. The method according to claim 15, wherein the single voltage is the highest voltage in the (N-1) level readout voltage.

17. The aforementioned method, The step of determining the voltage offset based on a first mapping table that includes a mapping relationship between the value of the number P and the value of the voltage offset. The method according to claim 11, including the method described in claim 11.

18. The aforementioned method, A step of calculating the numerical difference ΔP between the aforementioned number P and a default number P', wherein the default number P' is equal to the number of memory cells, at least a portion of the memory cells in the one unit, whose threshold voltage is greater than or equal to the single voltage, or less than the single voltage, after the program operation is completed. The method according to claim 11, including the method described in claim 11.

19. The aforementioned method, The step of determining the voltage offset based on a second mapping table that includes a mapping relationship between the difference ΔP of the aforementioned numbers and the voltage offset value. The method according to claim 18, including the method described in claim 18.

20. A storage medium containing instructions stored therein, wherein, at execution time, the instructions control a memory system to perform a method for reading a memory device of the memory system, the memory device includes an array of memory cells divided into one or more units, each memory cell in one unit storing N bits of data, and corresponding to the N bits of data 2 Ｎ It is configured to be set to one of the states, where N is an integer greater than 1. The method described above is A step of performing a verification read operation at a single voltage in at least a portion of the memory cells within a unit, A step of determining a voltage offset based on a predetermined relationship between the result of the verification read operation and a voltage offset value, wherein the result of the verification read operation includes a number P of memory cells, at least a portion of the memory cells in one unit, whose threshold voltage is greater than or equal to the single voltage, or less than the single voltage. The steps include: performing a read operation in the memory device using a compensated read voltage determined based on the voltage offset; Storage media, including

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