Stress and overlay management in semiconductor processing
By depositing a blanket film and correcting high-frequency and low-frequency components on the back side of semiconductor wafers, the method addresses wafer warping and strain, enhancing device yield and lithography processes for advanced semiconductor devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-03-25
AI Technical Summary
The complex layout of multilayer films and devices on semiconductor wafers leads to wafer warping and in-plane strain, limiting the adoption of high-stress films with advantageous properties and hindering the scaling required for advanced semiconductor devices like 3D-NAND and 3D-DRAM.
A method involving blanket film deposition and field-level film modification on the back side of the wafer is employed to reduce strain, using physical vapor deposition (PVD) and ion/photon injection to correct low-frequency and high-frequency components of the wafer's surface profile.
The method effectively reduces wafer strain, improving device yield by addressing both wafer warpage and in-plane strain, enabling better film overlapping and lithography processes.
Smart Images
Figure 2026053346000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure belong to the field of semiconductor devices and semiconductor device manufacturing. In particular, embodiments of the disclosure relate to a method for reducing the strain of a semiconductor wafer.
Background Art
[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. During the process of integrated circuit evolution, the functional density (i.e., the number of interconnected devices per chip area) has increased overall, while the feature size (i.e., the smallest component (or line) that can be fabricated using the manufacturing process) has decreased.
[0003] The layout of multilayer films and devices on a semiconductor wafer can result in complex wafer warping and in-plane strain that is not easily addressed. Often, the lack of the ability to address wafer warping and in-plane strain limits the adoption of some high-stress films that may have other advantageous properties, such as better etching selectivity.
[0004] Therefore, there is a need for a method to reduce the strain of a semiconductor wafer to enable the scaling required for 3D-NAND, 3D-DRAM, and stacked CMOS devices.
Summary of the Invention
[0005] One or more embodiments of the disclosure are directed to a method for reducing wafer strain. A blanket film is deposited on the back side of a wafer having at least one field formed on the front side. The at least one field includes a film, and the wafer has a first strain. Field-level film modification is performed on the blanket film on the back side of the wafer to reduce the wafer strain to a second strain that is less than the first strain.
[0006] Additional embodiments of the disclosure are directed toward a method for reducing film stress. A first surface profile of a film on a wafer is measured. The wafer has a front side and a back side. The film is formed on the front side. The measured first surface profile is decomposed into main components, including low-frequency and high-frequency components. A blanket film is deposited on the back side of the wafer to correct the low-frequency components of the first measured surface profile. One or more ions or photons are injected into the back side of the wafer to correct the high-frequency components.
[0007] Further embodiments of the disclosure are directed to a processing tool comprising a measurement station, a blanket film deposition station, a field-level film modification station, and a controller. The controller is configured to determine blanket deposition conditions and field-level film modification conditions to reduce wafer strain from a first strain to a second strain.
[0008] Therefore, a more detailed description of the disclosure, which is briefly summarized above, may be provided by reference to embodiments, some of which are illustrated in the accompanying drawings, in a manner that allows for a more detailed understanding of the features listed above. However, it should be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered to limit the scope of this disclosure in such a way that the disclosure may allow for other equally effective embodiments. Embodiments as described herein are illustrated as examples and are not limited to the figures in the accompanying drawings. In the drawings, similar reference numerals indicate similar elements. [Brief explanation of the drawing]
[0009] [Figure 1] This is a flowchart of a method for reducing wafer strain according to one or more embodiments of the disclosure. [Figure 2A] This is a diagram of a wafer for use in the disclosed embodiments. [Figure 2B]This is a diagram of the front surface of a wafer having low-frequency and high-frequency distortion components according to one or more embodiments of the disclosure. [Figure 3] Figure 1 shows the stress frequency profiles of an exemplary wafer before and after the method described in Figure 1. [Figure 4] This is a diagram of a processing tool according to one or more embodiments of the disclosure. [Modes for carrying out the invention]
[0010] Before describing some exemplary embodiments of the disclosure, it should be understood that the disclosure is not limited to the structural modes or process step details described below. The disclosure is possible in other embodiments and can be performed or carried out in a variety of ways.
[0011] As used in this specification and the claims set forth herein, the terms “substrate” or “wafer” refer to the surface or portion of a surface on which a process is performed. It will also be understood by those skilled in the art that a reference to a substrate may refer only to a portion of the substrate unless the context otherwise explicitly indicates otherwise. In addition, a reference to depositing on a substrate can mean both a bare substrate and a substrate having one or more films or features deposited or formed on it.
[0012] As used herein, “substrate” or “wafer” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, without limitation, a semiconductor wafer. A substrate may undergo pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV-cur, electron-beam-cured, and / or bake the substrate surface. In addition to directly treating the surface of the substrate itself, any of the film treatment steps disclosed herein may also be performed on an underlying layer formed on the substrate as more detailed below, and the term “substrate surface” means including such an underlying layer as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.
[0013] Semiconductor devices utilize multilayer stacks and films on wafers. These multilayer stacks and films have varying stress levels, resulting in considerable strain / warpage on the wafer. Such strain / warpage on the wafer can cause problems in both wafer chucking and overlapping between patterning steps, reducing device yield. One or more embodiments advantageously provide solutions for compensating for both wafer warpage and in-plane strain, thus resulting in better overlapping and device yield.
[0014] In one or more embodiments, a simple axisymmetric arc shape resulting from processing the front side of the wafer is corrected by annealing and / or back-side deposition of a film with variable stress. For more complex arc shapes, masking arrangements can be used for the back-side film. This, however, may require an additional back-side planarization step before further lithography steps.
[0015] One or more embodiments of the disclosure are directed towards processes that significantly alter the stress (and consequent strain) state on a wafer. In one or more embodiments, a wafer map of a self-supporting wafer is fabricated using available measurement tools. The wafer map is then converted to power spectral density (PSD) using a spatial frequency scale. The fundamental components of warpage are then corrected using a reasonably "uniform" film, such as silicon nitride (SiN), which is deposited on the back side of the wafer.
[0016] Wafer warpage typically involves large-amplitude distortion at low spatial frequencies. While in-plane distortion has been corrected to some extent in lithography, there are limitations to both amplitude and spatial frequency correction. In one or more embodiments, a film is deposited on the back of the wafer to address low spatial frequencies. A scanning process (using laser or injection) is then used to address high spatial frequencies.
[0017] In one or more embodiments, the film is deposited on the back of the wafer using physical vapor deposition (PVD). As used herein, the term “physical vapor deposition (PVD)” refers to a variety of vacuum deposition methods. Physical processes such as sputtering and vapor deposition are used in PVD to generate vapor in the form of atoms, molecules, or ions of the coating material supplied from the target. The coating material is then delivered to the substrate surface and deposited, resulting in coating formation. In the PVD process, the substrate temperature is substantially lower than the melting temperature of the target material, making it feasible to coat temperature-sensitive materials. PVD methods in which the coating is deposited to cover the entire surface of the entire wafer simultaneously have used vacuum deposition. In some embodiments, the film is deposited on the back of the wafer using one or more of the following: atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).
[0018] In one or more embodiments, PVD is used to deposit a film on the back side of the wafer to ensure stress retention even after heat treatment. Any suitable material known to those skilled in the art may be deposited. In one or more embodiments, a nitride film is formed on the back side of the wafer. In specific embodiments, a silicon nitride (SiN) film is formed on the back side of the wafer. In some embodiments, the film formed on the back side of the wafer includes one or more of oxides, nitrides, or oxynitrides.
[0019] Figure 1 is a flowchart of method 100 for reducing film stress according to one or more embodiments of the disclosure. As used herein, film stress relates to a film deposited on the front side of a wafer. A film under uniform compressive stress deforms the wafer into a bowl shape. A film under uniform tensile stress deforms the wafer into an umbrella shape. By mitigating wafer strain, film stress will become more neutral. Therefore, methods for reducing film stress are also methods for reducing wafer strain.
[0020] In process 110, the substrate or wafer surface profile is measured. Figure 2A shows a typical wafer 200 for use in the embodiments of the disclosure. The wafer 200, or substrate, has a front side 202 and a back side 204 that define the thickness T of the wafer 200. The wafer 200 includes an outer edge 206 that defines the diameter D of the wafer 200. In some embodiments, the wafer has a thickness T in the range of 0.25 mm to 1.5 mm, or in the range of 0.5 mm to 1.25 mm, or in the range of 0.75 mm to 1.0 mm. In some embodiments, the wafer has a diameter D of about 100 mm, 200 mm, or 300 mm.
[0021] Figure 2B shows a diagram of the front side 202 of a wafer 200 having multiple fields 210, which are shown as rectangular in shape. The fields 210 are separate regions on the wafer 200 that result from patterning and deposition processes. In some embodiments, the wafer 200 includes a surface 202 having multiple fields 210 formed on the wafer.
[0022] The first surface profile of the film on the wafer 200 can be measured by any preferred technique known to those skilled in the art. In some embodiments, the wafer 200 surface profile is measured at a measurement station in the processing chamber. The first surface profile is at least a measure of the degree of wafer curvature resulting from the processing conditions and the film.
[0023] The first surface profile provides a measure of surface variation and includes at least two principal components. The first of the principal components is the low-frequency component 220 illustrated in FIG. 2B. The low-frequency component 220 is often the most prominent component as it acts over a large portion of the wafer 200. For example, the low-frequency component 220 represents tensile membrane stress and the strain that results in an umbrella shape. The second component is the high-frequency principal component 230, also referred to as the field-level component. The high-frequency principal component 230 occurs within individual fields 210 and results in a number of - high-frequency - individual strains. The overall strain of the wafer 200 is the result of the combination of the low-frequency component 220 and the high-frequency component 230.
[0024] Thus, at process 120, the measured first surface profile is decomposed into principal components that include the low-frequency component 220 and the high-frequency component 230. Decomposing the principal components is also referred to as principal component deconvolution.
[0025] In one or more embodiments, the power spectral density (PSD) is filtered using the strain transfer characteristics of the PVD film, and the residue is mostly at higher spatial frequencies. The PSD is then used to calculate the profile of the scanned sub-aperture beam (of ions, photons, or other energy sources) on the back side of the wafer. The scanned beam described above provides a high spatial frequency stress component either by locally melting or distorting the lattice structure.
[0026] Based on the low-frequency component 220 of the measured first surface profile, a blanket deposition process is developed. A blanket film is deposited 130 on the back side 204 of the wafer 200 to cancel or correct the low-frequency component of the film stress on the front side 202 of the wafer 200.
[0027] Blanket deposition conditions are determined, for example, based on the film deposited on the front side 202 of the wafer 200. Possible blanket deposition parameters include, but are not limited to, deposition temperature, pressure, film thickness, and composition. In some embodiments, the blanket film 130 is deposited to a thickness in the range of 10 nm to 200 nm, or 20 nm to 180 nm, or 30 nm to 160 nm, or 40 nm to 140 nm.
[0028] In some embodiments, the blanket film 130 is deposited by physical vapor deposition (PVD). In some embodiments, the blanket film 130 is deposited by chemical vapor deposition (CVD). In some embodiments, the blanket film 130 includes a silicon-containing film. In some embodiments, the blanket film 130 includes silicon nitride. In some embodiments, the blanket film 130 is deposited at a temperature in the range of 100°C to 500°C.
[0029] The blanket film 130 is deposited to counteract stress-induced curvature of the wafer from the preceding surface film. In some embodiments, the first strain (before the deposition of the blanket film 130) is parabolic. In some embodiments, the parabolic shape bends upward at the edges, resulting in a bowl-shaped appearance due to the compressive stress of the film on the preceding surface 202. In embodiments having a bowl-shaped dominant component, the deposited blanket film is under compressive stress to counteract the compressive stress of the film on the preceding surface. In other words, the blanket film is deposited to reduce the degree of compressive stress on the wafer from the film on the preceding surface.
[0030] In some embodiments, the parabolic shape bends downward at the edges, resulting in an umbrella-shaped appearance due to the tensile stress on the film on the front surface 202. In embodiments having an umbrella-shaped main component, the blanket film deposited on the back side is under tensile stress to counteract the tensile stress on the film on the front surface. In other words, the blanket film is deposited in such a way that it reduces the degree of tensile stress on the wafer from the film on the front surface.
[0031] In some embodiments, after blanket film deposition 130, the wafer undergoes a second surface profile measurement 140. In some embodiments, the second surface profile measurement is performed at a lower sampling rate than the first surface profile measurement. The second surface profile measurement is then decomposed or deconvoluted into its principal components. The second surface profile measurement 140 is an optional process included in some embodiments of Method 100.
[0032] In some embodiments, a first surface profile is used to determine both the low-frequency and high-frequency components of the film stress. In this type of embodiment, the wafer undergoes a field-level film modification process 150. As used in this way, the term field-level film modification refers to a process configured to reduce wafer strain originating from high-frequency principal components generally related to multiple fields on the front surface.
[0033] In some embodiments, field-level film modification of the blanket film on the back side of the wafer reduces the wafer strain to a second strain that is smaller than the first strain. In some embodiments, the first strain is greater than 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, or 1 mm across the wafer diameter. In some embodiments, the second strain is less than 1 mm, 0.9 mm, 0.8 mm, 0.7 mm, 0.6 mm, 0.5 mm, or 0.4 mm across the wafer diameter. Figure 3 illustrates an exemplary strain / frequency graph showing the reduction of both low-frequency and high-frequency strain components.
[0034] The high-frequency principal component, also known as the field-level component, relates to the number of individual fields on the front surface. In some embodiments, there are fields ranging from 100 to 400 on the front side of the wafer. In some embodiments, each field has a width ranging from 10 mm to 30 mm. In some embodiments, each field has a length ranging from 20 mm to 50 mm.
[0035] The high-frequency principal components are used to determine the modification profile, whether they are from a first or second surface profile. In some embodiments, the field-level modification 150 includes an implantation process that includes one or more of photon implantation or ion implantation. The dose map of the wafer is determined based on the high-frequency principal components.
[0036] In some embodiments, field-level modification includes exposing the back side of the wafer to ions in a predetermined pattern (from a dose map). In some embodiments, field-level modification includes exposing the back side of the wafer to photons in a predetermined pattern (from a dose map). In some embodiments, implanting ions and / or photons into a blanket film on the back side of the wafer corrects high-frequency components.
[0037] An additional embodiment of the disclosure is directed toward a processing tool 300, as illustrated in Figure 4. The processing tool 300 comprises a measurement station 310, a blanket deposition station 320, and a field-level modification station 330. In the illustrated embodiment, the measurement station 310, the blanket deposition station 320, and the field-level modification station 330 are connected to a central transport station 340. In some embodiments, not all of the measurement station, blanket deposition station, and field-level modification station are connected to the central transport station.
[0038] The illustrated embodiment has separate stations for measurement, blanket deposition, and field-level modification. In some embodiments, one or more of the measurement station, blanket deposition station, or field-level modification station are combined into a single component.
[0039] In some embodiments, the processing tool 300 further comprises a controller 350 configured to determine blanket deposition conditions and field-level film modification conditions to reduce wafer strain from a first strain to a second strain. The illustrated controller 350 is connected to a central transport station 340. However, those skilled in the art will recognize that the controller can be connected to any or all of the components of the processing tool. In some embodiments, there are more than one controller, with each controller configured to perform some or all of the above methods.
[0040] In some embodiments, the controller 350 is further configured to decompose a first surface profile measurement of the front-side film of the wafer from the measurement station into a main component including low-frequency and high-frequency components, and to perform blanket deposition on the back side of the wafer at the blanket deposition station. In some embodiments, the controller is further configured to decompose a second surface profile measurement of the front-side film of the wafer after blanket deposition into low-frequency and high-frequency components. In some embodiments, the controller is further configured to perform an injection process at the field-level film modification station to correct the high-frequency component of the second surface profile measurement.
[0041] Throughout this specification, any reference to “one embodiment,” “certain embodiments,” “one or more embodiments,” or “a certain embodiment” means that the specific features, structures, materials, or properties described in relation to the embodiments are included in at least one embodiment of the disclosure. Thus, the appearance of phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment,” or “in a certain embodiment” in various places throughout this specification does not necessarily require a reference to the same embodiment of the disclosure. Furthermore, specific features, structures, materials, or properties may be combined in any suitable manner in one or more embodiments.
[0042] Although the disclosures herein have been described with reference to specific embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and alterations can be made to the methods and apparatus of the disclosure without deviating from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and alterations that fall within the scope of the claims and their equivalents as set forth separately.
Claims
1. A method for reducing wafer distortion, A blanket film is deposited on the back side of a wafer having at least one field formed on the front side, wherein the at least one field includes a film and the wafer has a first strain, and the blanket film is deposited on the back side of the wafer. In order to reduce the strain of the wafer to a second strain that is smaller than the first strain, field-level film modification is performed on the blanket film on the back side of the wafer. Methods that include...
2. The method according to claim 1, wherein the blanket film has a thickness in the range of 10 nm to 200 nm.
3. The method according to claim 1, wherein the deposition of the blanket film includes physical vapor deposition of the material.
4. The method according to claim 3, wherein the material comprises silicon nitride (SiN).
5. The method according to claim 1, wherein the first strain has a parabolic shape.
6. The method according to claim 1, wherein the blanket film is under compressive stress.
7. The method according to claim 1, wherein the blanket film is under tensile stress.
8. The method according to the claim, wherein the blanket film is deposited at a temperature within the range of .
9. The method according to claim 1, wherein performing the field-level film modification includes exposing the back side of the wafer to ions in a predetermined pattern.
10. The method according to claim 1, wherein performing the field-level film modification includes exposing the back side of the wafer to photons in a predetermined pattern.
11. The method according to claim 1, wherein the front side of the wafer has a field in the range of 100 to 400.
12. The method according to claim 11, wherein each of the fields has a width in the range of 10 mm to 30 mm.
13. The method according to claim 11, wherein each of the fields has a length in the range of 20 mm to 50 mm.
14. A method for reducing membrane stress, Measuring a first surface profile of a film on a wafer, wherein the wafer has a front side and a back side, and the film is formed on the front side, The measured first surface profile is decomposed into main components including low-frequency and high-frequency components, To correct the low-frequency components of the first measured surface profile, a blanket film is deposited on the back side of the wafer, To correct the aforementioned high-frequency components, one or more ions or photons are implanted into the back side of the wafer. Methods that include...
15. The method according to claim 14, further comprising depositing the blanket film on the back side of the wafer in order to determine the high-frequency components, and then measuring a second surface profile of the film, wherein the high-frequency components are corrected based on the second surface profile measurement.
16. The method according to claim 15, wherein the second surface profile is measured using a higher sampling rate than the first surface profile.
17. Measurement station and Blanket loading station and Field-level membrane modification station, A controller configured to determine blanket deposition conditions and field-level film modification conditions in order to reduce wafer strain from a first strain to a second strain. A processing tool equipped with these features.
18. The processing tool according to claim 17, wherein the controller is further configured to decompose a first surface profile measurement of the front side film of the wafer from the measurement station into main components including low-frequency and high-frequency components, and to perform blanket deposition on the back side of the wafer at the blanket deposition station.
19. The processing tool according to claim 18, wherein the controller is further configured to decompose the second surface profile measurement of the film on the front side of the wafer after blanket deposition into low-frequency and high-frequency components.
20. The processing tool according to claim 19, wherein the controller is further configured to perform an injection process at the field-level film modification station to correct the high-frequency components of the second surface profile measurement.