Display board and method for manufacturing the same, display device

Abstract

We provide a display board. [Solution] A display substrate, a method for manufacturing the same, and a display device, wherein the display substrate comprises a base (10), at least one insulating film layer provided on the base (10), and a first electrode provided on the side of the insulating film layer away from the base (10), wherein an uneven structure is provided on the side of at least one of the insulating film layers away from the base (10), and the orthographic projection of the uneven structure on the base (10) and the orthographic projection of the first electrode on the base (10) have an overlapping region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technology, but are not limited thereto, and particularly relate to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] An organic light-emitting diode (abbreviated as OLED) is an active light-emitting display element, and has advantages such as light emission, ultra-thin, wide viewing angle, high brightness, high contrast, low power consumption, and extremely high response speed. Depending on the driving method, OLEDs can be divided into two types: passive matrix driving (abbreviated as PM) type and active matrix driving (abbreviated as AM) type. Here, AMOLED is a current driver, and each sub-pixel is controlled using an independent thin film transistor (abbreviated as TFT), and each sub-pixel can emit light in a continuous and independent manner.

Summary of the Invention

[0003] The following is an overview of the theme to be described in detail in the text. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present disclosure provide a display substrate, comprising a base, at least one insulating film layer provided on the base, and a first electrode provided on a side of the insulating film layer away from the base, wherein an uneven structure is provided on a side of at least one of the insulating film layers away from the base, and a superposition region exists between a positive projection of the uneven structure on the base and a positive projection of the first electrode on the base.

[0005] In an exemplary embodiment, the display substrate comprises a flat layer, an emissive structure layer, a package layer, and a color filter layer sequentially formed on the base, wherein the emissive structure layer comprises a pixel definition layer, an anode, a cathode, and an organic emissive layer located between the anode and the cathode, the pixel definition layer comprises a plurality of pixel apertures, the pixel apertures expose at least a portion of the anode, and the cathodes cover the pixel definition layer. The color filter layer comprises a black matrix and a color filter provided at intervals, the black matrix having a plurality of aperture regions forming a matrix arrangement, at least a portion of the color filter filling the aperture regions, the color filter and the black matrix having at least a portion of overlapping regions, in which the color filter covers the black matrix.

[0006] In an exemplary embodiment, at least one of the insulating film layers comprises the pixel definition layer, and the first electrode comprises the cathode.

[0007] In an exemplary embodiment, the pixel definition layer comprises a plurality of first protrusions, and a first recess is formed between adjacent first protrusions.

[0008] In an exemplary embodiment, the first recess is a groove surrounding the pixel aperture, and the distance between adjacent grooves is 1 / 8 to 7 / 8 of the distance between the edge of the aperture region of the black matrix and the edge of the pixel aperture formed in the pixel definition layer.

[0009] In exemplary embodiments, the distance between adjacent grooves is 1 to 2 micrometers.

[0010] In the exemplary embodiment, the width of the groove is 0.8 to 1.5 micrometers.

[0011] In an exemplary embodiment, the first recess is an opening surrounding the pixel aperture, and the width of the opening is 0.5 to 1.8 micrometers.

[0012] In an exemplary embodiment, the plurality of openings constitute a plurality of annular structural units, at least one annular structural unit comprising N annular structures arranged around the pixel aperture and parallel to each other, the innermost annular structure comprising a plurality of first openings, the first openings and the pixel aperture being adjacent, and N being a natural number greater than 1.

[0013] In exemplary embodiments, sawtooth protrusions are formed between a plurality of the first openings, and the width of the sawtooth protrusions is 0.8 to 1.5 micrometers.

[0014] In this exemplary example, N is a natural number between 1 and 50.

[0015] In exemplary embodiments, at least one insulating film layer comprises the flat layer, and the first electrode comprises the anode.

[0016] In an exemplary embodiment, the flat layer comprises a plurality of second protrusions, and a second recess is formed between adjacent second protrusions.

[0017] In an exemplary embodiment, the second protrusion is serrated.

[0018] In an exemplary embodiment, the step between the second protrusion and the second recess is 1 / 8 to 7 / 8 of the thickness of the flat layer.

[0019] In an exemplary embodiment, the step between the second protrusion and the second recess is 0.2 to 0.8 micrometers.

[0020] In an exemplary embodiment, at least one insulating film layer comprises the pixel definition layer and the flat layer, the first electrode comprises the cathode and the anode, a first uneven structure is provided on the side of the pixel definition layer away from the base, the orthogonal projection of the first uneven structure on the base and the orthogonal projection of the cathode on the base have an overlapping region, a second uneven structure is provided on the side of the flat layer away from the base, the orthogonal projection of the second uneven structure on the base and the orthogonal projection of the anode on the base have an overlapping region.

[0021] In an exemplary embodiment, the display substrate further includes a touch structure layer provided between the package layer and the color filter layer. The touch structure layer includes a plurality of touch electrodes, and the orthographic projection of the black matrix on the base includes the orthographic projection of the touch electrodes on the base.

[0022] An embodiment of the present disclosure further provides a display device, which includes any one of the above display substrates.

[0023] An embodiment of the present disclosure provides a method for manufacturing a display substrate, including forming at least one insulating film layer on a base, providing a concavo-convex structure on a side of at least one of the insulating film layers away from the base, forming a first electrode on a side of the insulating film layer away from the base, and the orthographic projection of the concavo-convex structure on the base and the orthographic projection of the first electrode on the base having an overlapping region.

[0024] After reading and understanding the accompanying drawings and the detailed description, other aspects can be understood.

Brief Description of the Drawings

[0025] The drawings are for better understanding the technical solutions of the present disclosure, and form a part of the specification. They are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, rather than to limit the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale, and are only intended to schematically illustrate the content of the present disclosure.

[0026] [Figure 1] FIG. 1 is a schematic structural diagram of a display device. [Figure 2] FIG. 2 is a schematic plan structural diagram of a display substrate. [Figure 3] FIGS. 3a and 3b are schematic diagrams of the separation phenomenon of two colors. [Figure 4] FIG. 4 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure. [Figure 5]Figures 5a and 5b are schematic diagrams of the results after the improvement of color separation according to the present disclosure. [Figure 6] Figure 6 is a schematic diagram of a display substrate structure after a flexible base pattern is manufactured according to an embodiment of the present disclosure. [Figure 7] Figure 7 is a schematic diagram of a display substrate structure after a driving structure layer pattern is manufactured according to an embodiment of the present disclosure. [Figure 8] Figure 8 is a schematic diagram of a display substrate structure after a flat layer pattern is formed according to an embodiment of the present disclosure. [Figure 9] Figure 9 is a schematic diagram of a display substrate structure after an anode pattern is formed according to an embodiment of the present disclosure. [Figure 10] Figure 10 is a schematic diagram of a display substrate structure after a pixel definition layer pattern is formed according to an embodiment of the present disclosure. [Figure 11] Figure 11 is a schematic diagram of the structure of a pixel definition layer according to an embodiment of the present disclosure. [Figure 12] Figure 12 is a schematic diagram of the structure of a pixel definition layer according to an embodiment of the present disclosure. [Figure 13] Figure 13 is a schematic diagram of a display substrate structure after a spacer layer pattern is formed according to an embodiment of the present disclosure. [Figure 14] Figure 14 is a schematic diagram of a display substrate structure after a cathode pattern is formed according to an embodiment of the present disclosure. [Figure 15] Figure 15 is a schematic diagram of a display substrate structure after a package layer pattern is formed according to an embodiment of the present disclosure. [Figure 16] Figure 16 is a schematic diagram of a display substrate structure after a touch structure layer pattern is formed according to an embodiment of the present disclosure. [Figure 17] Figure 17 is a schematic diagram of a display substrate structure after a color filter layer pattern is formed according to an embodiment of the present disclosure. [Figure 18] Figure 18 is a schematic diagram of a display substrate structure after a cover plate is bonded according to an embodiment of the present disclosure. [Figure 19] Figure 19 is a schematic diagram of the structure of a test model for optical improvement of color separation according to an embodiment of the present disclosure. [Figure 20a] Figure 20a is a schematic diagram of the simulation results when the incident light in Figure 19 is aligned along the long axis of the color filter. [Figure 20b] Figure 20b is a schematic diagram of the simulation results when the incident light in Figure 19 is aligned along the long axis of the color filter. [Figure 21a] Figure 21a is a schematic diagram of the simulation results when the incident light in Figure 19 is aligned along the short axis of the color filter. [Figure 21b] Figure 21b is a schematic diagram of the simulation results when the incident light in Figure 19 is aligned with the short axis of the color filter. [Modes for carrying out the invention]

[0027] To clarify the purpose, technical proposals, and merits of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments may be carried out in multiple different forms. The methods and content may be transformed into various forms without deviating from the spirit and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited to the embodiments described below. The embodiments and features in these embodiments can be combined in any way, as long as they do not conflict.

[0028] The proportions in the drawings in this disclosure may, but are not limited to, be used as reference in actual processes. For example, the aspect ratio of the channels, the thickness and pitch of each film layer, and the width and pitch of each signal line can be adjusted as needed. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the quantities shown in the drawings, and the drawings described in this disclosure are schematic diagrams of the structure. One method of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0029] In this specification, ordinal numbers such as "1st," "2nd," and "3rd" are established to avoid confusion of constituent elements and are not intended to limit them in terms of quantity.

[0030] In this specification, for convenience, descriptions indicating directional or positional relationships, such as “center,” “top,” “bottom,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to describe the positional relationships of components with reference to the drawings. However, this is merely for the sake of simplicity in describing this specification and does not express or imply that the indicated devices or elements necessarily have a specific orientation or are configured and operated in a specific orientation, and should therefore not be considered a limitation of this disclosure. The positional relationships of components are appropriately modified depending on the direction in which each component is described. Therefore, the terminology used in this specification is not limited and can be appropriately substituted as appropriate depending on the context.

[0031] In this specification, unless otherwise explicitly stated or limited, the terms “attachment” and “connection” should be understood in a broad sense. For example, this could mean being permanently connected, or detachably connected, or integrally connected; it could be a mechanical connection or an electrical connection; it could be a direct connection, an indirect connection via an intermediate member, or internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of these terms in this disclosure from the specific context.

[0032] In this specification, a transistor refers to an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. However, in this specification, the channel region refers to the region through which the current primarily flows.

[0033] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When transistors with opposite polarity are used, or when the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may be swapped. Therefore, in this specification, the "source electrode" and the "drain electrode" can be swapped with each other, and the "source terminal" and the "drain terminal" can be swapped with each other.

[0034] In this specification, “electrical connection” includes cases where components are connected via an element having some electrical function. “An element having some electrical function” is not particularly limited, as long as it can transmit and receive electrical signals between the connected components. Examples of “elements having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements having different functions.

[0035] In this specification, "parallel" refers to a state in which the angle between two straight lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which the angle between two straight lines is 80° or more and 100° or less, and therefore also includes a state in which the angle is 85° or more and 95° or less.

[0036] In this specification, "film" and "layer" can be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0037] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, as well as chamfers, arcs, and other deformations.

[0038] In this disclosure, "approximately" means that the limits are not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0039] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scanning signal driver, and a pixel array. The timing controller is connected to the data signal driver and the scanning signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), and the scanning signal driver is connected to a plurality of scanning signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, where i and j are natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may include at least one scanning signal line, at least one data signal line, and a pixel driving circuit. In some exemplary embodiments, the timing controller may provide the data signal driver with gradation values ​​and control signals suitable for the specifications of the data signal driver, and may also provide the scanning signal driver with a clock signal, a scan start signal, etc., suitable for the specifications of the scanning signal driver. The data signal driver may use the gradation values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row-by-pixel basis, where n is a natural number. The scan signal driver may receive a clock signal, a scan start signal, etc., from a timing controller and generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm. For example, the scan signal driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register and generate scan signals so as to sequentially transmit scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m is a natural number.

[0040] Figure 2 is a schematic diagram of the planar structure of a display board. As shown in Figure 2, the display board may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color ray, a second subpixel P2 that emits a second color ray, a third subpixel P3 that emits a third color ray, and a fourth subpixel P4 that emits a fourth color ray, and each of the four subpixels may include a circuit unit and a light-emitting element, and the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line and the data signal line respectively, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting element. The light-emitting element in each subpixel is connected to the pixel driving circuit of the subpixel in which it is located, and the light-emitting element is configured to emit light of a corresponding brightness according to the current output from the pixel driving circuit of the subpixel in which it is located.

[0041] In some exemplary embodiments, the first subpixel P1 may be a red subpixel (R) that emits red light rays, the second subpixel P2 may be a green subpixel (G) that emits green light rays, the third subpixel P3 may be a white subpixel (W) that emits white light rays, and the fourth subpixel P4 may be a blue subpixel (B) that emits blue light rays.

[0042] In some exemplary embodiments, the shape of the subpixels may be rectangular, rhombus, pentagonal, or hexagonal. In one exemplary embodiment, four subpixels may be arranged in a horizontal parallel arrangement to form an RWBG pixel array. In other exemplary embodiments, four subpixels may be arranged in a square, diamond, or vertical parallel arrangement, and this disclosure is not limited thereto.

[0043] In some other exemplary embodiments, at least one of the multiple pixel units P may comprise one red (R) subpixel emitting a red ray, one green (G) subpixel emitting a green ray, and one blue (B) subpixel emitting a blue ray, or one red subpixel emitting a red ray, two green subpixels emitting green rays, and one blue subpixel emitting a blue ray, and the disclosure is not limited thereto. If a pixel unit comprises three subpixels, the three subpixels may be arranged in a horizontal parallel, vertical parallel, or in a square pattern, and if a pixel unit comprises four subpixels, the four subpixels may be arranged in a horizontal parallel, vertical parallel, or in a square pattern, and the disclosure is not limited thereto.

[0044] In some exemplary embodiments, multiple subpixels arranged sequentially in the horizontal direction are referred to as pixel rows, and multiple subpixels arranged sequentially in the vertical direction are referred to as pixel columns, and multiple pixel rows and multiple pixel columns constitute an array of pixels.

[0045] Currently, the most notable feature of OLED panels compared to liquid crystal displays (LCDs) is their all-solid-state display (without liquid crystals), giving them a clear advantage in terms of bending and folding capabilities. To improve the bending performance of OLED products, it is necessary to continuously reduce the module thickness, but the anti-reflective circular polarizer and the bonded touch module account for a large proportion of the overall thickness. To solve this problem, methods for integrating the touch structure and color filter structure into the OLED package layer, namely Touch on TFE (TOT) technology and Chromoresistive Structure (CF on Encapsulation (COE)) technology in the thin-film package layer, have been adopted, significantly reducing the module thickness. However, COE technology has a problem of color separation in dark conditions; that is, when the screen is off, as shown in Figures 3a and 3b, color separation of reflected light is clearly visible under light illumination, affecting the user's experience of an absolutely black screen.

[0046] Analysis and verification revealed that the main reason for the color separation phenomenon in dark conditions was that, after the circular polarizer was removed, the ambient light underwent red, green, and blue pixel reflection, and directional reflection to the cathode and anode, resulting in altered intensity distributions to varying degrees. Some techniques improve the color separation phenomenon by doping the coating protective layer (OC) with scattering particles to scatter light; however, the introduction of scattering particles reduces light transmittance, thereby negating the advantage of the COE's high transmittance.

[0047] Embodiments of the present disclosure provide a display substrate comprising a base, at least one insulating film layer provided on the base, and a first electrode provided on the side of the insulating film layer away from the base, wherein a ridged structure is provided on the side of the at least one insulating film layer away from the base, and the orthogonal projection of the ridged structure on the base and the orthogonal projection of the first electrode on the base have an overlapping region.

[0048] The display substrate according to the embodiment of this disclosure improves the color separation phenomenon by processing at least one insulating film layer at a position opposite the first electrode to form an uneven structure, interfering with the path of ambient light reflection and disrupting the emission of ambient light. Moreover, the manufacturing process of the display substrate according to this disclosure is simple, has high production efficiency, low production costs, and a high yield rate, among other advantages, and has good prospects for application.

[0049] Figure 4 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. As shown in Figure 4, the display substrate according to an embodiment of the present disclosure comprises a base, a flat layer 95 and an emissive structure layer formed sequentially on the base, the emissive structure layer comprises an anode 51, at least one insulating film layer comprises the flat layer 95, and the first electrode comprises the anode 51. A second uneven structure is provided on the side of the flat layer 95 away from the base, and the orthographic projection of the base of the second uneven structure and the orthographic projection of the base of the anode 51 have an overlapping region.

[0050] In this embodiment, the display substrate is processed so that the flat layer 95 directly opposite the anode 51 is gently undulating, causing the anode 51 to form a certain degree of undulating wave shape, that is, to form a diffuse reflecting anode, which interferes with the path of ambient light reflection, disrupts the emission of ambient light, and improves the color separation phenomenon. As shown in Figures 5a and 5b, the display substrate according to the embodiment of this disclosure significantly reduces the color separation phenomenon and can maintain good black color under strong light irradiation in dark conditions, and user experience tests have shown that it has a clear effect.

[0051] In some exemplary embodiments, the second uneven structure comprises a plurality of second protrusions, with second recesses formed between adjacent second protrusions.

[0052] In some exemplary embodiments, the second protrusion may be serrated.

[0053] In some exemplary embodiments, the step between the second protrusion and the second recess may be 0.2 to 0.8 micrometers.

[0054] In some exemplary embodiments, the light-emitting structure layer further comprises a pixel definition layer 96, the pixel definition layer 96 comprising a plurality of pixel apertures, the pixel apertures exposing an anode 51, and a first uneven structure is provided on the side of the pixel definition layer 96 away from the base.

[0055] In this embodiment, at least one insulating film layer comprises a pixel definition layer 96, and the first electrode comprises a cathode. The pixel definition layer 96 is also processed to have a gently undulating surface, thereby forming an uneven surface. When the cathode is deposited, an uneven surface is formed on the cathode as well, that is, a scattering cathode surface is formed, the reflection path of ambient light is interfered with, the emission of ambient light is disrupted, and the color separation phenomenon is further improved.

[0056] In some exemplary embodiments, the first uneven structure comprises a plurality of first protrusions, with first recesses formed between adjacent first protrusions.

[0057] In some exemplary embodiments, the first recess is a groove surrounding the pixel aperture, the width of the groove is 0.8 to 1.5 micrometers, and the distance between adjacent grooves is 1 to 2 micrometers.

[0058] In some exemplary embodiments, the distance between adjacent grooves is 1 / 8 to 7 / 8 of the distance between the edge of the aperture region of the black matrix and the edge of the pixel aperture formed in the pixel definition layer.

[0059] In several other exemplary embodiments, the first recess is an opening surrounding the pixel aperture, and the width of the opening is 0.5 to 1.8 micrometers.

[0060] In some exemplary embodiments, the multiple openings constitute multiple annular structural units, each annular structural unit comprising N annular structures arranged around a pixel aperture and parallel to each other, the innermost annular structure comprising multiple first openings, the first openings and pixel apertures being adjacent, and sawtooth protrusions formed between the multiple first openings, with each sawtooth protrusion having a width of 0.8 to 1.5 micrometers, where N is a natural number greater than 1.

[0061] In some exemplary implementations, N is a natural number between 1 and 50.

[0062] In some exemplary examples, N is 3.

[0063] In some exemplary embodiments, the light-emitting structure layer further comprises an organic light-emitting layer 52 and a cathode 53, wherein the organic light-emitting layer 52 is provided on the anode 51 and the cathode 53 is provided on the organic light-emitting layer 52, the organic light-emitting layer 52 and the anode 51 are connected, and the cathode 53 and the organic light-emitting layer 52 are connected, and the organic light-emitting layer 52 emits light rays of the corresponding colors under the driving of the anode 51 and the cathode 53. The positions corresponding to the first uneven structure and / or second uneven structure of the organic light-emitting layer 52 and the cathode 53 are non-flat surfaces.

[0064] In some exemplary embodiments, the organic light-emitting layer 52 may comprise a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron barrier layer (EBL), a light-emitting layer (EML), a hole barrier layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some exemplary embodiments, the hole injection layer, hole transport layer, electron barrier layer, hole barrier layer, electron transport layer, and electron injection layer of all subpixels may be a common layer connected to one another, the light-emitting layers of all subpixels may be a common layer connected to one another, or they may be separated from one another, and the light-emitting layers of adjacent subpixels may have a small overlap. In some possible implementations, the display substrate may comprise other film layers, and this disclosure is not limited thereto.

[0065] In some exemplary embodiments, the display substrate further includes a package layer 98 provided on the side away from the base of the light-emitting structure layer. The package layer 98 may comprise a stacked first package layer, a second package layer, and a third package layer, the first and third package layers may be made of inorganic materials, and the second package layer may be made of organic materials, the second package layer being provided between the first and third package layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0066] In some exemplary embodiments, the base comprises a base 10 and a drive structure layer 102 provided on the base 10. The base 10 may be a flexible base or a rigid base. The drive structure layer 102 of each subpixel may include a pixel drive circuit consisting of a plurality of transistors and memory capacitors. The anode 51 is connected to a first thin-film transistor in the drive structure layer via vias provided in the flat layer 95.

[0067] In some exemplary embodiments, as shown in Figure 4, the display substrate further comprises a color filter layer provided on the side away from the base of the package layer 98, the color filter layer comprising a spaced black matrix 71 and a color filter 72, the black matrix 71 having a plurality of aperture regions forming a matrix arrangement, and the color filter 72 filling the aperture regions. In exemplary embodiments, the color filter 72 and the black matrix 71 have at least some overlapping regions. In the overlapping regions of the black matrix 71 and the color filter 72, the color filter 72 covers the black matrix 71.

[0068] In some exemplary embodiments, the display substrate further comprises a touch structure layer 103 provided between the package layer 98 and the color filter layer, the touch structure layer 103 may comprise a plurality of touch electrodes, and the orthographic projection on the base of the black matrix 71 includes the orthographic projection on the base of the touch electrodes.

[0069] Next, the technical proposal of this embodiment will be further explained through the manufacturing process of the display substrate of this embodiment. The “patterning process” referred to in this embodiment includes processes such as film layer deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. The “photolithography process” referred to in this embodiment includes processes such as film layer coating, mask exposure, and development, and is a mature manufacturing process in related technologies. For deposition, one or more of sputtering, vapor deposition, and chemical vapor deposition can be employed; for coating, one or more of spray coating and spin coating can be employed; and for etching, one or more of dry etching and wet etching can be employed. A “thin film” refers to a thin film of one layer manufactured on a base material by a vapor deposition or coating process. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” may further be referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process contains at least one “pattern.” As used in this disclosure, “placing A and B in the same layer” means that A and B are formed simultaneously by the same patterning process. “The orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B is within the scope of the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0070] In some exemplary embodiments, the manufacturing process for the display substrate shown in Figure 4 may include the following steps (1) to (12).

[0071] (1) A flexible base 10 is manufactured on a glass substrate 1.

[0072] In one embodiment of the present disclosure, the flexible base 10 may employ a two-layer flexible layer structure, comprising a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer laminated on a glass substrate 1. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., used to enhance the water- and oxygen-resistant capacity of the base. The first inorganic material layer and the second inorganic material layer are also called barrier layers, and amorphous silicon (a-Si) may be used as the material for the semiconductor layer.

[0073] In some exemplary embodiments, taking the laminated structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the manufacturing process of the flexible base 10 may include, as shown in Figure 6, first coating the glass substrate 1 with one layer of polyimide, curing it to form a film, and then forming a first flexible (PI1) layer; next, depositing one layer of barrier thin film onto the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing one layer of amorphous silicon thin film onto the first barrier layer to form an amorphous silicon (a-Si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, curing it to form a film, and then forming a second flexible (PI2) layer; and finally depositing one layer of barrier thin film onto the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer.

[0074] In other examples, the flexible base 10 may employ a single-layer flexible structure, for example, the flexible base 10 comprising a stacked flexible (PI) layer and a barrier layer.

[0075] (2) A pattern for the drive structure layer 102 is manufactured on the flexible base 10. The drive structure layer comprises a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines intersecting perpendicularly to define a plurality of matrix array pixel units, each pixel unit comprising at least three subpixels, and at least one subpixel comprising at least one first thin film transistor (TFT) (in one possible embodiment, in the camera region below the screen, at least one subpixel does not have a TFT, but only an anode). The first thin film transistor may be a bottom gate structure, a top gate structure, an amorphous silicon (a-Si) thin film transistor, a low-temperature polysilicon (LTPS) thin film transistor, or an oxide (Oxide) thin film transistor, but is not limited thereto. In this embodiment, one pixel unit comprises three subpixels, a red subpixel R, a green subpixel G, and a blue subpixel B. Naturally, the concept of this embodiment also applies when one pixel unit comprises four subpixels (red subpixel R, green subpixel G, blue subpixel B, and white subpixel W). In some exemplary embodiments, the manufacturing process for the drive structure layer may include the following steps.

[0076] In the flexible base 10, a first insulating thin film and an active layer thin film are sequentially deposited, and the active layer thin film is patterned by a patterning process to form a first insulating layer 91 that covers the entire flexible base 10 and an active layer pattern provided on the first insulating layer 91, the active layer comprising at least a first active layer 11. In one exemplary embodiment, the first insulating layer 91 is called a buffer layer and is used to enhance the water- and oxygen-resistant capacity of the base.

[0077] Next, the second insulating thin film and the first metal thin film are sequentially deposited, and the first metal thin film is patterned by a patterning process to form a second insulating layer 92 covering the active layer and a first gate electrode layer pattern provided on the second insulating layer 92. The first gate electrode layer comprises at least a first gate electrode 21 and a first capacitor electrode 22, a plurality of gate wires (not shown), and a plurality of gate lead wires (not shown). In one exemplary embodiment, the second insulating layer 92 is called the first gate insulating (GI1) layer.

[0078] Next, the third insulating film and the second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 93 covering the first gate electrode layer and a second gate electrode layer pattern provided on the third insulating layer 93. The second gate electrode layer comprises at least a second capacitor electrode 31 and a second gate lead wire (not shown), and the position of the second capacitor electrode 31 corresponds to the position of the first capacitor electrode 22. In one exemplary embodiment, the third insulating layer 93 is also called the second gate insulating (GI2) layer.

[0079] Next, a fourth insulating thin film is deposited and patterned by a patterning process to form a pattern for the fourth insulating layer 94 covering the second gate electrode layer. The fourth insulating layer 94 is provided with a plurality of first vias, the positions of which correspond to the positions at both ends of the first active layer. The fourth insulating layer 94, the third insulating layer 93, and the second insulating layer 92 within the plurality of first vias are etched, exposing the surfaces of the first active layer, respectively. In one exemplary embodiment, the fourth insulating layer 94 is also called an interlayer dielectric (ILD) layer.

[0080] Next, a third metal thin film is deposited and patterned by a patterning process to form a source-drain metal layer (SD) pattern on the fourth insulating layer 94, the source-drain metal layer comprising at least a pattern of a first source electrode 41, a first drain electrode 42, a low-voltage (VSS) line (not shown), a plurality of data lines (not shown), and a plurality of data lead lines (not shown), the first source electrode 41 and the first drain electrode 42 are each connected to the ends of the first active layer 11 via a first via. In one exemplary embodiment, the source-drain metal layer may further comprise one or more of power lines (VDD), compensation lines, and auxiliary cathodes, depending on actual requirements.

[0081] As a result, the fabrication of the drive structure layer pattern on the flexible base 10 is completed, as shown in Figure 7. The first active layer 11, the first gate electrode 21, the first source electrode 41, and the first drain electrode 42 constitute the first thin-film transistor, the first capacitor electrode 22 and the second capacitor electrode 31 constitute the memory capacitor, and the multiple gate leads and data leads constitute the drive leads for the Gate Driver on Array (GOA).

[0082] (3) A first flat thin film is coated onto the flexible base on which the aforementioned pattern is formed, and the first flat thin film is patterned by a patterning process to form a flat (PLN) layer 95 that covers the entire flexible base 10. As shown in Figure 8, a second via V2 is provided in the flat layer 95, and the flat layer 95 within the second via V2 is etched to expose the surface of the first drain electrode 42 of the first thin film transistor. A second uneven structure 951 is provided on the side of the flat layer 95 away from the flexible base 10, and the orthographic projection of the second uneven structure 951 on the flexible base 10 and the orthographic projection of the anode 51 formed thereafter on the flexible base 10 have an overlapping region, that is, an uneven shape is formed on the flat layer 95 at the position corresponding to the anode 51.

[0083] In some exemplary embodiments, the second uneven structure 951 comprises a plurality of second protrusions, with second recesses formed between adjacent second protrusions.

[0084] In this embodiment, when patterning the first flat thin film, the aperture pattern on the photomask may be made to correspond to the second recess of the second uneven structure 951. This allows the position, shape, and arrangement method of the aperture pattern on the photomask to be designed according to the desired second uneven structure 951, thereby simplifying the manufacturing process of the display substrate.

[0085] In some exemplary embodiments, the second protrusion may be serrated.

[0086] In some exemplary embodiments, as shown in Figure 4, the step h1 between the second protrusion and the second recess may be 1 / 8 to 7 / 8 of the thickness h2 of the flat layer 95.

[0087] In some exemplary embodiments, the step height h1 between the second protrusion and the second recess may be 0.2 to 0.8 micrometers. In this embodiment, the step height between the second projection and the second recess refers to the difference in height between the highest point of the second projection and the lowest point of the second recess.

[0088] (4) A transparent conductive thin film is deposited on the base on which the aforementioned pattern is formed, and the transparent conductive thin film is patterned by a patterning process to form the pattern of the anode 51, and the anode 51 is connected to the first drain electrode D via the second via V2. Since the flat layer 95 at the position corresponding to the anode 51 has a undulating wave shape on the side away from the flexible base, the anode 51 can also form a undulating wave shape, thereby forming a diffuse reflecting anode surface.

[0089] In some exemplary embodiments, forming the pattern of the anode 51 includes, as shown in Figure 9, depositing a fourth metal thin film on a base on which the aforementioned pattern is formed, coating the fourth metal thin film with a layer of photoresist, exposing the photoresist using a monochrome photomask to form an unexposed region at the location of the anode 51 and a fully exposed region at other locations, developing and removing the photoresist in the fully exposed region, then etching the fourth metal thin film in the fully exposed region to remove the photoresist, and finally forming the pattern of the anode 51.

[0090] Since the display substrate in this embodiment has a top emission structure, the anode 51 is a reflective electrode, and a metal with high reflectivity, such as silver (Ag), gold (Au), palladium (Pd), platinum (Pt), or an alloy of these metals, or a composite layer of these metals may be used. In actual implementation, a composite layer structure of an indium tin oxide (ITO) layer and a metal reflective layer may also be used, which has good conductivity, high reflectivity, and good morphological stability.

[0091] (5) A pixel definition thin film is coated onto the base on which the aforementioned pattern is formed, and a pattern of the pixel definition (PDL) layer 96 is formed by a masking, exposure, and development process, as shown in Figure 10, a pixel aperture K is provided in the pixel definition layer 96, the pixel definition thin film within the pixel aperture K is developed to expose at least a portion of the surface of the anode 51, and a first uneven structure 961 is provided on the side of the pixel definition layer 96 away from the flexible base 10. The pixel aperture K and the first uneven structure 961 can be realized by designing a grayscale mask.

[0092] In some exemplary embodiments, the orthographic projection of the first uneven structure 961 on the flexible base 10 does not overlap with the orthographic projection of the pixel aperture K on the flexible base 10.

[0093] In some exemplary embodiments, the first uneven structure 961 is located on the side of the pixel definition layer 96 closer to the later-formed organic light-emitting layer 52, thereby enabling the formation of a undulating wave shape at the edge position close to the light-emitting region of the pixel definition layer 96.

[0094] In some exemplary embodiments, as shown in Figure 10, the first uneven structure 961 comprises a plurality of first protrusions 96a, with first recesses 96b formed between adjacent first protrusions 96a. In embodiments of the present disclosure, the pixel definition layer within the pixel aperture K is fully developed, and the pixel definition layer within the first recesses 96b is partially developed to prevent the cathode and anode, which are later formed, from short-circuiting through the first recesses 96b.

[0095] In some exemplary embodiments, as shown in Figures 4 and 11, the first recess 96b is a groove surrounding the pixel aperture K, the width d1 of the groove may be determined based on the resolution limit of the current exposure apparatus, and the distance d2 between adjacent grooves is 1 / 8 to 7 / 8 of the distance d3 between the edge of the aperture region of the black matrix 71 formed later and the edge of the pixel aperture K formed in the pixel definition layer 96.

[0096] In some exemplary embodiments, as shown in Figure 11, the first recess 96b is a groove surrounding the pixel aperture K, the width d1 of the groove is 0.8 to 1.5 micrometers, and the distance d2 between adjacent grooves is 1 to 2 micrometers.

[0097] In several other exemplary embodiments, as shown in Figures 4 and 12, the first recess 96b comprises an opening surrounding the pixel aperture K, and the width d4 of the opening may be determined based on the resolution limit of the current exposure apparatus. The distance d5 between adjacent openings is 1 / 8 to 7 / 8 of the distance d3 between the edge of the aperture region of the black matrix 71 formed later and the edge of the pixel aperture K formed in the pixel definition layer 96.

[0098] For example, the width d4 of the opening may be 0.5 to 1.8 micrometers.

[0099] In some exemplary embodiments, as shown in Figure 12, the multiple openings constitute multiple annular structure units 96c, each annular structure unit 96c comprising N annular structures arranged around a pixel aperture K and parallel to each other, the innermost annular structure comprising multiple first openings 96b1, the first openings 96b1 and the pixel aperture K being adjacent, and sawtooth-shaped protrusions 96a1 formed between the multiple first openings 96b1, where N is a natural number greater than 1.

[0100] In some exemplary embodiments, as shown in Figure 12, the width d6 of the sawtooth protrusions 96a1 may be determined based on the resolution limit of the current exposure apparatus. The distance d7 between adjacent sawtooth protrusions 96a1 is 1 / 8 to 7 / 8 of the distance between the edge of the aperture region of the black matrix 71 that is later formed and the edge of the pixel aperture K formed in the pixel definition layer 96.

[0101] For example, the width d6 of the serrated protrusion 96a1 is 0.8 to 1.5 micrometers.

[0102] In some exemplary embodiments, N is between 1 and 50. For illustrative purposes, N may also be 3.

[0103] In this embodiment, by setting the width of the opening to 0.5 to 1.8 micrometers, it is possible to ensure that the designed opening is not permeated by exposure even when the pixel aperture is exposed, thereby forming an uneven surface on the pixel definition layer 96. This allows for the formation of an uneven surface on the cathode 53 when it is subsequently deposited, thereby forming a scattering cathode surface.

[0104] (6) As shown in Figure 13, an organic material thin film is coated onto the base on which the aforementioned pattern is formed, and the pattern of the spacer (PS) layer 97 is formed by a masking, exposure, and development process.

[0105] (7) As shown in Figure 14, an organic light-emitting layer 52 and a cathode 53 are sequentially formed on the base on which the aforementioned pattern is formed. The organic light-emitting layer 52 comprises a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and is formed within the pixel aperture, thereby realizing a connection between the organic light-emitting layer 52 and the anode 51. Since the anode 51 is connected to the first drain electrode 42 of the first transistor, light emission control of the organic light-emitting layer 52 is realized. The cathode 53 is connected to the organic light-emitting layer 52. Since both the anode 51 and the pixel definition layer 96 have a wave-like shape, the organic light-emitting layer 52 and the cathode 53 can also form wave-like shapes, thereby forming a scattered cathode surface. In an exemplary embodiment, the cathode 53 may be an integrated structure that communicates with each other.

[0106] This completes the manufacturing of the light-emitting structure layer pattern in the drive circuit layer. The light-emitting structure layer comprises an anode, a pixel definition layer, a spacer layer, an organic light-emitting layer, and a cathode, with the organic light-emitting layer connected to the anode and cathode, respectively.

[0107] (8) As shown in Figure 15, the pattern of the package layer 98 is formed on the base on which the aforementioned pattern is formed, and the package layer 98 may adopt an inorganic material / organic material / inorganic material laminated structure, with the organic material layer being placed between the two inorganic material layers.

[0108] In some exemplary embodiments, forming the pattern of the package layer 98 may include first depositing a first inorganic thin film using plasma-enhanced chemical vapor deposition (PECVD) with an open mask plate to form a first package layer, then inkjet printing an organic material onto the first package layer using an inkjet printing process, curing it to form a film, and then forming a second package layer, and finally depositing a second inorganic thin film using an open mask plate to form a third package layer, so that the package layer is composed of the first package layer, the second package layer, and the third package layer. In some exemplary embodiments, the first and third package layers may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single layers, multilayer layers, or composite layers, and the second package layer may be made of a resin material to form an inorganic material / organic material / inorganic material laminated structure, and the organic material layer is provided between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0109] (9) As shown in Figure 16, the pattern of the touch structure layer 103 is formed on the base on which the aforementioned pattern is formed.

[0110] In some exemplary embodiments, the touch structure layer 103 may comprise a buffer layer, a first touch electrode layer (i.e., a bridge layer), a touch insulating layer (TLD), a second touch electrode layer, and a protective layer, all stacked on the package layer 98. A plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connectors may be co-located on the second touch electrode layer and formed by the same patterning process. The first touch electrodes and first connectors may be integral structures connected to each other. The second connectors may be provided on the first touch electrode layer, and adjacent second touch electrodes may be connected to each other via vias. A touch insulating layer is provided between the second touch electrode layer and the first touch electrode layer.

[0111] In several possible implementations, multiple first touch electrodes, multiple second touch electrodes, and multiple second connectors may be arranged in the same layer on the second touch electrode layer, the second touch electrodes and second connectors may be an integrated structure connected to each other, and the first connectors may be provided on the first touch electrode layer, with adjacent first touch electrodes being connected to each other via vias.

[0112] (10) A color filter layer pattern is formed on the base on which the above pattern is formed, and as shown in Figure 17, the color filter layer comprises a black matrix 71 and a color filter 72 arranged in the same layer, the black matrix 71 has a plurality of aperture regions forming a matrix arrangement, the color filter 72 is filled in the aperture regions, the color filter 72 and the black matrix 71 have at least a portion of overlapping regions, in which the color filter 72 covers the black matrix 71.

[0113] In some exemplary embodiments, forming a color filter layer pattern involves first coating a base on which the aforementioned pattern is formed with a polymer photoresist layer mixed with a black matrix material, and then exposing and developing it to form a black matrix 71 pattern; then coating the base on which the aforementioned pattern is formed with a polymer photoresist layer mixed with a red pigment, and then exposing and developing it to form a pattern of red regions; and then sequentially forming patterns of green regions and blue regions using the same method and procedure. Finally, a color filter 72 of the three primary colors of red, green, and blue arranged according to a certain rule is formed.

[0114] (11) A thin-film packaging process is performed on the base on which the above pattern is formed to form a pattern of coating protective layer 99 as shown in Figure 18, an optical adhesive 100 is coated onto the base on which the pattern of coating protective layer 99 is formed, and a cover plate 101 is bonded to the optical adhesive 100.

[0115] (12) After the manufacturing of the above film layer structure is completed, as shown in Figure 4, the display substrate is peeled off from the glass substrate 1 by a peeling process, and then one layer of the underlayment is attached to the back surface of the display substrate (the surface of the flexible base 10 that is away from the film layer) using a roller bonding method.

[0116] The manufacturing of the display board shown in Figure 4 of this embodiment is completed through the process described above. Although the display board of this embodiment was described using a top emission structure, the design of this embodiment can also be applied to a bottom emission structure or a double-sided emission structure, and can be applied to large or small size display boards.

[0117] The structures and manufacturing processes described herein are illustrative only, and in exemplary embodiments, the corresponding structures can be modified as needed in practice, and the patterning process can be increased or decreased. For example, each display unit may have three or four subpixels. Also, for example, the pixel driving circuit may be 5T1C or 7T1C. Furthermore, for example, other electrodes or leads may be provided in the film layer structure, and this disclosure does not specifically limit this. In exemplary embodiments, the source-drain metal layer may be a two-layer structure, i.e., in a plane perpendicular to the display substrate, the display substrate comprises a first insulating layer, an active layer, a second insulating layer, a first gate electrode layer, a third insulating layer, a second gate electrode layer, a fourth insulating layer, a first source-drain electrode layer, a first flat layer, a second source-drain electrode layer, and a second flat layer, formed sequentially on the base, the second source-drain electrode layer comprising at least an anode connection electrode, the anode connection electrode being connected to the drain electrode of a first thin-film transistor via a via in the first flat layer and to the anode via a via in the second flat layer.

[0118] As can be seen from the structure and manufacturing flow of the display substrate described above, the display substrate according to this disclosure is processed so that the flat layer directly facing the anode is gently undulating, thereby forming a shape with a certain degree of undulation, i.e., a diffuse reflecting anode. Furthermore, the pixel definition layer is also processed so that it is gently undulating, thereby forming a shape with unevenness, so that when the cathode is deposited, an uneven shape can be formed on the cathode as well, i.e., a scattering cathode surface is formed. As a result, when external ambient light enters the screen while the screen is off, the scattering cathode anode creates scattering with respect to the light, disrupting the direction of emission of ambient light, improving the color separation phenomenon, achieving a good screen-off effect, avoiding the problem of reduced transmittance when doping the coating protective layer with scattering particles, without increasing costs, and maintaining the advantage of high transmittance of the COE, thus meeting the future demands of 5G and low-power flexible products.

[0119] In the optical improvement color separation test model, as shown in Figure 19, when the incident light is aligned along the long axis of the color filter (CF), the simulation results are as shown in Figures 20a, 20b, and Table 1. When the incident light is aligned along the short axis of the color filter (CF), the simulation results are as shown in Figures 21a, 21b, and Table 2. [Table 1] [Table 2]

[0120] The manufacturing process for display substrates according to the embodiments of this disclosure can be implemented using existing mature manufacturing equipment, requires minimal improvement over existing processes, can improve color separation in dark conditions without adding processes or steps, is compatible with existing manufacturing processes, is easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0121] In exemplary embodiments, the display substrate of the present disclosure can be applied to display devices having pixel driving circuits, such as OLEDs, quantum dot displays (QLEDs), light-emitting diode displays (Micro LEDs or Mini LEDs), or quantum dot light-emitting diode displays (QDLEDs), etc., and the present disclosure is not limited thereto.

[0122] Exemplary embodiments of this disclosure further provide a method for manufacturing a display substrate, the display substrate may have a plurality of subpixels, and the manufacturing method is A base is formed with at least one insulating film layer, and an uneven structure is provided on the side of at least one of the insulating film layers away from the base. The invention includes forming a first electrode on the side of the insulating film layer away from the base, wherein the orthogonal projection of the uneven structure on the base and the orthogonal projection of the first electrode on the base have an overlapping region.

[0123] Embodiments of this disclosure further provide a display device comprising a display substrate of the above-described embodiment. The display device may be any product or component having a display function, such as a mobile phone, tablet PC, television, display, notebook PC, digital photo frame, or navigator.

[0124] The embodiments disclosed herein are as described above, but these are merely embodiments used to understand the disclosure and are not intended to limit the invention. Those skilled in the art may modify and change the form and details of the implementation without deviating from the spirit and scope disclosed herein, but the scope of patent protection of the invention should be limited to the scope set forth in the claims. [Explanation of Symbols]

[0125] 1. Glass substrate 10 base 10 Flexible Base 11. First Active Layer 21 First Gate 22 First capacitor electrode 31. Second capacitor electrode 41. First source electrode 42 First drain electrode 51 Anode 52 Organic light-emitting layer 53 Cathode 71 Black Matrix 72 Color Filters 91 First insulating layer 92 Second insulating layer 93 Third insulating layer 94. Fourth insulating layer 95 flat layer 96 Pixel Definition Layer 96a 1st convex part 96a1 Serrated protrusions 96b First recess 96b1 1st hole 96c Annular structure unit 97 Spacer layer 98 Packaging Layers 99 Coating protective layer 100 Optical Adhesives 101 Cover Plate 102 Driving structure layer 103 Touch Structure Layer 951 Second uneven structure 961 1st uneven structure

Claims

1. A display substrate comprising a base, at least one insulating film layer provided on the base, and a first electrode provided on the side of the insulating film layer away from the base, An uneven structure is provided on the side of at least one of the insulating film layers away from the base, and the orthogonal projection of the uneven structure on the base and the orthogonal projection of the first electrode on the base have an overlapping region. The display substrate comprises a flat layer, an emissive structure layer, a package layer, and a color filter layer sequentially formed on the base, and the emissive structure layer comprises a pixel definition layer, an anode, a cathode, and an organic emissive layer located between the anode and the cathode. The at least one insulating film layer comprises the flat layer, and the first electrode comprises the anode. The color filter layer comprises a black matrix and a color filter provided at intervals, and the pixel definition layer comprises a plurality of pixel apertures and a plurality of first protrusions, with a first recess formed between adjacent first protrusions. The first recess is a groove surrounding the pixel aperture, and the distance between adjacent grooves is 1 / 8 to 7 / 8 of the distance between the edge of the aperture region of the black matrix and the edge of the pixel aperture formed in the pixel definition layer. A display substrate wherein the flat layer comprises a plurality of second protrusions, and a second recess is formed between adjacent second protrusions.

2. The pixel aperture exposes at least a portion of the anode, and the cathode covers the pixel definition layer. The display substrate according to claim 1, wherein the black matrix has a plurality of aperture regions forming a matrix arrangement, at least a portion of the color filter is filled within the aperture regions, the color filter and the black matrix have at least a portion of overlapping regions, and in the overlapping regions the color filter covers the black matrix.

3. The display substrate according to claim 2, wherein at least one of the insulating film layers comprises the pixel definition layer, and the first electrode comprises the cathode.

4. The display substrate according to claim 1, wherein the step difference between the second protrusion and the second recess is 1 / 8 to 7 / 8 of the thickness of the flat layer.

5. The display substrate according to claim 1, wherein the distance between adjacent grooves is 1 to 2 micrometers.

6. The display substrate according to claim 1, wherein the width of the groove is 0.8 to 1.5 micrometers.

7. The display substrate according to claim 1, wherein the first recess is further configured as an opening surrounding the pixel aperture, and the width of the opening is 0.5 to 1.8 micrometers.

8. The display substrate according to claim 7, wherein the plurality of openings constitute a plurality of annular structural units, at least one annular structural unit comprises N annular structures provided around the pixel aperture and parallel to each other, the innermost annular structure comprises a plurality of first openings, the first openings and the pixel aperture are adjacent, and N is a natural number greater than 1.

9. The display substrate according to claim 8, wherein sawtooth-shaped protrusions are formed between a plurality of first openings, and the width of the sawtooth-shaped protrusions is 0.8 to 1.5 micrometers.

10. The display board according to claim 9, wherein N is a natural number between 1 and 50.

11. The display substrate according to claim 1, wherein the second protrusion is serrated.

12. The display substrate according to claim 1, wherein the step difference between the second protrusion and the second recess is 0.2 to 0.8 micrometers.

13. At least one of the insulating film layers comprises the pixel definition layer and the flat layer, and the first electrode comprises the cathode and the anode. A first uneven structure is provided on the side of the pixel definition layer away from the base, and the orthogonal projection of the first uneven structure on the base and the orthogonal projection of the cathode on the base have an overlapping region. The display substrate according to claim 2, wherein a second uneven structure is provided on the side of the flat layer away from the base, and the orthographic projection of the second uneven structure on the base and the orthographic projection of the anode on the base have an overlapping region.

14. Furthermore, the display substrate according to claim 5, further comprising a touch structure layer provided between the package layer and the color filter layer, wherein the touch structure layer comprises a plurality of touch electrodes, and the orthogonal projection of the black matrix on the base includes the orthogonal projection of the touch electrodes on the base.

15. A display device comprising the display board described in claim 1.

16. A method for manufacturing a display board, A base is formed with at least one insulating film layer, and an uneven structure is provided on the side of at least one of the insulating film layers away from the base. The first electrode is formed on the side of the insulating film layer away from the base, and the orthogonal projection of the uneven structure on the base and the orthogonal projection of the first electrode on the base have an overlapping region. The manufacturing method includes sequentially forming a flat layer, an emissive structure layer, a package layer, and a color filter layer on a base, wherein the emissive structure layer comprises a pixel definition layer, an anode, a cathode, and an organic emissive layer located between the anode and the cathode, the at least one insulating film layer comprises the flat layer, and the first electrode comprises the anode. The color filter layer comprises a black matrix and a color filter provided at intervals, and the pixel definition layer comprises a plurality of pixel apertures and a plurality of first protrusions, with a first recess formed between adjacent first protrusions. The first recess is a groove surrounding the pixel aperture, and the distance between adjacent grooves is 1 / 8 to 7 / 8 of the distance between the edge of the aperture region of the black matrix and the edge of the pixel aperture formed in the pixel definition layer. A method for manufacturing a display substrate, wherein the flat layer comprises a plurality of second protrusions, and a second recess is formed between adjacent second protrusions.

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