Systems and methods using multilayer qubit grid arrays for quantum computing

Abstract

We provide a quantum computing (QC) system that employs a lattice array structure with more than one dimension. [Solution] A quantum computing (QC) system comprising multiple qubits substantially arranged in multiple substantially parallel plane regions, wherein at least some of the substantially plane regions comprise two or more qubits 38a to 38c, and one or more qubits in each substantially plane region are configured to interact with one or more qubits in at least one other substantially plane region.

Description

Detailed description of the invention

[0001] [background] <Field> This application generally concerns quantum computing (QC), and more specifically, quantum computer architectures employing lattice array structures with more than one dimension.

[0002] <Explanation of related technologies> Technological pathways aimed at scalable quantum computing are diversifying. Performance, as demonstrated in various performance metrics, varies significantly depending on the type of physical qubit (also called "qubit") employed by each approach. Approaches based on trapped ions, or superconducting qubits, have consistently led this field for over 20 years. [overview]

[0003] Certain embodiments disclosed herein provide a quantum computer architecture that employs a lattice array structure of greater than one dimension for executing quantum gates in which more than two qubits can be simultaneously entangled and for mutual coupling. Certain embodiments disclosed herein provide a quantum microprocessor structure and gate array design platform for a field-programmable gate array (FPGA)-like quantum processing chip that can advantageously provide a certain degree of reconfiguration possibility. Certain embodiments disclosed herein provide a quantum microprocessor structure and gate array design platform for an application-specific integrated circuit (ASIC)-like quantum processing chip that can advantageously be optimized for a particular application and can advantageously provide custom design flexibility.

[0004] Certain embodiments disclosed herein include lattice arrangements comprising a plurality of fully connected qubits arranged as an array of three-dimensional (3D) lattice structures (e.g., cells), where simultaneous operation of multi-qubit gates is enabled by the qubits arranged in a geometric layout. For example, certain embodiments may be configured as a plurality of two-dimensional (2D) (e.g., planar) qubit arrays, which are substantially parallel to each other to form an array of three-dimensional (3D) cells. In another example, certain other embodiments may be configured as a plurality of one-dimensional (1D) (e.g., linear) qubit arrays (e.g., rows and columns, lattices, chains) which are substantially parallel to each other. In both of these examples, the array of cells can be analogous to and may be referred to as a three-dimensional crystal structure. While various embodiments utilize trapped ion qubits (e.g., in a microchip structure) to describe the nature of the quantum interactions utilized (e.g., optimized), other embodiments may employ one or more alternative qubit techniques.

[0005] Certain embodiments disclosed herein provide a quantum computing (QC) system comprising a plurality of qubits substantially arranged in a plurality of substantially planar regions (e.g., planes, layers) substantially parallel to each other, wherein at least some of the substantially planar regions comprise two or more qubits, and one or more qubits in each substantially planar region are configured to interact with one or more qubits in at least one adjacent substantially planar region. For example, the QC system may comprise a first substrate and a second substrate, the first and second substrates being substantially parallel to each other, and the QC system may further comprise a multi-qubit gate array comprising a plurality of qubits arranged as a plurality of multi-qubit gates located in the region between the first and second substrates. A surface electrode trap can be provided that is configured to include ions (e.g., charged atoms, charged molecules) on at least one surface of a plate or in the vicinity of the surface, and at least some of the qubits in at least one substantially planar region are configured to interact (e.g., become quantum mechanically entangled) with at least some of the qubits in at least one other (e.g., adjacent) substantially planar region, and can be disposed in a plurality of substantially planar regions (e.g., planes, layers, horizontal planes).

[0006] Certain embodiments disclosed herein provide a quantum computing (QC) system comprising a plurality of qubits disposed in a plurality of linear arrays that are substantially parallel to each other, at least some of the linear arrays comprising two or more qubits, and one or more qubits of each linear array being configured to interact with one or more qubits of at least one adjacent linear array. For example, the QC system can comprise a multi-qubit gate array comprising a plurality of qubits disposed as a plurality of multi-qubit gates in a region between two or more substrates. The qubits of the multi-qubit gate array can be provided with a surface electrode trap configured to include ions (e.g., charged atoms, charged molecules) on at least one surface of a substrate or in the vicinity of the surface, and at least some of the qubits in at least one linear array can be disposed in a plurality of linear arrays in a state configured to interact (e.g., become quantum mechanically entangled) with at least some of the qubits in at least one other (e.g., adjacent) linear array.

Brief Description of the Drawings

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments described herein and, together with the description, explain these embodiments. [Figure 1A] Schematically shows various aspects of an example of a multi-qubit gate (e.g., cell) according to certain embodiments described herein. [Figure 1B]Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 1C] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 2A] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 2B] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 2C] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 2D] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 2E] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 2F] Various aspects of examples of multi-qubit gates (e.g., cells) according to certain embodiments described herein are schematically shown. [Figure 3A] Schematic top views of four examples of the first part (e.g., base) of an example array having four multi-ionic qubit gates (e.g., cells) according to a particular embodiment described herein are schematically shown. [Figure 3B] Schematic top views are shown of four examples of the second parts (e.g., caps) of the array and four multi-ionic qubit gate examples according to certain embodiments described herein. [Figure 3C] Figures 3A-3B schematically show exploded views and top views, respectively, of an example of the array and four multi-ion qubit gates according to a particular embodiment described herein. [Figure 3D]Figures 3A-3B schematically show exploded views and top views, respectively, of an example of the array and four multi-ion qubit gates according to a particular embodiment described herein. [Figure 3E] A schematic exploded view of another example of an array having four 10-ion qubit gates according to a particular embodiment described herein is shown. [Figure 4A] The exploded view and top-down view schematicly show an example of an array having 16 multi-ion qubit gates in a 4x4 array according to a particular embodiment described herein. [Figure 4B] The exploded view and top-down view schematicly show an example of an array having 16 multi-ion qubit gates in a 4x4 array according to a particular embodiment described herein. [Figure 4C] A schematic top-down superposition diagram of another example of a multi-ion qubit gate array having 16 multi-ion qubit gates according to a particular embodiment described herein is shown. [Figure 4D] A schematic top view superposition diagram of another example of a multi-ion qubit gate array having four multi-ion qubit gates according to a particular embodiment described herein is shown. [Figure 4E] A schematic top-down superposition diagram of another example of a multi-ion qubit gate array having 16 multi-ion qubit gates according to a particular embodiment described herein is shown. [Figure 4F] The exploded view and top-down view of another example array having 16 multi-ionic qubit gates in a 4x4 array according to a particular embodiment described herein are schematically shown. [Figure 4G] The exploded view and top-down view of another example array having 16 multi-ionic qubit gates in a 4x4 array according to a particular embodiment described herein are schematically shown. [Figure 5A]Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5B] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5C] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5D] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5E] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5F] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5G] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5H] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 5I] Some schematic diagrams of various examples of QC structures according to certain embodiments described herein are shown below. [Figure 6A] A schematic superposition diagram of an example of a 4x4 array having multiple optical ports according to a particular embodiment described herein, in which 4-ion qubit gates and 13-ion qubit gates are alternated, is shown from above. [Figure 6B] The optical signals irradiating the ions of the array in Figure 6A according to a specific embodiment described herein are schematically shown. [Figure 6C] The optical signals irradiating the ions of the array in Figure 6A according to a specific embodiment described herein are schematically shown. [Figure 6D] The optical signals irradiating the ions of the array in Figure 6A according to a specific embodiment described herein are schematically shown. [Figure 6E]A schematic top view of the base portion of another example of a 4x4 array of 10-ion qubit gates having multiple ion input holes and optical ports according to a particular embodiment described herein, and a superimposed base and cap portion are shown. [Figure 6F] A schematic diagram shows the superposition of the base and cap portions of another example of a 4x4 array of 10-ion qubit gates having multiple microwave antenna regions according to a particular embodiment described herein. [Figure 7A] A schematic side view of a part of an example of a QC structure according to a particular embodiment described herein is shown. [Figure 7B] A schematic close-up view of a smaller portion of the QC structure in Figure 7A according to a particular embodiment described herein is shown. [Figure 7C] A schematic diagram of another example of a QC structure according to a particular embodiment described herein is shown. [Figure 7D] A schematic diagram of another example of a QC structure according to a particular embodiment described herein is shown. [Figure 7E] A schematic diagram of an ion input port and a single-ion photodetector according to a specific embodiment described herein is shown. [Figure 8] A schematic side view and a top projection view of an example of a QC structure comprising a 16 × 16 cell array according to a particular embodiment described herein are shown. [Figure 9] Four tables are shown comparing the total number of qubits for various 4x4 cell arrays according to certain embodiments described herein. [Modes for carrying out the invention]

[0008] [Detailed explanation] <Overview> Certain embodiments of the quantum computing (QC) systems described herein advantageously provide a multilayer architecture that allows an optimal number of qubits to be entangled simultaneously between the nearest and second nearest neighbors. Certain embodiments include electrical and optical access transmission paths for addressing, control, detection, and readout, as required to construct a scalable quantum processor. Arrays of fully connected qubits offer a more efficient and flexible choice for running quantum algorithms in hardware than designs where entanglement gate operations are limited to specific sets, depending on the type of qubits employed or their layout. This improved efficiency and flexibility increases rapidly with the number of qubits in the array. Adding the ability to perform gate operations involving two or more qubits at once can significantly accelerate the efficiency improvements over designs limited to 1- and 2-qubit gates, where a single 4-qubit gate can replace dozens of 1- and 2-qubit gates. Certain embodiments described herein employ multi-qubit arrays (e.g., multiple directly coupled planar and / or linear arrays) to advantageously avoid the problems of one-dimensional and two-dimensional geometric arrangements (e.g., coupling constraints, electrode congestion required to control each qubit within a gate, which can significantly widen gate spacing). In certain embodiments, multidimensional cells of qubits are formed, similar to crystals such as pyrochlore. Inverting the qubits and cells (e.g., in alternating rows) can enable tiling of more closely spaced cells, allowing for spacing for optical access, control, and readout. Utilizing a large number of qubits involved per gate can also reduce the need for circuit depth, error correction, and interference mitigation. Interchangeable component cells can enable quantum FPGAs (QFPGAs) and quantum ASICs (QASICs) chips.

[0009] Certain embodiments of the QC systems described herein consist of a multilayer arrangement comprising multiple fully connected qubits arranged as an array of three-dimensional (3D) lattice structures (e.g., cells), where simultaneous operation of multi-qubit gates is enabled by the qubits arranged in a geometric layout. For example, multiple layered planar or linear qubit arrays (e.g., rows and columns, lattices, chains) can be substantially parallel to each other and form an array of 3D cells that are analogous to and may be referred to as a crystal structure. In certain embodiments, qubits can be equivalently suspended (e.g., trapped) above and below (or above and below, left and right, etc.) multiple mutually aligned qubit storage regions (e.g., opposing parallel ion trap arrays) without requiring photons or other interconnections, or without significant time delays, to enable direct and optimal coherent coupling (e.g., entanglement) between nearest qubits, second nearest qubits, etc., across substantially planar regions of multiple arrays (e.g., layers, horizontal planes, planes), thereby enabling direct and optimal coherent coupling (e.g., entanglement) between nearest qubits, second nearest qubits, etc., across multiple mutually aligned qubit storage regions (e.g., opposing parallel ion trap arrays). Certain such embodiments utilize geometrically symmetric cell structures that result in the ability to perform gate operations involving two or more qubits at once, which can significantly accelerate efficiency improvements over designs limited to 1 and 2-qubit gates, with a single 4-qubit gate potentially replacing dozens of 1 and 2-qubit gates. Certain embodiments described herein utilize a qubit array in multiple directly coupled substantially planar regions (e.g., layers, horizontal planes, faces) to advantageously avoid the problems of one- and two-dimensional geometric arrangement (e.g., constraints on coupling, the need to control each qubit within the gate, which can significantly widen the gate spacing, and electrode crowding). In certain embodiments, a multidimensional cell of qubits is formed, which is analogous to a crystal such as pyrochlore. Inverting the qubits and cells (e.g., in alternating rows) can allow for tiling of more closely spaced cells, which can provide spacing for optical access, control, and readout.Utilizing a large number of qubits involved in each gate can reduce and minimize the need for circuit depth, error correction, and interference mitigation. Interchangeable component cells can enable quantum FPGAs (QFPGAs) and quantum ASICs (QASICs) chips.

[0010] While various embodiments of the trap-ion qubit approach are described herein due to their physical properties, other qubit approaches (e.g., superconducting qubits) can also be used in certain embodiments described herein without loss of generality.

[0011] Certain embodiments of the QC systems described herein comprise a plurality of multi-qubit three-dimensional (3D) gate cells, each cell comprising at least three qubits that can be fully coupled simultaneously across three dimensions, and the plurality of multi-qubit cells are configured for gate operations of two or more multi-qubit gates. A QC system of a particular embodiment may comprise a plurality of mutually aligned qubit storage regions, such as opposing parallel ion trap arrays, which directly enable optimal coherent coupling or entanglement between nearest-neighbor and second-neighbor qubits, etc., across layers, horizontal planes, or surfaces of the plurality of arrays, without requiring photons or other mutual coupling. The multi-qubit cells may be configured using geometric symmetry such that multi-qubit gates can be spontaneously affected in a single gate operation without relying on the coupling of a plurality of 1 and 2-qubit gates. Utilizing the symmetry of equilateral coupling distances between the plurality of qubits in the cell allows more than two entangled qubits to perform gate operations at once, otherwise more qubit gate operations involving only 1 and 2-qubit gates would be required. A multi-qubit cell may include, or may include, an asymmetric 3D structure having complementary bases and caps arranged in alternating directions (up / down, left / right, or other opposing planes). This alternating arrangement of asymmetric 3D cells can allow for an alternating arrangement of non-identical bases and caps of adjacent cells, including their, extended, or overlapping electrode regions, and for optimal tying of cells of a given size or region. This results in spacing and shaping. Multiple alternating directional lattices or arrays of asymmetric cell structures can mitigate the problems of one and two-dimensional geometric arrangement, such as the congestion of electrodes required to control each qubit within the gate, the limited optical access, the complex management of stray light, and the limited electrical connectivity, which can detrimentally increase gate spacing. Qubits and cells can be inverted in alternating rows in a way that allows for closer cell tiling and open transmission path space between cells for optical access, control, and readout. Symmetric or equilateral coupled geometry of multiple qubits per cell can enable more complex quantum gates to be executed in a single gate operation, further reducing the need for circuit depth, error correction, and interference mitigation. Replaceable component cells can enable quantum FPGAs (QFPGAs) and quantum ASICs (QASICs) chips, which can be highly reconfigurable.

[0012] Certain embodiments of the QC systems described herein advantageously provide a three-dimensional (3D) layout of qubits and / or qubit gates, which is less advantageous than a one-dimensional (1D) or two-dimensional (2D) layout (e.g., JICirac and P. Zolle). This facilitates the use of more qubits and / or qubit gates for computation than would be supplied by, for example, "A scalable quantum computer with ions in an array of microtraps," Nature, Vol. 404, p. 579 (2000), see J. Chiaverini et al., Quant. Inf. Comp. Vol. 5, 419 (2005). For example, certain embodiments described herein provide a 3D layout of qubit gates, each of which comprises multiple ions (e.g., four or more ions entangled simultaneously), with sufficient spacing to facilitate addressing, manipulating, controlling, reading, and electrical coupling and optical paths for potential sideband cooling of each qubit, while providing line-of-sight access angles.

[0013] When a particular arrangement or set of qubits allows all qubits to directly and quantum mechanically entangle with all other qubits in that set, these qubits can be described as "fully coupled." Even a small number of qubits containing fully coupled ions in a one-dimensional (1D) linear ion trap can exhibit significantly higher potential processing power than the same number of qubits simply coupled in pairs (e.g., NMLinke et al. "Experimental comparison"). See "comparative experiment of two quantum computing architectures" PNAS, Vol.114, no.13 (2017).

[0014] Quantum computing (QC) designs demonstrated over the past 20 years show that the parameter that most influences how quickly a quantum computer can outperform its corresponding classical computer is not simply based on how many qubits are coupled in some way. This is demonstrated by the increased interest in circuit model QC hardware, where the number of qubits is often less than one-hundredth of the number of qubits required by major quantum annealing approaches that do not perform single-gate operations. The demonstrated performance of such systems ultimately depends on the fidelity of the qubits (e.g., how accurately the system can perform gate operations), how the qubits are coupled together, and how much overhead is used to enable the qubits to work together to compute solutions to difficult problems.

[0015] A 1-qubit gate is a specific quantum superposition of "0" to "1", or "0" and "1". In addition, this simply and inevitably involves the switching of qubits by themselves. A two-qubit gate combines two qubits using superposition, which is combined with quantum entanglement, so that something that happens to one qubit affects the other. In such a two-qubit gate, the target qubit may start in state "0" or state "1", or it may be any superposition of "0" and "1" (e.g., somewhere between "0" and "1"). For example, the function of a quantum-controlled NOT (CNOT) gate is to switch the target qubit if the control qubit is in state "1", and do nothing otherwise. One- or two-qubit gates can be directly implemented in a number of different quantum gate architectures. For more complex gate operations, embodiments that can entangle more than two qubits at once can have a significant impact on the total number of qubits, the steps performed to achieve the operation, and the algorithms that embody them (see, for example, C. Figgatt et al. "Parallel entangling operations on a universal ion-trap quantum computer," Nature, Vol. 571 (2019) and Y. Lu et al. "Global entangling gates on arbitrary qubits," Nature, Vol. 571 (2019)). In some examples, a negligible reduction in the number of qubits and steps used beforehand leads to a dramatic reduction in the overhead required to achieve a successful result. One example might be a prototype demonstration that could provide a solution to a problem that is otherwise difficult to solve, with fewer associated ancilla and without large-scale error correction, even if only temporarily.

[0016] Certain embodiments described herein utilize multiple fully connected high-fidelity qubits. An advantage of such particular embodiments (for example, how much more efficient a particular quantum gate operation can be compared to using a combination of 1 and 2 qubit gates) is the quantum triple-controlled NOT gate (C) with four fully connected high-fidelity qubits. 3 This can be explained by considering the example of a NOT gate. 3 The NOT gate is also called a super-Toffoli gate. 3 In the example of a NOT gate, all three control qubits must be in a specific state (e.g., (1,1,1)) in order to switch the fourth target qubit from "1" to "0". When combined with one or more single qubit gate operations, such multi-qubit quantum gates can be used to complete a universal set for quantum computing. Multiple controlled NOT gates are described in reference as generally including an extended set of 1 and 2 qubit gate operations (see, for example, MANielsen and ILChuang, "Quantum Computing and Quantum Information," 1st ed. (Cambridge Univ. Press, 2000)). To what extent these 1 and 2 qubit gate series can be further increased in physical implementations depends on the type of qubits used and how many qubits can be fully connected and entangled with each other. However, in a suitable physical layout, C can be performed using four ions that are fully connected and simultaneously multiple entangled. 3 NOT gates are performed using only 1- and 2-qubit gates. 3 It can be constructed with far fewer quantum gate operations than those used in NOT gates. This is a simpler C 2It can be implemented by starting from an extension of the method described for the implementation of the NOT Toffoli gate (see, for example, J. I. Cirac and P. Zoller, "Quantum Computations with Cold Trapped Ions", Phys. Rev. Lett. Vol. 74(20)(1995)) and as subsequently demonstrated (see, for example, T. Monz et al., "Realization of the Quantum Toffoli gate with Trapped Ions", Phys. Rev. Lett. Vol. 102, 040501(2009)). The implementation of the 3-qubit C 2 NOT has already shown a significant reduction in the number of contributing gates and the time required to complete all gate operations. On the other hand, for concatenations of 1- and 2-qubit gates, even if they are individually very high fidelity, due to the aggregated gate errors, it results in an improvement in the net fidelity. This 3-qubit gate can be realized in a linear trap without strongly requiring geometric symmetry. In contrast, certain embodiments described herein utilize the full 3D symmetry of the design described herein to provide a C n NOT gate. In this way, the examples with improved efficiency as described above can be greatly expanded by the number of controls in each C n NOT gate through the accompanying reduction in the quantum gates required to implement them. Other multi-controlled gate operations including phase rotations show similar improvements in efficiency using physical arrangements involving more than two entangled qubits simultaneously. These prior improvements can significantly reduce error correction.

[0017] Even the highest quality qubits exhibit a significant error rate, which may be small per qubit but multiplied by the number of gates used to execute the algorithm. When the total error rate reaches a threshold where error correction is required to perform the operation with a sufficient probability of giving reliable results even with a small set of qubits, the efficiency of the architecture immediately decreases in proportion to the amount of overhead used for error correction.

[0018] For small quantum computers with several hundred relatively high-quality qubits intended to perform logical operations, the overhead of error-correcting qubits with added ancilla can be an order of magnitude, or approximately tenfold, increase in the number of qubits, along with a proportional decrease in efficiency. For larger systems, the overhead can increase by several orders of magnitude further. However, in certain embodiments described herein, quantum computers that benefit from the overall efficiency of fully connected high-quality qubits and employ multi-qubit gate operations (e.g., those performed naturally by utilizing multidimensional shapes) can use significantly fewer steps and a significantly smaller total number of qubits. As used herein, the term “natural” gate operation indicates that more than two qubits can be involved simultaneously due to the geometric layout. Certain embodiments of natural multi-qubit gates described herein can advantageously execute algorithms without using large error-correction overhead. Furthermore, the significant improvement in overall design efficiency due to the reduced overhead can be achieved with several orders of magnitude fewer quantum resources, running basic quantum computing algorithms or subroutines and demonstrating increased speed and practicality compared to classical computer systems.

[0019] To date, many QC systems using trapped ions employ one-dimensional (e.g., linear) traps, which can then be electrically or photonly coupled (e.g., U.S. Patent No. 9,858,531, Debnath et al. "Demonstration"). (See "Demonstration of a small programmable quantum computer with atomic qubits," Nature, Vol. 536, p. 63 (2016)). Such 1D traps allow linear chains of qubits to be fully coupled within a common potential well or trap region. The scale of the fully coupled is limited by how many qubits can be coupled together before the coupling force between qubits at or near both ends of the linear chain becomes too weak to be used for reliable multi-qubit gate operations, and for this reason it may be preferable to generate mutual coupling between multiple linear traps of a limited length. For example, optical mutual coupling can be employed to transfer a qubit state from an ion to a photon, and then send the photon to another linear trap in which the quantum state has been transferred to another ion. One type of protocol commonly used for such a process is called "quantum teleportation." Such mutual coupling allows for transformation (e.g., trap ion quantity) This gives rise to time delays and potential inefficiencies in the photon (from the child qubit and the second trapped ion from the trapped ion qubit). Certain embodiments described herein advantageously provide alternative arrangements for simultaneously optimizing direct interactions between qubits compared to those that can be efficiently done using linear or 2D elements with optical mutual coupling. When scaling to a larger number of qubits, certain such embodiments can favorably reduce or avoid the number of optical mutual couplings between nodes, along with their associated disadvantages (e.g., time delays, ion-photon conversion losses).

[0020] Rectangular two-dimensional (2D) grid arrangements have already been employed in several trap-ion approaches and superconducting qubit (SCQ) concepts. However, the interactions between qubits have been limited to one- and two-qubit operations occurring within the trap-ion grid lanes (e.g., by moving qubits back and forth in and out of lanes through intersections). Such approaches rely considerably on redundancy to increase the degree of fault tolerance in order to raise the probability of successful algorithm execution to a usable level. For example, some approaches use a global addressing of the qubit set, where qubits back and forth in and out of aligned intersections of the grid, thereby redundantly generating a single one- or two-qubit operation among many qubits, and then averaging to reduce errors. The overhead in such approaches increases sharply with the scale of the logical operations performed by the quantum computer in terms of the number of redundant qubits required to generate a single logical operation with sufficient fidelity. Conversely, in certain embodiments described herein, by providing qubits arranged in two or more dimensions, entanglement between more than two qubits is possible, thereby enabling simultaneous involvement and directly or naturally generating multi-qubit gate operations.

[0021] To distinguish certain embodiments described herein from other approaches that may appear similar in descriptive terminology and visual layout, attention should be paid to the overall layout of 2D periodic crystal structures, such as triangular lattice Penning traps (for example, the surface of a periodic electron potential well where ions can be arranged to form an extended 2D crystal or triangular lattice is useful for learning the physical properties of many-body interactions but not for performing gate operations between multiple qubits, and the hexagonal Kitaev model may be similar to, but different from, a part of, certain multilayer embodiments described herein (e.g., a single layer) (e.g., A. Kitaev, Ann. Phys. Vol. 321, 2 (2006), R. Schmied et al. New J. Phys. 13 115011 (2011) ("Schmied (See "2011"). However, such 2D periodic crystal structures differ significantly in design complexity and purpose from certain embodiments described herein. For example, such crystal lattice structures have been designed solely for the simulation of quantum systems. Such structures are not generally intended to perform gate operations and may be used to form an energy topology that mimics that of a modeled quantum system (e.g., to find the lowest electronic energy structure of a given molecule). In particular, quantum simulators with 2D hexagonal lattice ions (e.g., following the Kitaev model) can generally use fewer electrode structures than a "full-scale" quantum computer with quantum gate operation capabilities. Therefore, the shape of the electrode structures in a quantum simulator is less affected by overall design constraints than the shape of electrode structures for scalable gate-based quantum computing.

[0022] Nevertheless, the algorithm can still be used to assist in the design (e.g., optimization) of electrode structures for gate-model quantum computers, for trapping and holding individual ions within periodic lattices (e.g., for individual trap regions in larger trap-ion architectures) (see, e.g., R. Schmied, et al., Phys Rev. Lett. 2009 ("Schmied 2009")). One general guideline for electrode structure design, derived from ed 2009, states that, assuming M traps (e.g., microtraps) per unit cell, the number of surface patch electrodes is generally at least 8M for fully controlled and effective gate operation.

[0023] Furthermore, crowding of surface electrodes can occur to control each ion in the 2D layer of trapped ions for gate operation. Such crowding may be due to the region of eight or more surface electrodes, resulting in complete control of the ions within its electron potential well, limiting how close the ion trap regions can be positioned together, while still allowing for strong bonding for effective gate interaction. The bonding force is strongly dependent on the inter-ion distance (d), and the bonding force or exchange frequency Ω ex is, equation

number

[0024] Certain embodiments described herein favorably facilitate the resolution of other hardware challenges that may seem extremely difficult or impossible when designing gate model QC structures scaled up from 2D trapped ion lattices. For example, certain embodiments described herein incorporate optical components (e.g., lasers, optical ports, fibers, detectors) into the QC structure to address, process, read out, and provide potential sideband cooling for each qubit and line-of-sight access angles.

[0025] Certain embodiments described herein advantageously provide scalable hardware configurations that enable direct “writing” and execution of complex quantum algorithms by allowing simultaneous entanglement between an optimal number of adjacent qubits. In certain embodiments, embodiments of multidimensional quantum gates, similar to conventional firmware such as field-programmable gate arrays (FPGAs), can be directly written and flexibly reprogrammed in the form of multi-qubit gates.

[0026] Certain embodiments described herein advantageously enable multiple-controlled quantum gate operations that are naturally performed by utilizing multidimensional shapes. In certain embodiments, the quantum gate operation is performed on a quantum firmware platform in the fewest number of steps (for example, without using a chain of 1- and 2-qubit gate operations to result in a multiple-controlled NOT operation).

[0027] Certain embodiments described herein advantageously provide a feasible engineering structure that enables universal quantum computing by integrating electrical and optical transmission paths for complete control and readout of each qubit within the circuit model architecture, thereby allowing the quantum firmware platform to be arbitrarily scaled up.

[0028] Certain embodiments described herein advantageously provide a multilayer quantum computing structure configured to allow an optimal number of qubits to be entangled simultaneously beyond potential between nearest neighbors and second nearest neighbors. Certain such embodiments include electrical and optical access transmission paths for addressing, controlling, and reading qubits in a scalable quantum processor. For example, an array of fully connected qubits advantageously provides a more efficient and flexible choice for implementing quantum algorithms in hardware than other designs where entanglement gate operations are limited to specific pairs (e.g., by the type of qubits employed or their layout). This improved efficiency and flexibility can increase rapidly with the number of qubits in the array.

[0029] Certain embodiments described herein can advantageously perform gate operations involving more than two qubits at once, thereby resulting in a significant improvement in efficiency compared to conventional designs limited to 1- and 2-qubit gates (e.g., by replacing dozens of such gates with a single 4-qubit gate). Certain embodiments described herein advantageously overcome the coupling limitations found in 1- and 2-dimensional shapes using trapped ions. For example, arranging qubits in a multi-qubit array (e.g., a multi-planar and / or linear qubit array) with direct coupling (e.g., entanglement) between qubit arrays can solve the considerable time delays and inefficiencies of the conversion from ion qubits to photon qubits and back, in order to continue scaling up from dozens of ions in a 1D chain. Furthermore, arrays of qubits in multiple planes can solve the problem that arose from the congestion of electrodes for controlling each qubit in the gate, otherwise the electrode congestion would significantly widen the gate spacing. In another example, selectively inverting an electron potential well between opposing surfaces could allow the maximum number of adjacent qubits to participate in gate operations.

[0030] Certain embodiments described herein advantageously utilize a first set of trapped ions above a first surface and a second set of trapped ions below a second surface, where the second surface faces the first surface, and at least some ions of the second set of ions are entangled with at least some ions of the first set of ions. By integrating and alternating the first and second sets of trapped ions, and by adjusting the trap height of the central ion of the qubit gate relative to the ion at the vertex of the qubit gate, certain embodiments advantageously provide a multidimensional entanglement shape similar to a complex 3D crystal structure (e.g., pyrochlore). Furthermore, the space between the first and second surfaces in certain embodiments advantageously provides lateral optical access for globally or locally addressing the qubit, as well as optical access for reading it out by a detector. Multi-ion qubit gates (e.g., cells) can be constructed asymmetrically, so that the cap of each cell (e.g., either up or down) provides additional space for integrating the optics and electronics used to initialize, process, and read out the qubits individually or as a whole. For example, rows of these multi-ion qubit gates (e.g., cells) can be arranged alternately with alternating "up" and "down" cell orientations, forming transmission paths that provide additional multi-angle optical access and electronic control lines between rows of cells. Since gravity is not the dominant force with respect to trapped ions, the overall arrangement can be oriented at any angle (e.g., tilted 90 degrees, replacing "up" and "down" with "left" and "right"). For other types of qubits, this general insensitivity of orientation of trapped ions may not apply to the same degree, and other types of qubits may also limit the choice of orientation. <Examples>

[0031] Certain embodiments described herein involve a 3D crystal structure (e.g., pyrochlore) It utilizes multidimensional cells of qubits that may be similar to those found in other systems. In certain embodiments, inverting cells in alternating rows allows for tiling of cells closer together and spacing for optical access, control, and readout. Certain embodiments utilize a large number of qubits per gate, which is advantageous in reducing (e.g., minimizing) circuit depth, error correction, and interference mitigation. Certain embodiments utilize interchangeable component cells, which can advantageously enable quantum FPGA (QFPGA) and quantum ASIC (QASIC) chips.

[0032] While the physical structure of a particular embodiment is described herein using high-fidelity trapped ion qubits (e.g., having a low error rate), according to a particular embodiment described herein, any kind of qubit (e.g., naturally occurring, artificially formed) that can simultaneously entangle with multiple other qubits in multiple dimensions may be used. Examples of qubits suitable for a particular embodiment described herein include, but are not limited to, subatomic particles, neutral atoms, ions, neutral molecules, charged molecules, Bose-Einstein condensates, electrons, electron holes, excitons, magnetic qubits, nitrogen vacancy centers in diamond, phonons, photons, quantum dots, Rydberg atoms, spins in silicon, and, optionally, superconducting qubits. In a particular embodiment, the qubit is suitable for directly (e.g., naturally) generating gate operations between two or more qubits in a particular configuration. For example, the physical architecture of a particular embodiment may directly benefit from complex gate operations such as multiple controlled NOTs or phase rotations without using serial linking of 1- and 2-qubit gates.

[0033] The trapped ion qubits used in certain embodiments described herein exhibit the properties of optimized quantum interaction. The appropriate figure of merit exhibited by the trapped ions includes, but is not limited to, (i) the fact that they are identical within a given species, and therefore large-scale calibration or tuning can be advantageously avoided; (ii) the ability to form qubits with very long-term stability; and (iii) sustained and demonstrated high-fidelity gate operations compared to competing qubit technologies. In certain embodiments described herein, simultaneous multi-qubit gate operations can be realized by ions arranged in a 3D geometric layout of multiple identical fully connected qubits.

[0034] Figures 1A-1C and 2A-2D schematically illustrate various aspects of a multi-qubit gate (e.g., a cell) according to a particular embodiment described herein. The qubit gate is formed by scattering electron potential wells both above and below parallel surface planes and using the electron potential wells to trap (capture) ions that become entangled with other trapped ions. Examples of ions that fit the particular embodiment described herein, but are not limited to, Ba + Be + , Cd + Ca + Mg + Hg + Sr + Yb + This includes vertical directions. Vertical directions are not required, and therefore, "top" and "bottom" are not used.

[0035] Figure 1A schematically shows side and top views of an example of a single-ion portion 10 of a 4-ion qubit gate 100 according to a particular embodiment described herein. The single-ion portion 10 has a substantially planar substrate region 12, one or more electrical traces 14, an electrode region 16 including one or more electrodes (not shown), an electron potential well 17, and a single ion 18. In a particular embodiment, the substrate region 12 has an electrically insulating portion and / or a semiconductor (e.g., silicon oxide, silicon) chip, and at least some of the electrical traces 14 are in electrical contact with the electrodes of the electrode region 16. At least some of the other electrical traces 14 may be in electrical contact with the electrodes of the electrode region of other adjacent qubit portions. For example, the electrical traces 14 and the electrodes in the electrode region 16 are deposited on the surface of the substrate region 12. It can be made of a conductive material (e.g., aluminum, copper, gold) and may have at least one sealing coating configured to seal the conductive material from contaminants and / or corrosion. The electrodes of the electrode region 16 are configured to create an electron potential well 17 configured to contain (e.g., suspend, trap) a single ion 18 at a position spaced apart from the planar substrate region 12 (e.g., in a direction substantially perpendicular to the substrate region 12).

[0036] Figure 1B schematically shows side and top views of an example of a 3-ion portion 30 of an example of a 4-ion qubit gate 100 according to a particular embodiment described herein. The 3-ion portion 30 has a substantially planar substrate region 32, one or more electrical traces (not shown), an electrode region 36 including a plurality of electrodes (not shown), three electron potential wells 37a-c, and three ions 38a-c. In a particular embodiment, the substrate region 32 has an electrically insulating portion and / or a semiconductor (e.g., silicon oxide, silicon) chip, and at least some of the electrical traces are in electrical contact with the electrodes of the electrode region 36. At least some of the other electrical traces may be in electrical contact with the electrodes of the electrode region of other portions of adjacent qubits. For example, the electrical traces and electrodes in the electrode region 36 may include a conductive material (e.g., aluminum, copper, gold) deposited on the surface of the substrate region 32 and may include at least one sealing coating configured to seal the conductive material from contaminants and / or corrosion. In certain embodiments, electrical traces 14 that electrically communicate with electrodes in region 36 or other electrode regions may be present in a substrate layer (not shown) below the surface (e.g., a subsurface) and may run substantially in conjunction with other electrical traces 14 on the surface. The electrodes in electrode region 36 are configured to create three electron potential wells 37a-c, each of which is configured to contain (e.g., levitate, trap) one of three ions 38a-c at a distance from the planar substrate region 32 (e.g., substantially perpendicular to the substrate region 32). In certain embodiments, the three ions 38a-c form an equilateral triangle (e.g., spaced apart from each other by a distance ranging from 30 to 40 microns), such that the triangle is substantially parallel to the substrate region 32. The three ions 38a-c in the triangle are, according to certain embodiments described herein, examples of three qubits arranged in a substantially planar region and configured to interact.

[0037] In a particular embodiment, as shown in Figures 1A-1B, the substrate region 12 of the single-ion portion 10 and the substrate region 32 of the three-ion portion 30 (e.g., the respective chip portions that substantially correspond to the four-ion qubit gate 100) have a substantially hexagonal shape, while in a particular other embodiment, the substrate regions 12,32 have other shapes (e.g., rectangular, square, triangular, circular, elliptical, geometric, non-geometric, symmetrical, asymmetrical).

[0038] The hatched regions in Figures 1A and 1B, corresponding to electrode regions 16,36 (e.g., electrode patch regions), represent general "writing" zones, which are positioned and shaped to accommodate multiple individual electrodes within each zone to create electron potential wells 17,37a-c for confining the corresponding ions 18,38a-c. The positioning and shaping of various electrodes for specific structurable gate embodiments can be designed using algorithms (e.g., as provided by Schmied 2009). In a particular embodiment, electrode regions 16,36 are configured to trap, fully control, and perform a gate operation using the corresponding ions 18,38a-c. For example, electrode region 36 in Figure 1B may contain eight or more electrodes, each in an ion trap zone. In a particular embodiment, the electrodes and electrode regions 16,36 are based on electrodes and electrode regions already developed for the 2D layout of trapped ions (e.g., CWHogle et al. "Characterization of Microfabricated Surface Ion Traps," Sandia National Lab., SAND2017-611). 3C (2017)).

[0039] Figure 1C schematically shows side and top views of an example of a 4-ion qubit gate 100, according to a particular embodiment described herein, having a single-ion portion 10 in Figure 1A (e.g., as the "cap" of the 4-ion qubit gate 100) and a three-ion portion 30 in Figure 1B (e.g., as the "base" of the 4-ion qubit gate 100) together with ions 18,38a-c configured to be fully bonded to each other and / or to the ions of adjacent qubit gates (e.g., simultaneously or in any combination of subsets). The example of the 4-ion qubit gate 100 in Figure 1A has a substantially hexagonal shape, while in a particular other embodiment, the qubit gate 100 has other shapes (e.g., rectangular, square, triangular, circular, elliptical, geometric, non-geometric, symmetrical, asymmetrical). In a particular embodiment, the qubit gate 100 has a width W (e.g., in the range of 0.2 mm or less). The right side of Figure 1C shows at least some of the electrical traces 14 on the surface of portion 30, while in certain embodiments, at least some of the electrical traces 14 are located in a substrate layer (not shown) beneath the surface (e.g., a subsurface) and may run substantially in agreement with the other electrical traces 14 on the surface. In certain embodiments, the substrate region 12 is substantially parallel to the substrate region 32 and is spaced apart from the substrate region 32 by a distance S (e.g., in the range of 0.2 mm or less). In certain embodiments, a single ion 18 is spaced apart from each of the three ions 38a-c (e.g., by a distance in the range of 30 to 45 microns) and is positioned above the center of the triangle formed by the three ions 38a-c. Each of the ions 18,38a-c is entangled with each of the other ions 18,38a-c, as shown by the dashed lines in Figure 1C. In certain embodiments, an example of a four-ion qubit gate 100 has a width W (e.g., in the range of 0.2 mm or less).The three ions 38a-c are examples of three qubits located in a first substantially planar region (for example, the distances of the three ions 38a-c from the substrate region 32 may be within ±5 microns, ±2 microns, and / or ±1 micron from each other), and the single ion 18 is an example of a qubit located in a second substantially planar region substantially parallel to the first substantially planar region. The qubit in the second substantially planar region is configured to interact with the three qubits in the first substantially planar region, which are configured to interact according to certain embodiments described herein.

[0040] In a particular embodiment, the example of the 4-ion qubit gate 100 in Figure 1C is "natural" C 3 As a NOT gate (e.g., a triple-controlled NOT gate), and / or a "natural" C 3 It is used as a φ gate (e.g., a triple-controlled phase gate). An example of a 4-ion qubit gate 100 in a particular embodiment uses significantly fewer gate operations than would be used by a 1 or 2-qubit gate. 3 NOT / C 3 A φ gate can be realized. In a particular embodiment, the 4-ion qubit gate 100 does not aggregate the errors of a large number of consecutive operations to obtain the result, thus the natural C brought about by the example of the 4-ion qubit gate 100 3 NOT / C 3 The net fidelity of the φ gate is much higher than that of a large number of 2-qubit gates, including C, which can have a much higher individual gate fidelity. 3 NOT / C 3 It is significantly higher than that of a φ gate. In certain such embodiments, the C provided by the example of a 4-ion qubit gate 100 is 3 NOT / C 3 The φ gate is a C gate that includes many 2-qubit gates. 3 NOT / C 3 Using only a small portion of the φ gate steps, and thus C is brought about by the example of the 4-ion qubit gate 100. 3 NOT / C 3φ gates are faster and less prone to errors (for example, they significantly reduce the use of initial error correction), as can be seen in comparisons of the probabilities of successful gate operations using both structure and fidelity estimations.

[0041] Figure 2A schematically shows a side view of an example of a 7-ion qubit gate 200 according to a particular embodiment described herein. In a particular embodiment, the 7-ion qubit gate of Figure 2A An example of a qubit gate 200 is natural C 6 NOT / C 6 It is configured to be used as a φ gate. An example of the 7-ion qubit gate 200 in Figure 2A has a single-ion portion 10 (e.g., as the "cap" of the 7-ion qubit gate 200) and a 6-ion portion 50 (e.g., as the "base" of the 7-ion qubit gate 200) in Figure 1A. The 6-ion portion 50 has a planar substrate region 52, one or more electrical traces (not shown), six electrode regions 56a-f, six electron potential wells 57a-f, and six ions 58a-f. The electrodes of the electrode regions 56a-f are configured to create six electron potential wells 57a-f, and each of the six electron potential wells 57a-f is configured to contain (e.g., levitate, trap) one of the six ions 58a-f at a position spaced apart from the planar substrate region 52 (e.g., in a direction substantially perpendicular to the substrate region 52). As schematically shown in Figure 2A, an example of a 7-ion qubit gate 200 may have an additional electrode 59 (e.g., a cover electrode) positioned below the single ion 18 of the single-ion portion 10 and configured to assist in tuning the distance of the single ion 18 to the 6-ion portion 50 (e.g., CEPearson et al.). (See al., Phys. Rev. A Vol. 73, 032307 (2006)). In a particular embodiment, six ions 58a~f form an equilateral hexagon (spaced apart from each other by distances ranging from, for example, 35 to 70 microns), and this hexagon is substantially parallel to the substrate region 52. The spacing between the hexagons can be set based on various parameters, including, but not limited to, several tuning parameters, the type of ions, and the crystal lattice angles formed. In a particular embodiment, the nearest distance of each qubit in the hexagon from the substrate may be variable (for example, by a nominal distance of 40 microns ± 5 microns) depending on the 3D angle in the crystal lattice. The seven ions 18,58a~f are configured to be fully coupled to each other and / or to the ions of adjacent qubit gates (for example, simultaneously or in any subset combination), as schematically shown by dotted lines indicating entanglement between the seven ions 18,58a~f. As schematically shown in Figure 2A, in a particular embodiment, portions of the electrode regions 56a-f of the six-ion portion 50 extend onto the base substrate region of adjacent qubits, and portions of the electrode regions of adjacent portions extend onto the substrate region 12 of the single-ion portion 10. The six ions 58a-f are examples of six qubits substantially arranged in a first substantially planar region (for example, the distances of the six ions 58a-f from the substrate portion 52 may be within ±5 microns, ±2 microns, and / or ±1 micron from each other), and the single ion 18 is an example of a single qubit arranged in a second substantially planar region substantially parallel to the first substantially planar region. The qubit in the second substantially planar region is configured to interact with the six qubits in the first substantially planar region, which are configured to interact according to a particular embodiment described herein.

[0042] In a particular embodiment, a single ion 18 is contained in a first electron potential well 17 (e.g., suspended and trapped), and the single ion 18 is contained at a first distance (e.g., 40 microns) from the electrode region 16. In a particular other embodiment, a single ion 18 is contained in a second electron potential well, and the single ion 18 is contained at a second distance from the substrate region 52, where the second distance is approximately twice the first distance (e.g., 80 microns). For example, a second electron potential well can form naturally (see, for example, M. Mielenz et al. "Arrays of individually controlled ions suitable for two-dimensional quantum simulations," Nature Communications, 7:11839 (2016)). In one particular embodiment, the first electron potential well 17 and the second electron potential well coincide with or overlap each other so that a single ion 18 is simultaneously contained in both the first and second electron potential wells, while in one particular other embodiment, the first and second electron potential wells are separated from each other.

[0043] Figure 2B schematically shows side and top views of an example of an 8-ion qubit gate 300 according to a particular embodiment described herein. In a particular embodiment, the example of the 8-ion qubit gate 300 in Figure 2B is C 7 NOT / C 7The gate is configured to be used up to the φ gate. An example of the 8-ion qubit gate 300 in Figure 2B has a single-ion portion 10 (e.g., as the "cap" of the 8-ion qubit gate 300) and a 7-ion portion 70 (e.g., as the "base" of the 8-ion qubit gate 300) in Figure 1A. The 7-ion portion 70 has a planar substrate region 72, one or more electrical traces (not shown), seven electrode regions 76a-g, seven electron potential wells 77a-g, and seven ions 78a-g. The electrodes of the electrode regions 76a-g are configured to create seven electron potential wells 77a-g, and each of the electron potential wells 77a-g is configured to contain (e.g., levitate, trap) one of the seven ions 78a-g at a position spaced apart from the planar substrate region 72 (e.g., in a direction approximately perpendicular to the substrate region 72). The example of the 8-ion qubit 300 in Figure 2B is similar to the 7-ion qubit gate 200 in Figure 2A, with the addition of an 8th electrode region 76g, an 8th electron potential well 77g, and an 8th ion 78g (e.g., located in the range of 30 to 60 microns above the electrode region 76g). The distance of the 8th ion 78g from the substrate region 72 is not limited but can be based on various factors, including whether the 7-ion portion 70 is combined with a single-ion portion 10, a 3-ion portion 30, or another multi-ion portion as described herein. The eight ions 18, 78a-g are configured to be fully coupled to each other and / or to ions of adjacent qubit gates (e.g., simultaneously or in any subset combination) (the dotted lines indicating entanglement between the eight ions 18, 78a-g are omitted in Figure 2B for clarity). The six ions 78a-f are examples of six qubits, substantially arranged in a first substantially planar region (for example, the distances of the six ions 78a-f from the substrate portion 72 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other); the seventh ion 78g is an example of a single qubit, situated in a second substantially planar region substantially parallel to the first substantially planar region; and the single ion 18 is an example of a single qubit, situated in a third substantially planar region substantially parallel to the first substantially planar region.The qubits in the second substantially planar region and the qubits in the third substantially planar region are configured to interact with six qubits in the first substantially planar region, which are configured to interact with each other and interact with each other, according to certain embodiments described herein.

[0044] With respect to the example of a 7-ion qubit gate 200 in Figure 2A and the example of an 8-ion qubit gate 300 in Figure 2B, in a particular embodiment, each of the qubit gates 200 and 300 has a substantially hexagonal shape, while in a particular other embodiment, the qubit gates 200 and 300 have other shapes (e.g., rectangular, square, triangular, circular, elliptical, geometric, non-geometric, symmetrical, asymmetrical). In a particular embodiment, the substrate regions 52,72 have portions of an electrical insulator and / or semiconductor (e.g., silicon oxide, silicon) chip, and at least some of the electrical traces are in electrical contact with the electrodes of the electrode regions 56,76, while other electrical traces are in electrical contact with the electrode regions of the other base. In a particular embodiment, each of the electrode regions 56,76 has one or more electrodes that electrically contact at least some of the electrical traces, and the electrical traces and electrodes within the electrode regions 56,76 may have at least one sealing coating comprising a conductive material (e.g., aluminum, copper, gold) deposited on the surface of the substrate regions 52,72, and configured to seal the conductive material from contaminants and / or corrosion. In a particular embodiment, the electrodes of the electrode regions 56,76 extend at least partially into adjacent regions (e.g., regions of adjacent qubits) and are configured to provide space for electrical traces that run to the electrode regions of the qubit gates 200,300 and / or adjacent qubits. In a particular embodiment, the 7-ion qubit gate 200 and / or the 8-ion qubit gate 300 have a width W (e.g., in the range of 0.2 mm or less) and the substrate region 1 2 is approximately parallel to the substrate regions 52 and 72, and the substrate region 12 is spaced apart from the substrate regions 52 and 57 by a distance S (for example, within a range of 0.2 mm or less).

[0045] Figure 2C schematically shows a side view of an example of a 9-ion qubit gate 400 according to a particular embodiment described herein. In a particular embodiment, the 9-ion qubit gate 400 can assist in cross-chip connectivity (e.g., in a QFPGA architecture or QASIC architecture). In a particular embodiment, the example of the 9-ion qubit gate 400 in Figure 2C may also be configured to be used in multiple-control gate operations, or to employ a combination of redundant controls and / or target qubits to facilitate self-error correction gates at desired nodes. The example of the 9-ion qubit gate 400 in Figure 2C has a 6-ion portion 50 (e.g., as the "cap" of the 9-ion qubit gate 400) and a 3-ion portion 30 (e.g., as the "base" of the 9-ion qubit gate 400) in Figure 2A. The nine ions 38a-c, 58a-f are configured to be fully coupled to each other and / or to adjacent qubit gate ions (e.g., simultaneously or in any subset combination) (dotted lines indicating entanglement between the nine ions 38a-c, 58a-f are omitted in Figure 2C for clarity). The six ions 58a-f are an example of six qubits, arranged substantially in a region of the first substantially plane (e.g., the distances of the six ions 58a-f from the substrate portion 52 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other), and the three ions 38a-c are an example of three qubits, arranged in a region of the second substantially plane approximately parallel to the region of the first substantially plane (e.g., the distances of the three ions 38a-c from the substrate portion 32 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other). According to certain embodiments described herein, six qubits 58a-f in a first substantially planar region are configured to interact with each other, and three qubits 38a-c in a second substantially planar region are configured to interact with each other and with the qubits in the first substantially planar region.In a particular embodiment, three ions 38a-c and / or six ions 58a-f are further configured to interact with ions of other qubit gates adjacent to the 9-ion qubit gate 400 (e.g., inter-cell interactions).

[0046] Figure 2D schematically shows a side view of an example of a 10-ion qubit gate 450 according to a particular embodiment described herein. In a particular embodiment, the 10-ion qubit gate 450 can assist in cross-chip connectivity (e.g., in a QFPGA architecture or QASIC architecture). In a particular embodiment, the example of the 10-ion qubit gate 450 in Figure 2D can also be used (e.g., C 9 NOT / C 9 The gates may be configured to employ redundant control combinations and / or target qubits for use in multiple-controlled gate operations (up to φ gates) or to facilitate self-error-correcting gates at desired nodes. An example of a 10-ion qubit gate 450 in Figure 2D has a 7-ion portion 70 (e.g., as the "cap" of the 10-ion qubit gate 450) and a 3-ion portion 30 (e.g., as the "base" of the 10-ion qubit gate 450) in Figure 2B. The 10 ions 38a-c, 78a-g are configured to be fully coupled to each other and / or to the ions of adjacent qubit gates (e.g., simultaneously or in any subset combination) (the dotted lines showing entanglement between the nine ions 38a-c, 78a-g are omitted in Figure 2D for clarity). Six ions 78a-f are examples of six qubits, arranged substantially in a first substantially planar region (for example, the distances of the six ions 78a-f from the substrate portion 72 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other), the seventh ion 78g is an example of one qubit, arranged in a second substantially planar region substantially parallel to the first substantially planar region, and three ions 38a-c are arranged in a third substantially planar region substantially parallel to the first substantially planar region (for example, the distances of the three ions 38a-c from the substrate portion 32 may be within ±5 microns, ±2 microns, and / or ±1 micron of each other). Examples of three qubits (which may be within 10¹¹, within ±2 microns, and / or within ±1 micron). According to certain embodiments described herein, six qubits 78a-f in a first substantially planar region are configured to interact, three qubits 38a-c in a third substantially planar region are configured to interact with each other and with the qubits in the first substantially planar region, and a single qubit in a second substantially planar region is configured to interact with the qubits in the first substantially planar region and the qubits in the second substantially planar region. In certain embodiments, three ions 38a-c and / or seven ions 78a-g are further configured to interact with ions in other qubit gates adjacent to the 10-ion qubit gate 450 (e.g., inter-cell interactions).

[0047] Figure 2E schematically shows two side views of an example of a 13-ion qubit gate 500 (e.g., a "pyrochlore" cell) according to a particular embodiment described herein. In a particular embodiment, the example of the 13-ion qubit gate 500 in Figure 2E is C 12 NOT / C 12The gates are configured to be used up to the φ gate. An example of the 13-ion qubit gate 500 in Figure 2E has a 7-ion portion 70 in Figure 2B (e.g., as the "cap" of the 13-ion qubit gate 500), with an increased length of the electron potential well 77g and an accompanying distance of ion 78g from the electrode region 76g, and a 6-ion portion 50 (e.g., as the "base" of the 13-ion qubit gate 500). The 13 ions 58a~f, 78a~g are configured to be fully coupled to each other and / or to the ions of adjacent qubit gates (e.g., simultaneously or in any combination of subsets) (the dotted lines indicating entanglement between the 13 ions 58a~f, 78a~g are omitted in Figure 2E for clarity). Six ions 58a-f are examples of six qubits, substantially arranged in a first substantially planar region 502 (for example, the distances of the six ions 58a-f from the substrate portion 52 can be within ±5 microns, ±2 microns, and / or ±1 micron from each other at a distance H1 of approximately 40 microns from the substrate portion 52); six ions 78a-f are examples of six qubits, substantially arranged in a second substantially planar region 504 that is substantially parallel to the first substantially planar region 502 (for example, the distances of the six ions 78a-f from the substrate portion 72 can be within ±5 microns, ±2 microns, and / or ±1 micron from each other at a distance H1 of approximately 40 microns from the substrate portion 72); and a single ion 18 is an example of a single qubit, located in a third substantially planar region 506 that is substantially parallel to the first substantially planar region 502 (for example, at a distance H2 ranging from 50 to 60 microns from the substrate portion 72). According to certain embodiments described herein, six qubits in a first substantially planar region 502 are configured to interact with each other, six qubits in a second substantially planar region 504 are configured to interact with each other and with the six qubits in the first substantially planar region 502, and qubits in a third substantially planar region 506 are configured to interact with the qubits in the first substantially planar region 502 and the qubits in the second substantially planar region 504.In a particular embodiment, six ions 58a-f and / or seven ions 78a-g are further configured to interact with ions of other qubit gates adjacent to the 13-ion qubit gate 500 (e.g., inter-cell interactions).

[0048] Figure 2F schematically shows two side views of an example of a 14-ion qubit gate 550 according to a particular embodiment described herein. In a particular embodiment, the example of the 14-ion qubit gate 550 in Figure 2F is C 13 NOT / C 13 The configuration is such that φ gates can be used. An example of the 14-ion qubit gate 550 in Figure 2F includes a first 7-ion portion 70 (see, for example, Figure 2B) (for example, as a "cap" of the 14-ion qubit gate 550), and the distance of the ions 78g and electron potential well 77g of the first 7-ion portion 70 from the substrate portion 72 is longer than that of the ions 78g and electron potential well 77g in Figure 2B. An example of the 14-ion qubit gate 550 in Figure 2F further includes a second 7-ion portion 70 (see, for example, Figure 2B) (for example, as a "base" of the 14-ion qubit gate 550), and the ions 78g of the second 7-ion portion 70 The distance of the electron potential well 77g from the substrate portion 72 is shorter than that of ion 78g and electron potential well 77g in Figure 2B. The first set of ions 78a-g in the first seven-ion portion 70 and the second set of ions 78a-g in the second seven-ion portion 70 are configured to be fully coupled to each other and / or to the ions of adjacent qubit gates (for example, simultaneously or in any combination of subsets) (the dotted lines showing the entanglement between the first set of ions 78a-g and the second set of ions 78a-g are omitted in Figure 2F for clarity).

[0049] The six "base" ions 78a-f are approximately arranged in a first substantially planar region 552 (for example, the distances of the six ions 78a-f from the substrate portion 72 can be within ±5 microns, ±2 microns, and / or ±1 micron from each other at a distance H1 of approximately 40 microns from the substrate portion 72), and the six "cap" ions 78a-f are approximately arranged in a second substantially planar region 554 which is approximately parallel to the first substantially planar region 552 (for example, the distances of the six ions 78a-f from the substrate portion 72 can be within ±5 microns, ±2 microns, and / or ±1 micron from each other at a distance H1 of approximately 40 microns from the substrate portion 72). An example of six qubits (which may be within a 1000 cubic meter, within ±2 microns, and / or within ±1 micron), where one ion 78g above the base is an example of one qubit located in a third substantially planar region 556 substantially parallel to a first substantially planar region 552 (e.g., at a distance H2 ranging from 30 to 40 microns from the substrate portion 72), and one ion 78g below the cap is an example of one qubit located in a fourth substantially planar region 558 substantially parallel to a second substantially planar region 554 (e.g., at a distance H3 ranging from 50 to 60 microns from the substrate portion 72). The qubits in the first substantially planar region 552 are configured to interact, and the qubits in the second substantially planar region 554 are configured to interact with each other and with the qubits in the first substantially planar region 552. The qubits in the third substantially planar region 556 are configured to interact with the qubits in the first substantially planar region 552 and the qubits in the second substantially planar region 554. According to certain embodiments described herein, the qubits in the fourth substantially planar region 558 are configured to interact with the qubits in the first substantially planar region 552, the qubits in the second substantially planar region 554, and the qubits in the third substantially planar region 556. In certain embodiments, the first set of ions 78a-g and / or the second set of ions 78a-g are further configured to interact with ions in other qubit gates adjacent to the 14-ion qubit gate 550 (e.g., interacting between cells).

[0050] The provided examples correspond to structures configured to be adopted in subsequent embodiments of multiple multi-qubit gate arrays (such as QFPGA or QASIC embodiments) for the sake of ease of consideration. Other combinations of “cap” and “base” cells also fit certain embodiments described herein. For example, in the embodiment of QASIC, by combining the 7-ion portion 70 of Figure 2B, modified as described above by increasing or decreasing the length of the electron potential well 77g and the accompanying distance of ions 78g from the electrode region 76g, as schematically shown in Figure 2F, C 13 NOT / C 13 Creating 14-ion qubit gates that can be used up to φ gates may be advantageous. Furthermore, these and other numbers of qubits (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more qubits) for each first part 810 and / or second part 820 are adapted to certain embodiments described herein.

[0051] A particular embodiment described herein provides a quantum computing (QC) system 1000 comprising a substantially planar first substrate 600 and a substantially planar second substrate 700, wherein the first substrate 600 and the second substrate 700 are substantially parallel to each other. The quantum computing system 1000 further comprises a multi-qubit gate array 800 having a plurality of multi-qubit gates 802 located in the region between the first substrate 600 and the second substrate 700. A multi-qubit gate 802 comprises a first portion 810 (e.g., a base) on the surface of a first substrate 600 (e.g., upward, downward, upward) and a second portion 820 (e.g., a cap) on the surface of a second substrate 700 (e.g., upward, downward, upward), and the qubits interact between the surfaces of the first and second substrates 600 and 700. The first portion 810 of each multi-qubit gate 802 in the array 800 is selected from a group consisting of a single-qubit portion 10, a three-qubit portion 30, a six-qubit portion 50, and a seven-qubit portion 70. The first portion 810 is arranged along the surface of the first substrate 600 (e.g., the substrate regions 12, 32, 52, 72 of the single-qubit portion 10, the three-qubit portion 30, the six-qubit portion 50, and the seven-qubit portion 70 are regions of the first substrate 600). The second portion 820 of each multi-qubit gate 802 in array 800 is selected from a group consisting of a single-qubit portion 10, a three-qubit portion 30, a six-qubit portion 50, and a seven-qubit portion 70. The second portion 820 is positioned along the surface of the second substrate 700 (for example, the substrate regions 12, 32, 52, and 72 of the single-qubit portion 10, the three-qubit portion 30, the six-qubit portion 50, and the seven-qubit portion 70 are regions of the second substrate 700). In each multi-qubit gate 802, each qubit of the first portion 810 and the second portion 820 of the multi-qubit gate 802 is configured to be quantum mechanically entangled with the other qubits of the first portion 810 and the second portion 820 of the multi-qubit gate 802, respectively.

[0052] Figure 3A schematically shows a top view of four first parts 810 (e.g., bases) of an example array 800 having four multi-ionic qubit gates (e.g., cells) 802 according to a particular embodiment described herein. The four first parts 810 in Figure 3A have a single-ionic part 10, a three-ionic part 30, a six-ionic part 50, and a seven-ionic part 70. These four first parts 810 are tiled together with their respective substrate regions 12, 32, 52, 72, which are parts of a common first substrate 600 (e.g., the substrate regions 12, 32, 52, 72 are coplanar with each other on the surface of the first substrate 600). The tiling includes a rhombus-shaped region 830 enclosed by the four first parts 810. As shown in Figure 3A, at least some of the electrode regions of the 6-ion portion 50 and the 7-ion portion 70 (e.g., electrode regions 56a-f, 76a-f) extend into adjacent first portions 810 and / or rhombic regions 830. In certain embodiments, the first portions 810 of adjacent rows are configured to facilitate tight tiling of the first portions 810 (e.g., without the electrode regions overlapping each other). While Figure 3A shows the first portions 810 in a substantially rectangular pattern, the first portions 810 in other embodiments may be in a substantially hexagonal or substantially diagonal pattern. Furthermore, while the first portions 810 in Figure 3A are schematically shown as a 2x2 array, other combinations of array-like tiling of two, three or more portions also fit into certain embodiments described herein. For example, the first part 810 can be tiled in an array in linear (e.g., 1×2, 1×3, or more), square or rectangular (e.g., 2×3, 3×3, 2×4, 3×4, 4×4, 2×5, etc.) and other geometric shapes that can be regular or irregular (e.g., similar to domino tiling) and / or symmetric or asymmetric.

[0053] Figure 3B schematically shows a top view of four second parts 820 (e.g., caps) of an example of an array 800 and four multi-ionic qubit gates 802 according to a particular embodiment described herein. The four second parts 820 in Figure 3B have a single-ion part 10, a three-ion part 30, a six-ion part 50, and a seven-ion part 70. These four second parts 820 are tiled together with their respective substrate regions 12, 32, 52, 72, which are parts of a common second substrate 700 (e.g., the substrate regions 12, 32, 52, 72 are coplanar with each other on the surface of the second substrate 700). The tiling includes a rhombus-shaped region 840 surrounded by the four first parts 820. Electrode regions of the six-ion part 50 and the seven-ion part 70 (e.g., electrode regions 56a-f, 76a-f) are shown in Figure 3B. At least some of these extend into adjacent second portions 820 and / or rhombus regions 840. In certain embodiments, adjacent rows of second portions 820 are configured to facilitate tight tiling of the second portions 820 (e.g., without the electrode regions overlapping each other). While Figure 3B shows the second portions 820 in a substantially rectangular pattern, the second portions 820 in other embodiments may be in a substantially hexagonal or substantially diagonal pattern. Furthermore, while the second portions 820 in Figure 3B are schematically shown as a 2x2 array, other tiling combinations of arrays of two, three, or more portions also fit into certain embodiments described herein. For example, the second part 820 can be tiled in arrays in linear (e.g., 1x2, 1x3, or more), square or rectangular (e.g., 2x3, 3x3, 2x4, 3x4, 4x4, 2x5, etc.) and other geometric shapes that can be regular or irregular (e.g., similar to domino tiling) and / or symmetric or asymmetric.

[0054] Figures 3C-3D schematically show exploded and superimposed views from above, respectively, of an example of the array 800 and four multi-ion qubit gates 802 of Figures 3A-3B, according to a particular embodiment described herein. The four multi-ion qubit gates 802 include two 4-ion qubit gates 100 and two 13-ion qubit gates 500 between a first substrate 600 and a second substrate 700. One of the 4-ion qubit gates 100 has a 3-ion base portion 30 and a single-ion cap portion 10, another 4-ion qubit gate 100 has a single-ion base portion 10 and a 3-ion cap portion 30, one of the 13-ion qubit gates 500 has a 7-ion base portion 70 and a 6-ion cap portion 50, and another 13-ion qubit gate 500 has a 6-ion base portion 50 and a 7-ion cap portion 70. Other tiling combinations of bases and caps into the 3D gate cell layout may be used, as described herein with respect to Figures 3A and 3B.

[0055] Figure 3E schematically shows an exploded view of another example of an array 800 having four multi-ion qubit gates 802 according to a particular embodiment described herein. The four multi-ion qubit gates 802 include four 10-ion qubit gates 450 between a first substrate 600 and a second substrate 700. Two of the 10-ion qubit gates 450 each have a 3-ion base portion 30 and a 7-ion cap portion 70, and the other two 10-ion qubit gates 450 each have a 7-ion base portion 70 and a 3-ion cap portion 30. In the 2x2 array of substrate 600, the 3-ion base portions 30 and the 7-ion base portions 70 are alternated with each other, and in the 2x2 array of substrate 700, the 7-ion cap portions 70 and the 3-ion cap portions are alternated with each other. The layout of the electrical trace lines shown in Figure 3E differs from those in Figures 3C-3D.

[0056] Figures 4A-4B schematically show exploded view and top-down view, respectively, of an example array 900 having 16 multi-ionic qubit gates 902 in a 4x4 array, according to a particular embodiment described herein. Other multi-qubit gate arrays having a different number (e.g., more than 16) and / or different geometric arrangements (e.g., linear, rectangular, square, regular, irregular, symmetric, asymmetric) are also compatible with certain embodiments described herein. The 16 multi-ionic qubit gates 902 of array 900 are arranged in a substantially rectangular pattern having four rows, each having four multi-ionic qubit gates 902, and four columns, each having four multi-ionic qubit gates 902. Each row of the multi-ion qubit gate 902 contains two 4-ion qubit gates 100 and two 13-ion qubit gates 500 arranged alternately (e.g., "4-13-4-13"), and each column of the multi-ion qubit gate 902 contains two 4-ion qubit gates 100 and two 13-ion qubit gates 500 arranged alternately. (e.g., "4-13-4-13"). The first (e.g., base) portion 810 of the array 900 is arranged such that any four nearest first portions 810 include a single-ion portion 10, a 3-ion portion 30, a 6-ion portion 50, and a 7-ion portion 70, and the second (e.g., cap) portion 820 of the array 900 is arranged such that any four nearest second portions 820 include a single-ion portion 10, a 3-ion portion 30, a 6-ion portion 50, and a 7-ion portion 70. In a particular embodiment, the first and second portions 810 and 820 of the array 900 (e.g., for a QFPGA) are configured to reduce (e.g., minimize) the spacing between qubits and / or optimize cell-to-cell connectivity.

[0057] As schematically shown in Figures 4A-4B, at least some of the electrical traces 14 extending along the first substrate 600 and / or the second substrate 700 have substantially straight portions that are substantially perpendicular to the boundaries between adjacent first portions 810 of the first substrate 600 and / or the boundaries between adjacent second portions 820 of the second substrate 700. For example, the electrical trace 14 shown perpendicularly in Figure 4B is substantially perpendicular to the horizontal boundary in Figure 4B. Figure 4C schematically shows an overhead superposition of another example of a multi-ionic qubit gate array 900 having 16 multi-ionic qubit gates 902 of a particular embodiment described herein. At least some of the electrical traces 14 extending along the first substrate 600 and / or the second substrate 700 in Figure 4C have substantially straight portions that are not substantially perpendicular to the boundaries between adjacent first portions 810 of the first substrate and / or the boundaries between adjacent second portions 820 of the second substrate 700. For example, the electrical trace 14 shown substantially perpendicularly in Figure 4C extends beyond at least some of the hexagonal boundaries in Figure 4C, but is not substantially perpendicular to these hexagonal boundaries. Other positions and / or orientations of the electrical trace 14 also conform to certain embodiments described herein. For example, the electrical trace 14 may be curved to create space for an optical port to input and / or output a laser signal into the region between the first substrate 600 and the second substrate 700.

[0058] Figure 4D schematically shows an overhead superposition of another example of a multi-ion qubit gate array 800 having four multi-ion qubit gates 802 according to a particular embodiment described herein. The four multi-ion qubit gates 802 include two 8-ion qubit gates 300 (see, for example, Figure 2B) and two 9-ion qubit gates 400 (see, for example, Figure 2C) between a first substrate 600 and a second substrate 700. One of the 8-ion qubit gates 300 has a 7-ion base portion 70 and a single-ion cap portion 10, another 8-ion qubit gate 300 has a single-ion base portion 10 and a 7-ion cap portion 70, one of the 9-ion qubit gates 400 has a 3-ion base portion 30 and a 6-ion cap portion 50, and another 9-ion qubit gate 400 has a 6-ion base portion 50 and a 3-ion cap portion 30.

[0059] Figure 4E schematically shows an overhead superposition diagram of another example of a multi-ion qubit gate array 900 having 16 multi-ion qubit gates 902 according to a particular embodiment described herein. The 16 multi-ion qubit gates 902 of array 900 are arranged in a substantially rectangular pattern having four rows, each having four multi-ion qubit gates 902, and four columns, each having four multi-ion qubit gates 902. The rows of multi-ion qubit gates 902 are arranged alternately between four 9-ion qubit gates 400 (e.g., 9-9-9-9) and four 8-ion qubit gates 300 (e.g., "8-8-8-8"), and the multi-ion qubit gates 902 in each column include two 9-ion qubit gates 400 and two 8-ion qubit gates 300 (e.g., "9-8-9-8"). In a particular embodiment, array 900 (e.g., for a QFPGA) The layout of the first part 810 and the second part 820 is configured to provide a constant spacing between the ions of adjacent first part 810 and second part 820 of the array 900.

[0060] Figures 4F-4G schematically show exploded views and superimposed views from above, respectively, of another example of an array 900 having 16 multi-ionic qubit gates 902 in a 4x4 array, according to a particular embodiment described herein. The 16 multi-ionic qubit gates 902 of array 900 are arranged in a substantially rectangular pattern having four rows, each having four multi-ionic qubit gates 902, and four columns, each having four multi-ionic qubit gates 902. Each row of multi-ionic qubit gates 902 contains four 10-ionic qubit gates 450, and each column of multi-ionic qubit gates 902 contains four 10-ionic qubit gates 450. The rows and columns of the first (e.g., base) portion 810 of array 900 have alternating 3-ion portions 30 and 7-ion portions 70 (e.g., "3-7-3-7"), and the rows and columns of the second (e.g., cap) portion 820 of array 900 are also alternating (e.g., "3-7-3-7"). In a particular embodiment, the layouts of the first portion 810 and the second portion 820 of array 900 are configured to provide more uniform spacing.

[0061] Figures 5A–5I schematically illustrate some examples of QC structure 1000 according to certain embodiments described herein. Examples of QC structure 1000 can be used in QASIC or QFPGA layouts. In certain embodiments, the QC structure 1000 advantageously provides ample space for a cooling system and a magnetic field system for operating the QC structure 1000. In certain embodiments, the overall arrangement maintains transmission path space for electrical traces to control multiple electrodes per electrode region, while advantageously addressing the problem of electrode overlap that occurs between adjacent qubit gates when adjacent qubit gates are tiled tightly (for example, to maintain effective coherence) in a two-dimensional (2D) layout.

[0062] The QC structure 1000 includes an example of the array 900 in Figure 4C having an electrical trace 14 similar to that in Figure 4C. In certain embodiments, alternating inverted rows of cells in the base and / or cap portions of the array 900 facilitate the formation of electrical transmission paths through which electrical signals can be supplied to the ion traps of the array 900. For example, as shown in Figure 5A, the electrical trace 14 is configured to supply electrical signals to various electrodes of the ion traps. Rows and columns of cells, other arrangements of electrical traces, and cells having other numbers of ions and / or qubits also conform to certain embodiments described herein.

[0063] In a particular embodiment, alternating rows of inverted cells in the base and / or cap portions of the array 900 facilitate the formation of an optical transmission path through which optical signals can be input to and / or output from the ion traps of the array 900. An example of the QC structure 1000 further comprises a plurality of optical ports 905 according to a particular embodiment described herein. The plurality of optical ports 905 of the example of the QC structure 1000 has a first plurality of optical ports 910 that communicate optically with a first plurality of optical fibers 912, the first plurality of optical ports 910 located in a first portion 810 of a first substrate 600. The plurality of optical ports 905 of the example of the QC structure 1000 further has a second plurality of optical ports 920 that communicate optically with a second plurality of optical fibers 922, the second plurality of optical ports 920 located in a second portion 820 of a second substrate 700. At least some of the optical ports 910 are configured to emit optical signals 914 (e.g., pulses generated by one or more lasers, not shown) which are configured to irradiate specific ions of array 900 (e.g., to address and / or control specific qubits of array 900), and at least some of the optical ports 92 The optical ports 905 of the QC structure 1000 are configured to emit an optical signal 924 (e.g., pulses generated by one or more lasers, not shown) which is configured to irradiate a specific ion of the array 900 (for example, to address and / or control it). The optical ports 905 of the QC structure 1000 further comprise a third plurality of optical ports 930 and a third plurality of optical fibers 932. The optical ports 930 can optically communicate with the third plurality of optical fibers 932, which are located outside the periphery of the array 900 and are configured to emit an optical signal 934 (e.g., pulses generated by one or more lasers, not shown), which is configured to irradiate a specific ion of the array 900 (e.g., to address and / or control a specific qubit of the array 900). In a particular embodiment, the optical ports 910, 920, 930 have polished fiber ends configured to direct laser optical signals 914, 924, 934 to the corresponding specific ions of the array 900.

[0064] The multiple optical ports 905 of the example QC structure 1000 further comprises a fourth set of multiple optical emission ports 940 within the first section 810 and / or the second section 820, configured to allow light from optical signals 914,924 passing through a specific irradiated ion to be emitted or absorbed, thereby reducing (e.g., minimizing) crosstalk or other noise of optical reflection or scattering toward unintended qubits. The optical emission ports 940 may have pores and / or optical absorbing material.

[0065] An example of the QC structure 1000 further comprises multiple photodetectors 950 that optically communicate with a fourth set of multiple optical fibers 952. The multiple photodetectors 950 (e.g., charge-coupled device (CCD) cameras, superconducting nanowire single-photon detectors (SNSPDs), photomultiplier tubes (PMTs), bolometers) are configured to receive optical signals (e.g., fluorescence 926) from ions in the array 900 to read out the state of the qubits in the array 900.

[0066] Figure 5A schematically shows a top view of the first portion 810 of an example of an array 900 on the first substrate 600 with the second substrate 700 removed. As shown in Figure 5A, the electrical trace 14 may extend along the array 900 to provide electrical connectivity with various electrodes of the first portion 810. The optical ports 910 may be located within the first portion 810 (e.g., alternately arranged) and may be directed so that the optical signals 914 are directed to specific ions of the second portion 820.

[0067] Figures 5B-5C schematically show perspective and side views, respectively, of an example of QC structure 1000, including both the first and second substrates 600 and 700 of the example of QC structure 1000 (e.g., a multi-chip structure).

[0068] Figure 5D schematically shows a perspective view (without the second substrate 700) and a side view (with both the first substrate 600 and the second substrate 700) of an example of a QC structure 1000 in which optical signals 934 are emitted from a third set of optical ports 930. These optical signals 934 are directed to an ion 904 located at the center of the multi-ion qubit gate 902, where ion 904 is at a different distance from the first substrate 600 and the second substrate 700 than the other non-centered ions 906 of the multi-ion qubit gate 902.

[0069] According to certain embodiments described herein, Figure 5E schematically shows a perspective view (without optical signals 914, 924), Figures 5F-5G schematically show two side views of the QC structure 1000, and Figure 5H schematically shows another side view of the QC structure 1000. Figure 5F shows three optical signals 914 emanating from three of the first plurality of optical ports 910, each of the three optical signals 914 directed to the corresponding ion in the second portion 820 (e.g., the 6-ion portion 50) of the multi-ion qubit gate 902. Furthermore, Figure 5F shows a third plurality Figure 5G shows the optical signal 934 emitted from optical port 930. Figure 5G shows six optical signals 914 emitted from six of the first plurality of optical ports 910, each of which is directed to the corresponding ion in the second portion 820 (e.g., the 6-ion portion 50) of the multi-ion qubit gate 902. Furthermore, Figure 5G shows the optical signal 934 emitted from the third plurality of optical ports 930, and six of the six optical signals 924 emitted from six of the second plurality of optical ports 920, each of which is directed to the corresponding ion in the first portion 810 (e.g., the 7-ion portion 70) of the multi-ion qubit gate 902. Figure 5H shows an optical signal 924 emitted from a second set of optical ports 920 to irradiate corresponding ions, and some of the light from the optical signal 924 is made available for emission through the corresponding optical emission port 940 (e.g., emitted from the region between the first and second substrates 600, 700, and subsequently detected and / or absorbed).

[0070] Figure 5I schematically shows a side view of an example of the QC structure 1000 in Figures 5C-5D, with additional rows of optical ports 930 for emitting optical signals 934. For example, as shown in Figure 5I, the back support comprises two rows of optical ports 930 and one row of photodetectors 950, while the front support comprises one row of optical ports 930 and two rows of photodetectors 950. In certain embodiments, multiple optical signals may be advantageously used to utilize multiple ion species and perform gate operations optimized for each ion species. The type of optical addressing and optical transitions employed to address, initialize, and / or perform quantum gate operations with respect to one or more ions may depend on the ion species used. For example, a particular ion species may be addressed using a single optical wavelength transition, which may be called an "optical qubit" (e.g., 40 Ca +) may be referred to as such. In a particular embodiment, at least one optical signal 934 is used to illuminate a plurality of ions 904 (for example, to initialize or reset their qubit states to their lowest energy, ground state). In a particular embodiment, at least one optical signal 934 is used to entangle a plurality of ions 904 and perform a particular quantum gate operation involving one or more ions. Certain other ion species can be in a hyperfine state and also "hyperfine qubits" (for example, 43 Ca + , 171 Yb + These are sometimes referred to as (etc.), and typically employ two lasers in a Raman transition. In certain embodiments, two optical signals 934 of different wavelengths are advantageously used to address one or more ions and perform quantum gate operations.

[0071] Figure 6A schematically shows an overhead superposition of an example of a 4×4 array 900 having a plurality of optical ports 905 alternating with 4-ion qubit gates 100 and 13-ion qubit gates 500, according to a particular embodiment described herein. The array 900 shown in Figure 6A is an example of a QFPGA layout. At least some of the optical ports 910,920 (indicated by white circles in Figure 6A) are configured to emit optical signals 914,924 to the region between the first substrate 600 and the second substrate 700, and at least some of the optical output ports 940 (indicated by black circles in Figure 6A) are configured to allow the optical signals 914,924 to be emitted and / or absorbed. In a particular embodiment, the optical output port 940 is configured to prevent the reflection of the optical signals 914,924 from causing interference or degrading the performance of an example of a QC structure 1000. For example, the light-emitting port 940 may include a light-absorbing element. At least some of the optical ports 910, 920 and the light-emitting port 940 can be located within the first and second hexagonal portions 810 and 820 of the multi-ion qubit gate 902, while at least some of the light-emitting ports 940 can be located in the rhombus-shaped regions 830, 840 between the first and / or second hexagonal portions 810, 820. For example, as shown in Figure 6A, at least some of the optical ports 910, 920 and the light-emitting port 940 are located between the “petal-shaped” electrode regions 16, and some of the light-emitting ports 940 are located in the rhombus-shaped regions 830, 840.

[0072] Figures 6B–6D schematically show optical signals illuminating the ions of the array 900 in Figure 6A according to a particular embodiment described herein. In each of Figures 6B–6D, the central ions of the 4-ion qubit gate 100, the 7-ion qubit gate 200, and the 13-ion qubit gate 500 can be laser-addressable and / or manipulated (e.g., target) ions and can be illuminated by optical signals from optical ports 930 located outside the periphery of the array 900. The other ions of the 4-ion qubit gate 100, the 7-ion qubit gate 200, and the 13-ion qubit gate 500 can be laser-addressable (e.g., control) ions.

[0073] As shown in Figure 6B, three of the optical ports 910 emit an optical signal 914 that irradiates three corresponding ions of the four-ion qubit gate 100, and three of the optical output ports 940 allow a portion of the optical signal 914 passing through the three corresponding ions to be emitted in order to reduce (e.g., minimize) optical reflection or scattering within the array 900. In a particular embodiment, natural C 3 By using a 4-ion qubit gate 100 as the NOT gate, a single gate operation can advantageously utilize geometric symmetry and replace numerous 1- and 2-qubit gate operations with faster speed and fewer aggregation errors.

[0074] As shown in Figure 6C, the six optical ports 910 emit an optical signal 914 that irradiates six corresponding ions of the seven-ion qubit gate 200, and the six optical output ports 940 allow a portion of the optical signal 914 passing through the six corresponding ions to be emitted in order to reduce (e.g., minimize) optical reflection or scattering within the array 900. In a particular embodiment, natural C 6 By using the 7-ion qubit gate 200 as the NOT gate, a single gate operation can advantageously utilize geometric symmetry and replace hundreds of 1- and 2-qubit gate operations with faster speed and fewer aggregation errors.

[0075] As shown in Figure 6D, six of the optical ports 910 emit optical signals 914, six of the optical ports 920 emit optical signals 924 that irradiate twelve corresponding ions of the 13-ion qubit gate 500, and twelve of the optical output ports 940 allow some of the optical signals 914, 924 passing through the twelve corresponding ions to be emitted in order to reduce (e.g., minimize) light reflection or scattering within the array 900. In a particular embodiment, natural C 12 By using the 13-ion qubit gate 500 as the NOT gate, a single gate operation can advantageously utilize geometric symmetry and replace thousands of 1 and 2-qubit gate operations with faster speeds and fewer aggregation errors.

[0076] Figure 6E schematically shows the base portion and a top view of the superimposed base and cap portion of an example of a 4×4 array 900 of 10-ion qubit gates 450 having a plurality of ion input holes and optical ports 910, 920, according to a particular embodiment described herein. The base portion has eight 3-ion portions 30 and eight 7-ion portions 70 arranged alternately with respect to each other, and the cap portion has eight 3-ion portions 30 and eight 7-ion portions 70 arranged alternately with respect to each other (see, for example, Figures 4C, 4F, 4G).

[0077] Figure 6F schematically shows the superposition of the base and cap portions of an example of a 4×4 array 900 of 10-ion qubit gates 450 having a plurality of microwave antenna regions 942 located on at least one chip substrate 600,700, according to a particular embodiment described herein. Depending on the specific type of qubit used (for example, if the qubits are, 9 Be + , 43 Ca + , 171 Yb +In cases including many other ultrafine qubit states, certain embodiments described herein advantageously provide microwave addressing and control of trapped ions in addition to, or instead of, certain optical methods (e.g., C. Ospelkaus et al., Phys Rev. Lett. Vol 1). 01,090502 (2008), TP Harty et al., Phys Rev. Lett. Vol. 113, 220501 (2014)).

[0078] In accordance with certain embodiments described herein, Figure 7A schematically shows a partial side view of an example of a QC structure 1000, and Figure 7B schematically shows a close-up view of a smaller portion of the QC structure 1000 in Figure 7A. As shown in Figure 7A, an optical signal 924 (for example, light having a laser wavelength from an ion-addressing laser passing through optical fibers 912,922) emitted from optical ports 910,920 is directed to irradiate the corresponding ions 18,38,58,78. In response to the optical signal 924, the ions 18,38,58,78 can fluoresce and emit fluorescence 926. In certain embodiments, the ion fluorescence wavelength can be the laser wavelength of the optical signal 924, or near the laser wavelength, while in certain other embodiments, the ion fluorescence wavelength is different from the laser wavelength of the optical signal 924. The light that propagates to and passes through the light emission port 940 may include a mixture of fluorescence 926 from the irradiated ions 18, 38, 58, and 78 and optical signals 924 emitted from the optical ports 910 and 920, as shown in Figure 7B.

[0079] In a particular embodiment, as schematically shown in Figures 7A and 7B, the QC structure 1000 comprises at least one photoselective layer 1100 configured to separate the optical signal 924 from the fluorescence 926. For example, as shown in Figures 7A and 7B, the at least one photoselective layer 1100 includes a wavelength-selective material positioned between the light output port 940 and the corresponding photodetector 950, and is configured to prevent the optical signal 924 from reaching the photodetector 950 (e.g., by refracting, deflecting, reflecting, or diffracting) while allowing the fluorescence 926 to reach the photodetector 950 (e.g., by allowing it to proceed directly to the photodetector 950). Examples of photoselective layers 1100 configured to separate the optical signal 924 from the fluorescence 926 according to a particular embodiment described herein, but which are not limited to, include layers having a wavelength-dependent refractive index, prism-like layers, and diffraction gratings. In certain other embodiments, the photoselective layer 1100 includes a polarization-selective material (e.g., a polarizing filter, a birefringent crystal lattice) and / or a phase-selective material (e.g., a quarter-wave plate, a highly dispersive material, a prism-like layer) configured to block the optical signal 924 from reaching the photodetector 950 (e.g., by orthogonal polarization and / or phase shifting), while allowing the fluorescence 926 to reach the photodetector 950. In certain such embodiments, the fluorescence 926 includes randomly polarized and / or phase-shifted photons, and half of the fluorescence 926 passes through the photoselective layer 1100, while the optical signal 924 is blocked or heavily attenuated, resulting in fluorescence 926 with a preferred signal-to-noise ratio reaching the photodetector 950, so that the photoselective layer 1100 can reduce the intensity of the fluorescence 926 by an acceptable amount (e.g., about half, -3 dB). In a particular embodiment, the use of the photoselective layer 1100 can be used in conjunction with the pulse timing of the optical signal 924 and the gate operation of the readout of the photodetector 950 to further increase the detection of signal-to-noise noise of the fluorescence signal 926 relative to the optical signal 924.

[0080] Figures 7C and 7D schematically show two diagrams of another example of the QC structure 1000 according to a particular embodiment described herein. As schematically shown in Figures 7C and 7D, the QC structure 1000 comprises a light emission port 940, and the photodetector 950 is positioned such that (i) an optical signal 924a used to irradiate a first predetermined ion 928a propagates through the corresponding light emission port 940 but does not reach the photodetector 950 corresponding to the light emission port 940, and (ii) fluorescence 926 from a second predetermined ion 928b propagates from ion 928b through the light emission port 940 to the corresponding photodetector 950, while an optical signal 924 (for irradiating, for example, ion 924b, or other ions) does not propagate through the light emission port 940 to the corresponding photodetector 950. For example, in a particular such arrangement, the fluorescence 926 and the light signal 924 are (for example, wave This may be useful for QC structures 1000 that are not easily distinguishable from one another (by length, polarization, and / or phase).

[0081] Figure 7E schematically shows a partial side view of an example of a QC structure 1000 comprising an ion-injection port 1200 (e.g., vertical interconnect (VIA), through-silicon via (TSV), carbon nanotube (CNT) structure) and a single-ion photodetector 1210 (e.g., charge-coupled device (CCD), PMT, SNSPD, bolometer) according to a particular embodiment described herein. In a particular embodiment, the ion-injection port 1200 is configured to inject ions 18, 38, 58, 78 into the corresponding electron potential wells 17, 37, 57, 77 and to be controllably opened and / or closed in response to a signal from the corresponding single-ion photodetector 1210. For example, if the single-ion photodetector 1210 detects that a single ion has passed through the corresponding ion-injection port 1200, the single-ion photodetector 1210 may close the ion-injection port 1200 to prevent further ions from passing through. If the corresponding electron potential wells 17, 37, 57, 77 do not contain ions 18, 38, 58, 78, the single-ion photodetector 1210 may open the ion input port 1200 to supply a single ion 18, 38, 58, 78 to the electron potential wells 17, 37, 57, 77.

[0082] Figure 8 schematically shows a side view (left side of Figure 8A) of an example of a QC structure 1000 having an example of a 16×16 cell array 1300 according to a particular embodiment described herein, and a top projection view (right side of Figure 8) of a 16×16 cell array 900. The 16×16 cell array 1300 in Figure 8 comprises 16 4×4 cell arrays 900 from Figures 5A-5D tiled together. As shown on the right side of Figure 8, the 16×16 cell array 1300 has a nominal area of ​​1 square centimeter (1 cm²). 2 Approximately 1 / 4 square centimeter (0.25 cm) on a substrate of 600, 700. 2The region can be expanded or reduced. For example, a 16×16 cell array 1300 can realize 16,437 qubits within the region of substrate 600,700 (for example, using a trap spacing of about 40 microns) by alternately comprising a 4-ion gate array 100 and a 13-ion gate array 500. In another embodiment, a 16×16 cell array 1300 can realize 19,400 qubits within the region of substrate 600,700 (for example, using a trap spacing of about 40 microns) by comprising only a 10-ion gate array 450.

[0083] The number of qubits can increase if the QC structure 100 has a larger number of cells and a cell array that extends over a wider area. For example, 1 cm 2 A cell array having alternating 4-ion gate arrays 100 and 13-ion gate arrays 500 over a region can enable 65,750 qubits per square centimeter (for example, using a trapping interval of about 40 microns), and 1 cm 2 A cell array having only 10 ion gate arrays 450 across a given region can enable more than 77,000 qubits per square centimeter (for example, using a trapping interval of about 40 microns).

[0084] Figure 9 shows four tables comparing the total number of qubits for various 4x4 cell arrays according to a particular embodiment described herein, and an example of how the array's reconfiguration favorably allows for the selection of multiple complementary attributes. As shown in Figure 9, a 4x4 cell array having eight 4-ion gate arrays 100 and eight 13-ion gate arrays 500 alternately (e.g., labeled "QFPGA I" in Figure 9) has a total number of qubits of 136. While this represents a relatively low qubit density across the entire trade space, the scattering of ultra-high-capacity gates alongside adjacent low-capacity gates provides opportunities for error correction to be performed efficiently in situ, and / or for algorithms to be executed that benefit from multiple-controlled NOT or multiple-controlled phase gates with a large number (e.g., 10 or more) of controls. In a 4x4 cell array with three 13-ion gate arrays (for example, indicated as "QASIC I" in Figure 9), the total number of qubits is 133. However, for example, using an ASIC type (for example, a small number of C 12 Although NOT gates are used, if faster relay speeds or higher processing power are desired across the entire array, QASIC I is superior to QFPGA I, despite having three fewer qubits in the array. It can be more efficient than the above. In a 4x4 cell array with 16 10-ion gate arrays 450 (for example, shown as "QFPGA II" in Figure 9), the total number of qubits is 160. This is the highest qubit density presented for a single array, and it has the most efficient processing power and the most uniform design across all directions. In a 4x4 cell array with 4 4-ion gate arrays 100, 10 10-ion gate arrays 450 and 2 13-ion gate arrays 500 (for example, shown as "QASIC II" in Figure 9), the total number of qubits is 142. This targets the middle of the qubit density range, and nevertheless, such an array has a small number of C 12The use of NOT gates would be advantageous in the use of a special type of ASIC where the direction of the best relay speed or processing power (e.g., from bottom left to top right, or vice versa) can be predetermined.

[0085] The present invention has been described in several non-limiting embodiments. These embodiments are not mutually exclusive, and it will be understood that elements described in relation to one embodiment may be combined with, reconfigured, or removed from other embodiments in a manner appropriate to achieve the desired design objectives. No single feature or group of features is required or essential for each embodiment.

[0086] For the purpose of summarizing the present invention, certain aspects, advantages, and novel features of the present invention are described herein. However, it will be understood that not all such advantages must necessarily be realized according to any particular embodiment. Therefore, the present invention may be embodied or practiced in a manner that realizes one or more advantages without necessarily realizing other advantages that may be taught or proposed herein.

[0087] All references to “a certain embodiment,” “several embodiments,” or “one embodiment” as used herein mean that any particular element, feature, structure, or feature described in connection with this embodiment is included in at least one embodiment. The phrase “in a certain embodiment” appearing in various places within the specification does not necessarily refer to the same embodiment. Conditional terms used herein, such as “may,” “possibly,” “might,” “may,” “for example,” etc., are generally intended to indicate that a particular embodiment includes a particular feature, element, and / or step, while other embodiments do not, unless otherwise specified or understood in the context in which they are used. Furthermore, the articles “a,” “an,” or “it” used in this application and the appended claims are to mean “one or more” or “at least one,” unless otherwise specified.

[0088] Language as used herein, such as terms like “approximately,” “about,” “generally,” and “roughly,” still represents values, quantities, or features close to the stated values, quantities, or features that perform the desired function or achieve the desired result. For example, terms like “approximately,” “about,” “generally,” and “roughly” may refer to quantities within ±10%, ±5%, ±2%, ±1%, or ±0.1% of the stated quantity. As another example, terms like “generally parallel” and “roughly parallel” refer to values, quantities, or features that deviate by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees from exactly parallel, and terms like “generally perpendicular” and “roughly perpendicular” refer to values, quantities, or features that deviate by ±10 degrees, ±5 degrees, ± This refers to a value, quantity, or feature that deviates by 2 degrees, ±1 degree, or ±0.1 degrees. The scopes disclosed herein also encompass any overlaps, subranges, and combinations thereof. For example, the words “up to,” “at least,” “greater than,” “less than,” and “between” include the numbers listed. As used herein, the meanings of “a,” “an,” and “the foregoing” include multiple references unless explicitly indicated otherwise in the context. Also, as used herein, the meaning of “in” includes “into” and “on,” unless explicitly indicated otherwise in the context.

[0089] As used herein, the terms “equipment,” “possess,” “include,” “contain,” “have,” “possess,” or any other variation thereof are non-restrictive terms intended to encompass non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a list of elements does not have to be limited to those elements alone, and may include other elements not expressly described or inherent in such process, method, article, or apparatus. Furthermore, unless explicitly stated otherwise, “or” refers to an inclusive OR, not an exclusive OR. For example, condition A or B is satisfied by one of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), or both A and B are true (or exist). The phrase “at least one of” in a list of items, as used herein, refers to any combination of those items that contains one component. For example, "at least one of A, B, or C" is intended to encompass A, B, C, A and B, A and C, B and C, and A, B and C. Conjunctional phrases such as "at least one of X, Y, and Z" are generally used to indicate that an item, term, etc., may be at least one of X, Y, or Z, unless otherwise specified. Therefore, such conjunctional phrases do not generally imply that a particular embodiment must include at least one of X, at least one of Y, and at least one of Z, respectively.

[0090] Therefore, while only certain embodiments have been specifically described herein, it will be apparent that numerous modifications can be made without departing from the spirit and scope of the invention. Furthermore, acronyms are used solely to improve the readability of the specification and claims. It should be noted that these acronyms are not intended to diminish the generality of the terminology used and the claims should not be construed as limiting them to the embodiments described herein.

Claims

1. A quantum computing (QC) system comprising a plurality of qubits substantially arranged in a plurality of substantially parallel planes, wherein at least some of the substantially planes comprise two or more qubits, and one or more qubits in each of the substantially planes are configured to interact with one or more qubits in at least one other substantially plane.

2. A first substrate and a second substrate, wherein the first substrate and the second substrate are substantially parallel to each other, A plurality of qubits arranged as a multi-qubit gate array having a plurality of multi-qubit gates located in the region between the first substrate and the second substrate, wherein the qubits are provided on or near at least one surface of the first substrate and the second substrate, and are substantially arranged in a plurality of substantially planar regions, The system according to claim 1, further comprising:

3. The system according to claim 2, wherein the first substrate is substantially flat and the second substrate is substantially flat.

4. The system according to claim 2, wherein each of the multi-qubit gates of the array has a first portion on the surface of the first substrate and a second portion on the surface of the second substrate.

5. The system according to claim 4, wherein the multi-qubit gates are arranged along the surface of the first substrate in a substantially rectangular pattern having at least one row and at least one column, or a substantially hexagonal pattern, or a substantially diagonal pattern.

6. The system according to claim 5, wherein the substantially rectangular pattern has four rows, each having four of the multi-qubit gates, and four columns, each having four of the multi-qubit gates.

7. The system according to claim 6, wherein each row of the multi-qubit gate consists of two alternately arranged 4-qubit gates and two 13-qubit gates, and each column of the multi-qubit gate consists of two alternately arranged 4-qubit gates and two 13-qubit gates.

8. The system according to claim 7, wherein the first portion is arranged such that any four nearest first portions include a single-qubit portion, a three-qubit portion, a six-qubit portion, and a seven-qubit portion, and the second portion is arranged such that any four nearest second portions include a single-qubit portion, a three-qubit portion, a six-qubit portion, and a seven-qubit portion.

9. The system according to claim 4, wherein the first portion of each of the multi-qubit gates in the array is selected from a group consisting of a single-qubit portion, a three-qubit portion, a six-qubit portion, and a seven-qubit portion, and the second portion of each of the multi-qubit gates in the array is selected from a group consisting of a single-qubit portion, a three-qubit portion, a six-qubit portion, and a seven-qubit portion.

10. The system according to claim 4, wherein with respect to each of the multi-qubit gates, each of the qubits is configured to be quantum mechanically entangled with at least one of the other qubits of the multi-qubit gate.

11. The system according to claim 4, wherein the first portion of each of the multi-qubit gates in the array comprises 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more of the qubits, and / or the second portion of each of the multi-qubit gates in the array comprises 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more of the qubits.

12. The system according to claim 1, wherein the two or more qubits in each of the substantially planar regions, and the one or more qubits, are configured to directly interact with one or more of the qubits in at least one other substantially planar region, thereby forming a 3D cell array configured to undergo multi-qubit gate operations involving two or more of the qubits simultaneously.

13. A quantum computing (QC) system having a plurality of fully connected multi-ionic qubit gates arranged in a substantially rectangular lattice having a plurality of rows and a plurality of columns, wherein the plurality of multi-ionic qubit gates are configured for the simultaneous gate operation of two or more of the multi-ionic qubit gates.

14. The system according to claim 13, wherein the multi-ion qubit gates in at least one row of the plurality of rows and / or at least one column of the plurality of columns include alternately arranged 4-ion qubit gates and 13-ion qubit gates.

15. The system according to claim 13, wherein the multi-ion qubit gate in at least one row of the plurality of rows and / or at least one column of the plurality of columns comprises a plurality of 10-ion qubit gates.

16. The system according to claim 13, wherein the multi-ion qubit gates in at least one row of the plurality of rows and / or at least one column of the plurality of columns include a 4-ion qubit gate, a 13-ion qubit gate, and a plurality of 10-ion qubit gates.

17. The aforementioned multi-ion qubit gate is as follows: An equal number of 4-ion qubit gates and 13-ion qubit gates are alternately arranged along each row and each column, All of the multi-ion qubit gates in a lattice including a 10-ion qubit gate, The system according to claim 13, which includes one of the following.

18. A quantum computing (QC) system comprising a plurality of multi-qubit three-dimensional (3D) gate cells, each of which comprises at least three qubits configured to be fully connected to each other simultaneously across three dimensions, and the plurality of multi-qubit 3D gate cells are configured for gate operations of two or more of the multi-qubit 3D gate cells.

19. The system according to claim 18, wherein the plurality of multi-qubit 3D gate cells include an ion trap array configured to have optimal coherent coupling or direct entanglement between the nearest qubit or the second nearest qubit, without mutual coupling of photons between the qubits.

20. The aforementioned multi-qubit 3D gate cell does not rely on the linking of multiple 1- and 2-qubit gates, has a geometrically symmetrical structure, and can be activated spontaneously with a single gate operation. The system according to claim 18, configured as described above.

21. The system according to claim 18, wherein the multi-qubit cell has an asymmetric 3D structure having complementary bases and caps arranged in alternating directions, with alternating arrangements of bases and caps of non-identical adjacent cells.

22. The system according to claim 18, wherein the plurality of multi-qubit 3D gate cells are configured to operate as at least one quantum FPGA (QFPGA) and / or quantum ASIC (QASIC) chip.

23. A quantum computing (QC) system comprising an array of multi-qubit three-dimensional (3D) gate cells, wherein the array has one or more 9-qubit gates, 8-qubit gates, and / or 7-qubit gates.

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