Calculation method and semiconductor memory device

Abstract

This provides a calculation method that can reduce processing time. [Solution] The calculation method according to the embodiment is a calculation method using a first latch circuit including a first inverter having an input terminal connected to a first node and an output terminal connected to a second node, and a second inverter having an input terminal connected to a second node and an output terminal connected to a first node, comprising: driving the first inverter and the second inverter to store first data in the first node and storing second data, which is the inverted data of the first data, in the second node; driving the first inverter and the second inverter to read the first data from the first node to a bus connected to the first latch circuit; driving the first inverter to write the first data to the first node from which the first data was read, based on the second data; and driving the second inverter after writing the first data.

Description

Technical Field

[0001] Embodiments relate to an operation method in a sense amplifier module and a semiconductor memory device that executes the operation method.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatilely, a NAND type flash memory is known. The NAND type flash memory includes a sense amplifier module and reads data stored in the memory and writes data to the memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provide an operation method capable of shortening the processing time.

Means for Solving the Problems

[0005] The calculation method according to the embodiment is a calculation method using a first latch circuit including a first inverter having an input terminal connected to a first node and an output terminal connected to a second node, and a second inverter having an input terminal connected to a second node and an output terminal connected to a first node, comprising: driving the first inverter and the second inverter to store first data in the first node and storing second data, which is the inverted data of the first data, in the second node; de-driving the first inverter and the second inverter to read the first data from the first node to a bus connected to the first latch circuit; driving the first inverter to write the first data to the first node from which the first data was read, based on the second data; and driving the second inverter after writing the first data. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 3] Figure 3 is a block diagram showing an example of the configuration of a sense amplifier module included in a semiconductor memory device according to this embodiment. [Figure 4] Figure 4 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module included in a semiconductor memory device according to the embodiment. [Figure 5] Figure 5 is a circuit diagram showing an example of the circuit configuration of a latch circuit included in the sense amplifier module of the semiconductor memory device according to the embodiment. [Figure 6] Figure 6 is a timing chart showing an example of the voltages of various signals during the first arithmetic processing in a sense amplifier module provided in a semiconductor memory device according to the embodiment. [Figure 7] Figure 7 is a table showing the data held by each node and bus during the first arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. [Figure 8]Figure 8 is a timing chart showing an example of the voltages of various signals during the second arithmetic processing in a sense amplifier module provided in a semiconductor memory device according to the embodiment. [Figure 9] Figure 9 is a table showing the data held by each node and bus during the second arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. [Figure 10] Figure 10 is a timing chart showing an example of the voltages of various signals during the third arithmetic processing in a sense amplifier module provided in a semiconductor memory device according to the embodiment. [Figure 11] Figure 11 is a table showing the data held by each node and bus during the third arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. [Figure 12] Figure 12 is a timing chart showing an example of the voltages of various signals during the first arithmetic processing in a sense amplifier module provided in a semiconductor memory device according to the embodiment. [Figure 13] Figure 13 is a timing chart showing an example of the voltages of various signals during the second arithmetic processing in a sense amplifier module provided in a semiconductor memory device according to the embodiment. [Figure 14] Figure 14 is a timing chart showing an example of the voltages of various signals during the third arithmetic processing in a sense amplifier module provided in a semiconductor memory device according to the embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The drawings are schematic, and the dimensions and proportions shown are not necessarily the same as those of actual objects. In the following description, components having substantially the same function and configuration are denoted by the same reference numeral. When elements with similar configurations are to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0009] 1. Structure 1.1 Memory System A semiconductor memory device according to an embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0011] The semiconductor memory device 3 is, for example, a memory that stores data either volatilely or non-volatilely. The following description assumes that the semiconductor memory device 3 is a NAND flash memory.

[0012] The communication between the memory controller 2 and the semiconductor memory device 3 complies with, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface). Between the memory controller 2 and the semiconductor memory device 3, signals including, for example, signal IO<7:0>, CEn, CLE, ALE, WEn, REn, and RBn are exchanged.

[0013] 1.2 Semiconductor Memory Device Continuing, referring to the block diagram shown in FIG. 1, the internal configuration of the semiconductor memory device 3 according to the embodiment will be described. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0014] The memory cell array 10 is a set of memory cell transistors and a set of components connected to the memory cell transistors. The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is an aggregate of a plurality of memory cell transistors capable of storing data non-volatily. A block BLK is used, for example, as an erasure unit when erasing the data stored in the memory cell transistors. Also, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor is associated with, for example, a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The input / output circuit 11 is an interface circuit that controls the transmission and reception of the signal IO<7:0> between the memory controller 2. The signal IO<7:0> is an 8-bit signal. The signal IO<7:0> includes, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs the data DAT between the sense amplifier module 17 and the memory controller 2 respectively. The input / output circuit 11 outputs each of the command CMD and address information ADD transferred from the memory controller 2 to the register 13. The input / output circuit 11 outputs the status information STA transferred from the register 13 to the memory controller 2.

[0016] The logic control circuit 12 is an interface circuit that controls the reception of the signals CEn, CLE, ALE, WEn, and REn input from the memory controller 2, and the transmission of the signal RBn to the memory controller 2. The logic control circuit 12 controls each of the input / output circuit 11 and the sequencer 14 based on the signals CEn, CLE, ALE, WEn, and REn. For example, the logic control circuit 12 controls the sequencer 14 based on the signal CEn to enable the semiconductor memory device 3. The logic control circuit 12 notifies the input / output circuit 11 that the signal IO<7:0> received by the input / output circuit 11 is the command CMD and the address information ADD respectively based on the signals CLE and ALE. The logic control circuit 12 commands the input / output circuit 11 to input and output the signal IO<7:0> respectively based on the signals WEn and REn. Also, the logic control circuit 12 outputs the signal RBn indicating whether the semiconductor memory device 3 is in the ready state (a state of accepting commands from the outside) or the busy state (a state of not accepting commands from the outside) to the memory controller 2.

[0017] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read operations, write operations, erase operations, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used to select block BLK, word lines, and bit lines, respectively. Status information STA is used to notify the memory controller 2 whether the operation has been completed successfully or not. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0018] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, the sequencer 14 controls the driver module 15, the row decoder module 16, and the sense amplifier module 17, etc., based on the command CMD stored in register 13. The sequencer 14 also performs read operations, write operations, and erase operations, for example.

[0019] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0020] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0021] The sense amplifier module 17 includes a sense amplifier unit capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a predetermined voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0022] 1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. Figure 2 shows block BLK0. Block BLK0 includes, for example, five string units SU0 to SU4.

[0023] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0025] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Within string units SU0 to SU4, the gates of selection transistors ST1 are connected to selection gate lines SGD0 to SGD4, respectively. Within the same block BLK, the gate of selection transistor ST2 is connected to selection gate line SGS.

[0026] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared by a NAND string NS, which is assigned the same column address CA across multiple block BLKs. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0028] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to this embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0029] 1.4 Sense Amplifier Module Configuration 1.4.1 Overview Figure 3 is a block diagram showing an example of the configuration of a sense amplifier module included in a semiconductor memory device according to the embodiment.

[0030] As shown in Figure 3, the sense amplifier module 17 includes sense amplifier units SAU0 to SAUm and latch circuits XDL0 to XDLm. The sense amplifier units SAU0 to SAUm and latch circuits XDL0 to XDLm are each associated with bit lines BL0 to BLm. Hereafter, if the sense amplifier units SAU0 to SAUm are not distinguished, they will simply be referred to as sense amplifier unit SAU. If the latch circuits XDL0 to XDLm are not distinguished, they will simply be referred to as latch circuit XDL.

[0031] The sense amplifier unit SAU is, for example, a current-sensing sense amplifier unit that senses the current flowing through the bit line BL. The sense amplifier unit SAU senses the current flowing through the corresponding bit line BL and determines the state of the memory cell based on the sensing result. The sense amplifier unit SAU also transfers write data to the memory cell transistor MT via the corresponding bit line BL. The sense amplifier unit SAU may also be a voltage-sensing sense amplifier unit that senses the voltage of the bit line BL.

[0032] Each sense amplifier unit SAU includes, for example, a sense circuit SAC, and seven latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL. The sense circuit SAC and the seven latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL are all connected to the bus LBUS. The number of latch circuits included in each sense amplifier unit SAU may be set to any number of two or more.

[0033] During a read operation, the sense circuit SAC senses the data read onto the corresponding bit line BL and determines whether the read data is "0" or "1". During a write operation, the sense circuit SAC applies a voltage to the bit line BL based on the data stored in one of the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL.

[0034] The latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL are circuits that store read data, write data, sense results, calculation results, etc. For example, each latch circuit SDL, ADL, BDL, CDL, DDL, EDL, and FDL stores one bit of data, either "0" data or "1" data. For example, during a read operation, data may be transferred from the sense circuit SAC to one of the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL. During a write operation, a voltage is applied to the bit line BL based on the data stored in one or more of the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL.

[0035] The sense amplifier unit SAU performs AND and OR operations using data stored in the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL, for example, during read and write operations. The AND operation refers to data stored in multiple latch circuits and outputs "1" data if all referenced latch circuits store "1" data, and "0" data otherwise. The OR operation refers to data stored in multiple latch circuits and outputs "1" data if at least one of the referenced latch circuits stores "1" data, and "0" data otherwise.

[0036] The configuration of the sense amplifier unit SAU is not limited to this and can be modified in various ways. For example, the number of latch circuits in the sense amplifier unit SAU can be designed based on the number of bits of data stored in one memory cell transistor MT.

[0037] The latch circuit XDL is connected to one sense amplifier unit SAU via bus DBUS. The latch circuit XDL is also connected to input / output circuit 11 via bus XBUS to transmit and receive data DAT.

[0038] 1.4.2 Circuit Configuration Figure 4 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module included in a semiconductor memory device according to the embodiment. Figure 4 shows an extracted example of one sense amplifier unit SAU included in the sense amplifier module 17. Other sense amplifier units SAU have a similar configuration to that in Figure 4. In the following description, unless the source and drain of a transistor are specified, either the source or the drain of a transistor will be referred to as the "first terminal of the transistor," and either the source or the drain of a transistor will be referred to as the "second terminal of the transistor." The state in which the first and second terminals of a transistor are electrically connected through the transistor is called the "on state," and the state in which they are electrically isolated through the transistor is called the "off state."

[0039] As shown in Figure 4, the sense amplifier module 17 includes, in addition to the configuration shown in Figure 3, a transistor TR1 which is a high-voltage N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) corresponding to the sense amplifier unit SAU. In other words, within the sense amplifier module 17, a transistor TR1 is provided for each sense amplifier unit SAU.

[0040] The first terminal of transistor TR1 is connected to the corresponding bit line BL. The second terminal of transistor TR1 is connected to wiring BLIC. The control signal BLS is input to the gate of transistor TR1. The control signal BLS is, for example, a signal generated by sequencer 14. Transistor TR1 is used, for example, to prevent excessive high voltage from being supplied to sense amplifier unit SAU.

[0041] The sense amplifier unit SAU includes a sense circuit SAC, a precharge circuit LBP, a bus switch BSW, and seven latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL.

[0042] The circuit configuration of the sense circuit SAC will now be described. The sense circuit SAC comprises transistors TR2 to TR14 and capacitive elements C1 and C2. Transistors TR2 to TR3 and TR5 to TR14 include N-channel MOSFETs. Transistor TR4 includes a P-channel MOSFET.

[0043] The first terminal of transistor TR2 is connected to wiring BLIC. The second terminal of transistor TR2 is connected to node SCOM. The gate of transistor TR2 is input with the control signal BLX. The control signal BLX is, for example, a signal generated by sequencer 14.

[0044] The first terminal of transistor TR3 is connected to node SCOM. The second terminal of transistor TR3 is connected to the first terminal of transistor TR4 and the first terminal of transistor TR5. The gate of transistor TR3 is input to the control signal BLX. The control signal BLX is, for example, a signal generated by sequencer 14.

[0045] A voltage VHSA is applied to the second terminal of transistor TR4. VHSA is, for example, the power supply voltage VCC. The gate of transistor TR4 is connected to node INV_S, which will be described later.

[0046] The voltage SRCGND is applied to the second terminal of transistor TR5. The voltage SRCGND is, for example, the ground voltage VSS. The gate of transistor TR5 is connected to node INV_S, which will be described later.

[0047] The first terminal of transistor TR6 is connected to node SCOM. The voltage SRCGND is applied to the second terminal of transistor TR6. The control signal NLO is input to the gate of transistor TR6. The control signal NLO is, for example, a signal generated by sequencer 14.

[0048] The first terminal of transistor TR7 is connected to node SCOM. The second terminal of transistor TR7 is connected to node SEN1. The gate of transistor TR7 is input to control signal XXL. Control signal XXL is, for example, a signal generated by sequencer 14.

[0049] The first terminal of transistor TR8 is connected to node SEN1. A voltage VHLB is applied to the second terminal of transistor TR8. Voltage VHLB is, for example, the power supply voltage VCC. A control signal SPC is input to the gate of transistor TR8. Control signal SPC is, for example, a signal generated by sequencer 14.

[0050] The first terminal of transistor TR9 is connected to node SEN1. The second terminal of transistor TR9 is connected to node SEN2. The gate of transistor TR9 is input to the control signal S2S. The control signal S2S is, for example, a signal generated by sequencer 14.

[0051] The first terminal of transistor TR10 is connected to the first terminal of transistor TR11. A voltage VLOP is applied to the second terminal of transistor TR10. The voltage VLOP is, for example, the ground voltage VSS. The gate of transistor TR10 is connected to node SEN2.

[0052] The second terminal of transistor TR11 is connected to the bus LBUS. The gate of transistor TR11 is input to the control signal STB. The control signal STB is, for example, a signal generated by the sequencer 14.

[0053] The first terminal of transistor TR12 is connected to node SEN2. The second terminal of transistor TR12 is connected to bus LBUS. The gate of transistor TR12 is input with the control signal BLQ. The control signal BLQ is, for example, a signal generated by sequencer 14.

[0054] The first terminal of transistor TR13 is connected to the first terminal of transistor TR14. The voltage VLOP is applied to the second terminal of transistor TR13. The gate of transistor TR13 is connected to the bus LBUS.

[0055] The second terminal of transistor TR14 is connected to node SEN2. The gate of transistor TR14 is input to the control signal LSL. The control signal LSL is, for example, a signal generated by sequencer 14.

[0056] One electrode of the capacitive element C1 is connected to node SEN1. The other electrode of the capacitive element C1 is connected to bus LBUS.

[0057] One electrode of the capacitive element C2 is connected to node SEN2. A voltage VLOP is applied to the other electrode of the capacitive element C2.

[0058] The circuit configuration of the pre-charge circuit LBP will be described. The pre-charge circuit LBP is a circuit that pre-charges the bus LBUS. The pre-charge circuit LBP includes a transistor TR15 which contains an N-channel MOSFET.

[0059] The first terminal of transistor TR15 is connected to the bus LBUS. The voltage VDDSA is applied to the second terminal of transistor TR15. The voltage VDDSA is, for example, the power supply voltage VCC. The control signal LPC is input to the gate of transistor TR15. The control signal LPC is, for example, a signal generated by sequencer 14.

[0060] The circuit configuration of the bus switch BSW is described below. The bus switch BSW is a switch that connects bus LBUS and bus DBUS. The bus switch BSW includes a transistor TR16 which contains an N-channel MOSFET.

[0061] The first terminal of transistor TR16 is connected to the bus LBUS. The second terminal of transistor TR16 is connected to the bus DBUS. The gate of transistor TR16 is input to the control signal DSW. The control signal DSW is, for example, a signal generated by the sequencer 14.

[0062] Next, the circuit configurations of the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL will be described using Figure 5. Figure 5 is a circuit diagram showing an example of the circuit configuration of a latch circuit included in the sense amplifier module of the semiconductor memory device according to the embodiment. Figure 5 shows the circuit configurations of the latch circuits SDL, ADL, and BDL, as well as a part of the circuit configuration of the sense circuit SAC. In the following description, the circuit configurations of the latch circuits SDL and ADL will be described. Note that the circuit configurations of the latch circuits BDL, CDL, DDL, EDL, and FDL are the same as those of the latch circuits SDL and ADL.

[0063] The latch circuit SDL comprises transistors TR21 to TR28. Transistors TR21, TR22, TR24, and TR26 include N-channel MOSFETs. Transistors TR23, TR25, TR27, and TR28 include P-channel MOSFETs.

[0064] The first terminal of transistor TR21 is connected to the bus LBUS. The second terminal of transistor TR21 is connected to node LAT_S. The node of transistor TR21 receives a control signal STL as input. The control signal STL is, for example, a signal generated by sequencer 14.

[0065] The first terminal of transistor TR22 is connected to the bus LBUS. The second terminal of transistor TR22 is connected to node INV_S. The control signal STI is input to the node of transistor TR22. The control signal STI is, for example, a signal generated by sequencer 14.

[0066] The first terminal of transistor TR23 is connected to node LAT_S. The second terminal of transistor TR23 is connected to the first terminal of transistor TR27. The gate of transistor TR23 is connected to node INV_S.

[0067] The first terminal of transistor TR24 is connected to node LAT_S. A voltage VSS_S1 is applied to the second terminal of transistor TR24. The voltage VSS_S1 is, for example, the ground voltage VSS. The gate of transistor TR24 is connected to node INV_S.

[0068] The first terminal of transistor TR25 is connected to node INV_S. The second terminal of transistor TR25 is connected to the first terminal of transistor TR28. The gate of transistor TR25 is connected to node LAT_S.

[0069] The first terminal of transistor TR26 is connected to node INV_S. A voltage VSS_S2 is applied to the second terminal of transistor TR26. The voltage VSS_S2 is, for example, the ground voltage VSS. The gate of transistor TR26 is connected to node LAT_S.

[0070] A voltage VDDSA is applied to the second terminal of transistor TR27. A control signal SLL is input to the gate of transistor TR27. The control signal SLL is, for example, a signal generated by sequencer 14.

[0071] A voltage VDDSA is applied to the second terminal of transistor TR28. A control signal SLI is input to the gate of transistor TR28. The control signal SLI is, for example, a signal generated by sequencer 14.

[0072] When transistor TR27 is ON, transistors TR23 and TR24 function as inverter IV21, inverting the logic of node INV_S and outputting it to node LAT_S. In this case, node INV_S can be considered the input terminal of inverter IV21, and node LAT_S can be considered the output terminal of inverter IV21. Transistor TR27 controls the driving of transistors TR23 and TR24 as inverter IV21.

[0073] When transistor TR28 is ON, transistors TR25 and TR26 function as inverter IV22, inverting the logic of node LAT_S and outputting it to node INV_S. In this case, node LAT_S can be considered the input terminal of inverter IV22, and node INV_S can be considered the output terminal of inverter IV22. Transistor TR28 controls the driving of transistors TR25 and TR26 as inverter IV22.

[0074] The latch circuit SDL stores data by ensuring that the logic of node LAT_S and the logic of node INV_S are mutually exclusive. When the voltage of node LAT_S is at a "H" (High) level and the voltage of node INV_S is at a "L" (Low) level, the latch circuit SDL stores the data "1". When the voltage of node LAT_S is at a "L" level and the voltage of node INV_S is at a "H" level, the latch circuit SDL stores the data "0".

[0075] The latch circuit ADL comprises transistors TR31 to TR38. Transistors TR31, TR32, TR34, and TR36 include N-channel MOSFETs. Transistors TR33, TR35, TR37, and TR38 include P-channel MOSFETs.

[0076] The first terminal of transistor TR31 is connected to the bus LBUS. The second terminal of transistor TR31 is connected to node LAT_A. The control signal ATL is input to the node of transistor TR31. The control signal ATL is, for example, a signal generated by sequencer 14.

[0077] The first terminal of transistor TR32 is connected to the bus LBUS. The second terminal of transistor TR32 is connected to node INV_A. The control signal ATI is input to the node of transistor TR32. The control signal ATI is, for example, a signal generated by sequencer 14.

[0078] The first terminal of transistor TR33 is connected to node LAT_A. The second terminal of transistor TR33 is connected to the first terminal of transistor TR37. The gate of transistor TR33 is connected to node INV_A.

[0079] The first terminal of transistor TR34 is connected to node LAT_A. A voltage VSS_A1 is applied to the second terminal of transistor TR34. The voltage VSS_A1 is, for example, the ground voltage VSS. The gate of transistor TR34 is connected to node INV_A.

[0080] The first terminal of transistor TR35 is connected to node INV_A. The second terminal of transistor TR35 is connected to the first terminal of transistor TR38. The gate of transistor TR35 is connected to node LAT_A.

[0081] The first terminal of transistor TR36 is connected to node INV_A. A voltage VSS_A2 is applied to the second terminal of transistor TR36. The voltage VSS_A2 is, for example, the ground voltage VSS. The gate of transistor TR36 is connected to node LAT_A.

[0082] A voltage VDDSA is applied to the second terminal of transistor TR37. The control signal ALL is input to the gate of transistor TR37. The control signal ALL is, for example, a signal generated by sequencer 14.

[0083] A voltage VDDSA is applied to the second terminal of transistor TR38. The control signal ALI is input to the gate of transistor TR38. The control signal ALI is, for example, a signal generated by sequencer 14.

[0084] When transistor TR37 is ON, transistors TR33 and TR34 function as inverter IV31, inverting the logic of node INV_A and outputting it to node LAT_A. In this case, node INV_A can be considered the input terminal of inverter IV31, and node LAT_A can be considered the output terminal of inverter IV31. Transistor TR37 controls the driving of transistors TR33 and TR34 as inverter IV31.

[0085] When transistor TR38 is ON, transistors TR35 and TR36 function as inverter IV32, inverting the logic of node LAT_A and outputting it to node INV_A. In this case, node LAT_A can be considered the input terminal of inverter IV32, and node INV_A can be considered the output terminal of inverter IV32. Transistor TR38 controls the driving of transistors TR35 and TR36 as inverter IV32.

[0086] The latch circuit ADL stores data by ensuring that the logic of node LAT_A and the logic of node INV_A are mutually exclusive. When the voltage of node LAT_A is at a "H" (High) level and the voltage of node INV_A is at a "L" (Low) level, the latch circuit ADL stores the data "1". When the voltage of node LAT_A is at a "L" level and the voltage of node INV_A is at a "H" level, the latch circuit ADL stores the data "0".

[0087] As described above, in the sense amplifier unit SAU, the sense circuit SAC and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL can send and receive data from each other via the bus LBUS.

[0088] 2. Operation The operation of the sense amplifier module 17 using the data stored by the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL when the semiconductor memory device 3 according to the embodiment writes data to the memory cell array 10 will be described below. When the sense amplifier module 17 according to the embodiment writes data to the memory cell array 10, it applies a voltage corresponding to the data to be written to the bit line BL corresponding to the memory cell into which the data is input. At this time, the sense amplifier unit SAU performs a first arithmetic operation, a second arithmetic operation, and a third arithmetic operation using the data stored by the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL. The contents of each operation and the operation of the sense amplifier unit SAU at that time will be described below. In the following description, a voltage at the "H" level corresponds to the logic of "1", and a voltage at the "L" level corresponds to the logic of "0".

[0089] 2.1 First arithmetic processing The first arithmetic operation is a process that performs an AND operation by referencing data stored in multiple latch circuits and outputs the result to node SEN2. In the following explanation, the first arithmetic operation, which references the data stored in each of the latch circuits SDL and ADL and outputs the calculation result to node SEN2, will be described with reference to Figures 6 and 7.

[0090] Figure 6 is a timing chart showing an example of the voltages of various signals during the first arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. Figure 6 shows the signals input to the circuit provided between node SEN2 and bus LBUS in the sense circuit SAC, and the signals input to the latch circuits SDL and ADL.

[0091] Figure 7 is a table showing the data held by each node and bus during the first arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. Table (a) in Figure 7 shows the process of the first arithmetic processing when both latch circuits SDL and ADL store "0" data. Table (b) shows the process of the first arithmetic processing when latch circuit SDL stores "0" data and latch circuit ADL stores "1" data. Table (c) shows the process of the first arithmetic processing when latch circuit SDL stores "1" data and latch circuit ADL stores "0" data. Table (d) shows the process of the first arithmetic processing when both latch circuits SDL and ADL store "1" data. In Figure 7, the notation "0" indicates that the node or bus has an "L" level signal (voltage), and the notation "1" indicates that the node or bus has an "H" level signal (voltage). Furthermore, in the table in Figure 7, the hatched columns indicate the points where the logic changed as a result of the calculation process at each step.

[0092] Step S10 in Figures 6 and 7 shows the initial state in each case. The latch circuits SDL and ADL store the data corresponding to each case. Also, node SEN2 and bus LBUS are precharged to the "H" level. Precharging node SEN2 and bus LBUS is done, for example, by setting the control signals LPC and BLQ to the "H" level. After precharging, the control signals LPC and BLQ are set to the "L" level.

[0093] As shown in Figure 6, through the first calculation process, the voltages of the control signals STB and LSL are at the "L" level. That is, transistors TR11 and TR14 are in the off state throughout the first calculation process.

[0094] In step S11, the voltages of the control signals SLL and SLI are set to the "H" level. This turns off transistors TR27 and TR28. In other words, inverters IV21 and IV22 become non-driven. Nodes LAT_S and INV_S enter a floating state, retaining their respective initial levels.

[0095] In step S12, the voltages of the control signals ALL and ALI are set to the "H" level. This turns off transistors TR37 and TR38. In other words, inverters IV31 and IV32 become non-driven. Nodes LAT_A and INV_A enter a floating state, retaining their respective initial state data.

[0096] Steps S11 and S12 are executed with a certain time difference in order to stagger the execution timing of steps S13 and S14 in order to suppress overshoot, as will be described later.

[0097] Step S13 is executed a predetermined time after step S11. In step S13, the voltage of the control signal STL is set to the "H" level. This turns on transistor TR21. As a result, the data from node LAT_S is read to bus LBUS. If node LAT_S stores "0" data (i.e., latch circuit SDL stores "0" data) (Figures 7(a) and (b)), transistor TR24 is in the "O" state, so the voltage VSS_S1 is applied to bus LBUS via transistors TR21 and TR24. Therefore, bus LBUS stores "0" data. If node LAT_S stores "1" data (i.e., latch circuit SDL stores "1" data) (Figures 7(c) and (d)), transistor TR24 is in the "O" state, so bus LBUS stores "1" data. Note that step S13 may be executed at the same timing as step S12.

[0098] Step S14 is executed a predetermined time after step S12. In step S14, the voltage of the control signal ATL is set to the "H" level. This turns on transistor TR31. As a result, the data from node LAT_A is read to bus LBUS. If node LAT_A stores "0" data (i.e., latch circuit ADL stores "0" data) (Figures 7(a) and (c)), transistor TR34 is in the "O" state, so the voltage VSS_A1 is applied to bus LBUS via transistors TR31 and TR34. Therefore, bus LBUS stores "0" data. If node LAT_S stores "1" data (Figure 7(c)), the voltage VSS_A1 is applied to node LAT_S via transistors TR21, TR31, and TR34, as well as bus LBUS. Therefore, node LAT_S stores "0" data. At this time, node INV_S remains in a floating state while storing "0" data. When node LAT_A stores "1" data (i.e., latch circuit ADL stores "1" data) and node LAT_S stores "0" data (Figure 7(b)), the voltage VSS_S1 is applied to node LAT_A via transistors TR21, TR24, and TR31, and bus LBUS. Therefore, node LAT_A and bus LBUS store "0" data. In this case, node INV_A remains in a floating state while storing "0" data. When node LAT_A stores "1" data (i.e., latch circuit ADL stores "1" data) and node LAT_S stores "1" data (Figure 7(d)), transistor TR34 is in the off state, so bus LBUS stores "1" data.

[0099] Steps S13 and S14 are executed with a certain time difference. This is to suppress the phenomenon of the bus LBUS potential rising rapidly and overshooting when both nodes LAT_S and LAT_A store "1" data (Figure 7(d)), because a "H" level voltage is applied to the bus LBUS from both latch circuits SDL and ADL.

[0100] In step S15, the voltage of the control signal BLQ is set to the "H" level. This turns on transistor TR12. Since node SEN2 and bus LBUS are now conductive, node SEN2 stores data with the same logic as the data stored by bus LBUS. Note that step S15 may be executed at the same time as step S14.

[0101] In step S16, the voltage of the control signal BLQ is set to the "L" level. This turns off transistor TR12, electrically isolating node SEN2 and bus LBUS. Node SEN2 stores the result of the AND operation of the data stored in latch circuits SDL and ADL, respectively.

[0102] The process from steps S11 to S16 is called the AND operation process. The AND operation process allows the AND result of the data stored in the latch circuits SDL and ADL to be output to node SEN2.

[0103] In step S17, the voltages of the control signals STL and ATL are set to the "L" level. This turns off transistors TR21 and TR31, electrically isolating the latch circuits SDL and ADL, as well as the bus LBUS. Step S17 may be performed at the same timing as step S16.

[0104] In step S18, the voltages of the control signals SLL and ALL are set to the "L" level. This turns on transistors TR27 and TR37. That is, inverters IV21 and IV31 are driven. When the data stored in node LAT_S changes from "1" to "0" (Figure 7(c)), node INV_S stores "0" data, so transistor TR23 is in the "on" state, and the voltage VDDSA is applied to node LAT_S via transistors TR23 and TR27. Therefore, the data "1" is written to node LAT_S. When the data stored in node LAT_A changes from "1" to "0" (Figure 7(b)), node INV_A stores "0" data, so transistor TR33 is in the "on" state, and the voltage VDDSA is applied to node LAT_A via transistors TR33 and TR37. Therefore, the data "1" is written to node LAT_A.

[0105] In step S19, the voltages of the control signals SLI and ALI are set to the "L" level. This turns on transistors TR28 and TR38. That is, inverters IV22 and IV32 are driven. As a result, the logic of node LAT_S and the logic of node INV_S, and the logic of node LAT_A and the logic of node INV_A become mutually exclusive. Latch circuit SDL stores the same data as the data stored by node LAT_S. Latch circuit ADL stores the same data as the data stored by node LAT_A.

[0106] The process from steps S17 to S19 is called the DL recovery process. During the DL recovery process, the data stored in each latch circuit SDL and ADL is restored to the data it was initially stored in.

[0107] After step S19, the calculation is completed. As shown in Figure 7, the first calculation process allows the data stored in the latch circuits SDL and ADL to remain unchanged from their initial state (step S10), and the result of the AND operation of the data stored in both to be output to node SEN2.

[0108] As described above, the first arithmetic operation is performed. In the examples shown in Figures 6 and 7, the same process is performed even when data stored in one of the latch circuits BDL, CDL, DDL, EDL, or FDL is referenced instead of the latch circuit SDL or ADL.

[0109] 2.2 Second arithmetic processing The second arithmetic operation is the process of performing an AND operation by referencing data stored in multiple latch circuits, outputting the result to one of the referenced latch circuits, and storing it in new memory. In the following explanation, the second arithmetic operation, which references the data stored in latch circuits SDL and ADL, outputs the calculation result to latch circuit SDL, and stores it in new memory, will be explained with reference to Figures 8 and 9.

[0110] Figure 8 is a timing chart showing an example of the voltages of various signals during the second arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. Figure 8 shows the signals input to the latch circuits SDL and ADL.

[0111] Figure 9 is a table showing the data held by each node and bus during the second arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. Table (a) in Figure 9 shows the process of the second arithmetic processing when both latch circuits SDL and ADL store "0" data. Table (b) shows the process of the second arithmetic processing when latch circuit SDL stores "0" data and latch circuit ADL stores "1" data. Table (c) shows the process of the second arithmetic processing when latch circuit SDL stores "1" data and latch circuit ADL stores "0" data. Table (d) shows the process of the second arithmetic processing when both latch circuits SDL and ADL store "1" data. In Figure 9, the notation "0" indicates that the node or bus has an "L" level signal (voltage), and the notation "1" indicates that the node or bus has an "H" level signal (voltage). Furthermore, in the table in Figure 9, the hatched columns indicate the points where the logic changed as a result of the calculation process at each step.

[0112] Step S20 in Figures 8 and 9 shows the initial state in each case. The latch circuits SDL and ADL store the data corresponding to each case. The bus LBUS is precharged to the "H" level. Precharging of the bus LBUS is performed, for example, by setting the control signal LPC to the "H" level. After precharging, the control signal LPC is set to the "L" level.

[0113] Steps S21 to S24 are performed in the same way as steps S11 to S14 in the first arithmetic processing shown in Figures 6 and 7. As a result, inverters IV21, IV22, IV31, and IV32 become de-driven, and bus LBUS and nodes LAT_S and LAT_A store the AND operation result of the data stored in latch circuits SDL and ADL, respectively. The processing in steps S21 to S24 is called the AND operation processing.

[0114] In step S25, the voltages of the control signals STL and ATL are set to the "L" level. This turns off transistors TR21 and TR31, electrically isolating the latch circuits SDL and ADL, as well as the bus LBUS.

[0115] In step S26, the voltages of the control signals SLI and ALL are set to the "L" level. This turns on transistors TR28 and TR37. That is, inverters IV22 and IV31 are driven. When the data stored in node LAT_S changes from "1" to "0" (Figure 9(c)), transistor TR25 is in the "O" state, so the voltage VDDSA is applied to node INV_S via transistors TR25 and TR28. Therefore, the data "1" is written to node INV_S. When the data stored in node LAT_A changes from "1" to "0" (Figure 9(b)), node INV_A stores the data "0", so transistor TR33 is in the "O" state, and the voltage VDDSA is applied to node LAT_A via transistors TR33 and TR37. Therefore, the data "1" is written to node LAT_A.

[0116] In step S27, the voltages of the control signals SLL and ALI are set to the "L" level. This turns on transistors TR27 and TR38. That is, inverters IV21 and IV32 are driven. As a result, the logic of node LAT_S and the logic of node INV_S, and the logic of node LAT_A and the logic of node INV_A become mutually exclusive. Latch circuit SDL stores the same data as the data stored by node LAT_S. Latch circuit ADL stores the same data as the data stored by node LAT_A.

[0117] The process from steps S25 to S27 is called the DL recovery process. During the DL recovery process, the data stored in the latch circuit SDL is updated with the result of the AND operation, and the data stored in the latch circuit ADL is restored to the data it was initially stored with.

[0118] After step S27, the calculation is completed. As shown in Figure 9, the second calculation process allows the data stored in the latch circuit ADL to remain unchanged from its initial state (step S20), while the AND operation result of the data stored in the latch circuits SDL and ADL can be newly stored in the latch circuit SDL.

[0119] As described above, the second arithmetic operation is performed. In the examples shown in Figures 8 and 9, the same process is performed even when data stored in one of the latch circuits BDL, CDL, DDL, EDL, or FDL is referenced instead of the latch circuit SDL or ADL.

[0120] 2.3 Third arithmetic operation The third arithmetic operation is a process that performs an OR operation by referencing data stored in multiple latch circuits, outputs the result to one of the referenced latch circuits, and stores it in new memory. In the following explanation, the third arithmetic operation, which references the data stored in latch circuits SDL and ADL, outputs the calculation result to latch circuit SDL, and stores it in new memory, will be explained with reference to Figures 10 and 11.

[0121] Figure 10 is a timing chart showing an example of the voltages of various signals during the third arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. Figure 10 shows the signals input to the latch circuits SDL and ADL.

[0122] Figure 11 is a table showing the data held by each node and bus during the third arithmetic processing in the sense amplifier module of the semiconductor memory device according to the embodiment. Table (a) in Figure 11 shows the process of the third arithmetic processing when both latch circuits SDL and ADL store "0" data. Table (b) shows the process of the third arithmetic processing when latch circuit SDL stores "0" data and latch circuit ADL stores "1" data. Table (c) shows the process of the third arithmetic processing when latch circuit SDL stores "1" data and latch circuit ADL stores "0" data. Table (d) shows the process of the third arithmetic processing when both latch circuits SDL and ADL store "1" data. In Figure 11, the notation "0" indicates that the node or bus has an "L" level signal (voltage), and the notation "1" indicates that the node or bus has an "H" level signal (voltage). Furthermore, in the table in Figure 11, the hatched columns indicate the points where the logic changed as a result of the calculation process at each step.

[0123] Step S30 in Figures 10 and 11 shows the initial state in each case. The latch circuits SDL and ADL store the data corresponding to each case. The bus LBUS is precharged to the "H" level. Precharging of the bus LBUS is performed, for example, by setting the control signal LPC to the "H" level. After precharging, the control signal LPC is set to the "L" level.

[0124] In step S31, the voltages of the control signals SLL and SLI are set to the "H" level. This turns off transistors TR27 and TR28. In other words, inverters IV21 and IV22 become non-driven. Nodes LAT_S and INV_S enter a floating state, retaining their respective initial levels.

[0125] In step S32, the voltages of the control signals ALL and ALI are set to the "H" level. This turns off transistors TR37 and TR38. That is, inverters IV31 and IV32 become non-driven. Nodes LAT_A and INV_A enter a floating state, retaining their respective initial state data.

[0126] Steps S31 and S32 are executed with a certain time difference in order to stagger the execution timing of steps S33 and S34 in order to suppress overshoot, as will be described later.

[0127] Step S33 is executed a predetermined time after step S31. In step S33, the voltage of the control signal STI is set to the "H" level. This turns on transistor TR22. As a result, the data from node INV_S is read to bus LBUS. If node INV_S stores "1" data (i.e., latch circuit SDL stores "0" data) (Figures 11(a) and (b)), transistor TR26 is turned off, so bus LBUS stores "1" data. If node INV_S stores "0" data (i.e., latch circuit SDL stores "1" data) (Figures 11(c) and (d)), transistor TR26 is turned on, so the voltage VSS_S2 is applied to bus LBUS via transistors TR22 and TR26. Therefore, bus LBUS stores "0" data. Step S33 may be executed at the same timing as step S32.

[0128] Step S34 is executed a predetermined time after step S32. In step S34, the voltage of the control signal ATI is set to the "H" level. This turns on transistor TR32. As a result, the data from node INV_A is read to bus LBUS. If node INV_A stores "1" data (i.e., latch circuit ADL stores "0" data) and node INV_S stores "1" data (Figure 11(a)), transistor TR36 is turned off, and bus LBUS stores "1" data. If node INV_A stores "1" data (i.e., latch circuit ADL stores "0" data) and node INV_S stores "0" data (Figure 11(c)), the voltage VSS_S2 is applied to node INV_A via transistors TR22, TR26, and TR32, as well as bus LBUS. Therefore, node INV_A and bus LBUS store "0" data. In this case, node LAT_A remains in a floating state while storing the "0" data. When node INV_A stores the "0" data (i.e., the latch circuit ADL stores the "1" data) (Figures 11(b) and (d)), transistor TR36 is in the ON state, so the voltage VSS_A2 is applied to the bus LBUS via transistors TR32 and TR36. Therefore, the bus LBUS stores the "0" data. In this case, when node INV_S stores the "1" data (Figure 11(b)), the voltage VSS_A2 is applied to node INV_S via transistors TR22, TR32, and TR36, as well as the bus LBUS. Therefore, node INV_S stores the "0" data. In this case, node LAT_S remains in a floating state while storing the "0" data.

[0129] Steps S33 and S34 are executed with a certain time difference. This is to suppress the phenomenon of the bus LBUS potential rising rapidly and overshooting when both nodes INV_S and INV_A store the data "1" (Figure 11(a)), because a "H" level voltage is applied to the bus LBUS from both latch circuits SDL and ADL.

[0130] The processing in steps S31 to S34 is called the OR operation process. The OR operation process stores the inverted logic of the OR operation result of the data stored in latch circuits SDL and ADL on the bus LBUS and on nodes INV_S and INV_A. Note that the OR operation process reads the inverted logic of the data stored in latch circuit SDL and the inverted logic of the data stored in latch circuit ADL and performs an AND operation on the bus LBUS, so it can also be considered as performing a NAND operation on the data stored in latch circuits SDL and ADL respectively on the bus LBUS.

[0131] In step S35, the voltages of the control signals STI and ATI are set to the "L" level. This turns off transistors TR22 and TR32, electrically isolating the latch circuits SDL and ADL, as well as the bus LBUS.

[0132] In step S36, the voltages of the control signals SLL and ALI are set to the "L" level. This turns on transistors TR27 and TR38. That is, inverters IV21 and IV32 are driven. When the data stored in node INV_S changes from "1" to "0" (Figure 11(b)), transistor TR23 is in the "on" state, so the voltage VDDSA is applied to node LAT_S via transistors TR23 and TR27. Therefore, the data "1" is written to node LAT_S. When the data stored in node INV_A changes from "1" to "0" (Figure 11(c)), node LAT_A stores the data "0", so transistor TR35 is in the "on" state, and the voltage VDDSA is applied to node INV_A via transistors TR35 and TR38. Therefore, the data "1" is written to node LAT_A.

[0133] In step S37, the voltages of the control signals SLI and ALL are set to the "L" level. This turns on transistors TR28 and TR37. That is, inverters IV22 and IV31 are driven. As a result, the logic of node LAT_S and the logic of node INV_S, and the logic of node LAT_A and the logic of node INV_A become mutually exclusive. Latch circuit SDL stores the same data as the data stored by node LAT_S. Latch circuit ADL stores the same data as the data stored by node LAT_A.

[0134] The processing in steps S35 to S37 is called the DL return process. During the DL return process, the data stored in the latch circuit SDL is updated with the result of the OR operation, and the data stored in the latch circuit ADL is restored to the data it was initially stored with. It can also be considered that the latch circuit SDL stores the inverted result of the NAND operation stored in the bus LBUS.

[0135] After step S37, the calculation is completed. As shown in Figure 11, the third calculation process allows the data stored in latch circuit ADL to remain unchanged from its initial state (step S30), while the OR operation result of the data stored in latch circuits SDL and ADL can be newly stored in latch circuit SDL.

[0136] As described above, the third arithmetic operation is performed. In the examples shown in Figures 10 and 11, the same process is performed even when data stored in one of the latch circuits BDL, CDL, DDL, EDL, or FDL is referenced instead of the latch circuit SDL or ADL.

[0137] 3. Effects The calculation method according to this embodiment can reduce the processing time required to write data to the memory cell. This effect will be described in detail below.

[0138] According to this embodiment, in the first to third arithmetic processes, each latch circuit SDL, ADL, BDL, CDL, DDL, EDL, and FDL deactivates the inverter it contains. For example, in the first to third arithmetic processes, latch circuit SDL deactivates inverters IV21 and IV22. As a result, the voltage levels of nodes LAT_S and INV_S are stored in a floating state. Therefore, even if the voltage level of one of nodes LAT_S and INV_S changes due to the AND or OR operation in the first to third arithmetic processes, the voltage level of the other node can be referenced to write to the same voltage level as the initial state (DL return). Similarly, latch circuits ADL, BDL, CDL, DDL, EDL, and FDL can also perform DL return.

[0139] Therefore, in the first to third arithmetic processing, which involves referencing multiple data stored in one of the multiple latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL, the sense amplifier module 17 can simultaneously reference multiple latch circuits and perform calculations in a single operation.

[0140] Specifically, for example, when performing a first arithmetic operation that references data stored in multiple latch circuits, the number of times the bus LBUS is precharged is only once, regardless of the number of latch circuits being referenced. Similarly, the number of times data is exchanged between the bus LBUS and node SEN2 is also only once, regardless of the number of latch circuits being referenced. Therefore, compared to a configuration in which data is read from each latch circuit and sent to node SEN2 one by one to perform an AND operation, the number of times the bus LBUS is precharged and the number of times data is exchanged between the bus LBUS and node SEN2 can be reduced. Consequently, the processing time required for the AND operation can be shortened.

[0141] For example, when performing a second or third arithmetic operation that references data stored in multiple latch circuits, the number of times the bus LBUS is precharged is only once, regardless of the number of latch circuits being referenced. Similarly, the number of times data is exchanged between the bus LBUS and the latch circuit storing the calculation result is also only once, regardless of the number of latch circuits being referenced. Therefore, compared to a configuration in which data is read from each latch circuit and sent sequentially to the latch circuit storing the calculation result to perform an AND or OR operation, the number of times the bus LBUS is precharged and the number of times data is exchanged between the bus LBUS and the latch circuit storing the calculation result can be reduced. Consequently, the processing time required for AND and OR operations can be shortened.

[0142] Furthermore, since the bus LBUS is precharged only once during the first calculation process, the phenomenon of the voltage at node SEN2 rising during subsequent bus LBUS precharges does not occur. Therefore, the configuration of making the voltage of the control signal BLQ lower than other power supply voltages VCC to prevent the voltage at node SEN2 can be omitted. Consequently, the configuration of the sense amplifier module 17 can be simplified in the manufacturing process.

[0143] Furthermore, the sense amplifier module 17 in the semiconductor memory device 3 according to this embodiment does not share nodes that supply an "L" level voltage in each latch circuit SDL, ADL, BDL, CDL, DDL, EDL, and FDL. In addition, even within a single latch circuit, nodes that supply an "L" level voltage are not shared. Specifically, for example, the node to which the voltage VSS_S1 is applied in the latch circuit SDL is not connected to the node to which the voltage VSS_S2 is applied, the node to which the voltage VSS_A1 is applied, the node to which the voltage VSS_A2 is applied, etc. With this configuration, for example, when the charge of node LAT_S is discharged through the node to which the voltage VSS_S1 is applied, it is possible to suppress changes in the stored logic level due to the discharged charge flowing back to node INV_S, etc. Therefore, the reliability of the semiconductor memory device 3 is improved.

[0144] 4. Expansion In the above embodiment, we described arithmetic processing that references data stored in two of the multiple latch circuits included in the sense amplifier module 17, but this can be extended to arithmetic processing that references data stored in three or more latch circuits. Below, as an example, we will describe the first, second, and third arithmetic processing that reference the data stored in each of the three latch circuits SDL, ADL, and BDL.

[0145] The latch circuit BDL has the same configuration as the latch circuits SDL and ADL, as shown in Figure 5. Nodes LAT_B and INV_B correspond to nodes LAT_S and INV_S in the latch circuit SDL, and nodes LAT_A and INV_A in the latch circuit ADL, respectively. Control signals BTL, BTI, BLL, and BLI correspond to control signals STL, STI, SLL, and SLI in the latch circuit SDL, and control signals ATL, ATI, ALL, and ALI in the latch circuit ADL, respectively. Voltages VSS_B1 and VSS_B2 are, for example, the ground voltage VSS.

[0146] 4.1 First arithmetic operation The first arithmetic process, which performs an AND operation by referencing the data stored in each of the latch circuits SDL, ADL, and BDL, and outputs the calculation result to node SEN2, will be described. Figure 12 is a timing chart showing an example of the voltages of various signals during the first arithmetic process in the sense amplifier module of the semiconductor memory device according to the embodiment.

[0147] Step S40 in Figure 12 shows the initial state before the first arithmetic operation is performed. The latch circuits SDL, ADL, and BDL each store arbitrary data. Also, node SEN2 and bus LBUS are pre-charged to the "H" level. Precharging node SEN2 and bus LBUS is done, for example, by setting the control signals LPC and BLQ to the "H" level. After precharging, the control signals LPC and BLQ are set to the "L" level.

[0148] As shown in Figure 12, through the first calculation process, the voltages of the control signals STB and LSL are at the "L" level.

[0149] In step S41, the voltages of the control signals SLL and SLI are set to the "H" level. As a result, nodes LAT_S and INV_S enter a floating state, retaining their respective initial levels.

[0150] In step S42, the voltages of the control signals ALL and ALI are set to the "H" level. As a result, nodes LAT_A and INV_A enter a floating state, retaining their respective initial state data.

[0151] Step S43 is executed a predetermined time after step S41. In step S43, the voltage of the control signal STL is set to the "H" level. As a result, the data of node LAT_S is read to the bus LBUS. Note that step S43 may be executed at the same time as step S42.

[0152] In step S44, the voltages of the control signals BLL and BLI are set to the "H" level. As a result, nodes LAT_B and INV_B enter a floating state, while retaining their respective initial data.

[0153] Steps S41, S42, and S44 are executed with a certain time difference between them in order to stagger the execution timing of steps S43, S45, and S46 in order to suppress overshoot as described later.

[0154] Step S45 is executed a predetermined time after step S42. In step S45, the voltage of the control signal ATL is set to the "H" level. As a result, the data of node LAT_A is read to the bus LBUS. At this time, an AND operation is performed on the bus LBUS between the data stored by node LAT_S (i.e., stored by latch circuit SDL) and the data stored by node LAT_A (i.e., stored by latch circuit ADL). Note that step S45 may be executed at the same time as step S44.

[0155] Step S46 is executed a predetermined time after step S44. In step S46, the voltage of the control signal BTL is set to the "H" level. As a result, the data from node LAT_B is read to the bus LBUS. At this time, an AND operation is performed on the bus LBUS between the result of the AND operation performed in step S45 and the data stored by node LAT_B (i.e., stored by latch circuit BDL). As a result, the AND operation results of the data stored by each latch circuit SDL, ADL, and BDL are stored in the bus LBUS and in nodes LAT_S, LAT_A, and LAT_B.

[0156] Steps S43, S45, and S46 are executed with a certain time difference between them. This is to suppress the phenomenon of the bus LBUS potential rising rapidly and overshooting.

[0157] In step S47, the voltage of the control signal BLQ is set to the "H" level. This causes node SEN2 and bus LBUS to conduct, so node SEN2 stores data with the same logic as the data stored by bus LBUS. Note that step S47 may be executed at the same time as step S46.

[0158] In step S48, the voltage of the control signal BLQ is set to the "L" level. This electrically isolates node SEN2 from bus LBUS. Node SEN2 stores the result of the first arithmetic operation.

[0159] The processing in steps S41 to S48 is called the AND operation process. The AND operation process allows the AND operation result of the data stored in each of the latch circuits SDL, ADL, and BDL to be output to node SEN2.

[0160] In step S49, the voltages of the control signals STL, ATL, and BTL are set to the "L" level. This electrically isolates the latch circuits SDL, ADL, and BDL, as well as the bus LBUS. Step S49 may be performed at the same time as step S48.

[0161] In step S50, the voltages of the control signals SLL, ALL, and BLL are set to the "L" level. As a result, the initial state data is written to each node LAT_S, LAT_A, and LAT_B. Therefore, if the levels of each node LAT_S, LAT_A, and LAT_B have changed since before the calculation, they are restored to their initial state levels.

[0162] In step S51, the voltages of the control signals SLI, ALI, and BLI are set to the "L" level. This makes the logic of node LAT_S mutually exclusive with the logic of node INV_S, the logic of node LAT_A mutually exclusive with the logic of node INV_A, and the logic of node LAT_B mutually exclusive with the logic of node INV_B. Latch circuit SDL stores the same data as the data stored by node LAT_S. Latch circuit ADL stores the same data as the data stored by node LAT_A. Latch circuit BDL stores the same data as the data stored by node LAT_B.

[0163] The process from steps S49 to S51 is called the DL recovery process. The DL recovery process restores the data stored in each latch circuit, SDL, ADL, and BDL, to the data they stored in their initial state.

[0164] After step S51, the calculation is completed. The first calculation process allows the data stored in each of the latch circuits SDL, ADL, and BDL to remain unchanged from their initial state (step S40), and the result of the AND operation of the data stored in each latch circuit SDL, ADL, and BDL to be output to node SEN2.

[0165] As described above, the first arithmetic operation is performed. In the example shown in Figure 12, the same process is performed when data stored in one of the latch circuits CDL, DDL, EDL, or FDL is referenced instead of the latch circuits SDL, ADL, or BDL. Furthermore, even when there are four or more latch circuits holding the referenced data, the same calculation results are obtained by sequentially connecting the latch circuits to the bus LBUS, performing an AND operation, and then individually performing DL return processing after separating them from the bus LBUS, and these results are stored in node SEN2. The latch circuits are also returned to their initial state.

[0166] 4.2 Second Calculation Process The second arithmetic process, which involves performing an AND operation by referencing the data stored in each of the latch circuits SDL, ADL, and BDL, and outputting the result to the latch circuit SDL, will be described. Figure 13 is a timing chart showing an example of the voltages of various signals during the second arithmetic process in the sense amplifier module of the semiconductor memory device according to the embodiment.

[0167] Step S60 in Figure 13 shows the initial state before the execution of the second arithmetic process. The latch circuits SDL, ADL, and BDL each store arbitrary data. The bus LBUS is precharged to the "H" level. Precharging of the bus LBUS is performed, for example, by setting the control signal LPC to the "H" level. After precharging, the control signal LPC is set to the "L" level.

[0168] Steps S61 to S66 are performed in the same way as steps S41 to S46 in the first arithmetic processing shown in Figure 12. As a result, the AND operation results of the data stored in each latch circuit SDL, ADL, and BDL are stored in the bus LBUS and nodes LAT_S, LAT_A, and LAT_B. The processing in steps S61 to S66 is called the AND operation processing.

[0169] In step S67, the voltages of the control signals STL, ATL, and BTL are set to the "L" level. This electrically isolates the latch circuits SDL, ADL, and BDL, as well as the bus LBUS, from each other.

[0170] In step S68, the voltages of the control signals SLI, ALL, and BLL are set to the "L" level. As a result, in the latch circuit SDL, data indicating the inverted logic of the data of node LAT_S (i.e., the result of the AND operation) is written to node INV_S. In the latch circuits ADL and BDL, the initial state data is written to LAT_A and LAT_B, respectively. Therefore, if the levels of each node LAT_A and LAT_B change from before the operation, they are restored to their initial state levels.

[0171] In step S69, the voltages of the control signals SLL, ALI, and BLI are set to the "L" level. This makes the logic of node LAT_S mutually exclusive with the logic of node INV_S, node LAT_A mutually exclusive with the logic of node INV_A, and node LAT_B mutually exclusive with the logic of node INV_B. Latch circuit SDL stores the same data as node LAT_S. Latch circuit ADL stores the same data as node LAT_A. Latch circuit BDL stores the same data as node LAT_B.

[0172] The process from steps S67 to S69 is called the DL recovery process. During the DL recovery process, the data stored in the latch circuit SDL is updated with the result of the AND operation, and the data stored in the latch circuits ADL and BDL are restored to the data they were initially stored in.

[0173] After step S69, the calculation is completed. Through the second calculation process, the data stored in latch circuits ADL and BDL remains unchanged from its initial state (step S60), and the AND operation result of the data stored in latch circuits SDL, ADL, and BDL is newly stored in latch circuit SDL.

[0174] As described above, the second arithmetic operation is performed. In the example shown in Figure 13, the same process is performed when data stored in one of the latch circuits CDL, DDL, EDL, or FDL is referenced instead of the latch circuits SDL, ADL, or BDL. Furthermore, even when there are four or more latch circuits that hold the data to be referenced, the same calculation result is obtained by sequentially connecting the latch circuits to the bus LBUS, performing an AND operation, and then individually performing a DL return operation after separating them from the bus LBUS, and the calculation result is stored in the target latch circuit. The referenced latch circuit is also returned to its initial state.

[0175] 4.3 Third Operation A third arithmetic process will be described, which performs an OR operation by referencing the data stored in each of the latch circuits SDL, ADL, and BDL, and outputs the calculation result to the latch circuit SDL. Figure 14 is a timing chart showing an example of the voltages of various signals during the third arithmetic process in the sense amplifier module of the semiconductor memory device according to the embodiment.

[0176] Step S70 in Figure 14 shows the initial state before the execution of the third arithmetic operation. The latch circuits SDL, ADL, and BDL each store arbitrary data. The bus LBUS is precharged to the "H" level. Precharging of the bus LBUS is performed, for example, by setting the control signal LPC to the "H" level. After precharging, the control signal LPC is set to the "L" level.

[0177] In step S71, the voltages of the control signals SLL and SLI are set to the "H" level. As a result, nodes LAT_S and INV_S enter a floating state, retaining their respective initial levels.

[0178] In step S72, the voltages of the control signals ALL and ALI are set to the "H" level. As a result, nodes LAT_A and INV_A enter a floating state, retaining their respective initial state data.

[0179] Step S73 is executed a predetermined time after step S71. In step S73, the voltage of the control signal STI is set to the "H" level. As a result, the data of node INV_S is read to the bus LBUS. Step S73 may be executed at the same time as step S72.

[0180] In step S74, the voltages of the control signals BLL and BLI are set to the "H" level. As a result, nodes LAT_B and INV_B enter a floating state, while retaining their respective initial data.

[0181] Steps S71, S72, and S74 are executed with a certain time difference between them in order to stagger the execution timing of steps S73, S75, and S76 in order to suppress overshoot as described later.

[0182] Step S75 is executed a predetermined time after step S72. In step S75, the voltage of the control signal ATI is set to the "H" level. As a result, the data of node INV_A is read to the bus LBUS. At this time, an AND operation is performed on the bus LBUS between the data stored by node INV_S (i.e., data with the inverted logic of the data stored by latch circuit SDL) and the data stored by node INV_A (i.e., data with the inverted logic of the data stored by latch circuit ADL). Note that step S75 may be executed at the same time as step S74.

[0183] Step S76 is executed a predetermined time after step S74. In step S76, the voltage of the control signal BTI is set to the "H" level. As a result, the data of node INV_B is read to the bus LBUS. At this time, on the bus LBUS, an AND operation is performed between the result of the AND operation performed in step S75 and the data stored in node INV_B (i.e., data with inverted logic of the data stored in latch circuit BDL).

[0184] Steps S73, S75, and S76 are executed with a certain time difference between them. This is to suppress the phenomenon of the bus LBUS potential rising rapidly and overshooting.

[0185] The processing in steps S71 to S76 is called the OR operation process. The OR operation process stores the inverted logic of the OR operation result of the data stored in latch circuits SDL, ADL, and BDL in the bus LBUS and node INV_S. Note that the OR operation process reads the inverted logic of the data stored in each of the latch circuits SDL, ADL, and BDL and performs an AND operation on the bus LBUS, so it can also be considered as performing a NAND operation on the data stored in each of the latch circuits SDL, ADL, and BDL on the bus LBUS.

[0186] In step S77, the voltages of the control signals STI, ATI, and BTI are set to the "L" level. This electrically isolates the latch circuits SDL, ADL, and BDL, as well as the bus LBUS, from each other.

[0187] In step S78, the voltages of the control signals SLL, ALI, and BLI are set to the "L" level. As a result, in the latch circuit SDL, data representing the inverted logic of the data of node INV_S (i.e., the result of the OR operation) is written to node LAT_S. Therefore, the result of the OR operation is stored in the latch circuit SDL. In the latch circuits ADL and BDL, the data of their respective initial states is written to INV_A and INV_B. Therefore, if the levels of each node INV_A and INV_B change from before the operation, they are restored to their initial state levels.

[0188] In step S79, the voltages of the control signals SLI, ALL, and BLL are set to the "L" level. This makes the logic of node LAT_S mutually exclusive with the logic of node INV_S, the logic of node LAT_A mutually exclusive with the logic of node INV_A, and the logic of node LAT_B mutually exclusive with the logic of node INV_B. Latch circuit SDL stores the same data as the data stored by node LAT_S. Latch circuit ADL stores the same data as the data stored by node LAT_A. Latch circuit BDL stores the same data as the data stored by node LAT_B.

[0189] The processing in steps S77 to S79 ​​is called the DL return process. During the DL return process, the data stored in the latch circuit SDL is updated with the result of the OR operation, and the data stored in the latch circuits ADL and BDL are restored to the data they were initially stored in. It can also be considered that the latch circuit SDL stores the inverted result of the NAND operation stored in the bus LBUS.

[0190] After step S79, the calculation is completed. Through the third calculation process, the data stored in latch circuits ADL and BDL remains unchanged from its initial state (step S30), and the OR operation result of the data stored in latch circuits SDL, ADL, and BDL is newly stored in latch circuit SDL.

[0191] As described above, the third arithmetic operation is performed. In the example shown in Figure 14, the same process is performed when data stored in any of the latch circuits CDL, DDL, EDL, and FDL is referenced instead of the latch circuits SDL, ADL, or BDL. Furthermore, even when there are four or more latch circuits that hold the data to be referenced, the same calculation result is obtained by sequentially connecting the latch circuits to the bus LBUS, performing an OR operation, and then individually performing DL return processing after being separated from the bus LBUS, and the calculation result is stored in the target latch circuit. The referenced latch circuit is also returned to its initial state.

[0192] 5. Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0193] 1…Memory system 2…Memory controller 3…Semiconductor memory 10…Memory cell array 11…Input / Output Circuits 12…Logic control circuits 13…Register 14… Sequencer 15…Driver module 16… Raw Decoder Module 17…Sense Amp Module ADL, BDL, CDL, DDL, EDL, FDL, SDL, XDL… Latch circuits BL...bit line BLK...block BSW...Bus switch C1, C2... Capacitive elements CU... Cell Unit DBUS, LBUS, XBUS... bus IV21, IV22, IV31, IV32… Inverters LBP…Precharge circuit NS...NAND string SAC...Sense Circuit SAU...Sense Amplifier Unit SGD, SGS... Selectable gate lines SL…Source line ST1, ST2…Selection transistor SU... String Unit TR1-TR16, TR21-28, TR31-38... Transistors WL...Word line

Claims

1. A calculation method using a first latch circuit, which includes a first inverter having an input terminal connected to a first node and an output terminal connected to a second node, and a second inverter having an input terminal connected to the second node and an output terminal connected to the first node, The first inverter and the second inverter are driven, the first data is stored in the first node, and the second data, which is the inverted data of the first data, is stored in the second node. The first inverter and the second inverter are de-driven, and the first data is read from the first node to the bus connected to the first latch circuit. The first inverter is put into a driving state, and the first data is written to the first node from which the first data was read, based on the second data. After writing the first data, the second inverter is put into a driving state, Equipped with a calculation method.

2. The calculation method further includes using a second latch circuit that includes a third inverter having an input terminal connected to a third node and an output terminal connected to a fourth node, and a fourth inverter having an input terminal connected to a fourth node and an output terminal connected to a third node, to drive the third inverter and the fourth inverter, causing the third node to store the third data and the fourth node to store the inverted data of the third data, the fourth data. The aforementioned reading further includes deactivating the third inverter and the fourth inverter and reading the third data from the third node to the bus. The calculation method according to claim 1.

3. The calculation method further comprises performing an AND operation using the first data and the third data read onto the bus, and outputting a fifth data which is the result of the AND operation. The calculation method according to claim 2.

4. The output includes outputting the fifth data to a sense circuit connected to the bus. The calculation method according to claim 3.

5. The aforementioned writing further includes driving the third inverter and writing the third data to the third node from which the third data was read, based on the fourth data. The act of putting the inverter into the drive state further includes putting the fourth inverter into the drive state after writing the third data. The calculation method according to claim 2.

6. The output includes outputting the fifth data to the third node. The calculation method according to claim 3.

7. The aforementioned writing further includes outputting the fifth data to the third node, then driving the fourth inverter, and writing the sixth data, which is the inverted data of the fifth data, to the fourth node. The act of putting the device into the drive state further includes putting the third inverter into the drive state after writing the sixth data. The calculation method according to claim 6.

8. Sequencer and, Sense circuit, A bus connected to the aforementioned sense circuit, A first latch circuit including a first inverter having an input terminal connected to a first node connected to the bus and an output terminal connected to a second node connected to the bus, and a second inverter having an input terminal connected to the second node and an output terminal connected to the first node, Equipped with, The aforementioned sequencer, The first inverter and the second inverter are driven, the first data is stored in the first node, and the second data, which is the inverted data of the first data, is stored in the second node. The first inverter and the second inverter are deactivated, and the first data is read from the first node to the bus. The first inverter is driven, and the first data is written to the first node from which the first data was read, based on the second data. After writing the first data, the second inverter is put into a driving state. Semiconductor memory device.

9. The system further includes a second latch circuit comprising: a third inverter having an input terminal connected to a third node connected to the bus and an output terminal connected to a fourth node connected to the bus; and a fourth inverter having an input terminal connected to the fourth node and an output terminal connected to the third node. The aforementioned sequencer, The third inverter and the fourth inverter are driven, the third data is stored in the third node, and the fourth data, which is the inverted data of the third data, is stored in the fourth node. The third inverter and the fourth inverter are deactivated, and the third data is read from the third node to the bus. The semiconductor memory device according to claim 8.

10. The sequencer performs an AND operation using the first data and the third data read out onto the bus, and outputs the fifth data, which is the result of the AND operation, to the sense circuit. The semiconductor memory device according to claim 9.

11. The aforementioned sequencer, The third inverter is driven, and the third data is written to the third node from which the third data was read, based on the fourth data. After writing the third data, the fourth inverter is put into a driving state. The semiconductor memory device according to claim 10.

12. The sequencer performs an AND operation using the first data and the third data read onto the bus, and outputs the fifth data, which is the result of the AND operation, to the third node. The semiconductor memory device according to claim 9.

13. The aforementioned sequencer, After the fifth data is output to the third node, the fourth inverter is driven, and the sixth data, which is the inverted data of the fifth data, is written to the fourth node. After writing the sixth data, the third inverter is put into a driving state. The semiconductor memory device according to claim 12.

14. The voltage of the fourth node is input to the sense circuit as a control signal. The semiconductor memory device according to claim 13.

15. The voltage at the third node is input to the sense circuit as a control signal. The semiconductor memory device according to claim 13.

16. The first latch circuit is, A first transistor having a first terminal connected to the first node and a second terminal connected to the bus, A second transistor having a first end connected to the second node and a second end connected to the bus, A third transistor and a fourth transistor, each having a first end connected to the first node, a second end connected to the second node, and a gate end connected to the second node, A fifth transistor and a sixth transistor, each having a first end connected to the second node, a second end connected to the first node, and a gate end connected to the first node, A seventh transistor having a first terminal connected to the second terminal of the third transistor, An eighth transistor having a first terminal connected to the second terminal of the fifth transistor, Equipped with, The fifth and sixth transistors function as the first inverter. The third and fourth transistors function as the second inverter. The first transistor controls the connection between the first node and the bus. The second transistor controls the connection between the second node and the bus. The seventh transistor controls the drive of the second inverter. The eighth transistor controls the drive of the first inverter. The semiconductor memory device according to claim 8.

17. The second terminal of the fourth transistor and the second terminal of the sixth transistor are electrically isolated from each other. The semiconductor memory device according to claim 16.

18. The second latch circuit described above is: A ninth transistor having a first terminal connected to the third node and a second terminal connected to the bus, A tenth transistor having a first end connected to the fourth node and a second end connected to the bus, An eleventh transistor and a twelfth transistor having a first end connected to the third node, a second end connected to the fourth node, and a gate end connected to the fourth node, A thirteenth transistor and a fourteenth transistor, each having a first end connected to the fourth node, a second end connected to the third node, and a gate end connected to the third node, A 15th transistor having a first terminal connected to the second terminal of the 11th transistor, A 16th transistor having a first terminal connected to the second terminal of the 13th transistor, Equipped with, The 13th and 14th transistors function as the 3rd inverter, The 11th and 12th transistors function as the 4th inverter, The ninth transistor controls the connection between the third node and the bus. The tenth transistor controls the connection between the fourth node and the bus. The 15th transistor controls the drive of the 4th inverter. The sixteenth transistor controls the drive of the third inverter. The semiconductor memory device according to claim 9.

19. The first latch circuit is, A third transistor and a fourth transistor, each having a first end connected to the first node, a second end connected to the second node, and a gate end connected to the second node, A fifth transistor and a sixth transistor, each having a first end connected to the second node, a second end connected to the first node, and a gate end connected to the first node, Equipped with, The fifth and sixth transistors function as the first inverter. The third and fourth transistors function as the second inverter. The second terminal of the fourth transistor, the second terminal of the sixth transistor, the second terminal of the twelfth transistor, and the second terminal of the fourteenth transistor are electrically isolated from each other. The semiconductor memory device according to claim 18.

Images