Memory system

Abstract

Suppresses performance degradation of the memory system. [Solution] In one embodiment, the memory system receives CXL from the host. TM The system is accessible in accordance with the (Compute Express Link) interface protocol and includes non-volatile memory, volatile memory, and a memory controller that manages the number of accesses to the non-volatile memory for each address and stores the number of accesses for each address as a histogram in the volatile memory. The memory controller includes an update unit that, when it receives a command from a host, skips reading from the volatile memory the number of accesses for the command address specified in the command from the number of accesses included in the histogram if predetermined conditions are met, and reads the number of accesses for the command address from the volatile memory if the predetermined conditions are not met, and modifies the number of accesses for the command address stored in the volatile memory.

Description

Technical Field

[0001] Embodiments relate to a memory system.

Background Art

[0002] A memory system including a NAND flash memory as a non-volatile memory and a memory controller for controlling the non-volatile memory is known. The memory system is connected to a host to constitute an information processing system. In order to suppress deterioration of latency, the memory controller notifies the host of the access frequency to the non-volatile memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress performance degradation of the memory system.

Means for Solving the Problems

[0005] The memory system of the embodiment receives CXL from the host TMThe system is accessible in accordance with the Compute Express Link interface protocol and includes non-volatile memory, volatile memory, and a memory controller that manages the number of accesses to the non-volatile memory for each address and stores the number of accesses for each address as a histogram in the volatile memory. The memory controller includes an update unit that, when it receives a command from the host, skips reading from the volatile memory the number of accesses for the command address specified in the command from the number of accesses included in the histogram, if a predetermined condition is met, and reads the number of accesses for the command address from the volatile memory from the number of accesses included in the histogram, and modifies the number of accesses for the command address stored in the volatile memory, if the predetermined condition is not met. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of an information processing system according to the first embodiment. [Figure 2] A block diagram showing an example of the relationship between the functional configuration of the memory controller according to the first embodiment and the various types of information stored in the volatile memory. [Figure 3] A block diagram showing an example of the relationship between the functional configuration of the TLM management unit of the memory controller according to the first embodiment and a histogram, which is one of the various types of information stored in the volatile memory. [Figure 4] A diagram showing an example of the data structure of an access map stored by a memory controller according to the first embodiment. [Figure 5] This figure shows an example of the data structure of hot detection information stored by the memory controller according to the first embodiment. [Figure 6] A diagram showing an example of the data structure of the hot list stored by the memory controller according to the first embodiment. [Figure 7] A diagram showing an example of the data structure of a histogram stored in a volatile memory according to the first embodiment. [Figure 8]A flowchart showing an example of the overall process from histogram generation to transmission in the memory system according to the first embodiment. [Figure 9] A flowchart showing an example of the access map update process in the memory system according to the first embodiment. [Figure 10] A flowchart showing an example of the hotlist update process in the memory system according to the first embodiment. [Figure 11] A diagram showing an example of the hotlist update process in the memory system according to the first embodiment. [Figure 12] A flowchart showing an example of histogram update processing in the memory system according to the first embodiment. [Figure 13] A flowchart showing an example of telemetry transmission processing in a memory system according to the first embodiment. [Figure 14] A block diagram showing an example of the relationship between the functional configuration of the TLM management unit of the memory controller according to the second embodiment and a histogram, which is one of the various types of information stored in the volatile memory. [Figure 15] A flowchart showing an example of telemetry transmission processing in a memory system according to the second embodiment. [Figure 16] A flowchart showing an example of histogram update processing in the memory system according to the second embodiment. [Figure 17] A flowchart showing an example of telemetry transmission processing in a memory system according to the first modified example. [Figure 18] A flowchart showing an example of a hotlist update process in a memory system according to the second modified example. [Figure 19] A flowchart showing an example of a hotlist update process in a memory system according to the third modified example. [Figure 20] A flowchart showing an example of histogram update processing in a memory system according to the fourth modified example. [Figure 21] A flowchart showing an example of histogram update processing in a memory system according to the fifth modified example.

Embodiment for Implementing the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are assigned common reference numerals. When distinguishing between a plurality of components having the same reference numeral, a suffix is attached to the common reference numeral for distinction. When it is not necessary to particularly distinguish between a plurality of components, only the common reference numeral is assigned to the plurality of components, and no suffix is attached.

[0008] 1. First Embodiment 1.1 Configuration 1.1.1 Information Processing System The configuration of the information processing system according to the first embodiment will be described.

[0009] FIG. 1 is a block diagram showing an example of the configuration of the information processing system according to the first embodiment. As shown in FIG. 1, the information processing system 1 includes a host 2, a memory system 3, and a plurality of memory systems 4. The host 2 is connected to each of the memory system 3 and the plurality of memory systems 4 via a host bus. Communication between the host 2 and each of the memory system 3 and the plurality of memory systems 4 complies with, for example, the CXL TM (Compute Express Link) interface protocol.

[0010] The host 2 is, for example, a server in a data center. The host 2 performs information processing using the data stored in the memory system 3 and the plurality of memory systems 4. The host 2 selectively uses a memory system for storing data, for example, according to the access frequency of the data.

[0011] The memory system 3 is, for example, a memory card such as an SD TM card, a storage device such as UFS (Universal Flash Storage), or SSD (Solid State Drive).

[0012] The multiple memory systems 4 are storage devices having different latencies than the memory system 3. The multiple memory systems 4 may include, for example, memory systems having longer latencies than the memory system 3. The multiple memory systems 4 may also include, for example, memory systems having shorter latencies than the memory system 3.

[0013] 1.1.2 Memory System Next, referring to Figure 1, the internal configuration of the memory system 3 will be described. As shown in Figure 1, the memory system 3 includes a memory controller 5, volatile memory 6, and non-volatile memory 7.

[0014] The memory controller 5 is composed of an integrated circuit, such as a System-on-a-Chip (SoC). The memory controller 5 may also be composed of multiple semiconductor chips. The memory controller 5 controls the non-volatile memory 7 based on requests from the host 2. The memory controller 5 uses the volatile memory 6 as an auxiliary when controlling the non-volatile memory 7.

[0015] Specifically, for example, the memory controller 5 executes a write operation to write data to the non-volatile memory 7 based on a write command from the host 2. The memory controller 5 also executes a read operation to read the data written by the write operation from the non-volatile memory 7 based on a read command from the host 2. The memory controller 5 then aggregates information regarding the number of accesses to the data (or the logical address associated with that data) as telemetry and notifies the host 2 in a timely manner.

[0016] The volatile memory 6 is, for example, DRAM (Dynamic Random Access Memory). Various information is stored in the volatile memory 6 when writing, reading, and telemetry transmission operations are performed. Details of the information stored in the volatile memory 6 will be described later.

[0017] The non-volatile memory 7 is, for example, a NAND flash memory. The non-volatile memory 7 includes multiple memory cells. Each of the multiple memory cells is an element that stores data non-volatilely. The multiple memory cells are associated with a physical address space.

[0018] 1.1.3 Memory Controller Next, we will describe the internal configuration of the memory controller 5.

[0019] (Hardware configuration) First, referring to Figure 1, the hardware configuration of the memory controller 5 will be described. As shown in Figure 1, the memory controller 5 includes a control circuit 11, a host interface circuit (host I / F) 12, a volatile memory interface circuit (VM I / F) 13, and a non-volatile memory interface circuit (NVM I / F) 14. The functions of the control circuit 11, host interface circuit 12, volatile memory interface circuit 13, and non-volatile memory interface circuit 14, which are described below, can be implemented by dedicated hardware, a processor that executes programs, or a combination thereof.

[0020] The control circuit 11 is a circuit that controls the entire memory controller 5. The control circuit 11 includes, for example, a processor such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory).

[0021] The host interface circuit 12 is hardware that manages communication between the memory controller 5 and the host 2. The host interface circuit 12 is connected to the host 2 via the host bus.

[0022] The volatile memory interface circuit 13 is hardware that manages communication between the memory controller 5 and the volatile memory 6. The volatile memory interface circuit 13 is connected to the volatile memory 6 via the memory bus BUS.

[0023] The non-volatile memory interface circuit 14 is hardware that manages communication between the memory controller 5 and the non-volatile memory 7. The non-volatile memory interface circuit 14 communicates with the non-volatile memory 7 in accordance with, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0024] (Functional Configuration) Next, the functional configuration of the memory controller 5 will be described with reference to Figure 2. Figure 2 is a block diagram showing an example of the relationship between the functional configuration of the memory controller according to the first embodiment and the various types of information stored in the volatile memory. As shown in Figure 2, the memory controller 5 functions as an RC (Read Cache) management unit 21, a WB (Write Buffer) management unit 22, a LUT (Look Up Table) management unit 23, and a TLM (Telemetry) management unit 24. The volatile memory 6 stores RC information 31, WB information 32, LUT 33, and a histogram 34.

[0025] The RC management unit 21 manages the storage location of frequently accessed data within the memory system 3. Specifically, the RC management unit 21 stores frequently accessed data as RC information 31 in a storage area with shorter latency than the non-volatile memory 7 (for example, the cache area within the volatile memory 6). Then, when the RC management unit 21 receives a read command for the frequently accessed data, it accesses the cache area instead of the non-volatile memory 7. This enables a response to the host 2 with shorter latency.

[0026] The WB management unit 22 manages the size of the data written to the non-volatile memory 7 in a single write operation. Specifically, the WB management unit 22 stores the data received from the host 2 as WB information 32 in a storage area (for example, a buffer area in the volatile memory 6) until the data reaches a predetermined size. Then, when the buffered data reaches the predetermined size, the WB management unit 22 writes the data to the non-volatile memory 7. This enables more efficient data writing.

[0027] The LUT management unit 23 associates logical addresses and physical addresses in the memory system 3. Specifically, the LUT management unit 23 associates the address (physical address) of the memory cell where the data is stored with the logical address of the data. The LUT management unit 23 generates an LUT 33 to manage the set of logical and physical addresses associated with the same data. The LUT management unit 23 stores the generated LUT 33 in the volatile memory 6.

[0028] The TLM management unit 24 manages the generation and transmission of telemetry information in the telemetry transmission process. Specifically, the TLM management unit 24 counts the number of accesses to the memory space for each measurement unit in response to a request from the host 2, or periodically. The TLM management unit 24 stores the number of accesses as a histogram 34 in the volatile memory 6.

[0029] Thus, while the RC management unit 21, WB management unit 22, and LUT management unit 23 manage processes and information essential for controlling the non-volatile memory 7, the TLM management unit 24 manages processes and information of relatively lower importance. On the other hand, the RC management unit 21, WB management unit 22, LUT management unit 23, and TLM management unit 24 access the volatile memory 6 via a common memory bus when managing the RC information 31, WB information 32, LUT 33, and histogram 34, respectively. For this reason, it is preferable that the number of accesses from the TLM management unit 24 to the volatile memory 6 per unit time is suppressed to the extent that access from the TLM management unit 24 to the volatile memory 6 does not interfere with access from the RC management unit 21, WB management unit 22, and LUT management unit 23 to the volatile memory 6.

[0030] In the following, the number of accesses per unit time from the memory controller 5 to the volatile memory 6 will also be referred to as "bandwidth." Furthermore, the ratio of the number of accesses per unit time from the TLM management unit 24 to the volatile memory 6 to the bandwidth will also be referred to as "bandwidth load."

[0031] Figure 3 is a block diagram showing an example of the relationship between the functional configuration of the TLM management unit of the memory controller according to the first embodiment and a histogram, which is one of the various types of information stored in the volatile memory. As shown in Figure 3, the TLM management unit 24 includes an access map generation unit 41, a hot address detection unit 42, and a histogram generation unit 43.

[0032] The access map generation unit 41 includes a mapping unit 51. The access map generation unit 41 also stores the access map 52.

[0033] The mapping unit 51 uses the logical address (hereinafter referred to as the command address, or simply the address) included in the command from the host 2 to determine whether or not there is access to the memory space. The mapping unit 51 stores the determination result in the access map 52. Here, the command refers to, for example, a read command, a write command, etc.

[0034] Figure 4 shows an example of the data structure of the access map stored by the memory controller according to the first embodiment. Figure 4 shows the correspondence between the memory space of the non-volatile memory 7 and each entry in the access map 52.

[0035] As shown in Figure 4, the memory space is divided into multiple sub-memory spaces, each associated with a measurement unit by command address. The access map 52 consists of multiple access detection bits, each associated with one of the multiple sub-memory spaces. The data size of one access detection bit is, for example, 1 bit. That is, if the measurement unit for a 512GB memory space is 4KB, the data size of the access map 52 is 512GB / 4KB = 128Mbit = 16MB. The access map 52 is stored, for example, in the SRAM (Static Random Access Memory) within the memory controller 5.

[0036] If the access detection bit is "0", it indicates that no access has occurred in the corresponding sub-memory space. If the access detection bit is "1", it indicates that an access has occurred in the corresponding sub-memory space.

[0037] In the example in Figure 4, access detection bits indicating "1", "0", and "1" are assigned to the sub-memory spaces corresponding to logical addresses "0x1000", "0x2000", and "0x3000", respectively. In this case, by referring to the access map 52, it can be seen that access has occurred to the sub-memory spaces corresponding to logical addresses "0x1000" and "0x3000", but not to the sub-memory space corresponding to logical address "0x2000".

[0038] Referring again to Figure 3, the functional configuration of the TLM management unit 24 will be explained.

[0039] The hot address detection unit 42 includes a compression unit 61 and a determination unit 62. The hot address detection unit 42 also stores hot detection information 63 and a hot list 64.

[0040] The compression unit 61 compresses the command address into a hash value. The compression unit 61 sends the generated hash value to the determination unit 62.

[0041] Figure 5 shows an example of the data structure of hot detection information stored by the memory controller according to the first embodiment. Figure 5 shows the correspondence between the memory space of the non-volatile memory 7 and each entry of the hot detection information 63.

[0042] As shown in Figure 5, the hot detection information 63 has multiple entries. Each of the multiple entries is associated with a set of sub-memory spaces, which are portions of multiple sub-memory spaces. Sets of sub-memory spaces associated with the same entry correspond to the same hash value. The hot detection information 63 is stored, for example, in the SRAM within the memory controller 5.

[0043] Each entry constituting the hot detection information 63 consists, for example, of a pair of an address and a probability count value. The address storage area stores a logical address that indicates one of the sets of sub-memory spaces that serve as the source of the hash value corresponding to that entry. In the example in Figure 5, the logical address "0x30000" is stored in the entry corresponding to the set of sub-memory spaces that include the logical addresses "0x00000", "0x10000", "0x20000", "0x30000", ... and "0xF0000".

[0044] The probability count value is used as an indicator of the frequency of access to the corresponding logical address. The probability count value increases probabilistically when an access to the corresponding logical address occurs. In other words, a higher probability count value indicates a higher frequency of access to the corresponding logical address.

[0045] Referring again to Figure 3, the functional configuration of the TLM management unit 24 will be explained.

[0046] The determination unit 62 refers to the hot detection information 63 and reads a pair of a logical address and a probability count value from the entry corresponding to the hash value. The determination unit 62 determines whether the command address matches the logical address read from the hot detection information 63. If the command address matches the logical address read from the hot detection information 63, the determination unit 62 probabilistically determines whether to increment the probability count value corresponding to the logical address. If the probabilistic determination process determines that the probability count value should be incremented, the determination unit 62 increments the probability count value and then writes it back to the hot detection information 63.

[0047] Here, "making a probabilistic determination of whether or not to increment the probability count value" means that the determination unit 62 determines, for example, the probability of incrementing the probability count value according to the magnitude of the probability count value, and then determines whether or not to increment the probability count value based on the determined probability. For example, the probability of incrementing the probability count value is set to decrease as the probability count value increases.

[0048] If the command address and the logical address read from the hot detection information 63 are different, the determination unit 62 probabilistically determines whether or not to replace (change) the logical address stored in the hot detection information 63 with the command address. Here, "probabilistically determining whether or not to replace the logical address with the command address" means that the determination unit 62 determines the probability of replacing the logical address with the command address according to the magnitude of the probability count value, and then determines whether or not to replace the logical address with the command address based on the determined probability. For example, the probability of performing the replacement is set to decrease as the probability count value increases. If the probabilistic determination process determines that the logical address stored in the hot detection information 63 should be replaced with the command address, the determination unit 62 changes (overwrites) the logical address stored in the hot detection information 63 with the command address and changes (overwrites) the corresponding probability count value to "1". If it determines that the logical address stored in the hot detection information 63 should not be replaced with the command address, the determination unit 62 maintains the information stored in the hot detection information 63.

[0049] Furthermore, the determination unit 62 determines whether the probability count value is equal to or greater than a threshold. If the probability count value is equal to or greater than the threshold, the determination unit 62 stores the corresponding logical address in the hot list 64. If the probability count value is less than the threshold, the determination unit 62 does not change the information stored in the hot list 64.

[0050] Figure 6 shows an example of the data structure of the hot list stored by the memory controller according to the first embodiment.

[0051] As shown in Figure 6, the hot list 64 has multiple entries. Each of the multiple entries stores a logical address. In the example in Figure 6, the probability count value corresponding to the logical address "0x30000" becomes greater than or equal to a threshold. In such a case, the determination unit 62 stores the logical address "0x30000" in the hot list 64. The hot list 64 is stored, for example, in the SRAM of the memory controller 5.

[0052] Referring again to Figure 3, the functional configuration of the TLM management unit 24 will be explained.

[0053] The histogram generation unit 43 includes a filter unit 71 and an update unit 72.

[0054] The filter unit 71 filters command addresses using logical addresses stored in the hot list 64. Specifically, the filter unit 71 refers to the hot list 64 and determines whether a logical address identical to the command address is stored in the hot list 64. If a logical address identical to the command address is stored in the hot list 64, the filter unit 71 stops sending the command address to the update unit 72. If a logical address identical to the command address is not stored in the hot list 64, the filter unit 71 sends the command address to the update unit 72.

[0055] When the update unit 72 receives a command address from the filter unit 71, it refers to the histogram 34 in the volatile memory 6 and reads the number of accesses corresponding to that command address. The update unit 72 counts up the read number of accesses and then writes the number of accesses after the count-up back to the histogram 34.

[0056] Figure 7 shows an example of the data structure of a histogram stored in the volatile memory according to the first embodiment. Figure 7 shows the correspondence between the memory space of the non-volatile memory 7 and each entry in the histogram 34.

[0057] As shown in Figure 7, the histogram 34 is composed of multiple access counts, each associated with a different sub-memory space. The data size of one access count is, for example, 8 bits. That is, if the measurement unit for a 512 GB memory space is 4 KB, the data size of the histogram 34 is 512 GB / 4 KB × 8 bits = 128 MB.

[0058] In the example in Figure 7, the sub-memory spaces corresponding to logical addresses "0x1000", "0x2000", and "0x3000" are assigned access counts of "2", "0", and "10", respectively. In this case, by referring to histogram 34, it can be seen that the sub-memory spaces corresponding to logical addresses "0x1000" and "0x3000" have been accessed 2 times and 10 times, respectively, but the sub-memory space corresponding to logical address "0x2000" has not been accessed.

[0059] 1.2 Operation Next, the operation of the memory system according to the first embodiment will be described.

[0060] 1.2.1 Overall Processing Figure 8 is a flowchart showing an example of the overall process from the generation of telemetry information to its transmission to the host 2 in the memory system according to the first embodiment.

[0061] As shown in Figure 8, upon receiving a telemetry transmission request from the host, or periodically (at the start), the memory controller 5 initializes the access map 52, hot detection information 63, hot list 64, and histogram 34 (S1).

[0062] After processing S1, the memory controller 5 waits until it receives a command address or until the count period of the histogram 34 ends (S2).

[0063] After processing in S2, the memory controller 5 determines whether or not it has received a command address (S3).

[0064] If a command address is received (S3; yes), the access map generation unit 41 executes the access map update process (S4). The access map update process updates the access map 52. Details of the access map update process will be described later.

[0065] Next, the hot address detection unit 42 executes a hot list update process (S5). The hot list update process updates the hot detection information 63 and the hot list 64. Details of the hot list update process will be described later.

[0066] Next, the histogram generation unit 43 executes a histogram update process (S6). The histogram update process updates the histogram 34. Details of the histogram update process will be described later.

[0067] After processing S6, the memory controller 5 determines whether the counting period for histogram 34 has ended (S7). If the counting period for histogram 34 has not ended after processing S6 (S7; no), the memory controller 5 waits until it receives a command address or until the counting period for histogram 34 has ended (S2). After processing S2, the subsequent processes S3 to S7 are executed until the counting period for histogram 34 has ended.

[0068] If the command address has not been received (i.e., processing in S2 has proceeded due to the end of the counting period) (S3; no), or if the counting period for histogram 34 has ended after processing in S6 (S7; yes), the memory controller 5 executes the telemetry transmission process (S8). The telemetry transmission process sends the number of accesses in histogram 34 to host 2.

[0069] Once the S8 process is complete, the entire process is finished (end).

[0070] Note that while Figure 8 illustrates the case where processes S4 to S6 are executed sequentially in that order, this is not the only case. For example, processes S4 to S6 may be executed in parallel in response to the reception of command addresses.

[0071] 1.2.2 Access Map Update Process Figure 9 is a flowchart showing an example of the access map update process in the memory system according to the first embodiment. The processes S11 to S12 shown in Figure 9 correspond to the process S4 in Figure 8.

[0072] As shown in Figure 9, upon receiving a command address (start), the mapping unit 51 reads the access detection bit corresponding to the command address from the access map 52 and determines whether the value of the access detection bit is "0" or not (S11).

[0073] If the value of the access detection bit is "0" (S11; yes), the mapping unit 51 sets the value of the access detection bit to "1" and writes it back to the access map 52 (S12).

[0074] If the value of the access detection bit is "1" (S11; no), or after processing in S12, the access map update process ends (end).

[0075] 1.2.3 Hotlist Update Process Figure 10 is a flowchart showing an example of the hot list update process in the memory system according to the first embodiment. The processes S21 to S29 shown in Figure 10 correspond to the process S5 in Figure 8.

[0076] As shown in Figure 10, upon receiving a command address (start), the compression unit 61 generates a hash value based on the command address (S21).

[0077] The determination unit 62 refers to the hot detection information 63 and identifies a set of logical address and probability count value corresponding to the hash value generated in the processing of S21 (S22).

[0078] The determination unit 62 determines whether an address collision has occurred between the command address and the logical address identified in the processing of S22 (S23). Here, an address collision means that the two logical addresses are different from each other.

[0079] If an address collision occurs (S23; yes), the determination unit 62 probabilistically determines whether or not to replace the logical address to be stored in the hot detection information 63, based on the magnitude of the probability count value identified in the S22 process (S24).

[0080] If it is determined that a replacement of the logical address to be stored in the hot detection information 63 should be performed (S24; yes), the determination unit 62 replaces the logical address identified in the process of S22 with the command address, sets the probability count value to "1", and writes it back to the hot detection information 63 (S25).

[0081] If no address collision occurs (S23; no), the determination unit 62 probabilistically determines whether or not to increment the probability count value based on the magnitude of the probability count value (S26).

[0082] If it is determined that the probability count value should be incremented (S26; yes), the determination unit 62 increments the probability count value identified in the process of S22 and writes it back to the hot detection information 63 (S27).

[0083] After processing in S27, the determination unit 62 determines whether the counted probability value is equal to or greater than the threshold (S28).

[0084] If the probability count value is greater than or equal to the threshold (S28; yes), the determination unit 62 registers the logical address identified in the process of S22 in the hot list 64 (S29).

[0085] If it is determined that the replacement of the logical address to be stored in the hot detection information 63 will not be performed (S24; no), if it is determined after processing S25 that the probability count value will not be incremented (S26; no), if the probability count value is less than the threshold (S28; no), or after processing S29, the hot list update process will terminate (terminate).

[0086] Figure 11 shows an example of the hot list update process in the memory system according to the first embodiment. In the example in Figure 11, the transitions of logical addresses and probability count values ​​stored in entries corresponding to sets of sub-memory space containing the logical addresses "0x00000", "0x10000", "0x20000", "0x30000", ... and "0xF0000" from the hot detection information 63 are shown.

[0087] In Figure 11, one example shows that in the probabilistic decision process, the probability of counting up and replacing is halved each time the probability count value increases from "0", "1", "2", "3", "4", etc., to 100%, 50%, 25%, 12%, 6%, etc.

[0088] As shown in Figure 11, first, upon receiving the command address "0x10000", the determination unit 62 stores the set of logical address "0x10000" and probability count value "1" in the hot detection information 63.

[0089] Next, when the determination unit 62 receives the command address "0x10000", which is the same as the logical address stored in the target entry, it determines whether or not to increment the probability count value. Here, since the probability count value is "1", the probability of determining to increment the count is 50%. In the example in Figure 11, the determination unit 62 determines not to increment the count and maintains the information stored in the target entry.

[0090] Next, when the determination unit 62 receives a command address "0x30000" that is different from the logical address stored in the target entry, it determines whether or not to perform a logical address replacement. Here, the probability count value is "1", so the probability of determining to perform the replacement is 50%. In the example in Figure 11, the determination unit 62 determines to perform the replacement, replaces the logical address stored in the target entry with the command address "0x30000", and sets the probability count value to "1".

[0091] Next, when the unit receives the command address "0x30000", which is the same as the logical address stored in the target entry, the determination unit 62 determines whether or not to increment the probability count value. Here, since the probability count value is "1", the probability of determining to increment the count is 50%. In the example in Figure 11, the determination unit 62 determines to increment the count and sets the probability count value to "2".

[0092] Next, when the determination unit 62 receives the command address "0x30000", which is the same as the logical address stored in the target entry, it determines whether or not to increment the probability count value. Here, since the probability count value is "2", the probability of determining to increment the count is 25%. In the example in Figure 11, the determination unit 62 determines not to increment the count and maintains the information stored in the target entry. This operation is repeated twice.

[0093] Next, when the unit receives the command address "0x30000", which is the same as the logical address stored in the target entry, the determination unit 62 determines whether or not to increment the probability count value. Here, since the probability count value is "2", the probability of determining to increment the count is 25%. In the example in Figure 11, the determination unit 62 determines to increment the count and sets the probability count value to "3".

[0094] Next, when the determination unit 62 receives the command address "0x30000", which is the same as the logical address stored in the target entry, it determines whether or not to increment the probability count value. Here, since the probability count value is "3", the probability of determining to increment the count is 12%. In the example in Figure 11, the determination unit 62 determines not to increment the count and maintains the information stored in the target entry.

[0095] Next, when the determination unit 62 receives a command address "0x50000" that is different from the logical address stored in the target entry, it determines whether or not to perform a logical address replacement. Here, since the probability count value is "3", the probability of determining to perform the replacement is 12%. In the example in Figure 11, the determination unit 62 determines not to perform the replacement and maintains the information stored in the target entry.

[0096] Next, when the determination unit 62 receives the command address "0x30000", which is the same as the logical address stored in the target entry, it determines whether or not to increment the probability count value. Here, since the probability count value is "3", the probability of determining to increment the count is 12%. In the example in Figure 11, the determination unit 62 determines not to increment the count and maintains the information stored in the target entry.

[0097] Next, when the unit receives the command address "0x30000", which is the same as the logical address stored in the target entry, the determination unit 62 determines whether or not to increment the probability count value. Here, since the probability count value is "3", the probability of determining to increment the count is 12%. In the example in Figure 11, the determination unit 62 determines to increment the count and sets the probability count value to "4".

[0098] Next, when the determination unit 62 receives the command address "0x30000", which is the same as the logical address stored in the target entry, it determines whether or not to increment the probability count value. Here, since the probability count value is "4", the probability of determining to increment the count is 6%. In the example in Figure 11, the determination unit 62 determines not to increment the count and maintains the information stored in the target entry.

[0099] Next, when the determination unit 62 receives a command address "0x40000" that is different from the logical address stored in the target entry, it determines whether or not to perform a logical address replacement. Here, since the probability count value is "4", the probability of determining to perform the replacement is 6%. In the example in Figure 11, the determination unit 62 determines not to perform the replacement and maintains the information stored in the target entry.

[0100] Next, when the determination unit 62 receives a command address "0x50000" that is different from the logical address stored in the target entry, it determines whether or not to perform a logical address replacement. Here, since the probability count value is "4", the probability of determining to perform the replacement is 6%. In the example in Figure 11, the determination unit 62 determines not to perform the replacement and maintains the information stored in the target entry.

[0101] Next, when the determination unit 62 receives the command address "0x30000", which is the same as the logical address stored in the target entry, it determines whether or not to increment the probability count value. Here, since the probability count value is "4", the probability of determining to increment the count is 6%. In the example in Figure 11, the determination unit 62 determines not to increment the count and maintains the information stored in the target entry.

[0102] As described above, when the probability count value is small, the information stored in the hot detection information 63 is relatively easy to replace and easy to increment. On the other hand, when the probability count value is large, the information stored in the hot detection information 63 is relatively difficult to replace and easy to increment. When the probability count value rises above a threshold, it is determined that access is occurring frequently and is registered in the hot list 64.

[0103] 1.2.4 Histogram update process Figure 12 is a flowchart showing an example of histogram update processing in the memory system according to the first embodiment. The processes S31 to S34 shown in Figure 12 correspond to the process S6 in Figure 8.

[0104] As shown in Figure 12, upon receiving a command address (start), the filter unit 71 refers to the hot list 64 and determines whether or not the command address is a hit (S31).

[0105] If the command address is not found (i.e., the command address does not exist in the hot list 64) (S31; no), the update unit 72 reads the number of accesses from the histogram 34 based on the command address (S32).

[0106] The update unit 72 increments the number of accesses read during the processing in S32 (S33).

[0107] The update unit 72 writes back the number of accesses that was counted up in the processing of S33 to the histogram 34 (S34).

[0108] If a command address is found (i.e., the command address exists in the hot list 64) (S31; yes), or after processing in S34, the histogram update process ends (end).

[0109] 1.2.5 Telemetry transmission process Figure 13 is a flowchart showing an example of telemetry transmission processing in the memory system according to the first embodiment. The processes S41 to S45 shown in Figure 13 correspond to the process S8 in Figure 8.

[0110] As shown in Figure 13, when the count period of the histogram 34 ends (start), the memory controller 5 selects a logical address from the memory space (S41).

[0111] The memory controller 5 refers to the access map 52 and determines whether the access detection bit corresponding to the logical address selected in the process of S41 is "1" (S42).

[0112] If the access detection bit is "1" (S42; yes), the memory controller 5 reads the number of accesses from the histogram 34 based on the logical address selected in the process of S41 (S43). The read number of accesses is temporarily stored as part of the telemetry sent to the host 2.

[0113] If the access detection bit is "0", (S42; no), or after processing S43, the memory controller 5 determines whether or not all logical addresses in the memory space have been selected (S44).

[0114] If there are unselected logical addresses (S44; no), the memory controller 5 selects an unselected logical address from the memory space (S41). Then, the subsequent processes S42 to S44 are executed. In this way, processes S41 to S44 are repeated until all logical addresses are selected.

[0115] If all logical addresses have been selected (S44; yes), the memory controller 5 sends the total number of accesses read in the S43 process to the host 2 as telemetry (S45).

[0116] Once processing S45 is complete, the telemetry transmission process ends (end).

[0117] 1.3 Effects of the First Embodiment According to the first embodiment, the memory controller 5 manages the number of accesses to the non-volatile memory 7 for each measurement unit obtained by dividing the logical address, and stores the number of accesses as a histogram 34 in the volatile memory 6. When managing the number of accesses, the update unit 72 included in the histogram generation unit 43 skips reading the number of accesses for the command address from the volatile memory 6 when it receives a command from the host 2 and the conditions are met. If the conditions are not met, the update unit 72 reads the number of accesses for the command address from the volatile memory 6 and changes the number of accesses stored in the histogram 34. Specifically, if the command address is not registered in the hot list 64, the update unit 72 reads the number of accesses corresponding to the command address from the histogram 34, counts up the read number of accesses, and writes the counted number back to the histogram 34. If the command address is registered in the hot list 64, the update unit 72 skips reading the number of accesses corresponding to the command address from the histogram 34, counting up the read number of accesses, and writing the counted number back to the histogram 34. This suppresses frequent updates of access counts to command addresses that are known to be "hot." As a result, the bandwidth load on volatile memory 6 can be reduced. Therefore, performance degradation caused by the memory system 3 managing telemetry can be suppressed.

[0118] Furthermore, the hot address detection unit 42 stores a set of a logical address and a probability count value, which are referenced by a hash value generated by compressing the logical address, as hot detection information 63. The determination unit 62 of the hot address detection unit 42 determines whether or not to register the logical address corresponding to the probability count value in the hot list 64, based on whether or not the probability count value is equal to or greater than a threshold. This reduces the amount of SRAM required for the hot detection information 63 compared to managing a probability count value for each logical address.

[0119] Furthermore, if the logical address stored in the hot detection information 63 corresponding to the hash value generated based on the command address is different from the command address, the determination unit 62 probabilistically determines whether or not to replace the address based on the probability count value. If the logical address stored in the hot detection information 63 corresponding to the hash value generated based on the command address matches the command address, the determination unit 62 probabilistically determines whether or not to increment the probability count value based on the probability count value. The probability of replacement and the probability of incrementing are set to decrease as the probability count value increases. As a result, logical addresses with a high access frequency are more likely to be stored in the hot detection information 63 with a higher probability count value. Therefore, logical addresses with a high access frequency are more likely to be registered in the hot list 64.

[0120] 2. Second Embodiment Next, a memory system according to the second embodiment will be described. The second embodiment differs from the first embodiment in that it generates a histogram 34 based on the access map 52. The following description will mainly focus on the configuration and operation that differ from the first embodiment. The configuration and operation that are equivalent to the first embodiment will be omitted as appropriate.

[0121] 2.1 Functional Configuration of the Memory Controller Figure 14 is a block diagram showing an example of the relationship between the functional configuration of the TLM management unit in the memory controller according to the second embodiment and a histogram, which is one of the various types of information stored in the volatile memory. Figure 14 corresponds to Figure 3 in the first embodiment. As shown in Figure 14, the TLM management unit 24 includes an access map generation unit 41 and a histogram generation unit 43, but does not necessarily include a hot address detection unit 42.

[0122] The access map generation unit 41 includes a mapping unit 51. The access map generation unit 41 also stores the access map 52.

[0123] The mapping unit 51 generates an access map 52 using the command address. The mapping unit 51 transmits the generated access map 52 to the histogram generation unit 43.

[0124] The histogram generation unit 43 includes a filter unit 71 and an update unit 72.

[0125] The filter unit 71 filters command addresses using access detection bits stored in the access map 52. Specifically, the filter unit 71 refers to the access map 52 and determines whether the access detection bit corresponding to a command address has transitioned from "0" to "1" due to that command address. If the access detection bit has transitioned from "0" to "1", the filter unit 71 sends the command address along with information to the update unit 72 indicating that it is not necessary to read the number of accesses from the histogram 34. If the access detection bit is already "1", the filter unit 71 sends the command address along with information to the update unit 72 indicating that it is necessary to read the number of accesses from the histogram 34.

[0126] When the filter unit 71 receives information indicating that it is necessary to read the number of accesses from the histogram 34 along with the command address, the update unit 72 refers to the histogram 34 in the volatile memory 6 and reads the number of accesses corresponding to the command address. The update unit 72 counts up the read number of accesses and then writes the counted-up number of accesses back to the histogram 34.

[0127] On the other hand, when the filter unit 71 receives information indicating that it is unnecessary to read the number of accesses from the histogram 34 along with the command address, the update unit 72 writes "1" to the number of accesses corresponding to the command address without reading the number of accesses from the histogram 34.

[0128] 2.2 Telemetry transmission process Figure 15 is a flowchart showing an example of the overall processing from the generation to the transmission of a histogram 34 in the memory system according to the second embodiment. Figure 15 corresponds to Figure 8 in the first embodiment.

[0129] As shown in Figure 15, when the memory controller 5 receives a telemetry transmission request from the host, or periodically (at the start of a period), it initializes the access map 52 (S51). At this time, the memory controller 5 does not initialize the histogram 34. Therefore, the histogram 34 stores the number of accesses that were counted up in the previous counting period.

[0130] After processing in S51, the memory controller 5 waits until it receives a command address or until the count period of the histogram 34 ends (S52).

[0131] After processing in S52, the memory controller 5 determines whether or not it has received a command address (S53).

[0132] If a command address is received (S53; yes), the access map generation unit 41 executes the access map update process (S54). The access map update process updates the access map 52. The access map update process in the second embodiment is equivalent to the access map update process in the first embodiment.

[0133] Next, the histogram generation unit 43 performs a histogram update process (S55). The histogram update process updates the histogram 34. Details of the histogram update process will be described later.

[0134] After processing in S55, the memory controller 5 determines whether the counting period for histogram 34 has ended (S56). If the counting period for histogram 34 has not ended after processing in S56 (S56; no), the memory controller 5 waits until it receives a command address or until the counting period for histogram 34 has ended (S52). After processing in S52, the subsequent processes S53 to S56 are executed until the counting period for histogram 34 has ended.

[0135] If the command address has not been received (i.e., processing in S52 has proceeded due to the end of the counting period) (S53; no), or if the counting period for histogram 34 has ended after processing in S55 (S56; yes), the memory controller 5 executes the telemetry transmission process (S57). The telemetry transmission process sends the number of accesses in histogram 34 to the host 2. The telemetry transmission process in the second embodiment is equivalent to the telemetry transmission process in the first embodiment.

[0136] Once the S57 process is complete, the entire process is finished (end).

[0137] 2.3 Histogram update process Figure 16 is a flowchart showing an example of histogram update processing in the memory system according to the second embodiment. The processes S61 to S65 shown in Figure 16 correspond to the process S55 in Figure 15.

[0138] As shown in Figure 16, upon receiving a command address (start), the filter unit 71 refers to the access map 52 and determines whether the access detection bit corresponding to the command address has transitioned from "0" to "1" (S61).

[0139] If the access detection bit transitions from "0" to "1" (i.e., the first access to the command address in question has occurred during the counting period) (S61; yes), the update unit 72 writes "1" to the access count (S62). Note that the update unit 72 does not read the previous access count before writing "1" to the access count.

[0140] If the access detection bit is already "1" (i.e., this is not the first access to the command address during the counting period) (S61; no), the update unit 72 reads the number of accesses from the histogram 34 based on the command address (S63).

[0141] The update unit 72 counts up the number of accesses read in the process of S63 (S64).

[0142] The update unit 72 writes back the number of accesses that was counted up in the processing of S64 to the histogram 34 (S65).

[0143] After processing in S62 or S65, the histogram update process ends (end).

[0144] 2.4 Effects according to the second embodiment According to the second embodiment, the access map generation unit 41 stores access detection bits indicating whether or not there has been access to a logical address as an access map 52. The filter unit 71 of the histogram generation unit 43 determines, based on the access detection bits, whether or not the access to the logical address corresponding to the access detection bit is the first during the counting period. Specifically, the filter unit 71 determines that it is the first access if the access detection bit transitions from "0" to "1" before and after accessing the command address. The filter unit 71 determines that it is not the first access if the access detection bit is "1" both before and after accessing the command address. If it is determined that it is not the first access, the update unit 72 reads the number of accesses corresponding to the command address from the histogram 34, counts up the read number of accesses, and writes the counted number of accesses back to the histogram 34. If it is determined that it is the first access, the update unit 72 skips reading the number of accesses corresponding to the command address from the histogram 34 and counting up the read number of accesses, and writes "1" to the number of accesses. This allows the histogram 34 to be updated without having to initialize it for each count period. Therefore, the load on the bandwidth of the volatile memory 6 can be reduced. Consequently, performance degradation caused by the memory system 3 managing telemetry can be suppressed.

[0145] 3. Variations Various modifications can be applied to the first and second embodiments described above. The following will mainly describe configurations and methods that differ from the first embodiment. Configurations and operations equivalent to those of the first embodiment will be omitted as appropriate.

[0146] 3.1 First Variation In the first embodiment described above, the case in which the updating of the hot list 64 and the updating of the histogram 34 are started at the same time was explained, but the invention is not limited to this. For example, the updating of the histogram 34 may be started after a predetermined time has elapsed since the updating of the hot list 64 was started.

[0147] Figure 17 is a flowchart illustrating an example of the overall processing from the generation to the transmission of a histogram 34 in the memory system according to the first modified example. Figure 17 corresponds to Figure 8 in the first embodiment.

[0148] As shown in Figure 17, upon receiving a telemetry transmission request from the host, or periodically (at the start of a period), the memory controller 5 initializes the access map 52, hot detection information 63, hot list 64, and histogram 34 (S71).

[0149] After processing in S71, the memory controller 5 waits until it receives a command address or until the count period of the histogram 34 ends (S72).

[0150] After processing in S72, the memory controller 5 determines whether or not it has received a command address (S73).

[0151] If a command address is received (S73; yes), the access map generation unit 41 executes the access map update process (S74). The access map update process updates the access map 52.

[0152] Next, the hot address detection unit 42 executes a hot list update process (S75). The hot list update process updates the hot detection information 63 and the hot list 64.

[0153] After processing in S75, the memory controller 5 determines whether a predetermined time has elapsed since the start of the count period (S76). The predetermined time can be set to any time shorter than the count period.

[0154] If a predetermined time has elapsed (S76; yes), the histogram generation unit 43 executes a histogram update process (S77). The histogram update process updates the histogram 34.

[0155] If the predetermined time has not elapsed (S76; no), or after processing S77, the memory controller 5 determines whether the counting period of the histogram 34 has ended (S78). If the counting period of the histogram 34 has not ended after processing S77 (S78; no), the memory controller 5 waits until it receives a command address or until the counting period of the histogram 34 has ended (S72). After processing S72, the subsequent processing S73 to S78 is executed until the counting period of the histogram 34 has ended.

[0156] If the command address has not been received (i.e., processing in S72 has proceeded due to the end of the counting period) (S73; no), or if the counting period for histogram 34 has ended after processing in S77 (S78; yes), the memory controller 5 executes the telemetry transmission process (S79). The telemetry transmission process sends the number of accesses in histogram 34 to host 2.

[0157] Once processing S79 is complete, the entire process is finished (end).

[0158] According to the first modification, the memory controller 5 starts the histogram update process after a predetermined period has elapsed since the start of the hot list update process. This prevents the histogram 34 from being updated before the command addresses determined to be frequently accessed are registered in the hot list 64. As a result, the load on the bandwidth of the volatile memory 6 can be further reduced.

[0159] 3.2 Second Variation In the first embodiment described above, the case in which logical addresses corresponding to probability count values ​​above a threshold are registered in the hot list 64 was explained, but it is not limited to this. For example, the determination unit 62 may further determine probabilistically whether or not to register the logical address in the hot list 64. Here, "determining probabilistically whether or not to register the logical address in the hot list 64" means that the determination unit 62 determines, for example, the probability of registering the logical address in the hot list 64 according to the magnitude of the probability count value, and then determines whether or not to register the logical address in the hot list 64 based on the determined probability.

[0160] Figure 18 is a flowchart illustrating an example of a hotlist update process in a memory system according to a second modified example. Figure 18 corresponds to Figure 10 in the first embodiment.

[0161] As shown in Figure 18, upon receiving a command address (start), the compression unit 61 generates a hash value based on the command address (S81).

[0162] The determination unit 62 refers to the hot detection information 63 and identifies a set of logical address and probability count value corresponding to the hash value generated in the processing of S81 (S82).

[0163] The determination unit 62 determines whether or not an address collision has occurred between the command address and the logical address identified in the processing of S82 (S83).

[0164] If an address collision occurs (S83; yes), the determination unit 62 probabilistically determines whether or not to replace the logical address to be stored in the hot detection information 63, based on the magnitude of the probability count value identified in the process of S82 (S84).

[0165] If it is determined that a replacement of the logical address to be stored in the hot detection information 63 should be performed (S84; yes), the determination unit 62 replaces the logical address identified in the process of S82 with the command address, sets the probability count value to "1", and writes it back to the hot detection information 63 (S85).

[0166] If no address collision occurs (S83; no), the determination unit 62 probabilistically determines whether or not to increment the probability count value based on the magnitude of the probability count value (S86).

[0167] If it is determined that the probability count value should be incremented (S86; yes), the determination unit 62 increments the probability count value identified in the process of S82 and writes it back to the hot detection information 63 (S87).

[0168] If it is determined that the replacement of the logical address to be stored in the hot detection information 63 is not performed (S84; no), then after processing S85 or S87, the determination unit 62 probabilistically determines whether or not to register the logical address read in processing S82 in the hot list 64 (S88).

[0169] If it is determined that the logical address should be registered in the hot list 64 (S88; yes), the determination unit 62 registers the logical address identified in the process of S82 in the hot list 64 (S89).

[0170] If it is determined that the logical address should not be registered in the hot list 64 (S88; no), or after processing S89, the hot list update process ends (end).

[0171] According to the second modification, the larger the probability count value, the higher the probability of being registered in the hot list 64. This allows for a more probabilistic determination of whether a logical address is registered in the hot list 64.

[0172] 3.3 Third Modified Example In the first embodiment described above, the case in which logical addresses corresponding to probability count values ​​above a threshold are registered in the hotlist 64 was explained, but it is not limited to this. For example, multiple hotlists 64 may be generated for each probability count or for each group of probability counts.

[0173] Figure 19 is a flowchart illustrating an example of a hotlist update process in a memory system according to the third modified example. Figure 19 corresponds to Figure 10 in the first embodiment.

[0174] As shown in Figure 19, upon receiving a command address (start), the compression unit 61 generates a hash value based on the command address (S91).

[0175] The determination unit 62 refers to the hot detection information 63 and reads out the set of logical address and probability count value corresponding to the hash value generated in the processing of S91 (S92).

[0176] The determination unit 62 determines whether or not an address collision has occurred between the command address and the logical address read in the processing of S92 (S93).

[0177] If an address collision occurs (S93; yes), the determination unit 62 probabilistically determines whether or not to replace the logical address to be stored in the hot detection information 63, based on the magnitude of the probability count value read in the process of S92 (S94).

[0178] If it is determined that a replacement of the logical address to be stored in the hot detection information 63 should be performed (S94; yes), the determination unit 62 replaces the logical address read in the process of S92 with the command address, sets the probability count value to "1", and writes it back to the hot detection information 63 (S95).

[0179] If no address collision occurs (S93; no), the determination unit 62 probabilistically determines whether or not to increment the probability count value based on the magnitude of the probability count value (S96).

[0180] If it is determined that the probability count value should be incremented (S96; yes), the determination unit 62 increments the probability count value read in the process of S92 and writes it back to the hot detection information 63 (S97).

[0181] If it is determined that the replacement of the logical address to be stored in the hot detection information 63 is not performed (S94; no), after processing S95 or after processing S97, the determination unit 62 registers the logical address read in processing S92 in the hot list 64 corresponding to the probability count value (S98). For example, if the probability count value is incremented in processing S97, the entry is registered in the hot list 64 corresponding to the probability count value after the increment, and the entry is deleted from the hot list 64 corresponding to the probability count value before the increment.

[0182] After processing S98, the hotlist update process is completed (end).

[0183] According to the third modification, the hot address detection unit 42 can manage the hot list 64 for each probability count value. This allows for the management of logical addresses not only for logical addresses that are frequently accessed from host 2, but also for logical addresses with various access frequencies. Therefore, by sending the hot list 64 for each probability count value to host 2 as telemetry, more detailed information regarding access frequency can be provided to host 2.

[0184] 3.4 Fourth Variation In the first embodiment described above, the case in which the number of accesses corresponding to the logical addresses registered in the hot list 64 is not updated during the histogram update process was explained, but the invention is not limited to this case. For example, if the access frequency is low, the number of accesses corresponding to the logical addresses registered in the hot list 64 may be updated during the histogram update process.

[0185] Figure 20 is a flowchart showing an example of histogram update processing in a memory system according to the fourth modified example. Figure 20 corresponds to Figure 12 in the first embodiment.

[0186] As shown in Figure 20, upon receiving a command address (start), the filter unit 71 refers to the hot list 64 and determines whether or not the command address is a hit (S101).

[0187] If a command address is found (i.e., the command address exists in the hot list 64) (S101; yes), the update unit 72 determines whether the frequency of access to the non-volatile memory 7 from host 2 is below a threshold (S102). In determining the frequency of access, the update unit 72 pre-determines the number of times a command containing a command address is received from host 2 per unit time as the frequency of access to the non-volatile memory 7.

[0188] If the command address is not found (i.e., the command address does not exist in the hot list 64) (S101; no), or if the access frequency is below the threshold (S102; yes), the update unit 72 reads the number of accesses from the histogram 34 based on the command address (S103).

[0189] The update unit 72 increments the number of accesses read in the process of S103 (S104).

[0190] The update unit 72 writes back the number of accesses that was counted up in the processing of S104 to the histogram 34 (S105).

[0191] If the access frequency exceeds the threshold (S102; no), or after processing in S105, the histogram update process ends (end).

[0192] According to the fourth modification, the memory controller 5 performs a histogram update process regardless of whether the command address is registered in the hot list 64, if the frequency of access to the non-volatile memory 7 from the host 2 is below a threshold. This makes it possible to generate a histogram 34 that more accurately reflects the number of accesses to frequently accessed logical addresses. Therefore, more detailed telemetry can be provided to the host 2 without increasing the bandwidth load on the volatile memory 6.

[0193] 3.5 Fifth Variation In the first embodiment described above, the hot list 64 is updated in the histogram update process based on the probability count value stored in the hot detection information 63, but it is not limited to this. For example, the hot list 64 may also be updated based on the number of accesses stored in the histogram 34.

[0194] Figure 21 is a flowchart showing an example of histogram update processing in a memory system according to the fifth modified example. Figure 21 corresponds to Figure 12 in the first embodiment.

[0195] As shown in Figure 21, upon receiving a command address (start), the filter unit 71 refers to the hot list 64 and determines whether or not the command address is a match (S111).

[0196] If the command address is not found (i.e., the command address does not exist in the hot list 64) (S111; no), the update unit 72 reads the number of accesses from the histogram 34 based on the command address (S112).

[0197] The update unit 72 counts up the number of accesses read in the process of S112 (S113).

[0198] The update unit 72 writes back the number of accesses that was counted up in the process of S113 to the histogram 34 (S114).

[0199] After processing in S114, the update unit 72 determines whether the number of accesses counted up in processing S113 is equal to or greater than the threshold (S115).

[0200] If the number of accesses after the count-up is greater than or equal to the threshold (S115; yes), the update unit 72 registers the command address in the hot list 64 (S116).

[0201] If a command address is found (i.e., the command address exists in the hot list 64) (S111; yes), or after processing S116, the histogram update process ends (end).

[0202] According to the fifth modification, the update unit 72 registers logical addresses in the histogram 34 whose access count is above a threshold in the hot list 64. This makes it possible to efficiently register logical addresses that are accessed relatively frequently but are not registered in the hot list 64 due to the influence of the probabilistic judgment process. As a result, the load on the bandwidth of the volatile memory 6 can be further reduced.

[0203] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0204] 1… Information processing system 2… Host 3…Memory System 4…Multiple memory systems 5…Memory controller 6. Volatile memory 7…Non-volatile memory 11…Control circuits 12…Host interface circuit 13…Volatile memory interface circuit 14…Non-volatile memory interface circuit 21…RC Management Department 22...WB Management Department 23…LUT management department 24…TLM Management Department 31…RC information 32...WB information 33…LUT 34... Histogram 41... Access map generation unit 42...Hot address detection unit 43...Histogram generation section 51…Mapping section 52…Access Map 61... Compression section 62...Judgment section 63…Hot detection information 64…Hotlist 71...Filter section 72…Update section

Claims

1. Host and CXL TM Accessible in accordance with the (Compute Express Link) interface protocol, Non-volatile memory and Volatile memory and A memory controller manages the number of accesses to the non-volatile memory for each address and stores the number of accesses for each address as a histogram in the volatile memory. Equipped with, The aforementioned memory controller When receiving a command from the aforementioned host, If the predetermined conditions are met, the number of accesses included in the histogram that correspond to the command address specified by the command will be skipped from the volatile memory. If the predetermined conditions are not met, the update unit reads the number of accesses for the command address from the number of accesses included in the histogram from the volatile memory and modifies the number of accesses for the command address stored in the volatile memory. including, Memory system.

2. The aforementioned memory controller A first storage unit that stores a set of address and count value referenced by a hash value generated by compressing the address, This also includes, The memory system according to claim 1.

3. The aforementioned memory controller Referencing the set, the first address is identified from the first storage unit based on the first hash value generated by compressing the command address, and the first count value corresponding to the identified first address is identified. Based on the first count value, it is determined whether the command address satisfies the predetermined conditions. Further including a determination unit, The memory system according to claim 2.

4. The determination unit, If the first address is different from the command address, the pair of the first address and the first count value is probabilistically changed to the pair of the command address and the first initial value. If the first address matches the command address, the first count value is probabilistically incremented. After the probabilistic replacement or probabilistic count-up, it is determined whether the command address satisfies the predetermined conditions based on the first count value. It is configured in such a way. The memory system according to claim 3.

5. The first initial value is 1. The memory system according to claim 4.

6. The probability of the above change is lower the larger the first count value. The memory system according to claim 4.

7. The probability of the aforementioned count increasing is lower the larger the first count value is. The memory system according to claim 4.

8. The determination unit is configured to determine that the command address satisfies the predetermined conditions when the first count value is equal to or greater than the first threshold. The memory system according to claim 4.

9. The determination unit is configured to probabilistically determine whether the command address satisfies the predetermined conditions based on the first count value. The probability of making the above determination decreases as the first count value increases. The memory system according to claim 4.

10. The aforementioned update unit is, If the command address does not satisfy the predetermined conditions, read the number of accesses corresponding to the command address from the histogram, increment the read number of accesses, and write the incremented number of accesses back to the histogram. If the command address satisfies the predetermined conditions, the read operation, the count-up operation, and the write-back operation are skipped. It is configured in such a way. The memory system according to claim 4.

11. The update unit is configured to start making the change after a predetermined time has elapsed from the start of the determination. The memory system according to claim 10.

12. The aforementioned update unit is, If the command address satisfies the predetermined conditions and the access frequency to the non-volatile memory is less than the second threshold, read the number of accesses to the command address from the histogram, increment the read access count, and write the incremented access count back to the histogram. If the command address satisfies the predetermined conditions and the frequency of access to the non-volatile memory is equal to or greater than the second threshold, the read operation, the count-up operation, and the write operation are skipped. It is configured in such a way. The memory system according to claim 10.

13. The update unit identifies the number of times a command including the command address is received from the host per unit time as the access frequency to the non-volatile memory. The memory system according to claim 12.

14. The update unit determines, regardless of the determination made by the determination unit, that the command address satisfies the predetermined conditions if the counted access count is equal to or greater than the third threshold. The memory system according to claim 10.

15. The first memory unit is an SRAM (Static Random Access Memory). The memory system according to claim 2.

16. The aforementioned memory controller A second storage unit that stores bit information indicating whether or not an address has been accessed, A determination unit that determines whether the address corresponding to the bit information satisfies the predetermined conditions based on the bit information, This also includes, The memory system according to claim 1.

17. The determination unit, The second storage unit references the first bit information corresponding to the command address, If the first bit information transitions from a first value to a second value before and after accessing the command address, it is determined that the command address satisfies the predetermined conditions. If the first bit information is the second value both before and after accessing the command address, it is determined that the command address does not satisfy the predetermined condition. It is configured in such a way. The memory system according to claim 16.

18. The aforementioned update unit is, If the command address satisfies the predetermined conditions, the read operation is skipped, and the number of accesses to the specified command address stored in the volatile memory is changed to the second initial value. It is configured in such a way. The memory system according to claim 17.

19. The second initial value is 1. The memory system according to claim 18.

20. The second memory unit is SRAM (Static Random Access Memory). The memory system according to claim 16.

21. The aforementioned volatile memory is DRAM (Dynamic Random Access Memory). The memory system according to claim 1.

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