Memory system and control method

Abstract

To provide a high-performance memory system and a method for controlling the same. [Solution] The memory system comprises multiple memory cells and a controller. The controller obtains a dataset corresponding to the distribution of threshold voltages of the multiple memory cells by performing reads on the multiple memory cells using a reference read voltage. The controller selects one acquisition operation from several acquisition operations based on the dataset to obtain actual read voltages for reading data stored in the multiple memory cells. The multiple acquisition operations include a first acquisition operation that obtains actual read voltages from the dataset using a first model, which is a trained machine learning model, and a second acquisition operation that is different from the first acquisition operation. The controller obtains actual read voltages using the selected acquisition operation and performs reads on the multiple memory cells using the obtained actual read voltages.

Description

[Technical Field]

[0001] This embodiment relates to a memory system and a control method. [Background technology]

[0002] Memory systems equipped with semiconductor memory containing memory cell transistors are becoming widespread. In such memory systems, during sense operation, a predetermined voltage (referred to as the read level) is applied to the memory cell transistor, and it is determined whether the memory cell transistor is in an on or off state under the application of the read level. Based on the determination result, the data stored in the memory cell transistor is then determined. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 9069659 [Patent Document 2] U.S. Patent Application Publication No. 2023 / 317201 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment aims to provide a high-performance memory system and a method for controlling the same. [Means for solving the problem]

[0005] According to one embodiment, the memory system comprises a plurality of memory cells and a controller. The controller obtains a dataset corresponding to the distribution of threshold voltages of the plurality of memory cells by performing reads on the plurality of memory cells using a reference read voltage. The controller selects one acquisition operation from a plurality of acquisition operations that obtain actual read voltages for reading data stored in the plurality of memory cells, based on the dataset. The plurality of acquisition operations include a first acquisition operation that obtains actual read voltages from the dataset using a first model, which is a trained machine learning model, and a second acquisition operation that is different from the first acquisition operation. The controller obtains actual read voltages using the selected acquisition operation and performs reads on the plurality of memory cells using the obtained actual read voltages. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing an example configuration of a memory system according to the first embodiment. [Figure 2] A diagram showing an example of the configuration of a memory chip according to the first embodiment. [Figure 3] A diagram showing the circuit configuration of a block according to the first embodiment. [Figure 4] A diagram illustrating an example of data coding according to the first embodiment. [Figure 5] A figure showing an example of the threshold voltage distribution of a memory cell according to the first embodiment. [Figure 6] A diagram showing the threshold voltage distribution of memory cells belonging to either state "A" or state "B" according to the first embodiment. [Figure 7] A diagram showing an example of the configuration of the first estimator according to the first embodiment. [Figure 8] A figure showing an example of the frequency of occurrence of difference bit count groups included in each training data according to the first embodiment. [Figure 9] A diagram showing an example of the configuration of the second estimator according to the first embodiment. [Figure 10]A diagram illustrating an example of the second acquisition operation according to the first embodiment. [Figure 11] A flowchart illustrating an example of the operation of the memory system according to the first embodiment. [Figure 12] A diagram illustrating the method for generating the histogram input to the estimation matrix in Modification Example 1. [Figure 13] This figure shows the calculation for estimating the optimal read level using the estimation matrix applied to Modification Example 1. [Figure 14] A diagram illustrating the node values ​​of the first estimator according to the second embodiment. [Figure 15] A diagram showing the information stored according to the second embodiment. [Figure 16] A flowchart illustrating an example of the operation of the memory system according to the second embodiment. [Figure 17] A diagram showing the information stored in RAM according to the third embodiment. [Figure 18] A flowchart illustrating an example of the operation of the memory system according to the third embodiment. [Modes for carrying out the invention]

[0007] The memory system and control method according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (First Embodiment) Figure 1 shows an example configuration of a memory system according to the first embodiment. As shown in Figure 1, the memory system 1 is connectable to a host 300. The host 300 is, for example, a server, a personal computer, or a mobile information processing device. The memory system 1 functions as an external storage device for the host 300. The host 300 can issue commands to the memory system 1. Commands to the memory system 1 include read commands and write commands.

[0009] The memory system 1 comprises a controller 100 and a NAND flash memory 200. The NAND flash memory 200 includes one or more memory chips CP. One or more channels are connected to the controller 100, and the controller 100 and the one or more memory chips CP are interconnected via one or more channels.

[0010] Here, the memory system 1 includes one or more memory chips CP, namely memory chips CP0-0, CP0-1, CP0-2, CP0-3, CP1-0, CP1-1, CP1-2, and CP1-3, and one or more channels, namely channels ch0 and ch1. Memory chips CP0-0, CP0-1, CP0-2, and CP0-3 are connected to the controller 100 via channel ch0. Memory chips CP1-0, CP1-1, CP1-2, and CP1-3 are connected to the controller 100 via channel ch1. The number of memory chips CP in the memory system 1 is not limited to 8. The number of channels connected to the controller 100 is not limited to 2. Furthermore, the connection relationships between the controller 100 and one or more memory chips CP are not limited to the relationships described above.

[0011] Each memory chip CP is equipped with multiple memory cell transistors and can store data non-volatilely.

[0012] The controller 100 includes a host interface (I / F) circuit 101, a CPU (Central Processing Unit) 102, a memory interface (I / F) circuit 103, a RAM (Random Access Memory) 104, and a bus 105. The host interface circuit 101, CPU 102, memory interface circuit 103, and RAM 104 are electrically connected to the bus 105. The memory interface circuit 103 includes an ECC (Error-Correcting Code) circuit 106.

[0013] The controller 100 may be configured, for example, as a System-On-a-Chip (SoC). The controller 100 may be composed of multiple chips. The controller 100 may have an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit) instead of a CPU 102. In other words, the controller 100 may be composed of software, hardware, or a combination thereof. The RAM 104 may be located outside the controller 100.

[0014] The host interface circuit 101 is connected to the host 300 via a bus conforming to a predetermined standard and is responsible for communication between the controller 100 and the host 300.

[0015] The memory interface circuit 103 is connected to eight memory chips CP via two channels and is responsible for communication between the controller 100 and each memory chip CP.

[0016] The CPU 102 controls the operation of the controller 100.

[0017] RAM104 is used as a work area for CPU102. RAM104 is also used as a buffer area to temporarily store data sent to and received from the memory chip CP. RAM104 can be composed of, for example, DRAM (dynamic random access memory), SRAM (static random access memory), or a combination thereof. However, the type of memory that makes up RAM104 is not limited to these.

[0018] During the operation of the memory system 1, the RAM 104 stores management information 110, first estimator information 111, and second estimator information 112. The management information 110, first estimator information 111, and second estimator information 112 will be described later.

[0019] The ECC circuit 106 uses error correction codes to detect errors and correct detected errors. Error detection and correction are simply referred to as error correction.

[0020] Figure 2 shows an example configuration of a memory chip CP according to the first embodiment. Note that memory chips CP0-0, CP0-1, CP0-2, CP0-3, CP1-0, CP1-1, CP1-2, and CP1-3 may have a common configuration.

[0021] In the example shown in Figure 2, the memory chip CP comprises a processing circuit 210 and a memory cell array 211.

[0022] The memory cell array 211 is divided into, for example, multiple planes (plane 0, plane 1). Each plane is a sub-array that can be accessed in parallel. Each plane comprises multiple blocks BLK (BLK0, BLK1, ...), each of which is a set of multiple non-volatile memory cell transistors. Each block BLK comprises multiple string units SU (SU0, SU1, ...), each of which is a set of memory cell transistors associated with word lines and bit lines. Each string unit SU comprises multiple NAND strings 214, in which memory cell transistors are connected in series. The number of NAND strings 214 in a string unit SU is arbitrary. The number of planes in the memory cell array 211 is not limited to 2. Also, the memory cell array 211 does not necessarily have to be divided.

[0023] The processing circuit 210 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generation circuit. The processing circuit 210 performs program operations, sense operations, and erase operations on the memory cell array 211 of each plane in response to instructions from the controller 100.

[0024] The program operation is the operation of writing data to the memory cell array 211. The sense operation is the operation of reading data from the memory cell array 211.

[0025] The series of operations by which the controller 100 writes data to the memory chip CP will be referred to as a write operation. The write operation consists of a data-in operation in which the controller 100 transfers data to the memory chip CP, and a program operation in which the processing circuit 210 writes the data received by the data-in operation to the memory cell array 211.

[0026] The series of operations by which the controller 100 reads data from the memory chip CP is referred to as a read operation. The read operation consists of a sense operation in which the processing circuit 210 reads data from the memory cell array 211, and a data out operation in which the controller 100 acquires the data read by the sense operation from the memory chip CP.

[0027] Figure 3 shows the circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. A block BLK has, for example, four string units SU0 to SU3. Each string unit SU contains multiple NAND strings 214.

[0028] Each NAND string 214 contains, for example, 64 memory cell transistors MT (MT0 to MT63) and selection transistors ST1 and ST2. Each memory cell transistor MT comprises a control gate and a charge storage layer, and stores data nonvolatilically. The 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The memory cell transistors MT may be of the MONOS type with an insulating film in the charge storage layer, or of the FG type with a conductive film in the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 214 is not limited to 64.

[0029] The gates of the selection transistor ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistor ST2 in each of the string units SU0 to SU3 are connected in common to, for example, the selection gate line SGS. The gates of the selection transistor ST2 in each of the string units SU0 to SU3 may be connected to different selection gate lines for each string unit SU. The control gates of the memory cell transistors MT0 to MT63 within the same block BLK are connected in common to the word lines WL0 to WL63, respectively.

[0030] The drains of the selection transistor ST1 of each NAND string 214 within the string unit SU are connected to different bit lines BL (BL0 to BL(L-1), where L is a natural number greater than or equal to 2). Furthermore, the bit lines BL connect one NAND string 214 within each string unit SU to multiple blocks BLK. Additionally, the sources of each selection transistor ST2 are connected to a common source line SL.

[0031] In other words, a string unit SU is a collection of NAND strings 214 connected to different bit lines BL and the same selected gate line SGD. A block BLK is a collection of multiple string units SU that share a common word line WL. And a memory cell array 211 is a collection of multiple block BLK that share a common bit line BL.

[0032] The program and sense operations performed by the processing circuit 210 on a single plane are carried out collectively on the memory cell transistors MT connected to a single word line WL in a single string unit SU. Hereafter, the group of memory cell transistors MT selected collectively during the program and sense operations on a single plane will be referred to as the "memory cell group MCG". The storage area of ​​a collection of 1-bit data written to or read from a single memory cell group MCG will be referred to as a "page".

[0033] The processing circuit 210 can perform erase operations on a single plane in units of block BLK.

[0034] Hereafter, the memory cell transistor MT will be simply referred to as the memory cell.

[0035] Each memory cell can be written to n (n≧1) bits of data. When n bits of data are written to each memory cell, the storage capacity per memory cell group (MCG) is equal to the size of n pages. The mode where n is 1 is called SLC (Single Level Cell) mode. The mode where n is 2 is called MLC (Multi Level Cell) mode. The mode where n is 3 is called TLC (Triple Level Cell) mode. The mode where n is 4 is called QLC (Quad Level Cell) mode.

[0036] The threshold voltage of each memory cell is controlled by the processing circuit 210 to stay within a certain range. The controllable range of the threshold voltage is divided into 2 to the power of n intervals, and a different n-bit value is assigned to each interval.

[0037] In this embodiment, a mode in which n is 2 or greater is adopted. Hereafter, an example of a mode in which n is 2 or greater is described in which the memory cell is used in TLC mode. Note that this embodiment is not limited to systems in which the memory cell is used in TLC mode, but is applicable to systems in which the memory cell is used in any mode in which n is 2 or greater.

[0038] Figure 4 is a diagram illustrating an example of data coding according to the first embodiment.

[0039] As mentioned above, in TLC mode, 3 bits of data are stored per memory cell. Each bit that makes up the 3 bits of data stored in the memory cell is referred to as the upper bit, middle bit, and lower bit, according to their order. Of the three pages that the memory cell group MCG has, the page where the upper bits are stored is referred to as the upper page, the page where the middle bits are stored is referred to as the middle page, and the page where the lower bits are stored is referred to as the lower page.

[0040] According to the TLC mode, the range of possible threshold voltages is divided into eight intervals. These eight intervals, in order from lowest to highest threshold voltage, are called the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G” state. The threshold voltage of each memory cell is controlled by the processing circuit 210 to belong to one of the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G state.” As a result, the distribution of threshold voltages plotted against the number of memory cells ideally has eight lobe-like shapes, each belonging to a different state and not overlapping with the others, as shown in the middle of Figure 4. Hereafter, the distribution for each state may simply be referred to as a lobe.

[0041] The eight states correspond to 3 bits of data. The upper table in Figure 4 shows an example of the correspondence between states and 3 bits of data, i.e., data coding. In this example, the “Er” state corresponds to “111”, the “A” state corresponds to “110”, the “B” state corresponds to “100”, the “C” state corresponds to “000”, the “D” state corresponds to “010”, the “E” state corresponds to “011”, the “F” state corresponds to “001”, and the “G” state corresponds to “101”. Note that when the 3 bits of data are written as “abc”, “a” is the upper bit, “b” is the middle bit, and “c” is the lower bit. In this way, each memory cell can store data corresponding to the state to which its threshold voltage belongs. Note that the correspondence between states and data shown in Figure 4 is an example of data coding. Data coding is not limited to the example in this figure.

[0042] The threshold voltage is reduced to the "Er" state by the erase operation. Alternatively, the threshold voltage can be maintained in the "Er" state or increased to one of the following states by the program operation: "A", "B", "C", "D", "E", "F", or "G".

[0043] From now on, a memory cell whose threshold voltage has been set to a certain state by program operation may be referred to as a memory cell belonging to that state.

[0044] A read level, which is a voltage used for data determination, is set between two adjacent states. For example, as illustrated in Figure 4, a read level VA is set between the "Er" state and the "A" state, a read level VB is set between the "A" state and the "B" state, a read level VC is set between the "B" state and the "C" state, a read level VD is set between the "C" state and the "D" state, a read level VE is set between the "D" state and the "E" state, a read level VF is set between the "E" state and the "F" state, and a read level VG is set between the "F" state and the "G" state.

[0045] In the sensing operation, the processing circuit 210 sequentially applies multiple types of read levels to the selected word line WL. The processing circuit 210 determines for each memory cell whether it is in a conductive state (in other words, on state) or a non-conductive state (in other words, off state) when each read level is applied to the selected word line WL. Then, the processing circuit 210 determines the data associated with the state to which the memory cell belongs by performing a logical operation using the determination result obtained for each applied read level. In other words, data is acquired based on a comparison between the threshold voltage of each memory cell and the read level.

[0046] Hereafter, the operation of applying a single type of read level VX (where X is one of A to G) to the selection word line WL to determine whether each memory cell is in the ON or OFF state will be referred to as X read or XR. The result of the X read will be referred to as the result XR.

[0047] The following explains the correspondence between the state to which the threshold voltage of a memory cell belongs and the data stored in the memory cell when the data coding shown in Figure 4 is adopted. If the memory cell belongs to any of the "Er", "E", "F", and "G" states, the lower bit of the data stored in that memory cell is "1". If the memory cell belongs to any of the "A", "B", "C", and "D" states, the lower bit of the data stored in that memory cell is "0". Therefore, in the sense operation for the lower page, the processing circuit 210 determines the data of the lower page by using two types of read levels, VA and VE. In other words, the processing circuit 210 determines the data of the lower page based on the results of the A read and E read.

[0048] If a memory cell belongs to one of the following states: “Er”, “A”, “D”, or “E”, the middle bit of the data stored in that memory cell is “1”. If a memory cell belongs to one of the following states: “B”, “C”, “F”, or “G”, the middle bit of the data stored in that memory cell is “0”. Therefore, in sensing operations for the middle page, the processing circuit 210 determines the data of the middle page by using three types of read levels: VB, VD, and VF. In other words, the processing circuit 210 determines the data of the middle page based on the results of B read, D read, and F read.

[0049] If a memory cell belongs to any of the "Er," "A," "B," or "G" states, the upper bit of the data stored in that memory cell is "1." If a memory cell belongs to any of the "C," "D," "E," or "F" states, the upper bit of the data stored in that memory cell is "0." Therefore, in sensing the upper bit, the processing circuit 210 uses two types of read levels, VC and VG, to determine the data on the upper page. In other words, the processing circuit 210 determines the data on the upper page based on the results of the C read and the G read.

[0050] Note that the sense operation for each page is not limited to the examples described above.

[0051] Figure 4 illustrates the case where a memory cell forms eight non-overlapping lobes. However, the threshold voltage of a memory cell changes due to various factors. Therefore, during sense operation, for example, as shown in Figure 5, a portion of one lobe may overlap with a portion of the other lobe.

[0052] If the threshold voltage of a memory cell belonging to a certain state changes beyond the read level corresponding to the boundary of that state, a memory cell that should be judged as off may be judged as on, or conversely, a memory cell that should be judged as on may be judged as off. As a result, the data read from that memory cell will be erroneous. The number of erroneous bits in the data read from a group of memory cells is denoted as FBC (Fail Bit Count).

[0053] Errors in data read from the NAND flash memory 200 are corrected by the ECC circuit 106. However, a large FBC increases the time required for error correction by the ECC circuit 106. In the worst case, it can lead to error correction failure, which degrades QoS (Quality of Service). Therefore, identifying the read level voltage value that best suppresses FBC and performing read operations using that read level voltage value is necessary to improve the performance of the memory system. However, as mentioned above, since the threshold voltage of the memory cell changes, the read level voltage value that best suppresses FBC may also change.

[0054] To accommodate changes in the threshold voltage of the memory cells, each memory chip CP is configured to allow the controller 100 to set the voltage value for each read level. The controller 100 is configured to estimate and obtain the voltage value of the read level that best suppresses FBC for each read level. The obtained read level voltage value is recorded in management information 110, and during a read operation, the controller 100 sets the memory chip CP so that the voltage value recorded in management information 110 is used as the read level.

[0055] Various methods can be designed for setting the read level voltage values ​​for each memory chip CP. For example, each memory chip CP may have preset initial values ​​for each type of read level, and the controller 100 may set a shift value from the initial value for the memory chip CP. In this case, the controller 100 sets the read level to a voltage value obtained by adding the shift value to the initial value. Alternatively, the controller 100 and each memory chip CP may be configured so that the controller 100 sets the net voltage value for each type of read level.

[0056] In the following description, it will be assumed that the controller 100 is configured such that the management information 110 records a shift value from the initial setting value for each type of read level, and the memory chip CP is set to the shift value.

[0057] Each read level may differ for each unit storage area. A unit storage area is, for example, one memory cell group MCG, two or more memory cell groups MCG, a block BLK, multiple block BLKs, or a memory chip CP. If the shift values ​​for each read level differ for each unit storage area, the management information 110 records the shift values ​​for each type of read level for each unit storage area.

[0058] In the following explanation, the voltage value of the read level Vi that best suppresses FBC (where i is A, B, C, D, E, F, or G) will be referred to as the optimal read level Vi. opt This is how it is written. If the types of read levels are not distinguished, the read level that best suppresses FBC is referred to as the optimal read level. Furthermore, the read levels VA to VG used for data determination are referred to as actual read levels to distinguish them from the reference read levels described later. Note that actual read levels are examples of actual read voltages, and reference read levels are examples of reference read voltages.

[0059] The trigger for obtaining the optimal read level is not limited to specific events. For example, the controller 100 may obtain the optimal read level in response to the result of error correction performed on the data obtained by the read operation. More specifically, if the controller 100 fails to correct the error on the data read by the read operation, it may obtain the optimal read level to be used for the read operation of the memory cell group MCG in which the data was stored. The controller 100 may then re-execute the read operation on the memory cell group MCG using the optimal read level obtained.

[0060] Furthermore, the voltage at which two adjacent lobes intersect can be considered to correspond to the optimal lead level. In other words, as shown in Figure 5, the voltage at the intersection of the lobe in the “Er” state and the lobe in the “A” state is the optimal lead level VA. optis such that the voltage at the intersection of the lobe of the "A" state and the lobe of the "B" state is the optimal read level VB opt is such that the voltage at the intersection of the lobe of the "B" state and the lobe of the "C" state is the optimal read level VC opt is such that the voltage at the intersection of the lobe of the "C" state and the lobe of the "D" state is the optimal read level VD opt is such that the voltage at the intersection of the lobe of the "D" state and the lobe of the "E" state is the optimal read level VE opt is such that the voltage at the intersection of the lobe of the "E" state and the lobe of the "F" state is the optimal read level VF opt is such that the voltage at the intersection of the lobe of the "F" state and the lobe of the "G" state is the optimal read level VG opt is as follows.

[0061] The controller 100 can execute a first acquisition operation for obtaining an optimal read level using a trained machine learning model, and a second acquisition operation different from the first acquisition operation. The controller 100 may be able to execute, as an operation for obtaining an optimal read level, a third acquisition operation different from both the first acquisition operation and the second acquisition operation in addition to the first acquisition operation and the second acquisition operation.

[0062] In the first acquisition operation, a first estimator (first estimator 11) is used as an example of a trained machine learning model. The first estimator 11 is a trained neural network model. The method for obtaining the optimal read level using the first estimator 11 will be described with reference to FIGS. 6 and 7. Note that the acquisition of the optimal read level is executed individually for each type of actual read level. In the following description, as an example, the processing when the optimal read level XB opt is the acquisition target will be described.

[0063] FIG. 6 is a diagram showing the distribution of the threshold voltages of memory cells belonging to either the "A" state or the "B" state according to the first embodiment. In this figure, VB ini is the initial setting value of the read level VB. The read level VB iniThe optimal read level is XB. opt It is deviating from the optimal read level XB. Therefore, the controller 100 is set to the optimal read level XB. opt Estimate the corresponding shift value y.

[0064] The controller 100 first performs a reference read operation. In the reference read operation, the controller 100 instructs the processing circuit 210 to read at the optimal read level (in this case, the optimal read level XB). opt One or more voltage values ​​within a voltage range that may include ) are sequentially applied to the word line WL to which a certain memory cell group MCG is connected, and the controller 100 determines whether each memory cell included in the memory cell group MCG is in an ON state or an OFF state. The controller 100 then counts the number of memory cells in the ON state among the memory cells included in the memory cell group MCG for each voltage value applied to the word line WL. Each of the multiple voltage values ​​applied to the word line WL in a reference read operation is referred to as the reference read level. A memory cell in an ON state will be referred to as an ON cell from now on. The count value of ON cells obtained by the reference read operation will be referred to as the bit count.

[0065] The number of memory cells included in the memory cell group MCG is known. Therefore, the controller 100 may be configured to count memory cells in the OFF state instead of counting ON cells.

[0066] The one or more reference read levels used in a reference read operation are determined, for example, by the following method. Here, we will explain using eight different reference read levels as an example.

[0067] If the read level for which the optimal read level is to be acquired is the read level corresponding to the boundary between the Mth state and the (M+1)th state from the low voltage side, the controller 100 will C MCG *V is the closest voltage value to M / 8 base This is considered the standard. Voltage value V base This is expressed as the DAC value. Note that CMCG This is the number of memory cells contained in one memory cell group MCG. Controller 100 controls the voltage value V base From there, eight voltage values ​​are assigned to the positive and negative sides at predetermined intervals (in this case, 4DAC as an example), i.e., V base -16, V base -12, V base -8, V base -4, V base , V base +4, V base +8 and V base Select +12 and use the eight selected voltage values ​​as the reference lead levels.

[0068] However, the method for determining the reference lead level is not limited to this. The reference lead level may be predetermined by the designer for each type of lead level. Alternatively, if the minimum value of the actual lead level is determined for each type of actual lead level, the controller 100 may determine a plurality of voltage values ​​as the reference lead level, selected in ascending order in predetermined increments based on the minimum value of the actual lead level.

[0069] In the example shown in Figure 6, the dashed line indicates the number of ON cells for a given reference read level. The controller 100 uses eight different reference read levels sequentially through a reference read operation, thereby obtaining bit counts at eight points indicated by circles on the dashed line shown in Figure 6. The controller 100 then calculates a group of difference bit counts x', which is the collection of the differences in bit counts obtained for each of two adjacent reference read levels. Since eight reference read levels are used here, the group of difference bit counts x' contains seven elements. The seven elements included in the group of difference bit counts x' are denoted as x0', x1', x2', x3', x4', x5', and x6', in the order of the voltages of pairs of adjacent reference read levels.

[0070] The difference bit count group x' can be considered as an example of a histogram of the number of memory cells in which the threshold voltage is included in each of the multiple voltage intervals separated by a reference read level of 1 or more. This histogram is an example of a dataset corresponding to the distribution of threshold voltages of memory cells.

[0071] The first estimator 11, when given the difference bit count group x', determines the optimal read level VB opt The estimated value of the initial setting (i.e., read level VB) ini It is configured to output the difference y based on ). The difference y is the shift value.

[0072] Figure 7 shows an example of the configuration of the first estimator 11 according to the first embodiment.

[0073] The first estimator 11 has a multi-layer perceptron (MLP) configuration with one or more hidden layers. The first estimator 11 may be a fully connected MLP or a sparsely connected MLP.

[0074] In the example shown in Figure 7, the first estimator 11 comprises an input layer, two hidden layers, and an output layer. The input layer has seven nodes, each receiving a different element from the difference bit count group x'. Each of the two hidden layers has four nodes. The output layer has one node that outputs a shift value y. Note that a node may also be called a neuron.

[0075] In the hidden and output layers, each node multiplies each input value from the node in the previous layer by a weight, applies an activation function to the sum of each weighted value plus a bias, and outputs the value obtained by applying the activation function.

[0076] The biases and weights are predetermined through training. In other words, the first estimator 11 is pre-trained to map the difference bit count group x' to the shift value y.

[0077] The configuration of the first estimator 11 described above is recorded in the first estimator information 111. The first estimator information 111 includes, for example, definitions of multiple nodes and definitions of the connection relationships between nodes. In the first estimator information 111, each node is associated with an activation function, a trained bias, and a trained weight.

[0078] The first estimator information 111 is pre-stored in a predetermined location, for example, in the NAND flash memory 200. When the memory system 1 is started up, the CPU 102 loads the first estimator information 111 into the RAM 104. Then, based on the first estimator information 111 loaded into the RAM 104, the CPU 102 performs calculations based on the weights, biases, and activation functions associated with each node, thereby realizing the calculation as the first estimator 11.

[0079] Generally, neural network models can accurately handle nonlinear relationships between explanatory and dependent variables. On the other hand, neural network models can produce unexpectedly large estimation errors when used with samples from different populations than the data used for training.

[0080] Therefore, in the first embodiment, the controller 100 calculates a confidence score c as an index representing the accuracy of the estimation based on whether the difference bit count group x' is close to the group of data used to train the first estimator 11. Based on the confidence score c, the controller 100 determines whether or not to adopt the shift value y obtained by the first acquisition operation, that is, the shift value y output from the first estimator 11. This prevents the use of a voltage value containing a large estimation error as the actual read level.

[0081] The training data for the first estimator 11 is generated, for example, as follows: One or more sample memory chips CP are connected to the test device, and the test device performs tests on each sample that simulate the actual use of the memory system 1. The test device obtains many pairs of difference bit count group x and optimal read level from the sample. The difference bit count group x is obtained in the same way as the difference bit count group x'. Therefore, the difference bit count group x has seven elements, just like the difference bit count group x'. The seven elements included in the difference bit count group x are denoted as x0, x1, x2, x3, x4, x5, and x6 in order of voltage, corresponding to the voltage of the adjacent reference read level pair. The method for obtaining the optimal read level from the sample is arbitrary, as long as an appropriate value can be obtained. The pairs of difference bit count group x and optimal read level are used as training data. Many training data are generated while the test conditions are changed in various ways.

[0082] Figure 8 shows an example of the frequency of occurrence of the difference bit count group x included in each training data according to the first embodiment. In this explanation, to avoid making the diagram complicated, the difference bit count group x is assumed to consist of two elements, namely x0 and x1, and the distribution of the frequency of occurrence of the difference bit count group x is shown on the x0x1 plane. In the following explanation, the frequency of occurrence of the difference bit count group x will be simply referred to as the frequency of occurrence.

[0083] Region A0 is a region with a high frequency of occurrence. Region A2 is a region with a low frequency of occurrence. Region A1 is a region with a higher frequency of occurrence than region A2, and a lower frequency of occurrence than region A1.

[0084] For example, if the difference bit count group x' is included in region A0, highly accurate estimation is possible using the first estimator 11. If the difference bit count group x' is included in region A1, the estimation is possible with the second highest accuracy, after the case where the difference bit count group x' is included in region A0. If the difference bit count group x' is included in region A2, the estimation accuracy is lower than when the difference bit count group x' is included in region A1. Thus, the accuracy of the estimation by the first estimator 11 is related to the frequency of occurrence of the difference bit count group x.

[0085] In one example, the confidence score c is a value that falls within the interval from 0 to 1. The confidence score c takes a larger value depending on the frequency of occurrence of the difference bit count group x at the position x'. The method for calculating the confidence score c is defined such that the higher the frequency of occurrence of the difference bit count group x at the position x', the closer the confidence score c is to 1, and the lower the frequency of occurrence of the difference bit count group x at the position x', the closer the confidence score c is to 0.

[0086] In the first embodiment, the controller 100 calculates the confidence score c using a second estimator (second estimator 12), which is a trained neural network model.

[0087] Figure 9 shows an example of the configuration of the second estimator 12 according to the first embodiment.

[0088] The second estimator 12 has an MLP configuration with one or more hidden layers. The first estimator 11 may be a fully connected MLP or a non-fully connected MLP.

[0089] According to the example shown in Figure 9, the second estimator 12 comprises an input layer, two hidden layers, and an output layer. The input layer has seven nodes, each receiving a different element from the difference bit count group x'. Each of the two hidden layers has four nodes. The output layer has one node that outputs the confidence score c.

[0090] In the hidden and output layers, each node multiplies each input value from the node in the previous layer by a weight, applies an activation function to the sum of each weighted value plus a bias, and outputs the value obtained by applying the activation function.

[0091] The biases and weights are predetermined through training. In other words, the second estimator 12 is pre-trained to map the difference bit count group x' to confidence levels c.

[0092] The configuration of the second estimator 12 described above is recorded in the second estimator information 112. The second estimator information 112 includes, for example, definitions of multiple nodes, definitions of the connection relationships between nodes, and biases. In the second estimator information 112, each node is associated with an activation function, trained biases, and trained weights.

[0093] The second estimator information 112 is pre-stored in a predetermined location, for example, in the NAND flash memory 200. When the memory system 1 is started up, the CPU 102 loads the second estimator information 112 into the RAM 104. Then, based on the second estimator information 112 loaded into the RAM 104, the CPU 102 performs calculations based on the weights, biases, and activation functions associated with each node, thereby realizing the calculations for the second estimator 12.

[0094] In the example shown in Figure 9, the node configuration of the second estimator 12 is the same as that of the first estimator 11. However, the node configuration of the second estimator 12 may be different from that of the first estimator 11.

[0095] The controller 100 compares a pre-set threshold Th1, which corresponds to an occurrence frequency that yields sufficient estimation accuracy, with a confidence level c.

[0096] If the confidence level c is greater than the threshold Th1, the difference bit count group x' can be considered to be in a region where the difference bit count group x appears frequently (referred to as the first region). The frequency of appearance of the difference bit count group x in the first region is higher than the frequency at which sufficient estimation accuracy can be obtained. Therefore, the controller 100 adopts the shift value y obtained by the first acquisition operation.

[0097] If the confidence level c is less than a predetermined threshold Th1, the difference bit count group x' can be considered to be in a region where the difference bit count group x appears infrequently (referred to as the second region). The frequency of appearance of the difference bit count group x in the second region is lower than the frequency at which sufficient estimation accuracy can be obtained. Therefore, the controller 100 does not adopt the shift value y obtained by the first acquisition operation. The controller 100 acquires the shift value y by the second acquisition operation and adopts the shift value y obtained by the second acquisition operation.

[0098] If the confidence level c is equal to the threshold Th1, the controller 100 may use the shift value y obtained by the first acquisition operation, or it may use the shift value y obtained by the second acquisition operation. Hereafter, as an example, if the confidence level c is equal to the threshold Th1, the controller 100 will use the shift value y obtained by the second acquisition operation.

[0099] Figure 10 is a diagram illustrating an example of the second acquisition operation according to the first embodiment. This figure shows the distribution of memory cells belonging to either state "A" or state "B", and the change in the number of ON cells.

[0100] The controller 100 first performs an operation similar to a reference read operation, determining the optimal read level VB optMultiple bit counts are acquired within a voltage range that may include the specified value. Then, the controller 100 calculates the difference bit counts of multiple points from the multiple bit counts. Note that the controller 100 may also use the difference bit count group x' acquired for estimation using the first estimator 11 as the difference bit counts of multiple points in the second acquisition operation. Based on the difference bit counts of multiple points, the controller 100 determines the voltage value at which the difference bit counts take their minimum value as the optimal read level VB opt Estimated value (VB opt The controller 100 may fit the difference bit counts of multiple points to a predetermined curve, for example, by the least squares method, and identify the voltage value at which the difference bit count takes its minimum value based on the curve. The controller 100 then determines the estimated value VB opt 'and initial settings VB ini The difference between this value and the original value is obtained as the shift value y.

[0101] The example of the second acquisition operation explained using Figure 10 will be referred to as the minimum value method. The accuracy of the estimation of the optimal read level using the minimum value method may not be as high as the accuracy of the estimation using the neural network model (i.e., the first estimator 11) described above. However, unlike the estimation method using the first estimator 11, the minimum value method can estimate the optimal read level without significantly degrading the estimation accuracy under any circumstances.

[0102] In addition to the minimum value method, any other method can be applied as the second acquisition operation. As another example of an applicable second acquisition operation, the median tracking method will be explained.

[0103] In TLC mode, memory cells can take on eight states. In many use cases, the group of programmed memory cells is divided almost equally among the eight states. That is, it can be considered that 1 / 8 of the programmed memory cells belong to each state. Therefore, in the median tracking method, the controller 100 obtains seven voltage values, each representing 1 / 8 of the number of ON cells relative to the number of memory cells in a given set (e.g., one memory cell group MCG), as seven estimates of the optimal read level. Thus, according to the median tracking method, the optimal read level is estimated based on the number of possible states and the number of ON cells. With the median tracking method, similar to the minimum value method, the optimal read level can be estimated with stable accuracy under any circumstances.

[0104] Figure 11 is a flowchart showing an example of the operation of the memory system 1 according to the first embodiment.

[0105] First, the controller 100 performs a reference read operation (S101).

[0106] The controller 100 calculates the difference bit count group x' based on the bit count obtained for each reference read level by the processing in S101 (S102).

[0107] The controller 100 uses the second estimator 12 to calculate the confidence score c from the difference bit count group x' (S103). In S103, the controller 100 inputs the difference bit count group x' to the input layer of the second estimator 12 and obtains the value output from the output layer of the second estimator 12 in response to the input of the difference bit count group x' as the confidence score c.

[0108] The controller 100 determines whether the confidence level c is greater than the threshold Th1 (S104).

[0109] If the confidence level c is greater than the threshold Th1 (S104: Yes), the controller 100 uses the first estimator 11 to calculate the shift value y from the difference bit count group x' (S105).

[0110] If the confidence level c is not greater than the threshold Th1 (S104: No), the controller 100 calculates the shift value y using the minimum value method (S106).

[0111] After S105 or S106, the controller 100 records the shift value y in the management information 110 (S107). Then the series of operations ends.

[0112] In this way, the controller 100 obtains the difference bit count group x' by performing reads using multiple reference read levels (see, for example, Figure 6 and S101, S102 in Figure 11). The controller 100 selects one of the multiple acquisition operations for obtaining the reference read level based on the difference bit count group x' (see, for example, S103 to S106 in Figure 11). The multiple acquisition operations include a first acquisition operation that obtains the optimal read level using a first estimator 11, which is an example of a trained machine learning model, and a second acquisition operation that is different from the first acquisition operation. The controller 100 performs reads using the acquired reference read levels.

[0113] More specifically, the controller 100 inputs the difference bit count group x' into the second estimator 12, which is a trained machine learning model. Based on the output value from the second estimator 12, the controller 100 determines whether the difference bit count group x' is located in a region where the difference bit count group x appears frequently or in a region where the difference bit count group x appears frequently (see, for example, S103 and S104 in Figures 8, 9, and 11). If the difference bit count group x' is located in a region where the difference bit count group x appears frequently, the controller 100 selects the first acquisition operation (see, for example, S105 in Figure 11). If the difference bit count group x' is located in a region where the difference bit count group x appears frequently, the controller 100 selects the second acquisition operation (see, for example, S106 in Figure 11).

[0114] Therefore, it is possible to suppress the decrease in the accuracy of estimating the optimal read level caused by unexpected estimation errors in the machine learning model. Since the optimal read level can be estimated accurately, it becomes possible to provide a high-performance memory system 1.

[0115] (Variation 1) In the first embodiment, a first estimator 11, which is a neural network model, was used to estimate the optimal read level. Any machine learning model other than a neural network model can be used to estimate the optimal read level. As a modification of the first embodiment, a configuration in which matrix calculations are used to estimate the optimal read level instead of the first estimator 11 will be described.

[0116] The controller 100 performs a read operation similar to a reference read operation using multiple voltage values ​​Vr selected from the entire range of possible threshold voltages. The controller 100 generates a histogram (denoted as histogram 400) with multiple intervals delimited by the voltage values ​​used as bins, and the number of memory cells as the frequency.

[0117] For example, in the example shown in the upper part of Figure 12, bit counts are obtained using seven voltage values ​​Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 selected from the entire range in which the eight lobes are distributed. Then, based on the bit counts obtained for each voltage value, a histogram 400 with eight bins is generated, for example, as shown in the lower part of Figure 12. Note that the histogram is another example of a dataset corresponding to the distribution of threshold voltages of memory cells.

[0118] Figure 13 shows the calculation for estimating the optimal read level using the estimation matrix applied to Modification 1.

[0119] RAM 104 stores the estimation matrix 111a in place of the first estimator information 111. The estimation matrix 111a has the same number of rows as the number of bins in the histogram 400 and the same number of columns as the total number of read levels. The estimation matrix 111a is pre-trained to map the histogram 400 to all types of optimal read levels. The controller 100 obtains the voltage value VA by applying the estimation matrix 111a to the histogram 400. opt ", VB opt ", VC opt ", VD opt ", VE opt ", VF opt ", and VG opt The group marked with " is considered the group of estimated optimal read levels.

[0120] The estimation matrix 111a may be configured to output shift values ​​for each type of read level.

[0121] Furthermore, when the estimation matrix 111a is applied to the estimation of the optimal read level, the second estimator 12 is configured to obtain the confidence level c from the histogram 400.

[0122] (Second embodiment) In the first embodiment, the confidence level c was calculated using the second estimator 12, and the acquisition operation was selected based on the confidence level c. The method for selecting the acquisition operation is not limited to this. In the second embodiment, another example of the method for selecting the acquisition operation is described. Note that in the second embodiment, matters that differ from the first embodiment will be described. Matters that are the same as in the first embodiment will be omitted or described in a simplified manner.

[0123] In the second embodiment, the controller 100 selects an acquisition operation based on the node value of the first estimator 11 when the difference bit count x' is input.

[0124] Figure 14 is a diagram illustrating the node values ​​of the first estimator 11 according to the second embodiment.

[0125] As described above, each node multiplies each input value from the previous layer's node by a weight, applies an activation function to the sum of each weighted value and the bias, and outputs the value obtained by applying the activation function. The node value is the value output by the node, that is, the value immediately after the activation function is applied.

[0126] The controller 100 inputs the difference bit count group x' to the first estimator 11, and when the shift value y is output from the difference bit count group x', it obtains the node values ​​of some or all of the nodes that make up the first estimator 11. Here, as an example, the controller 100 obtains the node values ​​of each node that makes up the hidden layer.

[0127] h is the node value of the q-th node of the p-th hidden layer obtained in response to the input of the difference bit count group x'. p_q This is denoted as '. In the example shown in Figure 14, there are eight node values ​​h 1_1 ', h 1_2 ', h 1_3 ', h 1_4 ', h 2_1 ', h 2_2 ', h 2_3 ', h 2_4 ' is obtained. Note that the eight node values ​​h 1_1', h 1_2 ', h 1_3 ', h 1_4 ', h 2_1 ', h 2_2 ', h 2_3 ', h 2_4 Sometimes, these are collectively referred to as node values ​​h.

[0128] For all nodes from which node values ​​h' are to be acquired, a minimum and maximum value are predetermined for each node individually. The controller 100 compares each of the acquired node values ​​h' with the minimum and maximum values ​​of the corresponding node. If each of the acquired node values ​​h' falls within the interval between the minimum and maximum values ​​of the corresponding node, the controller 100 selects the first acquisition operation. If any of the acquired node values ​​h' do not fall within the interval between the minimum and maximum values ​​of the corresponding node, the controller 100 selects the second acquisition operation.

[0129] The minimum and maximum values ​​of node values ​​are determined, for example, in a manufacturing process, as follows: Each time the difference bit count group x included in the training data is input to the first estimator 11, the node values ​​(h) of all nodes for which the node value h' is to be obtained are determined. p_q (To be denoted as) is collected. Then, for each node, the node value h p_q The minimum value of min(h) p_q ) and node value h p_q The maximum value of max(h p_q ) and are obtained. Controller 100 sets the minimum value min(h p_q ) and maximum value max(h p_q ) to node value h p_q Used as the minimum and maximum values ​​to be compared with '.

[0130] The node value h for each node p_q ' is the minimum value min(h p_q ) and maximum value max(h p_q If it falls between ) then the difference bit count group x' is considered to be in a region where the difference bit count group x has a high frequency of occurrence. Therefore, the controller 100 considers the node value h of each node to bep_q ' is the minimum value min(h p_q ) and maximum value max(h p_q If it falls between ) then select the first acquisition operation. The node value h of any node p_q ' is the minimum value min(h p_q ) and maximum value max(h p_q If the data does not fall within the range of ), the controller 100 selects the second acquisition operation.

[0131] Note that the node value h p_q ' is the minimum value min(h p_q ) or maximum value max(h p_q The handling of the case where it is equal to ) is optional. Node value h p_q ' is the minimum value min(h p_q ) or maximum value max(h p_q If it is equal to ), the controller 100 will set the node value h p_q ' is the minimum value min(h p_q ) and maximum value max(h p_q It can be considered to fall between ) and the node value h p_q ' is the minimum value min(h p_q ) and maximum value max(h p_q It can be considered that it does not fall within the range of ).

[0132] Figure 15 shows the information stored in the RAM 104 according to the second embodiment. As shown in this figure, the RAM 104 stores node value information 113 instead of second estimator information 112. The node value information 113 contains the minimum value min(h) for each node from which the node value h' is to be obtained. p_q ) and maximum value max(h p_q ) is the information recorded. The node value information 113 is pre-stored in a predetermined location in, for example, the NAND flash memory 200. When the memory system 1 is started up, the CPU 102 loads the node value information 113 into the RAM 104. The CPU 102 then uses the node value information 113 loaded into the RAM 104 to estimate the optimal read level.

[0133] FIG. 16 is a flowchart showing an example of the operation of the memory system 1 according to the second embodiment.

[0134] First, the controller 100 executes the processes of S101 and S102 that have been described above.

[0135] When the process of S102, that is, the calculation of the differential bit count group x' using the first estimator 11, is completed, the shift value y is calculated from the differential bit count group x' using the first estimator 11 (S201). Then, the controller 100 obtains the node value h p_q ' of each node of the first estimator 11 (S202).

[0136] The controller 100 determines whether the relationship of the following equation (1) is satisfied at each node where the node value h p_q ' has been obtained (S203). min(h p_q ) ≦ h p_q ' ≦ max(h p_q ) ···(1)

[0137] If the relationship of equation (1) is not satisfied at any node where the node value h p_q ' has been obtained (S203: No), the controller 100 discards the shift value y obtained by the process of S201 (S204), calculates the shift value y using the minimum value method (S205). The controller 100 records the shift value y in the management information 110 (S206). Then, the series of operations ends.

[0138] If the relationship of equation (1) is satisfied at all nodes where the node value h p_q ' has been obtained (S203: Yes), the controller 100 skips the processes of S204 and S205 and executes the process of S206.

[0139] As described above, the controller 100 inputs the difference bit count group x' to the first estimator 11, inputs it to the first model, and obtains the node values ​​of the nodes of the first estimator 11 when the difference bit count group x' was input (see, for example, S201 and S202 in Figure 16). Based on the node values, the controller 100 determines whether the difference bit count group x' is included in a region where the difference bit count group x appears frequently or in a region where the difference bit count group x appears frequently (see, for example, S203 in Figure 16).

[0140] More specifically, when the difference bit count group x' is input to the first estimator 11, if the node value of the node of the first estimator 11 is greater than the minimum value and less than the maximum value, the controller 100 selects the first acquisition operation. When the difference bit count group x' is input to the first estimator 11, if the node value of the node of the first estimator 11 is either less than the minimum value or greater than the maximum value, the controller 100 selects the second acquisition operation.

[0141] Thus, if the first estimator 11 is a neural network model, it is possible to select an acquisition operation based on the node values ​​of the nodes in the first estimator 11.

[0142] (Modification 2) Instead of the node values ​​of the nodes constituting the hidden layer of the first estimator 11, the values ​​input to the first estimator 11, i.e., the difference bit count group x', may be used to determine whether or not to select the first acquisition operation.

[0143] When the determination of whether the differential bit count group x' selects the first acquisition operation is used, for example, in the node value information 113, the minimum value and the maximum value of the differential bit count group x are pre-recorded for each element of the differential bit count group x. When the values of all elements of the differential bit count group x' fall within the range between the minimum value and the maximum value, the controller 100 adopts the estimation result of the optimal read level using the first estimator 11. When the value of any element of the differential bit count group x' does not fall within the range between the minimum value and the maximum value, the controller 100 does not adopt the estimation result of the optimal read level using the first estimator 11.

[0144] Note that the second modification is applicable not only to the first estimator 11 that adopts the neural network model, but also to any system that estimates the optimal read level using a machine learning model. That is, the second modification can be used in combination with the first modification.

[0145] (Second Modification) The controller 100 may be configured to determine whether to select the first acquisition operation by using the average and variance of the node value h p_q instead of the minimum value and the maximum value of the node value h p_q .

[0146] For example, for each node, the lower limit value and the upper limit value calculated based on the standard deviation σ from the average value of the node value h p_q are pre-recorded in the node value information 113. In one example, the lower limit value is a value obtained by subtracting c a *σ (where c a is a constant) from the average value, and the upper limit value is a value obtained by adding c a *σ to the average value. In the process of S203, the controller 100 uses the lower limit value and the upper limit value instead of the minimum value min(h p_q ) and the maximum value max(h p_q ) of the node value h p_q .

[0147] Alternatively, the controller 100 may use the node value h p_q 's node value h p_qThe controller may be configured to decide whether or not to select a first acquisition operation based on the Lp norms up to a certain group. For example, the controller 100 calculates an Lp norm for each node. If all the calculated Lp norms are less than a predetermined threshold, the controller 100 selects a first acquisition operation. If there are any nodes whose Lp norms are greater than the predetermined threshold, the controller 100 selects a second acquisition operation.

[0148] Note that in variation 3, the node value h p_q By replacing ' with an element of the difference bit count group x', this can also be applied to variation 2.

[0149] (Third embodiment) Memory cells are subjected to various stresses depending on the access pattern to the memory chip CP. Known stresses on memory cells include read disturbance (RD), temperature crossover (CT), and data retention (DR). Read disturbance refers to the phenomenon where the threshold voltage of memory cells contained in a string unit SU changes to a higher voltage each time a sense operation is performed on that string unit SU. Temperature crossover refers to the difference between the temperature during program operation and the temperature during sense operation. Data retention refers to the phenomenon where, after a program operation is performed on a memory cell, the threshold voltage of that memory cell changes to a lower voltage over time. The optimal read level can vary depending on the type of stress.

[0150] The test apparatus may collect training data sets while varying the stress applied to the sample. In such cases, two or more frequently occurring regions may appear, or a large frequently occurring region with a distorted shape may appear, formed by the connection of two small, frequently occurring regions.

[0151] In the third embodiment, the training data set is classified into several subgroups according to the type of stress, and a minimum value min(h) is set for each subgroup. p_q ) and maximum value max(h p_q ) and are obtained in advance. Controller 100 uses the minimum value min(h) obtained for each small group. p_q ) and maximum value max(h p_q Based on this, a decision is made as to whether or not to adopt the estimation result of the optimal read level using the first estimator 11. The following describes the differences from the second embodiment. The same matters as in the second embodiment will be omitted from the explanation.

[0152] Figure 17 shows the information stored in the RAM 104 according to the third embodiment. As shown in this figure, the RAM 104 has node value information 113 instead of node value information 113 RD Node value information 113 CT , and node value information 113 DR This is stored.

[0153] Node value information 113 RD This is a node value h obtained from a small group of differential bit counts x collected in a test in which data retention stress is applied to a sample product. p_q The minimum value (min(h) p_q ) RD (This is written as) and the maximum value (max(h p_q ) RD This is the information recorded for each node (denoted as follows).

[0154] Node value information 113 CT This is the node value h obtained from a small group of differential bit counts x collected in a test in which a sample is subjected to temperature cross-stress. p_q The minimum value (min(h) p_q ) CT (This is written as) and the maximum value (max(h p_q ) CT This is the information recorded for each node (denoted as follows).

[0155] Node value information 113 DRThis is a node value h obtained from a small group of differential bit counts x collected in a test in which data retention stress is applied to a sample product. p_q The minimum value (min(h) p_q ) DR (This is written as) and the maximum value (max(h p_q ) DR This is the information recorded for each node (denoted as follows).

[0156] Figure 18 is a flowchart showing an example of the operation of the memory system 1 according to the third embodiment.

[0157] First, the controller 100 executes the processes S101, S102, S201, and S202 that have already been described.

[0158] After processing S202, the controller 100 will determine the node value h p_q It is determined whether the relationship in equation (2) below is satisfied for all nodes from which ' was obtained (S301). min(h p_q ) RD ≤h p_q '≦max(h p_q ) RD ...(2)

[0159] Node value h p_q If the relationship in equation (2) is not satisfied in any node where ' is obtained (S301: No), the controller 100 will determine the node value h p_q It is determined whether the relationship in equation (3) below is satisfied for all nodes from which ' was obtained (S302). min(h p_q ) CT ≤h p_q '≦max(h p_q ) CT ...(3)

[0160] Node value h p_q If the relationship in equation (3) is not satisfied in any node where ' is obtained (S302: No), the controller 100 will determine the node value h p_qIt is determined whether the relationship in equation (4) below is satisfied for all nodes from which ' was obtained (S303). min(h p_q ) DR ≤h p_q '≦max(h p_q ) DR ...(4)

[0161] Node value h p_q If the relationship in equation (4) is not satisfied in any node where ' is obtained (S303: No), the controller 100 executes the processes in S204 to S206 and the series of operations ends.

[0162] Node value h p_q If the relationship in equation (2) is satisfied in all nodes from which ' is obtained (S301: Yes), or if the node value h p_q If the relationship in equation (3) is satisfied in all nodes from which ' is obtained (S302:Yes), or if the node value h p_q If the relationship in equation (4) is satisfied at all nodes from which ' is obtained (S303: Yes), the controller 100 executes the process in S206 and the series of operations ends.

[0163] In the above explanation, the training data set was classified into subgroups based on the type of stress applied to the sample products when the training data was obtained. However, the classification method is not limited to this. For example, the training data set may be classified into multiple subgroups using clustering methods based on the distance between them.

[0164] As described above, according to the third embodiment, the controller 100 is configured to compare the node value h' with the minimum and maximum values ​​for each of the multiple subgroups.

[0165] Therefore, even if there are two or more regions with high frequency of occurrence, or if the shape of the regions with high frequency of occurrence is distorted, it is possible to estimate the optimal read level with high accuracy.

[0166] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0167] 1 Memory system, 11 First estimator, 12 Second estimator, 100 Controller, 101 Host interface circuit, 102 CPU, 103 Memory interface circuit, 104 RAM, 105 Bus, 106 ECC circuit, 110 Management information, 111 First estimator information, 111a Estimation matrix, 112 Second estimator information, 113,113 CT ,113 DR ,113 RD Node value information, 200 NAND flash memory, 210 processing circuits, 211 memory cell array, 214 NAND string, 300 host, 400 histogram.

Claims

1. Multiple memory cells, A controller is configured to obtain a dataset corresponding to the distribution of threshold voltages of the plurality of memory cells by performing reads on the plurality of memory cells using a reference read voltage, and to select one of a plurality of acquisition operations based on the dataset to obtain an actual read voltage for reading data stored in the plurality of memory cells, wherein the plurality of acquisition operations include a first acquisition operation that obtains the actual read voltage from the dataset using a first model which is a trained machine learning model, and a second acquisition operation which is different from the first acquisition operation, and to obtain the actual read voltage using the selected acquisition operation and to perform reads on the plurality of memory cells using the obtained actual read voltage. A memory system equipped with the following features.

2. The controller is configured to determine, based on the dataset, whether the dataset is included in a first region or a second region, and if the frequency of occurrence of the training data for the first model in the first region is higher than the frequency of occurrence of the training data for the first model in the second region, and the dataset is included in the first region, then select the first acquisition operation; and if the dataset is included in the second region, then select the second acquisition operation. The memory system according to claim 1.

3. The controller is configured to input the dataset into a second model, which is a trained machine learning model, and to determine whether the dataset is included in the first region or the second region based on the output value from the second model. The memory system according to claim 2.

4. The first model described above is a neural network model comprising nodes, The controller is configured to input the dataset into the first model, obtain the node value of the node when the dataset was input, and determine whether the dataset is included in the first region or the second region based on the node value. The memory system according to claim 2.

5. The first model described above is a neural network model comprising nodes, The system further includes a memory that stores node value information, which records the minimum and maximum node values ​​of the nodes when each of the multiple training data is input to the first model. The controller is configured to select the first acquisition operation if the node value of the node when the dataset is input to the first model is greater than the minimum value and less than the maximum value, and to select the second acquisition operation if the node value is less than the minimum value or greater than the maximum value. The memory system according to claim 1.

6. The aforementioned training data are classified into multiple groups, The node value information records the minimum and maximum values ​​for each of the multiple groups. The controller is configured to perform a comparison of the node value of the node with the minimum and maximum values ​​for each of the multiple groups when the dataset is input to the first model. The memory system according to claim 5.

7. The controller selects the first acquisition operation if the node value of the node when the dataset is input to the first model is the same as the minimum value or the maximum value. The memory system according to claim 5.

8. The controller selects the second acquisition operation if the node value of the node when the dataset is input to the first model is the same as the minimum value or the maximum value. The memory system according to claim 5.

9. By performing reads on multiple memory cells using a reference read voltage, a dataset corresponding to the distribution of threshold voltages of the multiple memory cells is obtained. One of several acquisition operations for acquiring the actual read voltage to read the data stored in the plurality of memory cells is selected based on the dataset. The actual read voltage is obtained using the selected acquisition operation, and the acquired actual read voltage is used to perform reads on the plurality of memory cells. The aforementioned acquisition operations include a first acquisition operation that acquires the actual read voltage from the dataset using a first model, which is a trained machine learning model, and a second acquisition operation that is different from the first acquisition operation. The control method performed by the controller.

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