Semiconductor device and method for manufacturing the same

Abstract

To reduce the capacitance between the gate electrode and the field plate electrode. [Solution] The semiconductor device according to the embodiment includes a first electrode, a second electrode facing the first electrode in a first direction, and a semiconductor layer provided between the first electrode and the second electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type electrically connected to the second electrode, and a second semiconductor region of a second conductivity type provided on the first semiconductor region. The semiconductor device includes an insulating region provided within the semiconductor layer, having a cavity extending from its upper end in a first direction, a first control electrode provided within the insulating region so as to face the second semiconductor region in a second direction, a second control electrode provided in the insulating region so as to face the first control electrode in a second direction across the cavity, and a conductive portion provided within the insulating region, with at least a portion of its upper surface exposed at the bottom of the cavity.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] One type of MOSFET is the MOSFET equipped with a field plate electrode (also abbreviated as FPMOSFET or FPMOS). Among FPMOSs, the FP trench MOS is known in which the gate electrode and field plate electrode are arranged in an insulating region embedded in a trench in the semiconductor layer.

[0003] In FP trench MOS transistors, the gate electrode and field plate electrode are separated by an insulating region. Due to the high dielectric constant of the insulating region, the capacitance between the gate electrode and field plate electrode is large. This can lead to increased switching losses and other issues affecting device performance. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-93392 [Patent Document 2] Japanese Patent Publication No. 2022-107025 [Patent Document 3] Japanese Patent Publication No. 2020-136587 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] The problem that this invention aims to solve is to provide a semiconductor device and a method for manufacturing the same that can reduce the capacitance between the gate electrode and the field plate electrode. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a first electrode, a second electrode facing the first electrode along a first direction, and a semiconductor layer provided between the first electrode and the second electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type electrically connected to the second electrode, and a second semiconductor region of a second conductivity type provided on the first semiconductor region. The semiconductor device further includes an insulating region provided in the semiconductor layer and having a cavity portion extending along the first direction from an upper end thereof, a first control electrode provided in the insulating region so as to face the second semiconductor region along a second direction orthogonal to the first direction, a second control electrode provided in the insulating region so as to face the first control electrode along the second direction with the cavity portion interposed therebetween, and a conductive portion electrically connected to the first electrode, provided in the insulating region, and having at least a part of an upper surface exposed at the bottom of the cavity portion.

Brief Description of Drawings

[0007] [Figure 1] It is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] It is an enlarged view of region A in FIG. 1. [Figure 3A] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 3B] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment following FIG. 3A. [Figure 3C] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment following FIG. 3B. [Figure 3D] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment following FIG. 3C. [Figure 3E] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment following FIG. 3D. [Figure 3F] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the first embodiment following FIG. 3E. [Figure 3G]Figure 3F is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 3H] Figure 3G is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 3I] Figure 3H is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 5A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 5B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment, following Figure 5A. [Figure 5C] Figure 5B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 5D] Figure 5C is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 5E] Figure 5D is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 5F] Figure 5E is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those already described are denoted by the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] In the following explanation, to represent the relative highs and lows of impurity concentrations in the semiconductor region, n + , n, n - , and, p + , p, p- notation may be used. n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n, indicating p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p, indicating that these notations represent the relative levels of the net impurity concentration after the impurities compensate each other when both p-type and n-type impurities are included in each region. n-type, n + type and n - type are examples of the first conductivity type in the claims. p-type, p + type and p - type are examples of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. That is, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0010] Note that the impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Also, the relative level of the impurity concentration can be determined, for example, from the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy).

[0011] In the description of the embodiments, the XYZ orthogonal coordinate system is used. The direction from the drain electrode towards the n - type semiconductor region is defined as the Z direction. Two directions perpendicular to the Z direction and orthogonal to each other are defined as the X direction and the Y direction. Also, for the sake of explanation, the direction from the drain electrode towards the n - type semiconductor region is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the drain electrode and the n - type semiconductor region and are independent of the direction of gravity.

[0012] (First Embodiment) A semiconductor device 1 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view of the semiconductor device 1, and Figure 2 is an enlarged view of region A in Figure 1. The semiconductor device 1 is an FP trench MOS in which a gate electrode and a field plate electrode are arranged in an insulating region formed within a trench of a semiconductor layer.

[0013] The semiconductor device 1 comprises a source electrode 2, a drain electrode 3, a semiconductor layer 4, an insulating region 5, a pair of gate electrodes 6A and 6B, a field plate electrode 7, and an interlayer insulating film 8.

[0014] Source electrode 2 is an example of the first electrode in the claims, and drain electrode 3 is an example of the second electrode in the claims. Gate electrode 6A is an example of the first control electrode in the claims, and gate electrode 6B is an example of the second control electrode in the claims. Field plate electrode 7 is an example of the conductive part in the claims.

[0015] The following describes each component of the semiconductor device 1.

[0016] Source electrode 2 functions as the source electrode of the MOSFET. As will be described later, source electrode 2 is electrically connected to the source region 43 and high-density region 44 of the semiconductor layer 4, which will be described later. Source electrode 2 is also electrically connected to the field plate electrode 7. Source electrode 2 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc.

[0017] The drain electrode 3 functions as the drain electrode of the MOSFET. The drain electrode 3 faces the source electrode 2 along the Z-axis direction. The drain electrode 3 is electrically connected to the drain region 41a of the semiconductor layer 4. The drain electrode 3 is made of, for example, copper (Cu), titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), etc.

[0018] The semiconductor layer 4 includes a drift region 41, a drain region 41a, a base region 42, a source region 43, and a high-concentration region 44. In this embodiment, the semiconductor layer 4 is made of silicon. However, the semiconductor layer 4 may be made of a semiconductor other than silicon.

[0019] The drift region 41 and the drain region 41a are examples of the first semiconductor region in the claims. The base region 42 is an example of the second semiconductor region in the claims, and the source region 43 is an example of the third semiconductor region in the claims. The first semiconductor region in the claims may include both the drift region 41 and the drain region 41a, or it may include only one of the drift region 41 and the drain region 41a.

[0020] The drift region 41 functions as the drift region of the MOSFET. The drift region 41 is located above the drain region 41a. In this embodiment, the drift region 41 is n - This is a semiconductor region of a certain shape. The n-type impurity concentration in the drift region 41 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 16 cm -3 The following applies:

[0021] The drain region 41a functions as the drain region of the MOSFET. The drain region 41a is positioned between the drift region 41 and the drain electrode 3, and is electrically connected to the drain electrode 3 by ohmic contact with the drain electrode 3, etc. In this embodiment, the drain region 41a is n + This is a semiconductor region of a certain type. The n-type impurity concentration in the drain region 41a is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0022] Thus, the n-type semiconductor region consisting of the drift region 41 and the drain region 41a is provided between the source electrode 2 and the drain electrode 3, and is electrically connected to the drain electrode 3 by ohmic contact or the like.

[0023] The base region 42 functions as the base region of the MOSFET. The base region 42 is located on top of the drift region 41 and is provided within the semiconductor layer 4 so as to be sandwiched between the insulating regions 5. In this embodiment, the base region 42 is a p-type semiconductor region. The p-type impurity concentration of the base region 42 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0024] The source region 43 functions as the source region of the MOSFET. The source region 43 is located between the base region 42 and the source electrode 2 when viewed in the Z-axis direction, and is provided on top of the base region 42. The source region 43 is electrically connected to the source electrode 2 by ohmic contact or the like. In this embodiment, the source region 43 is n + This is a semiconductor region of a certain type. The n-type impurity concentration in the source region 43 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 The following applies:

[0025] The high-concentration region 44 is located above the base region 42 and is electrically connected to the source electrode 2. The high-concentration region 44 is located adjacent to the bottom of the contact plug of the source electrode 2 in order to reduce recovery loss. In this embodiment, the high-concentration region 44 is located where the impurity concentration is higher than that of the base region 42. + This is a semiconductor region of a certain type. The p-type impurity concentration in the high-concentration region 44 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3The following occurs: Due to the high-concentration region 44, minority carriers accumulated in the base region 42 are injected into the high-concentration region 44, pass through the contact plug, and are discharged to the source electrode 2.

[0026] The insulating region 5 is provided within the semiconductor layer 4. The insulating region 5 is an insulating film that electrically insulates the gate electrodes 6A and 6B from the source electrode 2 and the field plate electrode 7. In this embodiment, the insulating region 5 is a silicon oxide film. However, the insulating region 5 may be composed of other materials such as a silicon nitride film.

[0027] As shown in Figures 1 and 2, the insulating region 5 is provided with a cavity C extending from the upper end along the Z-axis toward the drain electrode 3. This cavity C has a tapered portion Ctp in which the length (i.e., width) in the X-axis direction increases as it moves from the source electrode 2 toward the drain electrode 3 (i.e., from the upper surface to the lower surface of the semiconductor layer 4). The tapered portion Ctp creates an air gap between the gate electrodes 6A, 6B and the field plate electrode 7. This reduces the capacitance Cgs between the gate electrodes 6A, 6B and the field plate electrode 7.

[0028] As shown in Figures 1 and 2, the opening at the top of the cavity C is closed with the insulating material that constitutes the interlayer insulating film 8.

[0029] The gate electrode 6A is located within the insulating region 5 so as to face the base region 42 along the X-axis direction. The gate electrode 6A extends in the Y-axis direction.

[0030] The gate electrode 6B is located in the insulating region 5 so as to face the gate electrode 6A along the X-axis direction, with the cavity C in between. The gate electrode 6B extends in the Y-axis direction.

[0031] The gate electrode 6A and the gate electrode 6B are electrically connected to each other. In this embodiment, the gate electrode 6A and the gate electrode 6B are made of conductive polysilicon containing p-type or n-type impurities.

[0032] The field plate electrode 7 is located within the insulating region 5 so as to be below the gate electrodes 6A and 6B. However, the field plate electrode 7 is not positioned directly below the gate electrodes 6A and 6B. The field plate electrode 7 is electrically connected to the source electrode 2. The field plate electrode 7 extends in the Y-axis direction.

[0033] The field plate electrode 7 is made of conductive polysilicon doped with p-type or n-type impurities. In this embodiment, the impurity is phosphorus (P). The impurity concentration is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 The following applies. Note that impurities may include elements larger than silicon, such as arsenic (As) and antimony (Sb).

[0034] As shown in Figure 2, the upper surface of the field plate electrode 7 is exposed to the bottom of the cavity C. As a result, an air gap exists between the gate electrodes 6A and 6B and the field plate electrode 7.

[0035] The interlayer insulating film 8 covers the insulating region 5 and a portion of the source region 43. In this embodiment, the interlayer insulating film 8 is made of borophosphosilicate glass (BPSG). However, the interlayer insulating film 8 may be composed of other insulating films such as silicon oxide film, silicon nitride film, high-k film, or low-k film. The interlayer insulating film 8 ensures sufficient insulation between the gate electrodes 6A and 6B and the source electrode 2. However, the interlayer insulating film 8 may be omitted.

[0036] <Effects and Effects> As described above, in the semiconductor device 1 according to the first embodiment, a cavity C is provided in the insulating region 5, extending along the Z-axis direction from its upper end. The gate electrodes 6A and 6B are provided within the insulating region 5 so as to sandwich the cavity C, and the field plate electrode 7 is provided within the insulating region 5 so that at least a portion of its upper surface is exposed to the bottom of the cavity C. As a result, an air gap of the cavity C exists between the gate electrodes 6A and 6B and the field plate electrode 7, thereby reducing capacitance Cgs. In the semiconductor device 1, a tapered cavity Ctp is provided between the gate electrode 6A and the field plate electrode 7, and between the gate electrode 6B and the field plate electrode 7, so capacitance Cgs can be effectively reduced.

[0037] As shown in Figure 2, the upper end of the field plate electrode 7 may be located near the lower end of the tapered portion Ctp. This allows for a sufficient reduction in capacitance Cgs while maintaining the effect of the field plate electrode 7 in improving withstand voltage. In other words, if the upper end of the field plate electrode 7 is located above the tapered portion Ctp (on the source electrode 2 side) (when the field plate electrode 7 fills the tapered portion Ctp), there is no air gap between the gate electrodes 6A, 6B and the field plate electrode 7, which may prevent a sufficient reduction in capacitance Cgs. On the other hand, if the upper end of the field plate electrode 7 is located below the tapered portion Ctp (on the drain electrode 3 side), the original function of the field plate electrode (improving withstand voltage) may be weakened.

[0038] Furthermore, the insulating material of the interlayer insulating film 8 may extend from the upper opening of the cavity C into the tapered portion Ctp. Moreover, the insulating material may extend to the field plate electrode 7. Even in these cases, an air gap remains in the tapered portion Ctp, which reduces the capacitance Cgs.

[0039] <Method for manufacturing semiconductor device 1> An example of a manufacturing method for the semiconductor device 1 will be explained with reference to the process cross-sectional diagrams in Figures 3A to 3I.

[0040] First, a semiconductor layer (such as a silicon wafer) having an n-type semiconductor region 41A is prepared, and a trench is formed on the upper surface of the semiconductor layer. Then, by thermal oxidation, an insulating film (in this case, a silicon oxide film) is formed on the upper surface of the semiconductor layer and on the inner wall of the trench, forming an insulating region 5A that fills the trench. Subsequently, a groove is formed in the insulating region 5A by performing chemical dry etching (CDE).

[0041] Next, as shown in Figure 3A, polysilicon is deposited in the groove by chemical vapor deposition (CVD) or the like. The polysilicon contains impurities such as phosphorus and arsenic. Subsequently, the conductive portion 7A is formed by etching back the excess polysilicon by performing CDE.

[0042] Next, as shown in Figure 3B, a portion of the insulating region 5A is selectively removed by wet etching, exposing the upper part of the conductive portion 7A.

[0043] Next, as shown in Figure 3C, thermal oxidation is performed to form an insulating film 45 on the upper surface of the semiconductor layer, the inner wall of the trench, and the exposed conductive portion 7A. Specifically, a first insulating film is formed on one inner wall of the trench (the left inner wall), a second insulating film is formed on the other inner wall of the trench (the right inner wall), and a third insulating film is formed on the exposed conductive portion.

[0044] Because the conductive portion 7A contains impurities such as phosphorus, it is more easily oxidized (amplified oxidation) than the semiconductor region 41A. For this reason, the third insulating film formed on the conductive portion 7A is thicker than the first and second insulating films formed on the inner wall of the trench. In addition, even in the unexposed portion of the conductive portion 7A, the portion relatively close to the upper surface of the insulating region 5A is thermally oxidized. Within the insulating region 5A, the conductive portion 7A is thermally oxidized more closely to the upper surface of the insulating region 5A, forming a thicker oxide film. As a result, as shown in Figure 3C, a tapered region 7Atp is automatically formed on the conductive portion 7A.

[0045] Next, as shown in Figure 3D, polysilicon is deposited in the groove between the insulating film 45 formed on the inner wall of the trench and the insulating film 45 formed on the conductive part 7A by CVD. Note that the material deposited in the groove is not limited to polysilicon as long as it is conductive. After that, the excess polysilicon is etched back to form the gate conductive parts 6AA and 6BA that sandwich the conductive part 7A. In this process, the first gate conductive part is formed by depositing conductive material in the groove between the first insulating film and the third insulating film, and the second gate conductive part is formed by depositing conductive material in the groove between the second insulating film and the third insulating film.

[0046] Next, as shown in Figure 3E, thermal oxidation (buffer oxidation) is performed to oxidize the upper parts of the gate conductive parts 6AA and 6BA and integrate them with the insulating film 45. The unoxidized parts of the gate conductive parts 6AA and 6BA become the gate electrodes 6A and 6B. The gate electrodes 6A and 6B are formed so as to sandwich the conductive part 7A. After that, etching is performed to thin the insulating film 45 on the upper surface of the semiconductor layer.

[0047] Next, as shown in Figure 3F, a base region 42 is formed by ion implantation of p-type impurities into the semiconductor region 41A. Subsequently, a source region 43 is formed above the base region 42 by ion implantation of n-type impurities into the base region 42. The portion of the semiconductor region 41A where the base region 42 and source region 43 were not formed becomes the drift region 41.

[0048] Next, as shown in Figure 3G, a resist film R with an opening at a position corresponding to the conductive portion 7A is formed on the insulating film 45. The opening in the resist film R is formed by photolithography. Subsequently, the insulating film 45 directly above the conductive portion 7A is removed by performing reactive ion etching (RIE) using the resist film R as a mask, thereby forming a hole H on the bottom surface in which the conductive portion 7A is exposed.

[0049] Next, as shown in Figure 3H, the conductive portion 7A exposed in the hole H is selectively removed by etching with a CDE or similar process. Specifically, the conductive portion 7A is removed until its upper surface is located below the gate electrodes 6A and 6B. This forms the field plate electrode 7 and the cavity C. The tapered region 7Atp is removed to form the tapered portion Ctp. The portion of the conductive portion 7A that remains after this process becomes the field plate electrode 7. Note that by knowing the etching rate in advance, the upper surface of the field plate electrode 7 may be positioned near the lower end of the tapered portion Ctp.

[0050] Next, as shown in Figure 3I, after removing the resist film R, an interlayer insulating film 8 is formed on the insulating film 45 by CVD. In this process, there is a possibility that the interlayer insulating film 8 (in this case, a silicon oxide film) may enter the cavity C. However, since the tapered portion Ctp is not filled with insulating material, an air gap remains at least in the tapered portion Ctp.

[0051] Subsequently, although not shown in the diagram, a contact hole is formed that penetrates the interlayer insulating film 8 and the source region 43 and reaches the base region 42, and a high-concentration region 44 is formed by ion implantation of p-type impurities into the contact hole. Then, by CVD, a metallic material is deposited to fill the contact hole and embed the interlayer insulating film 8, thereby forming the source electrode 2. After that, a metallic material is deposited on the lower surface of the semiconductor layer to form the drain electrode 3.

[0052] (Second embodiment) Referring to Figure 4, the semiconductor device 1A according to the second embodiment will be described. In the semiconductor device 1A, an insulating film 7s, which is an etching stopper film, is provided on the upper surface of the field plate electrode 7. The second embodiment will be described below, focusing on the differences from the first embodiment.

[0053] The semiconductor device 1A of this embodiment includes a source electrode 2, a drain electrode 3, a semiconductor layer 4, an insulating region 5, a pair of gate electrodes 6A and 6B, a field plate electrode 7, and an interlayer insulating film 8.

[0054] The upper surface of the field plate electrode 7 is covered with an insulating film 7s. In this embodiment, the insulating film 7s is a silicon oxide film. However, the material of the insulating film 7s is not limited to silicon oxide; any material that functions as an etching stopper is acceptable.

[0055] Similar to the first embodiment, the insulating region 5 of the semiconductor device 1A is provided with a cavity C having a tapered portion Ctp that extends from the upper end along the Z-axis toward the drain electrode 3. This embodiment allows for the same effects as the first embodiment. Specifically, because an air gap exists between the gate electrodes 6A, 6B and the field plate electrode 7, the capacitance Cgs between the gate electrodes 6A, 6B and the field plate electrode 7 can be reduced.

[0056] <Manufacturing method for semiconductor device 1A> An example of a manufacturing method for the semiconductor device 1 will be explained with reference to the process cross-sectional diagrams in Figures 5A to 5F.

[0057] First, a semiconductor layer (such as a silicon wafer) having an n-type semiconductor region 41A is prepared, and a trench is formed on the upper surface of the semiconductor layer. Then, by thermal oxidation, an insulating region 5A (in this case, a silicon oxide film) is formed on the upper surface of the semiconductor layer and on the inner wall of the trench. Subsequently, by CDE, grooves are formed in the insulating region 5A that fills the trench.

[0058] Next, as shown in Figure 5A, polysilicon is deposited in the groove by CVD. The polysilicon contains impurities such as phosphorus and arsenic. Subsequently, the conductive portion 7A is formed by etching back the excess polysilicon by CDE. At this time, more polysilicon is removed (deeper) from the groove than in the case described in the first embodiment. Specifically, polysilicon is removed down to below the area where the gate electrodes 6A and 6B are to be formed. The conductive portion 7A becomes the field plate electrode 7 of the semiconductor device 1A.

[0059] Next, as shown in Figure 5B, an insulating film 7s (etching stopper film) is formed on the upper surface of the conductive part 7A by thermal oxidation. Here, the insulating film 7s is made of silicon oxide.

[0060] Next, polysilicon is deposited on the insulating film 7s by CVD. The polysilicon contains impurities such as phosphorus and arsenic. Then, as shown in Figure 5C, the excess polysilicon is etched back by CDE to form the conductive portion 7B. The conductive portion 7B is an example of the second conductive portion in the claims.

[0061] Next, as shown in Figure 5D, a portion of the insulating region 5A is selectively removed by wet etching to expose the conductive portion 7B. At this time, the upper surface of the insulating region 5A is positioned above the insulating film 7s. Afterward, the steps described in the first embodiment with reference to Figures 3C to 3G are performed.

[0062] Next, as shown in Figure 5E, the conductive portion 7B exposed in the hole H is selectively removed by etching with CDE or the like. At this time, the insulating film 7s acts as an etching stopper, so the conductive portion 7A is not removed. This process forms a cavity C having a tapered portion Ctp.

[0063] Next, as shown in Figure 5F, after removing the resist film R, an interlayer insulating film 8 is formed on the insulating film 45 by CVD. Thereafter, as in the first embodiment, contact holes are formed to form a high-concentration region 44. Subsequently, the source electrode 2 and drain electrode 3 are formed.

[0064] After the above process, the semiconductor device 1A according to the second embodiment is manufactured. According to this embodiment, by covering the upper surface of the conductive portion 7A with an insulating film 7s, it is possible to prevent the conductive portion 7A from being removed in the etching process that forms the cavity portion C. As a result, it becomes easier to control the height of the upper surface of the field plate electrode 7. This makes it easier to position the upper end of the field plate electrode 7 near the lower end of the tapered portion Ctp, for example, as shown in Figure 4. This makes it possible to provide a semiconductor device 1A that can sufficiently reduce capacitance Cgs while maintaining the effect of improving the breakdown voltage by the field plate electrode 7.

[0065] According to at least one embodiment described above, the capacitance between the gate electrode and the field plate electrode can be reduced.

[0066] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0067] 1.1A Semiconductor Equipment 2 Source electrodes 3 Drain electrode 4 Semiconductor layer 41 Drift Region 41a Drain region 42 Base area 43 Source Area 44 High concentration area 45 Insulating film 5. Insulated area 6A, 6B Shuttle gate 6AA, 6BA Gate Conductors 7. Field plate electrodes 7A,7B Conductive part 7s insulating film (etching stopper film) 8 interlayer insulating film Area A C Cavity Ctp tapered section Cgs capacitance H hole R resist film

Claims

1. First electrode and, A second electrode facing the first electrode along the first direction, A semiconductor layer comprising a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode and electrically connected to the second electrode, and a second semiconductor region of a second conductivity type provided on the first semiconductor region, An insulating region is provided within the semiconductor layer, and a cavity is provided extending from the upper end along the first direction, A first control electrode is provided within the insulating region so as to face the second semiconductor region along a second direction perpendicular to the first direction, A second control electrode is provided in the insulating region so as to face the first control electrode and the second control electrode along the second direction, with the cavity in between. A conductive portion is electrically connected to the first electrode, provided within the insulating region, and at least a portion of its upper surface is exposed at the bottom of the cavity, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the cavity portion has a tapered portion whose length in the second direction increases as it moves from the first electrode toward the second electrode.

3. The semiconductor device according to claim 2, wherein the upper end of the conductive portion is located near the lower end of the tapered portion.

4. The semiconductor device according to claim 1, wherein the upper surface of the conductive portion is covered with an insulating film.

5. The semiconductor device according to claim 4, wherein the conductive portion is made of polysilicon and the insulating film is made of silicon oxide.

6. The semiconductor device according to claim 1, wherein the conductive portion is not located directly below the first control electrode and the second control electrode.

7. The semiconductor device according to claim 1, wherein the conductive portion is made of polysilicon containing phosphorus as an impurity, and the insulating region is made of silicon oxide.

8. A trench is formed on the upper surface of a semiconductor layer having a semiconductor region of the first conductivity type. An insulating region is formed to fill the trench, A groove is formed in the aforementioned insulating region. A conductive material is deposited in the groove to form a conductive portion. By removing a portion of the insulating region, the upper part of the conductive portion is exposed. A first insulating film is formed on one inner wall of the trench, a second insulating film is formed on the other inner wall of the trench, and a third insulating film is formed on the exposed conductive portion. A conductive material is deposited in the groove between the first insulating film and the third insulating film to form a first gate conductive portion. A conductive material is deposited in the groove between the second insulating film and the third insulating film to form a second gate conductive portion. A base region is formed by ion implantation of a second conductivity type impurity into the semiconductor region. Ion implantation of a first conductivity type impurity is performed on the base region to form a source region on the upper part of the base region. A method for manufacturing a semiconductor device, comprising removing the conductive portion until its upper surface is located below the first and second gate conductive portions, thereby forming a cavity that extends from the upper end along the thickness direction of the semiconductor layer and has a tapered portion whose width increases from the upper surface to the lower surface of the semiconductor layer.

9. A trench is formed on the upper surface of a semiconductor layer having a semiconductor region of the first conductivity type. An insulating region is formed to fill the trench, A groove is formed in the aforementioned insulating region. A conductive material is deposited in the groove, and the conductive material is removed below the area where the gate electrode is to be formed to form a conductive portion. An etching stopper film is formed on the conductive portion. A second conductive portion is formed on the etching stopper film. By removing a portion of the insulating region, the second conductive portion is exposed. A first insulating film is formed on one inner wall of the trench, a second insulating film is formed on the other inner wall of the trench, and a third insulating film is formed on the exposed second conductive portion. A conductive material is deposited in the groove between the first insulating film and the third insulating film to form a first gate conductive portion. A conductive material is deposited in the groove between the second insulating film and the third insulating film to form a second gate conductive portion. A base region is formed by ion implantation of a second conductivity type impurity into the semiconductor region. Ion implantation of a first conductivity type impurity is performed on the base region to form a source region on the upper part of the base region. A method for manufacturing a semiconductor device, comprising removing the second conductive portion formed on the etching stopper film to form a cavity having a tapered portion that extends from the upper end along the thickness direction of the semiconductor layer and whose width increases from the upper surface to the lower surface of the semiconductor layer.

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