Semiconductor laminate

Abstract

The present invention provides a semiconductor laminate in which a compound semiconductor layer formed from a III-V compound semiconductor is arranged on a substrate formed from silicon, and which can reduce the number of crystal defects while reducing costs. [Solution] The semiconductor laminate comprises a substrate formed from silicon, an oxide buffer layer formed from any of zirconia, hafnia, or a composite oxide of zirconia and hafnia, an orientation layer formed from gallium arsenide, and a compound semiconductor layer formed from a III-V compound semiconductor. The substrate, the oxide buffer layer, the orientation layer, and the compound semiconductor layer are laminated in this order.

Description

Technical Field

[0001] This disclosure relates to a semiconductor laminate.

Background Art

[0002] A semiconductor laminate in which a compound semiconductor layer formed of a III-V compound semiconductor is laminated on a substrate formed of silicon is known. By using a substrate formed of silicon, it is easy to achieve cost reduction of materials.

[0003] However, when using a substrate formed of silicon, if a compound semiconductor layer is directly grown on the substrate, due to the difference in lattice constants between silicon and the III-V compound semiconductor, a large number of crystal defects may occur in the compound semiconductor layer.

[0004] From this perspective, a substrate formed of silicon is made into an off-angle substrate (see, for example, Patent Document 1). In an off-angle substrate, the main surface of the substrate is formed to have an off-angle of, for example, about several degrees with respect to the (100) plane according to the required device performance and conditions.

[0005] By adopting an off-angle substrate, a buffer layer due to the off-angle substrate can be formed between the substrate formed of silicon and the compound semiconductor layer formed of the III-V compound semiconductor. As a result, while using a substrate formed of silicon, the crystallinity of the compound semiconductor layer formed of the III-V compound semiconductor can be improved.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Incidentally, the cost of manufacturing a substrate that includes an off-angle surface is greater than the cost of manufacturing a substrate that does not have an off-angle surface. Therefore, semiconductor laminates employing off-angle substrates have the problem of high manufacturing costs, even when using substrates made from silicon. Thus, one of the objectives of this disclosure is to provide a semiconductor laminate in which a compound semiconductor layer made from a III-V compound semiconductor is arranged on a silicon substrate, and which can reduce the number of crystal defects while reducing costs. [Means for solving the problem]

[0008] A semiconductor laminate according to this disclosure comprises a substrate formed from silicon, an oxide buffer layer formed from any of zirconia, hafnia, or a composite oxide of zirconia and hafnia, an orientation layer formed from gallium arsenide, and a compound semiconductor layer formed from a III-V compound semiconductor. The substrate, the oxide buffer layer, the orientation layer, and the compound semiconductor layer are laminated in this order. [Effects of the Invention]

[0009] According to the above semiconductor laminate, in a semiconductor laminate in which a compound semiconductor layer formed from a III-V compound semiconductor is arranged on a substrate formed from silicon, it is possible to provide a semiconductor laminate that can reduce the number of crystal defects while reducing costs. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic cross-sectional view showing the structure of a semiconductor laminate according to an embodiment. [Figure 2] Figure 2 is a schematic flowchart of the method for manufacturing a semiconductor laminate according to the embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view illustrating the oxide buffer layer formation step in the semiconductor stack manufacturing method according to the embodiment. [Figure 4]Figure 4 is a schematic cross-sectional view illustrating the orientation layer formation process in the semiconductor laminate manufacturing method according to the embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating the surface flatness improvement layer formation step in the semiconductor laminate manufacturing method according to the embodiment. [Modes for carrying out the invention]

[0011] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0012] (1) The semiconductor laminate according to this disclosure comprises a substrate formed from silicon, an oxide buffer layer formed from any of zirconia, hafnia, or a composite oxide of zirconia and hafnia, an orientation layer formed from gallium arsenide, and a compound semiconductor layer formed from a III-V compound semiconductor. The substrate, the oxide buffer layer, the orientation layer, and the compound semiconductor layer are laminated in this order.

[0013] In the semiconductor laminate of this disclosure, an oxide buffer layer and an orientation layer are arranged between the substrate and the compound semiconductor layer. This improves the crystallinity of the compound semiconductor layer even if there is a difference in lattice constants between the substrate and the compound semiconductor layer. Therefore, there is no need to use an off-angle substrate. As a result, in a semiconductor laminate in which a compound semiconductor layer formed from a III-V compound semiconductor is arranged on a substrate formed from silicon, the number of crystal defects can be reduced while reducing costs.

[0014] (2) The above (1) further comprises a surface planarity improving layer disposed between the orientation layer and the compound semiconductor layer. The roughness of the main surface of the planarity improving layer facing the compound semiconductor layer may be smaller than the roughness of the main surface of the orientation layer facing the surface planarity improving layer. By adopting such a configuration, the crystallinity of the compound semiconductor layer can be further improved.

[0015] (3) In the above (1) or (2), the film thickness of the alignment layer may be thinner than the film thickness of the oxide buffer layer. By adopting such a configuration, the overall thickness of the semiconductor laminate can be reduced.

[0016] (4) In the above (2), the surface flatness improving layer may be formed of gallium phosphide or gallium antimonide. By adopting such a configuration, the crystallinity of the compound semiconductor layer can be easily improved.

[0017] [Details of Embodiments of the Present Invention] Next, embodiments of the semiconductor laminate according to the present disclosure will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their descriptions will not be repeated.

[0018] (Outline of the Structure of the Semiconductor Laminate 1) FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor laminate 1. Referring to FIG. 1, the semiconductor laminate 1 in the present embodiment includes a substrate 6, an oxide buffer layer 5, an alignment layer 4, a surface flatness improving layer 3, and a compound semiconductor layer 2. The substrate 6, the oxide buffer layer 5, the alignment layer 4, the surface flatness improving layer 3, and the compound semiconductor layer 2 are laminated in this order. Hereinafter, in the lamination direction, the direction from the substrate 6 toward the compound semiconductor layer 2 is defined as the "first direction D1", and the opposite direction is defined as the "second direction D2".

[0019] The substrate 6 is formed of silicon (Si). The compound semiconductor layer 2 is formed of a III-V compound semiconductor. Although there is a lattice constant difference between the substrate 6 and the compound semiconductor layer 2, in the semiconductor laminate 1 according to the present embodiment, since the oxide buffer layer 5 and the alignment layer 4 are disposed between the substrate 6 and the compound semiconductor layer 2, the compound semiconductor layer 2 is less likely to be affected by the lattice constant difference. Although there is a difference in thermal expansion coefficient between the substrate 6 and the compound semiconductor layer 2, in the semiconductor laminate 1, since the oxide buffer layer 5 is disposed between the substrate 6 and the compound semiconductor layer 2, the compound semiconductor layer 2 is less likely to be affected by the difference in thermal expansion coefficient. As a result, in the semiconductor laminate 1 according to the present embodiment, the crystallinity of the compound semiconductor layer 2 is improved.

[0020] Here, in the present disclosure, the expression “formed of (a certain element)” means being formed using a certain element and may include elements other than the said element. The expression “consisting only of (a certain element)” means not including elements other than a certain element. However, those “consisting only of (a certain element)” may include impurities. Examples of the impurities include dopants for the purpose of adjusting an appropriate conductivity type (for example, P-type or N-type).

[0021] (Substrate 6) The substrate 6 is a semiconductor substrate formed of silicon. The substrate 6 according to the present embodiment consists only of a single crystal of silicon. Referring to FIG. 1, the substrate 6 has a first main surface 61 and a second main surface 62. The first main surface 61 is a surface facing in the first direction D1 in the substrate 6. The first main surface 61 according to the present embodiment is a plane orthogonal to the first direction D1. The second main surface 62 is a surface facing in the second direction D2 in the substrate 6. The second main surface 62 according to the present embodiment is a plane orthogonal to the second direction D2. The first main surface 61 and the second main surface 62 are parallel to each other. The thickness of the substrate 6 is not particularly limited, but is, for example, 50 μm or more and 5 mm or less.

[0022] In this embodiment, the first main surface 61 of the substrate 6 is formed from a (100) plane. The Miller index of the first main surface 61 of the substrate 6 is not particularly limited and may be, for example, a (111) plane or a (101) plane. The Miller index of the second main surface 62 of the substrate 6 is not particularly limited. The second main surface 62 of the substrate 6 is formed from, for example, a (100) plane.

[0023] (Oxide buffer layer 5) The oxide buffer layer 5 is laminated on the first main surface 61 of the substrate 6. In this embodiment, the oxide buffer layer 5 is formed from epitaxially grown zirconia (ZrO2) on the first main surface 61 of the substrate 6. The oxide buffer layer 5 may also be formed from hafnia (HfO2), or from a composite oxide of zirconia and hafnia.

[0024] The oxide buffer layer 5 has a first main surface 51 and a second main surface 52. The first main surface 51 is the surface of the oxide buffer layer 5 facing the first direction D1. In this embodiment, the first main surface 51 is a plane perpendicular to the first direction D1. The first main surface 51 of the oxide buffer layer 5 faces the orientation layer 4. The second main surface 52 is the surface of the oxide buffer layer 5 facing the second direction D2. In this embodiment, the second main surface 52 is a plane perpendicular to the second direction D2. The second main surface 52 faces the first main surface 61 of the substrate 6 and is in contact with each other. In the oxide buffer layer 5, the first main surface 51 and the second main surface 52 are parallel to each other. The film thickness of the oxide buffer layer 5 is, for example, 10 nm or more and 30 nm or less, and more specifically, 15 nm or more and 25 nm or less. The film thickness of the oxide buffer layer 5 can be, for example, 25 nm.

[0025] When laminating the alignment layer 4 onto the oxide buffer layer 5, the alignment layer 4 is epitaxially grown while the substrate 6 is heated to a predetermined temperature or higher, so that the crystal structure of the oxide buffer layer 5 changes to match the crystal structure of the alignment layer 4. The predetermined temperature is 600°C or higher, and may be 650°C or higher, or 700°C or higher. By placing the oxide buffer layer 5 between the substrate 6 and the compound semiconductor layer 2, the crystallinity of the compound semiconductor layer 2 is improved.

[0026] Since the oxide buffer layer 5 is formed from zirconia, hafnia, or a composite oxide of zirconia and hafnia, it dissolves with hydrofluoric acid. Hydrofluoric acid has little effect on the compound semiconductor layer 2. Therefore, for example, by dissolving the oxide buffer layer 5 with hydrofluoric acid during use, the substrate 6 can be removed from the compound semiconductor layer 2 while reducing the impact on the compound semiconductor layer 2.

[0027] (Orientation layer 4) The orientation layer 4 is laminated on the first main surface 51 of the oxide buffer layer 5. In this embodiment, the orientation layer 4 is formed from epitaxially grown gallium arsenide (GaAs) on the first main surface 51 of the oxide buffer layer 5. The orientation layer 4 may be a single crystal. Alternatively, the orientation layer 4 may be formed as a single crystal in the first direction D1 from the oxide buffer layer 5 and as a polycrystalline material formed from multiple crystals along the main surface. By arranging the orientation layer 4 between the oxide buffer layer 5 and the compound semiconductor layer 2, it is easier to grow the compound semiconductor layer 2 in a state of orientation in a certain direction. As a result, the crystal plane of the compound semiconductor layer 2 can be the same as the crystal plane of the first main surface 61 of the substrate 6.

[0028] The orientation layer 4 has a first main surface 41 and a second main surface 42. The first main surface 41 is the surface in the orientation layer 4 that faces a first direction D1. The first main surface 41 in the orientation layer 4 faces the surface flatness improvement layer 3. The second main surface 42 is the surface in the orientation layer 4 that faces a second direction D2. The second main surface 42 faces the first main surface 51 in the oxide buffer layer 5 and is in contact with it.

[0029] In the alignment layer 4, the first main surface 41 and the second main surface 42 are parallel to each other. The film thickness of the alignment layer 4 according to this embodiment is thinner than the film thickness of the oxide buffer layer 5. This makes it possible to make the film thickness of the semiconductor laminate 1 relatively thin. However, the film thickness of the alignment layer 4 may be the same as the film thickness of the oxide buffer layer 5. The film thickness of the alignment layer 4 is, for example, 10 nm or more and 30 nm or less, and more specifically, 15 nm or more and 25 nm or less. The film thickness of the alignment layer 4 can be, for example, 20 nm. In this disclosure, "equivalent" includes a range in which the comparison objects are substantially the same. For example, if the difference between the film thickness of the alignment layer 4 and the film thickness of the oxide buffer layer 5 is less than 1 nm, it is included in "equivalent". In this disclosure, unless otherwise specified, "film thickness" means the minimum value of the film thickness.

[0030] The second main surface 42 in the orientation layer 4 has the same Miller index as the first main surface 61 in the substrate 6. In the orientation layer 4 according to this embodiment, the second main surface 42 is formed from the (100) plane. The second main surface 42 in the orientation layer 4 has the same Miller index as the first main surface 41, and is specifically formed from the (100) plane.

[0031] (Surface flatness improvement layer 3) The surface flatness improving layer 3 is laminated on the first main surface 41 of the orientation layer 4. In this embodiment, the surface flatness improving layer 3 is formed from epitaxially grown gallium phosphide (GaP) on the first main surface 41 of the orientation layer 4. The surface flatness improving layer 3 is not limited to gallium phosphide, but may also be formed from, for example, gallium antimony (GaSb). By arranging the surface flatness improving layer 3 between the orientation layer 4 and the compound semiconductor layer 2, the crystallinity of the compound semiconductor layer 2 can be improved.

[0032] The surface flatness improving layer 3 has a first main surface 31 and a second main surface 32. The first main surface 31 is a surface in the surface flatness improving layer 3 that faces a first direction D1. In this embodiment, the first main surface 31 is a plane perpendicular to the first direction D1. The first main surface 31 of the surface flatness improving layer 3 faces the compound semiconductor layer 2. The second main surface 32 is a surface in the surface flatness improving layer 3 that faces a second direction D2. In this embodiment, the second main surface 32 is a plane perpendicular to the second direction D2. The second main surface 32 faces the first main surface 41 in the orientation layer 4 and is in contact with it.

[0033] The first main surface 31 and the second main surface 32 of the surface flatness improvement layer 3 have fine irregularities. The roughness of the first main surface 31 is less than the roughness of the second main surface 32. That is, in the semiconductor laminate 1, the roughness of the first main surface 31 of the surface flatness improvement layer 3 facing the compound semiconductor layer 2 is less than the roughness of the first main surface 41 of the orientation layer 4 facing the surface flatness improvement layer 3. The roughness in this disclosure can be measured, for example, as follows: An arbitrary cross-section is taken in the semiconductor laminate 1, and for each of the first main surface 31 and the second main surface 32, a roughness curve is extracted along the boundary line with the contacting surface. An average line is calculated from the roughness curves. From the roughness curve, a reference length is extracted in a direction parallel to the mean line. In the extracted portion, the sum of the average absolute values ​​of the heights of the top five peaks protruding furthest in the first direction D1 from the mean line and the average absolute values ​​of the depths of the top five valleys recessed in the second direction D2 from the mean line is calculated and used as an index. A larger index indicates a rougher surface. By comparing these indices, the roughness of the first main surface 31 and the second main surface 32 can be compared.

[0034] The thickness of the surface flatness improving layer 3 according to this embodiment is, for example, 10 nm to 500 nm, and more specifically, 20 nm to 50 nm.

[0035] (Compound semiconductor layer 2) The compound semiconductor layer 2 is laminated on the first main surface 31 of the surface flatness improvement layer 3. In this embodiment, the compound semiconductor layer 2 is formed on the first main surface 31 of the surface flatness improvement layer 3 from an epitaxially grown III-V compound semiconductor. Examples of III-V compound semiconductors include gallium arsenide (GaAs), indium phosphide (InP), and indium arsenide (InAs). The compound semiconductor layer 2 may be a single crystal. The compound semiconductor layer 2 may be formed as a plurality of columnar crystalline bodies that extend from the surface flatness improvement layer 3 in a first direction D1 and are formed from a plurality of crystals along the main surface.

[0036] The compound semiconductor layer 2 has a first main surface 21 and a second main surface 22. The first main surface 21 is a surface in the compound semiconductor layer 2 that faces a first direction D1. In this embodiment, the first main surface 21 is a plane perpendicular to the first direction D1. In the semiconductor laminate 1 according to this embodiment, the first main surface 21 of the compound semiconductor layer 2 is the end face in the first direction D1. The second main surface 22 is a surface in the compound semiconductor layer 2 that faces a second direction D2. In this embodiment, the second main surface 22 is a plane perpendicular to the second direction D2. The second main surface 22 faces the first main surface 31 in the surface flatness improvement layer 3 and is in contact with it.

[0037] In the compound semiconductor layer 2, the first main surface 21 and the second main surface 22 are parallel to each other. The thickness of the compound semiconductor layer 2 is greater than the combined thickness of the oxide buffer layer 5 and the alignment layer 4. In this embodiment, the thickness of the compound semiconductor layer 2 is greater than the combined thickness of the oxide buffer layer 5, the alignment layer 4 and the surface flatness improving layer 3. As a result, the semiconductor laminate 1 according to this embodiment can reduce its overall thickness even when the oxide buffer layer 5 and the alignment layer 4 are placed between the substrate 6 and the semiconductor laminate 1. The thickness of the compound semiconductor layer 2 can be, for example, 1.5 μm or less. The thickness of the compound semiconductor layer 2 is, for example, 0.5 μm or more and 1.5 μm or less, and more specifically, 0.7 μm or more and 1.2 μm or less.

[0038] The crystal plane of the second main surface 22 in the compound semiconductor layer 2 is the same as the Miller index of the first main surface 31 in the surface flatness improvement layer 3. The crystal plane of the second main surface 22 in the compound semiconductor layer 2 is the same as the Miller index of the first main surface 41 in the orientation layer 4. In other words, the second main surface 22 in the compound semiconductor layer 2 is the same as the Miller index of the first main surface 61 in the substrate 6. In this embodiment, the second main surface 22 in the compound semiconductor layer 2 is formed from the (100) plane. The crystal plane of the first main surface 21 in the compound semiconductor layer 2 has the same Miller index as the second main surface 22, and in this embodiment, it is formed from the (100) plane.

[0039] (Manufacturing method) Next, an example of a method for manufacturing the semiconductor laminate 1 according to this embodiment will be described. Figure 2 shows a block diagram illustrating the procedure for manufacturing the semiconductor laminate 1 according to this embodiment. Referring to Figure 2, the method for manufacturing the semiconductor laminate 1 according to this embodiment comprises a substrate preparation step, an oxide buffer layer formation step, an alignment layer formation step, a surface flatness improvement layer formation step, and a compound semiconductor layer formation step. The substrate preparation step, oxide buffer layer formation step, alignment layer formation step, surface flatness improvement layer formation step, and compound semiconductor layer formation step are carried out in this order. When manufacturing a semiconductor laminate 1 without a surface flatness improvement layer 3, after completing the alignment layer formation step, the compound semiconductor layer formation step is carried out without performing the surface flatness improvement layer formation step.

[0040] As the ST1 process, a substrate preparation process is carried out. In the ST1 process, a substrate 6 formed from silicon is prepared. In the ST1 process, a substrate 6 having a first main surface 61 is prepared. Specifically, an ingot formed from silicon is sliced, and the substrate 6 is prepared through processes such as washing and drying.

[0041] Next, the ST2 process involves the formation of an oxide buffer layer. In the ST2 process, as shown in Figure 3, an oxide buffer layer 5 is formed on the first main surface 61 of the substrate 6. Specifically, for example, an oxide buffer layer 5 containing zirconia is laminated on the first main surface 61 of the substrate 6 by epitaxial growth.

[0042] The ST2 process is carried out, for example, as follows: The substrate 6 is placed in a vacuum atmosphere and heated by a heater. The substrate 6 is heated to, for example, about 700°C. After the substrate 6 is heated, a high voltage is applied between the deposition material and the substrate 6. The deposition material is zirconium (Zr) formed from a single crystal. With a high voltage applied between the deposition material and the substrate 6, the deposition material is irradiated with an electron beam from an electron gun. At this time, the evaporated zirconium reacts with oxygen on the substrate 6, forming zirconia on the first main surface 61 of the substrate 6. As a result, an oxide buffer layer 5 containing zirconia can be formed on the first main surface 61 of the substrate 6 by epitaxial growth, and the oxide buffer layer formation process is completed.

[0043] Next, the ST3 step, the orientation layer formation step, is carried out. In the ST3 step, as shown in Figure 4, the orientation layer 4 is formed on the first main surface 51 of the oxide buffer layer 5. Specifically, the orientation layer 4, formed from gallium arsenide by epitaxial growth, is laminated on the first main surface 51 of the oxide buffer layer 5.

[0044] The ST3 process is carried out, for example, as follows: A substrate 6 on which the oxide buffer layer 5 is formed is placed in a growth furnace and heated by a heater. The substrate 6 is heated to, for example, about 700°C. In this state, an orientation layer 4 is formed on the first main surface 51 of the oxide buffer layer 5 by vapor phase growth. Specifically, the orientation layer 4 can be formed by supplying a raw material gas so as to contact the first main surface 51 of the oxide buffer layer 5, while appropriately adjusting the pressure inside the growth furnace. The orientation layer formation process is completed when the orientation layer 4 is formed on the first main surface 51 of the oxide buffer layer 5.

[0045] Next, the ST4 process is carried out, which is the surface flatness improvement layer formation process. In the ST4 process, as shown in Figure 5, the surface flatness improvement layer 3 is formed on the first main surface 41 of the orientation layer 4. Specifically, the surface flatness improvement layer 3, which is formed from, for example, gallium phosphide, is laminated on the first main surface 41 of the orientation layer 4 by epitaxial growth. In the ST4 process, the surface flatness improvement layer 3 is formed on the first main surface 41 of the orientation layer 4 by, for example, vapor phase growth. The surface flatness improvement layer formation process is completed when the surface flatness improvement layer 3 is formed on the first main surface 41 of the orientation layer 4.

[0046] Next, the compound semiconductor layer formation process is carried out as the ST5 process. Referring to Figure 1, in the ST5 process, a compound semiconductor layer 2 is formed on the first main surface 31 of the surface flatness improvement layer 3. Specifically, a compound semiconductor layer 2, for example, formed from indium arsenide, is laminated on the first main surface 31 of the surface flatness improvement layer 3 by epitaxial growth. In the ST5 process, the compound semiconductor layer 2 is formed on the first main surface 31 of the surface flatness improvement layer 3 by vapor phase growth, for example. The compound semiconductor layer formation process is completed when the compound semiconductor layer 2 is formed on the first main surface 31 of the surface flatness improvement layer 3. After these steps, the fabrication of the semiconductor laminate 1 according to this embodiment is completed.

[0047] As mentioned above, the material used to form the compound semiconductor layer 2 by the compound semiconductor layer formation process is not limited to indium arsenide, but may also be, for example, gallium arsenide (GaAs) or indium phosphide (InP). Furthermore, any compound semiconductor may be laminated on top of the compound semiconductor layer 2.

[0048] (modified version) In this embodiment, the oxide buffer layer 5 is formed from zirconia, but it may also be formed from hafnia (HfO2). The oxide buffer layer 5 formed from hafnia is laminated on the first main surface 61 of the substrate 6 by epitaxial growth. In the oxide buffer layer formation process, the oxide buffer layer 5 formed from hafnia is formed, for example, by pulsed laser deposition. The oxide buffer layer 5 formed from hafnia is not limited to pulsed laser deposition, but may also be formed by other deposition methods (for example, sputtering). The oxide buffer layer 5 may also be formed from a composite oxide of zirconia and hafnia.

[0049] In this embodiment, a surface flatness improving layer 3 is placed between the orientation layer 4 and the compound semiconductor layer 2. However, depending on the required crystallinity of the compound semiconductor layer 2, the surface flatness improving layer 3 may be omitted. In this case, the first main surface 41 of the orientation layer 4 and the second main surface 22 of the compound semiconductor layer 2 face each other and are in contact.

[0050] In this embodiment, the semiconductor laminate 1 is constructed by sequentially stacking a substrate 6, an oxide buffer layer 5, an alignment layer 4, a surface flatness improving layer 3, and a compound semiconductor layer 2. However, layers made of other materials may be placed between each layer.

[0051] [Examples] Experiments were conducted to confirm the effects of the semiconductor laminate according to this embodiment. Sample No. 1 was formed as a semiconductor laminate comprising a substrate, an oxide buffer layer, an alignment layer, a surface flatness improving layer, and a compound semiconductor layer, similar to the embodiment. Sample No. 2 was formed as a semiconductor laminate comprising a substrate, an oxide buffer layer, an alignment layer, and a compound semiconductor layer. Sample No. 3 was formed as a semiconductor laminate comprising a substrate, an oxide buffer layer, and a compound semiconductor layer. Samples No. 1 and No. 2 are examples. Sample No. 3 is a comparative example.

[0052] Orientation and surface flatness were checked for each sample. Orientation was evaluated as follows: "A" indicated that the compound semiconductor layer was axially oriented, and "B" indicated that it was randomly oriented. "Axial orientation" means that the crystal axes can be evaluated as being aligned in the first direction D1. Random orientation means any state other than "axial orientation". Surface flatness was evaluated as follows: "A" indicated that the ten-point average roughness of the main surface (first main surface) of the compound semiconductor layer was less than 5 nm, and "B" indicated that it was 5 nm or more.

[0053] The results are shown in Table 1. [Table 1] As can be seen from Table 1, semiconductor laminates with an orientation layer were found to have improved axial orientation and crystallinity compared to semiconductor laminates without an orientation layer. Semiconductor laminates with a surface flatness-improving layer were found to have improved surface flatness compared to semiconductor laminates without a surface flatness-improving layer.

[0054] The embodiments disclosed herein should be understood to be illustrative in all respects and not restrictive in any way. The scope of the invention is defined by the claims and not by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included. [Explanation of Symbols]

[0055] 1. Semiconductor stack 2 Compound semiconductor layer 21 First Main Surface 22 Second Main Surface 3 Surface flatness improvement layer 31. First Main Surface 32 Second Main Surface 4. Orientation layer 41. First Main Surface 42 Second Main Surface 5. Oxide buffer layer 51 First Main Surface 52 Second Main Surface 6 circuit boards 61 First Main Surface 62 Second Main Surface D1 First direction D2 Second direction B1 1st boundary surface B2 2nd boundary surface ST1 process ST2 process ST3 process ST4 process ST5 process

Claims

1. A substrate formed from silicon, An oxide buffer layer formed from one of zirconia, hafnia, or a composite oxide of zirconia and hafnia, An orientation layer formed from gallium arsenide, A compound semiconductor layer formed from a III-V compound semiconductor, Equipped with, A semiconductor laminate in which the substrate, the oxide buffer layer, the orientation layer, and the compound semiconductor layer are stacked in this order.

2. The semiconductor laminate according to claim 1, further comprising a surface planarity improving layer disposed between the orientation layer and the compound semiconductor layer, wherein the roughness of the main surface of the surface planarity improving layer facing the compound semiconductor layer is smaller than the roughness of the main surface of the orientation layer facing the surface planarity improving layer.

3. The semiconductor laminate according to claim 1 or claim 2, wherein the thickness of the orientation layer is thinner than the thickness of the oxide buffer layer.

4. The aforementioned surface flatness improving layer is formed from gallium phosphide or gallium antimony. The semiconductor laminate according to claim 2.

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