Components for semiconductor manufacturing equipment

Abstract

The present invention provides a semiconductor manufacturing apparatus component comprising a ceramic substrate having a top surface on which a wafer can be placed and side walls forming the outer edge of the top surface, wherein particle sources adhering to the surface of the top surface and / or side walls can be easily removed. [Solution] A ceramic substrate having a reference surface, an upper surface having a plurality of wafer-mounting protrusions extending upward from the reference surface, and a side wall forming the outer edge of the upper surface, wherein the surface of the reference surface and / or the side wall has an arithmetic mean roughness Ra1 of 0.2 μm or less and a periodic roughness curve with an average length RSm of 5 μm or more, comprising a ceramic substrate for semiconductor manufacturing equipment.

Description

Technical Field

[0001] The present invention relates to a member for a semiconductor manufacturing apparatus.

Background Art

[0002] Conventionally, members for semiconductor manufacturing apparatuses used for holding, temperature control, conveyance, etc. of wafers are known. This type of member for a semiconductor manufacturing apparatus is also referred to as a wafer stage, an electrostatic chuck, a susceptor, etc., and generally has a function of applying electrostatic adsorption power to an internal electrode and adsorbing a wafer by electrostatic force, and there is also known one having a function of controlling the temperature of a wafer by flowing a gas between the wafer mounting surface and the wafer which is an adsorption object.

[0003] Members for semiconductor manufacturing apparatuses generally include a ceramic substrate having an upper surface on which a wafer can be mounted. A plurality of protrusions for supporting the wafer are provided on the upper surface on which the wafer can be mounted. Further, the ceramic substrate can have a side wall forming an outer edge of the upper surface on which the wafer can be mounted, and furthermore, on the outer peripheral side of the upper surface on which the wafer can be mounted and at a position lower than the upper surface, it can also have an upper surface on which a focus ring for in-plane uniform processing of the wafer can be mounted (Patent Document 1).

Prior Art Documents

Patent Documents

[0004] [[ID=二十五]]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The top and sidewall surfaces of ceramic substrates are typically finished by machining processes such as grinding and polishing. After machining, the top and sidewall surfaces of ceramic substrates have minute depressions, where the slurry and processing residue used in machining tend to remain, becoming a source of particles. If these particles adhere to the wafer, they can affect the quality of the semiconductor and reduce yield. Therefore, it is necessary to remove these particle sources remaining in the depressions beforehand. However, no surface treatment technology was known that could easily remove particle sources embedded in minute depressions.

[0006] In view of the above circumstances, the present invention aims to provide a semiconductor manufacturing apparatus component comprising a ceramic substrate having an upper surface on which a wafer can be placed and a side wall forming the outer edge of the upper surface, wherein a particle source adhering to the surface of the upper surface and / or side wall can be easily removed. [Means for solving the problem]

[0007] The inventors of this invention have diligently studied and developed the present invention as illustrated below in order to solve the above problems.

[0008] [Aspect 1] A ceramic substrate having a reference surface, an upper surface having a plurality of wafer-supporting protrusions extending upward from the reference surface, and a side wall forming the outer edge of the upper surface, wherein the surface of the reference surface and / or the side wall has an arithmetic mean roughness Ra1 of 0.2 μm or less and a periodic roughness curve with an average length RSm of 5 μm or more, comprising a ceramic substrate for semiconductor manufacturing equipment. [Aspect 2] The semiconductor manufacturing apparatus component according to [Aspect 1], wherein the surface of the reference surface and / or the side wall has a periodic roughness curve with an average length RSm of 5 μm or more and 30 μm or less. [Aspect 3] The semiconductor manufacturing apparatus component according to [Aspect 1] or [Aspect 2], wherein the periodic roughness curve is due to the surface of the reference surface and / or the side wall having a plurality of patterned dimples. [Aspect 4] The semiconductor manufacturing apparatus component according to [Aspect 3], wherein the shortest distance between the peripheries of adjacent dimples is 5 μm or more. [Aspect 5] The semiconductor manufacturing apparatus component according to any one of [Aspect 1] to [Aspect 4], wherein the reference surface and / or the surface of the side wall are laser processed. [Aspect 6] A semiconductor manufacturing apparatus component according to any one of [Aspect 1] to [Aspect 5], wherein the upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean roughness Ra2 of the surface of the chamfered portion is 0.2 μm or less. [Effects of the Invention]

[0009] A semiconductor manufacturing equipment component according to one embodiment of the present invention allows for easy removal of particle sources adhering to the upper surface and / or side wall surface of a ceramic substrate. Therefore, the semiconductor manufacturing equipment component can be shipped with a low residual particle source, contributing to improved semiconductor quality stability and yield. [Brief explanation of the drawing]

[0010] [Figure 1-1] This is a schematic partial longitudinal cross-sectional view of a semiconductor manufacturing apparatus component according to the first embodiment of the present invention (a partial cross-sectional view when cut by a plane including the central axis of the semiconductor manufacturing apparatus component). [Figure 1-2] Figure 1-1 shows a schematic magnified view of the area enclosed by the thick border. [Figure 1-3] This is a schematic plan view of a ceramic substrate according to the first embodiment of the present invention. [Figure 2-1] This is a schematic partial longitudinal cross-sectional view of a semiconductor manufacturing apparatus component according to the second embodiment of the present invention (a partial cross-sectional view when the semiconductor manufacturing apparatus component is cut by a plane including the central axis). [Figure 2-2] Figure 2-1 shows a schematic magnified view of the area enclosed by the thick border. [Figure 2-3] This is a schematic plan view of a ceramic substrate according to a second embodiment of the present invention. [Figure 3-1] Shows a schematic specific example of a texture patterned by laser processing. [Figure 3-2] It is an enlarged view of the No. 1 pattern in FIG. 3-1. [Figure 4] It is a manufacturing process diagram of a member for a semiconductor manufacturing apparatus according to the second embodiment of the present invention.

Mode for Carrying Out the Invention

[0011] Next, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments, and it should be understood that design changes, improvements, etc. can be appropriately made based on the ordinary knowledge of those skilled in the art without departing from the spirit of the present invention. Also, in this specification, "upper" and "lower" are used to conveniently represent the relative positional relationship when the upper surface of the ceramic substrate of the member for a semiconductor manufacturing apparatus is placed on the horizontal plane with the upper side facing up, and do not represent an absolute positional relationship. Therefore, depending on the orientation of the member for a semiconductor manufacturing apparatus, "upper" and "lower" can become "lower" and "upper", "left" and "right", or "front" and "rear".

[0012] <1. Configuration of a Member for a Semiconductor Manufacturing Apparatus> Referring to the partial longitudinal sectional views shown in FIGS. 1-1 and FIGS. 2-1, the member 10 for a semiconductor manufacturing apparatus according to the first and second embodiments of the present invention can be used when performing processes such as CVD and etching on the wafer W using plasma. The member 10 for a semiconductor manufacturing apparatus according to the first and second embodiments includes a ceramic substrate 20 having a reference plane 21b and an upper surface 21 having a plurality of protrusions 22 for placing the wafer W extending upward from the reference plane 21b, and side walls 28a, 28b forming the outer edge of the upper surface 21. Also, the member 10 for a semiconductor manufacturing apparatus according to the first and second embodiments includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and having a built-in refrigerant flow path 32. The ceramic substrate 20 and the base plate 30 can be joined via a joining layer 40.

[0013] The ceramic substrate 20 of the member 10 for a semiconductor manufacturing apparatus according to the first embodiment can have, for example, a diameter of 300 to 400 mm and a thickness of 1 to 6 mm. A wafer W can be placed on the upper surface 21.

[0014] The ceramic substrate 20 of the member 10 for a semiconductor manufacturing apparatus according to the second embodiment includes a central portion 20a having a circular upper surface 21 in plan view, and an outer peripheral portion 20b having an annular upper surface 27 in plan view on the outer periphery of the central portion 20a. The central portion 20a of the ceramic substrate 20 can have, for example, a diameter of 300 to 400 mm and a thickness of 1 to 6 mm. A wafer W can be placed on the upper surface 21 of the central portion 20a, and a focus ring can be placed on the upper surface 27 of the outer peripheral portion 20b. Hereinafter, the focus ring may be abbreviated as "FR". A step formed by the side wall 28b of the central portion 20a is provided between the upper surface 21 of the central portion 20a and the upper surface 27 of the outer peripheral portion 20b, whereby the upper surface 27 of the outer peripheral portion 20b is at a position lower than the upper surface 21 of the central portion 20a. The height (step) of the side wall 28b can be, for example, 0.5 to 5 mm. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b may be on the same plane.

[0015] A plurality of protrusions 22 for placing the wafer W are provided on the upper surface 21 of the ceramic substrate 20 of the first embodiment and the upper surface 21 of the central portion 20a of the ceramic substrate 20 of the second embodiment. Further, a seal band 25 protruding upward from the reference surface 21b may be formed along the outer edge of the upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the seal band 25 and the upper end surfaces 21a of the plurality of protrusions 22. The seal band 25 and the plurality of protrusions 22 are preferably of the same height. As shown in FIGS. 1-3 and FIGS. 2-3, in one embodiment, an annular seal band 25 is formed along the outer edge on the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 22 are formed over the entire inner surface of the seal band 25.

[0016] In both the first and second embodiments of the ceramic substrate 20, it is effective to smooth the reference surface 21b of the upper surface 21 and / or the surfaces of the side walls 28a and 28b in order to easily remove particle sources that may adhere to the surfaces of the upper surface 21 and / or side walls 28a and 28b of the ceramic substrate 20. This is because smoothing the reference surface 21b of the upper surface 21 and / or the surfaces of the side walls 28a and 28b, which have a large area ratio on the surface of the ceramic substrate 20, significantly reduces the number of minute depressions where particle sources such as slurry and processing residues used in machining during the manufacturing process tend to remain.

[0017] As a method for smoothing the surface of the reference surface 21b and / or the side walls 28a, 28b, polishing is preferred. Polishing has the effect of removing minute depressions from the surface, as well as suppressing the formation of a fractured layer and microcracks in the ceramics. More specifically, it is desirable to smooth the surface of the side walls 28a, 28b to the extent that minute depressions where particle sources tend to remain are removed from the surface of the reference surface 21b and / or the side walls 28a, 28b. It is also advantageous to remove the fractured layer, which is the starting point for detachment. The fractured layer is a fragile surface layer consisting of irregularities and cracks that occur during machining, so removing the fractured layer and smoothing the surface can reduce the risk of detachment. As an indicator that minute depressions have been removed, it is preferable that the arithmetic mean roughness Ra1 of the surface of the reference surface 21b and / or the side walls 28a, 28b be 0.2 μm or less, and more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra1 of the reference surface 21b and / or side walls 28a, 28b, but from the viewpoint of cost-effectiveness, it is preferable that it be 0.05 μm or more. Therefore, the arithmetic mean roughness Ra1 of the reference surface 21b and / or side walls 28a, 28b is preferably, for example, 0.05 to 0.2 μm, and more preferably 0.05 to 0.1 μm.

[0018] In both the first and second embodiments, it is preferable that at least one of the surfaces of the reference surface 21b and the side walls 28a, 28b of the ceramic substrate 20 satisfies the above-described arithmetic mean roughness conditions, and it is more preferable that both satisfy the above-described arithmetic mean roughness conditions.

[0019] In the first embodiment, it is preferable that the upper surface 21 and the side wall 28a of the ceramic substrate 20 are connected via a chamfered portion 29. Similarly, in the second embodiment, it is preferable that the upper surface 21 and the side wall 28b of the central portion 20a of the ceramic substrate 20 are connected via a chamfered portion 29. Chamfering the corners of the wafer mounting surface is advantageous from the viewpoint of suppressing the fractured layer at the corners and preventing particle detachment. Examples of the shape of the chamfered portion 29 include, but are not limited to, C-chamfers and R-chamfers. The chamfered portion 29 is a small area but can be affected by plasma during wafer processing, and it is desirable to keep the surface smooth from the viewpoint of removing minute recesses where particle sources tend to remain.

[0020] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean roughness Ra2 of the surface of the chamfered portion 29 is preferably 0.2 μm or less, and more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra2 of the surface of the chamfered portion 29, but from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra2 of the surface of the chamfered portion 29 is preferably, for example, 0.05 to 0.2 μm, and more preferably 0.05 to 0.1 μm.

[0021] Typically, in the second embodiment, both the side walls 28b of the central portion 20a and the upper surface 27 of the outer peripheral portion 20b of the ceramic substrate 20 are formed by machining, such as cutting. After machining, unless special polishing is performed, the side walls 28b of the central portion 20a and the upper surface 27 of the outer peripheral portion 20b have similar surface roughness. However, since the upper surface 27 of the outer peripheral portion 20b is the mounting surface for the focus ring, it is protected by the focus ring, so there is little need to make it smooth. From the standpoint of manufacturing costs, it is desirable not to perform unnecessary polishing on the upper surface 27 of the outer peripheral portion 20b. Therefore, if polishing is performed to smooth the surface of the side walls 28b of the central portion 20a, the arithmetic mean roughness Ra1 of the surface of the side walls 28b of the central portion 20a becomes smaller than the arithmetic mean roughness Ra3 of the upper surface 27 of the outer peripheral portion 20b.

[0022] Thus, the required level of smoothness for the surfaces of the reference surface 21b, the side walls 28a and 28b, and the chamfered portion 29 is approximately the same. Therefore, it is convenient for quality control to perform the same polishing process on these surfaces and set their surface roughness to approximately the same level. Accordingly, the absolute value of the difference between the arithmetic mean roughness Ra2 of the chamfered portion 29 and the arithmetic mean roughness Ra1 of the surfaces of the reference surface 21b and / or side walls 28a and 28b is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. The absolute value of this difference may be 0.

[0023] The arithmetic mean roughness Ra1 of the reference surface 21b, side walls 28a and 28b, the arithmetic mean roughness Ra2 of the chamfered surface 29, and the arithmetic mean roughness Ra3 of the upper surface 27 of the outer perimeter 20b are each measured from the roughness curve with a cutoff value (λc) of 0.8 mm, in accordance with JIS B0601:2013. The arithmetic mean roughness for each measurement location is measured in four directions, changing the measurement direction by 45° clockwise each time, and the average of the measurements taken in the four directions is used as the measurement value. Furthermore, the average of five measurements taken at different measurement locations in each direction is adopted.

[0024] In both the first and second embodiments of the ceramic substrate 20, it is preferable that the surface of the reference surface 21b and / or the side walls 28a, 28b have a periodic roughness curve. By intentionally creating a periodic roughness curve, it is possible to select an appropriate ultrasonic frequency that takes into account the cleaning effect according to the wavelength of the roughness curve when ultrasonically cleaning the surface of the reference surface 21b and / or the side walls 28a, 28b. Conversely, if the roughness curve is non-periodic, it becomes difficult to select the optimal ultrasonic frequency at once, and it becomes necessary to change the frequency while ultrasonically cleaning in order to remove particle sources. In this specification, the "roughness curve" may include a linear component.

[0025] Ultrasonic cleaning is generally performed by immersing the object to be cleaned in a liquid such as acid, alkali, organic solvent, or pure water. When ultrasound is generated in a liquid, numerous cavities (bubbles) are generated by cavitation. The size of the cavity nuclei varies depending on the frequency. The larger the cavity nuclei, the stronger the impact and the higher the cleaning power. However, they become less able to enter into small gaps. Conversely, fine cavities can enter into small gaps but have less cleaning power. Therefore, by increasing the size of the cavity nuclei to increase cleaning power, and by bringing the wavelength closer to the roughness curve of the surface of the reference surface 21b and / or side walls 28a, 28b, the cavities can enter the recesses defined by the roughness curve without excess or deficiency and collide with the surface of the recesses, thereby effectively removing particle sources that may adhere to the recesses.

[0026] When the size of the cavity nuclei is 5 μm or larger, preferably 10 μm or larger, it is easier to obtain high cleaning power against particle sources. Therefore, the average length RSm of the periodic roughness curve on the surface of the reference surface 21b and / or the side walls 28a, 28b is preferably 5 μm or larger, and more preferably 10 μm or larger. On the other hand, there is a limit to the size of the cavity nuclei that can be generated by ultrasound. Also, if the average length RSm is not made excessively large, it is advantageous that particles flying from inside the chamber during wafer processing are more easily captured by the anchoring effect, and the captured particles are less likely to fall off. Therefore, the average length RSm of the periodic roughness curve on the surface of the reference surface 21b and / or the side walls 28a, 28b is preferably 30 μm or less, more preferably 25 μm or less, and even more preferably 20 μm or less. Therefore, the periodic roughness curve on the surface of the reference surface 21b and / or the side walls 28a, 28b is preferably such that the average length RSm is 5 μm or more and 30 μm or less, more preferably 10 μm or more and 25 μm or less, and even more preferably 10 μm or more and 20 μm or less.

[0027] The relationship between the size of the cavity nuclei generated by an ultrasonic cleaning device and the ultrasonic frequency depends on the ultrasonic cleaning device and the type of liquid used. For example, it is possible to generate cavities with nuclei of approximately 16 μm in size at an ultrasonic frequency of 40 kHz, approximately 10 μm at 70 kHz, and approximately 6 μm at 100 kHz. The optimal ultrasonic frequency should be selected according to the average length RSm of the periodic roughness curve on the surface of the reference surface 21b and / or the side walls 28a, 28b. For example, if the average length RSm of the periodic roughness curve is 5 to 20 μm, it is advantageous to use an ultrasonic frequency of 40 kHz to 100 kHz during ultrasonic cleaning.

[0028] The average length RSm on the surface of the reference surface 21b and side walls 28a and 28b is measured from the roughness curve with a cutoff value (λc) of 0.8 mm, in accordance with JIS B0601:2013. The average length RSm for each measurement location is measured in four directions, changing the measurement direction by 45° clockwise each time, and the average of the measurements from the four directions is taken as the measurement value. Furthermore, the average value of five measurements taken at different measurement locations in each direction is adopted.

[0029] On both the reference surface 21b and the surfaces of the side walls 28a and 28b, the average length RSm of the roughness curve is measured in four directions by changing the measurement direction clockwise by 45° each time, and the coefficient of variation (standard deviation divided by the mean) when the average value is calculated is preferably 30% or less, more preferably 10% or less, and even more preferably 5% or less.

[0030] Although the surface of the chamfered portion 29 occupies a small area on the surface of the ceramic substrate 20, it may have a periodic roughness curve with an average length RSm similar to that of the reference surface 21b and / or side walls 28a, 28b. This is thought to further remove particle sources from the surface of the ceramic substrate 20.

[0031] One method for forming a surface with a periodic roughness curve on predetermined parts of the ceramic substrate 20, such as the reference surface 21b, the surfaces of the side walls 28a and 28b, and the surface of the chamfered portion 29, is to form a periodic pattern by laser processing after polishing. Alternatively, after forming a periodic pattern by laser processing, the pattern may be polished to a mirror finish by soft blasting.

[0032] There are no particular restrictions on the periodic pattern of the texture. Figure 3-1 shows four specific examples of textures patterned by laser processing.

[0033] Textures No. 1 and No. 2 have a patterned arrangement of multiple dimples (point-like recesses). While there are no particular restrictions on the peripheral shape of each dimple, it can be a circular, elliptical, racetrack-shaped, or oval-shaped round shape, or a polygonal shape such as a triangular or square shape. Among these, a circular shape is preferred because it exhibits less anisotropy in the average length RSm of the roughness curve, and a high cleaning effect can be expected without switching frequencies during ultrasonic cleaning. In this case, it is preferable that the multiple dimples are evenly arranged on the surface of the reference surface 21b, the side walls 28a, 28b, and / or the surface of the chamfered portion 29. The area of ​​each dimple when viewed from a direction perpendicular to the surface is relatively large, for example, 3 to 20 mm². 2 This can be done (No. 1). Alternatively, the area of ​​each dimple when observed from a direction perpendicular to the surface is relatively small, for example, 0.01 to 0.07 mm. 2 This can be done (No. 2).

[0034] Regardless of the area of ​​each dimple, when a surface having multiple patterned dimples (point-like recesses) is observed from a direction perpendicular to the surface, the shortest distance M between the peripheries of adjacent dimples 12 is preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 20 μm or more, in order to ensure the penetration of cavities by ultrasound (see Figure 3-2). Note that the shortest distance M between the peripheries of adjacent dimples 12 means the shortest distance between a dimple of interest and the dimple with the shortest distance between its peripheries.

[0035] Textures No. 3 and No. 4 have a pattern composed of a mesh-like structure where multiple linear protrusions intersect. In this case, it is preferable that the mesh-like protrusions are evenly arranged on the surface of the reference surface 21b, the side walls 28a, 28b and / or the surface of the chamfered portion 29. It is preferable that they are arranged without bias on the surface. Each mesh of the mesh-like protrusions may be a polygonal shape, such as a triangle, square, pentagon, hexagon, or octagon, although this is not limited to these shapes. Multiple polygonal shapes, such as a pentagon and a triangle, may also be combined. Among these, regular polygons (square for No. 3, regular hexagon for No. 4) are preferred because they have less anisotropy in the average length RSm of the roughness curve and allow for a high cleaning effect without changing the frequency during ultrasonic cleaning. The line width of each linear protrusion when observed from a direction perpendicular to the surface can be, for example, 20 to 200 μm. The area of ​​each mesh when observed from a direction perpendicular to the surface can be, for example, 2000 to 250000 μm. 2 It can be done this way.

[0036] Figures 1-2 and 2-2 show the schematic structure of the projection 22 provided on the upper surface 21 of the ceramic substrate 20 in the first and second embodiments, respectively. The shape of the projection 22 is not limited, but can be a columnar shape such as a cylinder or a rectangular prism. The height h of the projection 22 is, for example, 5 to 100 μm, and can typically be 10 to 30 μm. The diameter d of the projection 22 is, for example, 0.5 to 5 mm, and can typically be 0.5 to 3 mm. Here, the diameter d of the projection 22 refers to the equivalent diameter of a circle when the projection 22 is viewed from above.

[0037] Each of the multiple protrusions 22 has an upper end surface 21a. The wafer W in contact with the upper end surface 21a of the protrusion 22 may slide against the upper end surface 21a of the protrusion 22 due to thermal expansion or the like. To suppress the shedding of ceramic particles constituting the protrusion 22 during sliding, it is desirable to make the upper end surface 21a of the protrusion 22 as smooth as possible.

[0038] Specifically, the arithmetic mean roughness Ra4 of the upper end surfaces 21a of the multiple protrusions 22 is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra4 of the upper end surfaces 21a of the multiple protrusions 22, but from the viewpoint of cost-effectiveness, it is preferably 0.01 μm or more. Therefore, the arithmetic mean roughness Ra4 of the upper end surfaces 21a of the multiple protrusions 22 is preferably 0.01 to 0.4 μm, more preferably 0.01 to 0.2 μm, and even more preferably 0.01 to 0.1 μm.

[0039] For similar reasons, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25, but from the viewpoint of cost-effectiveness, it is preferably 0.01 μm or more. Therefore, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 is preferably 0.01 to 0.4 μm, more preferably 0.01 to 0.2 μm, and even more preferably 0.01 to 0.1 μm.

[0040] The arithmetic mean roughness Ra4 of the upper end surface 21a of the projection 22 and the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 are measured in the same manner as the arithmetic mean roughness Ra1 of the reference surface 21b and / or the side walls 28a, 28b.

[0041] The ceramic substrate 20, including the protrusions 22 and the sealing band 25, can be formed from a ceramic material such as alumina or aluminum nitride. In a preferred embodiment, the ceramic substrate 20 contains one or two selected from alumina and aluminum nitride. In a more preferred embodiment, the ceramic substrate 20 contains 80% by mass or more of one or two selected from alumina and aluminum nitride. In an even more preferred embodiment, the ceramic substrate 20 contains 95% by mass or more of one or two selected from alumina and aluminum nitride.

[0042] Electrode 26 is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). Electrode 26 is formed from a material containing, for example, W, Mo, WC, MoC, etc. A low-pass filter may be placed in the middle of the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to electrode 26, the wafer W is attracted and fixed to the wafer mounting surface, specifically the upper end surface 21c of the seal band 25 and the upper end surface 21a of the projection 22, by electrostatic attraction force. When the DC voltage is removed, the attraction and fixation of the wafer W to the wafer mounting surface are released.

[0043] The electrode 26 may incorporate a heater electrode (resistive heating element) in place of or in addition to the electrostatic adsorption electrode, or it may incorporate an RF electrode for plasma generation. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may have one layer of electrode 26, or it may have two or more layers spaced apart.

[0044] The base plate 30 can be, for example, disc-shaped. The base plate 30 may have an annular flange on its lower side used to clamp the semiconductor manufacturing equipment component 10 to a jig inside the chamber. The thickness of the base plate 30 can be 10 to 30 mm, typically 15 to 30 mm. The base plate 30 can be connected to a radio frequency (RF) power supply and used as an RF electrode.

[0045] The base plate 30 can be a disc with good electrical and thermal conductivity (a disc with the same diameter as or larger than the ceramic substrate 20). A refrigerant channel 32 through which the refrigerant circulates may be formed inside the base plate 30. The refrigerant flowing through the refrigerant channel 32 is preferably a liquid and preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant channel 32 can be formed, for example, in a single continuous line from one end (inlet) to the other end (outlet) across the entire base plate 30 in a plan view. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant channel 32, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant channel 32 passes through the refrigerant channel 32, returns to the recovery port of the external refrigerant device from the other end of the refrigerant channel 32, is temperature-adjusted, and then supplied again from the supply port to one end of the refrigerant channel 32.

[0046] The base plate 30 can be made of, for example, a metallic material or a composite material of metal and ceramics. Examples of metallic materials include Al, Ti, Mo, or alloys thereof. Examples of composite materials of metal and ceramics include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include materials containing Si, SiC, and Ti (also called SiSiCTi), materials in which Al and / or Si are impregnated into a porous SiC body, and composite materials of Al2O3 and TiC. A material in which Al is impregnated into a porous SiC body is called AlSiC, and a material in which Si is impregnated into a porous SiC body is called SiSiC. It is preferable to select a material for the base plate 30 that has a coefficient of thermal expansion close to that of the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, and the base plate 30 is a composite material of metal and ceramics, it is preferable that the base plate 30 be made of SiSiCTi or AlSiC, which have a coefficient of thermal expansion close to that of alumina, and if it is a metallic material, Al or Ti is preferable.

[0047] As shown in Figures 1-1 and 2-1, the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be composed of a metal layer formed from, for example, solder or metal brazing material. The bonding layer 40 is formed, for example, by TCB (Thermal Compression Bonding). TCB is a known method in which a metal bonding material is sandwiched between two members to be bonded, and the two members are pressed together while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of a metal layer. The resin bonding layer can be composed of, for example, a cured product of a silicone resin adhesive, epoxy resin adhesive, acrylic resin adhesive, or urethane resin adhesive.

[0048] At least one of the sides of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the sides of the base plate 30 can be covered with an insulating film 60. Examples of insulating films 60 include thermal spray films of alumina or yttria.

[0049] In the first and second embodiments, the semiconductor manufacturing equipment member 10 may have a plurality of holes that penetrate the semiconductor manufacturing equipment member 10 in the vertical direction. Such holes include a plurality of gas holes 50 that open to the upper surface 21 and lift pin holes for inserting lift pins to move the wafer W up and down on the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see Figures 1-3 and 2-3). A heat-conducting gas such as He gas is supplied to the gas holes 50. Typically, the gas holes 50 can be provided to open to a portion of the upper surface 21 where the seal band 25 and the plurality of protrusions 22 are not provided (reference surface 21b). When heat-conducting gas is supplied to the gas holes 50, the space on the back side of the wafer W placed on the upper surface 21 is filled with heat-conducting gas. A plug 55 having a gas flow path may be embedded in the gas holes 50. Multiple lift pin holes can be provided at equal intervals along concentric circles on the upper surface 21 when the upper surface 21 is viewed from above.

[0050] <2. Method of using components for semiconductor manufacturing equipment> Next, a representative example of how to use the semiconductor manufacturing equipment component 10 will be described. First, with the semiconductor manufacturing equipment component 10 installed in a chamber (not shown), the wafer W is placed on the upper surface 21 of the ceramic substrate 20. Then, the pressure inside the chamber is reduced using a vacuum pump to adjust to a predetermined vacuum level, and a voltage is applied to the electrodes 26 of the ceramic substrate 20 to generate electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface (specifically, the upper end surface 21c of the seal band 25 and the upper end surface 21a of the projection 22).

[0051] Next, the chamber is transformed into a reaction gas atmosphere at a predetermined pressure (e.g., several tens to several hundred Pas). In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) located on the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment component 10 to generate plasma. The surface of the wafer W is then treated with the generated plasma.

[0052] <3. Examples of manufacturing components for semiconductor manufacturing equipment> Next, an example of the manufacturing of the semiconductor manufacturing equipment component 10 will be illustrated using Figure 4. Here, an example of the manufacturing of the semiconductor manufacturing equipment component 10 according to the second embodiment shown in Figure 2-1 will be described. First, a disc-shaped ceramic sintered body 120, which will be the basis for the ceramic substrate 20, is manufactured by hot-press firing a molded body of ceramic powder (Figure 4A). The molded body may be manufactured by stacking multiple tape molded bodies, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 contains electrodes 26.

[0053] Next, after polishing the upper surface of the ceramic sintered body 120, multiple protrusions 22 and sealing bands 25 are provided by blasting or laser processing (Figure 4B). This makes it possible to smooth the upper end surfaces 21a of the multiple protrusions 22. As for the polishing method, lapping is one option, but it is preferable to perform polishing in addition to lapping. Diamond slurry can be used for lapping, and colloidal silica can be used for polishing. Furthermore, multiple protrusions 22 and sealing bands 25 are formed on the upper surface of the ceramic sintered plate by laser processing or the like. The timing of forming the multiple protrusions 22 and sealing bands 25 may be after the bonding of the ceramic substrate 20 and the base plate 30.

[0054] In parallel with this, two disc members 131 and 136 are manufactured (Figure 4C). Then, a groove 132, which will ultimately become the refrigerant flow path 32, is formed on the lower surface of the upper disc member 131 by machining (Figure 4D). A through hole 133 for refrigerant introduction and a through hole 134 for refrigerant discharge are made in the lower disc member 136 (Figure 4D).

[0055] Next, a bonding material 135 is placed between the lower surface of the upper disc member 131 and the upper surface of the lower disc member 136, and a bonding material 137 is placed on the upper surface of the upper disc member 131. Then, the ceramic sintered body 120 is placed on top of the bonding material 137 placed on the upper surface of the upper disc member 131. This results in a laminated body 110 in which the lower disc member 136 and bonding material 135, the upper disc member 131 and bonding material 137, and the ceramic sintered body 120 are stacked in this order from bottom to top (Figure 4E). By heating and pressurizing this laminated body 110, a bonded body is obtained. The bonded body is formed by joining the ceramic sintered body 120 to the upper surface of the block 130 that will become the base plate 30 via a bonding layer. The block 130 is formed by joining the upper disc member 131 and the lower disc member 136 via a bonding layer. Block 130 has a refrigerant flow path 32, a refrigerant inlet 36, and a refrigerant outlet 38.

[0056] The base plate 30 can be made from metal and joined to the ceramic sintered body 120 using a resin adhesive sheet as a bonding material. Alternatively, the base plate 30 may be made from MMC and joined to the ceramic sintered body 120 by TCB using a metal bonding material.

[0057] Furthermore, when a metal bonding material is used to form the bonding layer 40, the insulating film 60 can be formed by thermal spraying onto the base plate 30 either before or after bonding with the ceramic substrate 20. When a resin adhesive sheet is used to form the bonding layer 40, the resin melts, so the insulating film 60 is formed by thermal spraying before bonding with the ceramic substrate 20.

[0058] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, thereby creating a ceramic substrate 20 having a central portion 20a and an outer peripheral portion 20b. Then, the surface of the reference surface 21b, the side walls 28a and 28b, and / or the surface of the chamfered portion 29 are smoothed. As a method of smoothing, polishing by a machining center using fine grinding wheels or wet blasting can be employed. Next, a surface with a periodic roughness curve is formed on the smoothed surface by laser processing. After that, residual particle sources are removed by ultrasonic cleaning at an appropriate frequency corresponding to the average length RSm of the periodic roughness curve. This gives rise to a semiconductor manufacturing equipment component 10 (Figure 4F).

[0059] Although the base plate 30 in Figure 1 is shown as a single piece, it may also be a structure in which two members are joined by a bonding layer, as shown in Figure 4F, or a structure in which three or more members are joined by a bonding layer. [Explanation of Symbols]

[0060] 10: Components for semiconductor manufacturing equipment 12: Dimple 20: Ceramic substrate 20a: Central part 20b: Outer periphery 21:Top surface 21a: Upper end surface 21b: Reference plane 21c: Upper end surface 22: Protrusion 23: Bottom surface 25: Seal band 26: Electrode 27:Top surface 28a: Side wall 28b: Side wall 29: Chamfered section 30: Base plate 31:Top surface 32: Refrigerant flow path 36: Refrigerant inlet 38: Refrigerant discharge part 40: Bonding layer 50: Gas hole 55: Plug 60: Insulating film 110: Laminate 120: Ceramic sintered body 130: Block 131: Disc member 132: Groove 133: Through hole 134: Through hole 135: Bonding material 136: Disc member 137: Bonding material

Claims

1. A ceramic substrate having a reference surface, an upper surface having a plurality of wafer-supporting protrusions extending upward from the reference surface, and a side wall forming the outer edge of the upper surface, wherein the surface of the reference surface and / or the side wall has an arithmetic mean roughness Ra 1 A component for semiconductor manufacturing equipment, comprising a ceramic substrate having a periodic roughness curve with a surface thickness of 0.2 μm or less and an average length RSm of 5 μm or more.

2. The semiconductor manufacturing apparatus component according to claim 1, wherein the surface of the reference surface and / or the side wall has a periodic roughness curve with an average length RSm of 5 μm or more and 30 μm or less.

3. The semiconductor manufacturing apparatus component according to claim 1, wherein the periodic roughness curve is due to the surface of the reference surface and / or the side wall having a plurality of patterned dimples.

4. The semiconductor manufacturing apparatus component according to claim 3, wherein the shortest distance between the peripheries of adjacent dimples is 5 μm or more.

5. The semiconductor manufacturing apparatus component according to claim 1, wherein the surface of the reference surface and / or the surface of the side wall is laser processed.

6. The upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean roughness Ra of the surface of the chamfered portion 2 The semiconductor manufacturing apparatus component according to claim 1, wherein the diameter is 0.2 μm or less.

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