Memory systems and information processing systems

Abstract

We provide a memory system and information processing system that incorporates measures to prevent soft errors. [Solution] The memory system comprises a non-volatile memory chip and a controller that controls the non-volatile memory chip. The non-volatile memory chip has a first storage unit that stores address translation information that translates logical addresses to physical addresses and management information that the controller uses to manage the non-volatile memory chip, and a second storage unit that stores a copy of the address translation information and the management information stored in the first storage unit for each first cycle, and the controller controls whether or not to reflect the copy information stored in the second storage unit in the first storage unit.

Description

Technical Field

[0001] One embodiment of the present invention relates to a memory system and an information processing system.

Background Art

[0002] Artificial satellites have different orbits according to their usage purposes. For example, a low orbit such as 300 km to 2,000 km from the ground is often used for civil artificial satellites. Since the radiation dose of cosmic rays is less in the low orbit than in the high orbit, it has been considered to use general-purpose electronic components similar to those on the ground for electronic devices used in the low orbit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, an embodiment of the present invention provides a memory system and an information processing system with countermeasures against soft errors.

Means for Solving the Problems

[0005] In order to solve the above problems, according to one embodiment of the present invention, there is provided a non-volatile memory chip, a controller for controlling the non-volatile memory chip, wherein the controller stores address conversion information for converting a logical address into a physical address and management information for the controller to manage the non-volatile memory chip in a first storage unit of the non-volatile memory chip, For each first cycle, the address translation information and the management information stored in the first storage unit are stored in the second storage unit of the non-volatile memory chip. Determine whether or not to reflect the copy information stored in the second storage unit in the first storage unit. A memory system is provided. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing the schematic configuration of an information processing system equipped with a memory system according to one embodiment. [Figure 2] A flowchart illustrating the processing operation of the memory system according to this embodiment. [Figure 3] A flowchart illustrating the processing operation of a memory system according to a first modified example of this embodiment. [Figure 4] A flowchart illustrating the processing operation of the information processing system according to a second modified example of this embodiment. [Figure 5] A flowchart illustrating the processing operation of an information processing system according to a third modification of this embodiment. [Modes for carrying out the invention]

[0007] The following description will focus on the main components of the memory system and information processing system, with reference to the drawings. While the following description will primarily focus on the main components of the memory system and information processing system, there may be other components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0008] Figure 1 is a block diagram showing the schematic configuration of an information processing system 2 equipped with a memory system 1 according to one embodiment. The memory system 1 and information processing system 2 according to this embodiment are intended for use not only in various electronic devices used on Earth, but also in various electronic devices mounted on artificial satellites located in low Earth orbit at an altitude of 300 km to 2,000 km above the Earth. Since the amount of radiation, such as cosmic rays, is greater in low Earth orbit than on Earth, the memory system 1 and information processing system 2 according to this embodiment are equipped with countermeasures against radiation.

[0009] The information processing system 2 shown in Figure 1, according to one embodiment, comprises a memory system 1, a host device 3, and a power management chip 4. The memory system 1 according to this embodiment is, for example, an SSD (Solid State Drive) 5 using NAND flash memory (hereinafter referred to as NAND memory). Alternatively, the memory system 1 according to this embodiment may be, for example, an AFA (All Flash Array), a UFS (Universal Flash Storage) device, an MMC (Multi Media Card), or an SD TM This embodiment is also applicable to memory systems consisting of a memory chip and a memory controller, such as cards and USB (Universal Serial Bus) memory. Furthermore, the memory system 1 according to this embodiment is also applicable to systems using non-volatile memory other than NAND memory (for example, MRAM: Magnetoresistive Random Access Memory, ReRAM: Resistive Random Access Memory, PRAM: Phase-change Random Access Memory, etc.) and a memory controller. Below, we will mainly describe an example in which the memory system 1 according to one embodiment is an SSD 5 using NAND memory.

[0010] As shown in Figure 1, the SSD 5 has a NAND memory chip 6 and an SSD controller 7. The NAND memory chip 6 has multiple NAND memory units. More specifically, the NAND memory chip 6 has a first storage unit 11 and a second storage unit 12. Both the first storage unit 11 and the second storage unit 12 are constructed using NAND memory.

[0011] The SSD controller 7 stores address translation information, which converts logical addresses to physical addresses, and management information, which the SSD controller 7 uses to manage the NAND memory chip 6, in the first storage unit 11. The SSD controller 7 updates the address translation information and management information stored in the first storage unit 11 at any time.

[0012] The SSD controller 7 stores a copy of the address translation information and management information stored in the first storage unit 11 in the second storage unit 12 at the beginning of each cycle. Furthermore, the copy information may be stored in the second storage unit 12 each time the information in the first storage unit 11 is updated. The second storage unit 12 may also store a copy of user data stored in the NAND memory chip 6 along with the address translation information and management information. User data includes, for example, at least one of the following: the operating system program, the application software program running on the operating system, data used by the operating system, or data used by the application software.

[0013] The NAND memory chip 6 has a third storage unit 13 for storing firmware. As will be described later, when the SSD 5 is started up, the SSD controller 7 reads and executes the firmware stored in the third storage unit 13. Firmware is a program that controls the SSD 5 and is executed by the CPU within the SSD controller 7.

[0014] The SSD controller 7 controls the NAND memory chip 6 and communicates with the host device 3 by executing firmware. Specifically, the SSD controller 7 updates the address translation information and management information stored in the first storage unit 11 at any given time, and controls the storage of a copy of the address translation information and management information stored in the first storage unit 11 in the second storage unit 12 every first cycle.

[0015] Furthermore, the SSD controller 7 decides whether or not to reflect the copy information stored in the second storage unit 12 to the first storage unit 11. If the SSD controller 7 determines that a soft error has occurred due to radiation such as cosmic rays, it reflects the copy information stored in the second storage unit 12 to the first storage unit 11. For example, the SSD controller 7 determines whether or not a soft error due to radiation has occurred for a time period of two or more cycles, which is shorter than the first cycle in which the second storage unit 12 stores the copy information of the first storage unit 11. Alternatively, the SSD controller 7 may determine whether or not a soft error due to radiation has occurred by communicating with the host device 3. When the copy information stored in the second storage unit 12 is reflected in the first storage unit 11, the address translation information and management information of the first storage unit 11 used by the SSD controller 7 are updated with the copy information stored in the second storage unit 12. Hereinafter, the SSD controller 7 may be referred to as the controller or memory controller.

[0016] The host device 3 makes an access request to the SSD 5. The host device 3 issues various commands to the SSD 5 indicating the type of access request. The host device 3 can issue various commands such as writing data to the SSD 5, reading data from the SSD 5, and erasing data from the SSD 5. The host device 3 may also send a special command or a signal using a communication line to the SSD controller 7 to request that the duplicate information stored in the second storage unit 12 be reflected in the first storage unit 11.

[0017] The SSD 5 and the host device 3 perform high-speed serial transmission in accordance with, for example, the communication standard of PCI (Peripheral Component Interconnect) Express. Note that the communication standard between the SSD 5 and the host device 3 is arbitrary, and a communication standard other than PCI Express may be adopted.

[0018] The SSD controller 7 has a plurality of storage units. These plurality of storage units may be built in the SSD controller 7 or may be connected to the SSD controller 7. Hereinafter, an example in which the plurality of storage units include a fourth storage unit 14 and a fifth storage unit 15 and these fourth storage unit 14 and fifth storage unit 15 are built in the SSD controller 7 will be described.

[0019] The fourth storage unit 14 stores firmware for controlling the SSD controller 7. When the SSD 5 is powered on or reset, the SSD controller 7 saves the firmware stored in the third storage unit 13 of the NAND memory chip 6 to the fourth storage unit 14. Thereafter, the SSD controller 7 reads out and executes the firmware stored in the fourth storage unit 14.

[0020] The fifth storage unit 15 stores address conversion information for converting the logical address issued by the host device 3 into a physical address of the NAND memory chip 6 and management information for the controller to manage the NAND memory chip 6. The address conversion information includes, for example, a lookup table (LUT). The lookup table is an address conversion table between a logical address and a physical address. The management information includes write / erase count information of the NAND memory and bad block information including address information of a broken block.

[0021] When the SSD 5 is powered on and the firmware is executed, the SSD controller 7 refers to the address translation information and management information stored in the fifth storage unit 15. The SSD controller 7 also updates at least one of the address translation information or management information stored in the fifth storage unit 15 as needed. When the SSD controller 7 updates at least one of the address translation information or management information, it reflects the updated address translation information and management information in the first storage unit 11 of the NAND memory chip 6. As will be described later, the first storage unit 11 may store multiple sets of address translation information and management information as a pair, separated by generation. In this case, the SSD controller 7 stores the updated pair of address translation information and management information in the first storage unit 11 separately from the previous pairs of address translation information and management information.

[0022] The SSD controller 7 may store at least one of the updated address translation information or management information in the first storage unit 11 whenever at least one of the address translation information or management information is updated, or it may store the latest address translation information and management information stored in the fifth storage unit 15 in the first storage unit 11 at predetermined intervals.

[0023] For example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) can be used for the fourth memory unit 14 and the fifth memory unit 15. Although SRAM can write and read at higher speeds than NAND memory, it is more susceptible to soft errors caused by radiation such as cosmic rays. The SSD controller 7 updates the address translation information and management information stored in the fifth memory unit 15 as needed, and the updated address translation information and management information are reflected in the first memory unit 11 of the NAND memory chip 6. Furthermore, if the SSD controller 7 determines that the firmware stored in the fourth memory unit 14 has experienced a soft error, it first resets the power to the SSD 5. If it still cannot recover from the error state, the SSD 5 is initialized, the firmware stored in the third memory unit 13 of the NAND memory chip 6 is saved to the fourth memory unit 14, and the firmware saved in the fourth memory unit 14 is executed to avoid the effects of the soft error.

[0024] The SSD controller 7 determines whether a soft error caused by radiation such as cosmic rays has occurred by communicating with the host device 3. If the host device 3 is operating normally, it will make an access request to the SSD 5 immediately before and then make another access request within a predetermined period. Therefore, the SSD controller 7 can determine whether a soft error caused by radiation has occurred within the SSD controller 7 by whether or not the host device 3 made an access request to the SSD 5 within the predetermined period.

[0025] The power management chip 4 resets or initializes the power to the SSD 5 according to instructions from the host device 3. When the SSD controller 7 determines that a soft error has occurred due to radiation such as cosmic rays, it reflects the copy information stored in the second storage unit 12 to the first storage unit 11. During initialization, the SSD controller 7 stores the firmware stored in the third storage unit 13 of the NAND memory chip 6 in the fourth storage unit 14 and executes it. At that time, it stores and references the address translation information and management information stored in the first storage unit 11 of the NAND memory chip 6 in the fifth storage unit 15.

[0026] Figure 2 is a flowchart showing the processing operation of the memory system 1 according to this embodiment. The flowchart in Figure 2 starts after the host device 3 is powered on and the initialization of the SSD 5 is completed.

[0027] The SSD controller 7 copies the firmware stored in the third storage unit 13 of the NAND memory chip 6 to the fourth storage unit 14, and copies the address translation information and management information stored in the first storage unit 11 of the NAND memory chip 6 to the fifth storage unit 15, and then reads the firmware from the fourth storage unit 14 and executes it (step S1).

[0028] Once the initialization process for SSD5 is complete, the host device 3 requests access to SSD5, such as writing or reading data, at predetermined intervals. For example, when writing data to SSD5, the host device 3 issues a command, address, and data. Since the address issued by the host device 3 is a logical address, the SSD controller 7 converts the logical address to a physical address based on the address translation information described above. The SSD controller 7 also determines where to write the data from the host device 3, avoiding bad blocks, based on management information. This interval can also be changed while using SSD5.

[0029] The SSD controller 7 writes data to a memory block containing a specific physical address of the NAND memory chip 6, and then performs a verification to confirm whether the data was written correctly. If the verification is unsuccessful, the memory block on which the data was written is added to the management information as a bad block. In this case, the SSD controller 7 updates the management information of the first storage unit 11.

[0030] The SSD controller 7 stores a copy of the address translation information and management information stored in the first storage unit 11 in the second storage unit 12 at the beginning of each cycle (step S2). In addition, whenever at least one of the address translation information or management information stored in the first storage unit 11 is updated, the SSD controller 7 stores a copy of the updated address translation information and management information in the second storage unit 12.

[0031] The SSD controller 7 determines whether the host device 3 has made an access request to the SSD 5 within a predetermined period (step S3). The length of the predetermined period is arbitrary, but for example, the SSD controller 7 may determine whether the host device 3 has made an access request to the SSD 5 every two cycles, which are less than or equal to the length of the first cycle.

[0032] When initializing the SSD 5, the SSD controller 7 copies the firmware stored in the third storage unit 13 of the NAND memory chip 6 to the fourth storage unit 14 of the SSD controller 7 and executes it. The fourth storage unit 14 is composed of SRAM or DRAM, which can read and write faster than the third storage unit 13, which is composed of NAND memory, but it is more susceptible to soft errors caused by radiation than NAND memory. When a soft error occurs, bit inversion occurs, preventing the SSD controller 7 from executing the firmware correctly. Therefore, if a soft error occurs due to radiation, even if the host device 3 makes any access requests to the SSD 5, the SSD 5 may not be able to respond to those access requests. In this case, the host device 3 uses the power management chip 4 to reset the power to the SSD 5, restarts it, and then makes an access request to the SSD 5. If the SSD 5 still does not recover, the host device 3 continues to wait for a response from the SSD 5 and stops making access requests to the SSD 5 within a predetermined period. Thus, step S3 described above becomes NO.

[0033] Thus, in this embodiment, it is assumed that if a permanent error caused by a soft error occurs in the firmware, the SSD 5 will stop responding to access requests from the host device 3, and thereafter, the host device 3 will stop making access requests to the SSD 5 within a predetermined period. Therefore, in step S3, if the host device 3 does not make an access request to the SSD 5 within the predetermined period, it is determined that a permanent error caused by a soft error has occurred in the firmware executed by the SSD controller 7.

[0034] If step S3 is NO, the SSD controller 7 determines that a soft error has occurred due to radiation and performs a power reset operation (step S4). During the power reset operation, the power to the SSD 5 is cut off and then restored, so the contents of the fourth storage unit 14 and the fifth storage unit 15 in the SSD controller 7, which are composed of SRAM or DRAM, are erased. Then, the address translation information and management information stored in the first storage unit 11 are copied to the fifth storage unit 15, and the firmware stored in the third storage unit 13 is stored in the fourth storage unit 14.

[0035] Next, similar to step S3, it is determined whether the host device 3 accessed SSD 5 within a predetermined period after the power reset operation (step S5). If step S5 is YES, it is determined that the soft error has been resolved by the power reset operation, and the process in Figure 2 is terminated. If step S5 is NO, the copy information stored in the second storage unit 12 is reflected in the first storage unit 11 (step S6). Since a soft error in the firmware may cause the first storage unit 11 to be updated with inappropriate address translation information and management information, the address translation information and management information from before the soft error occurred are reflected from the second storage unit 12 to the first storage unit 11.

[0036] After the processing in step S6 is completed, the power management chip 4 initializes the SSD 5 (step S7). As a result, the SSD controller 7 reads and executes the firmware stored in the third storage unit 13 of the NAND memory chip 6, and in doing so, refers to the address translation information and management information stored in the first storage unit 11 (step S8). More specifically, the SSD controller 7 copies the firmware stored in the third storage unit 13 to the fourth storage unit 14, and copies the address translation information and management information stored in the first storage unit 11 to the fifth storage unit 15. The SSD controller 7 then reads and executes the firmware from the fourth storage unit 14, and in doing so, refers to the address translation information and management information stored in the fifth storage unit 15.

[0037] When the process in step S8 is completed, or when it is determined in step S3 or S5 that the host device 3 has made an access request to SSD5 within a predetermined period, the process in the flowchart of Figure 2 is terminated. The process in the flowchart of Figure 2 is repeated as long as the host device 3 is powered on.

[0038] Figure 3 is a flowchart showing the processing operation of the memory system 1 according to a first modified example of this embodiment. Steps S11 to S15 in Figure 3 are the same as steps S1 to S5 in Figure 2. If NO is determined in step S15, the SSD controller 7 sends a predetermined command to the host device 3 (step S16).

[0039] The SSD controller 7 determines whether the host device 3 responded to the command sent in step S16 (step S17). Steps S16 and S17 are performed to confirm whether communication between the SSD controller 7 and the host device 3 is performed correctly. If step S17 is NO, that is, if the host device 3 did not respond, the same processing as in steps S6 to S8 is performed (steps S18 to S20).

[0040] If it is determined in step S13 or S15 that the host device 3 has made an access request to the SSD5 within a predetermined period, or if it is determined in step S17 that the host device 3 has responded to the command, the process shown in the flowchart of Figure 3 is terminated. The process shown in the flowchart of Figure 3 is repeated as long as the host device 3 is powered on.

[0041] Figure 4 is a flowchart showing the processing operation of the information processing system 2 according to a second modified example of this embodiment. In the information processing system 2 according to the second modified example, once the initialization of the SSD 5 is complete, the host device 3 requests access to the SSD 5 every second cycle.

[0042] In steps S21 and S22 of Figure 4, the same processes as in steps S1 and S2 of Figure 2 are performed. Once the initialization of SSD5 is complete, the host device 3 repeatedly performs an operation to request access to SSD5 every second cycle (step S23).

[0043] The SSD controller 7 determines whether the host device 3 will not access the SSD 5 even after the second cycle has elapsed (step S24). More specifically, in step S24, the determination is made based on a time period of two or more cycles but less than the first cycle, starting from the time when the host device 3 made an access request. If the determination in step S24 is YES, the same processing as in steps S4 to S8 in Figure 2 is performed (steps S25 to S29).

[0044] Thus, assuming that the host device 3 requests access to the SSD 5 every two cycles when the SSD controller 7 is not experiencing a soft error, the SSD controller 7 determines whether or not there was an access request from the host device 3 within a time period of two or more cycles but less than one cycle. If it is determined that there was no access request, the SSD controller 7 determines that a soft error caused by radiation has occurred.

[0045] If the process in step S29 is completed, or if it is determined in step S24 that the host device 3 has made an access request to SSD5 before the second cycle has elapsed, or if it is determined in step S26 that the host device 3 has accessed SSD5 within a predetermined period, the process in the flowchart of Figure 4 is terminated. The process in the flowchart of Figure 4 is repeated as long as the host device 3 is powered on.

[0046] Figure 5 is a flowchart showing the processing operation of the information processing system 2 according to a third modified example of this embodiment. Steps S31 to S36 in Figure 5 perform the same processing as steps S21 to S26 in Figure 4. If NO is determined in step S36, the SSD controller 7 sends a predetermined command to the host device 3 (step S37).

[0047] The SSD controller 7 determines whether the host device 3 responded to the command sent in step S37 (step S38). If the host device 3 did not respond, the same processing as in steps S4 to S6 is performed (steps S39 to S41).

[0048] As described above, in the process shown in Figure 5, the SSD controller 7 determines whether or not there was an access request from the host device 3 for a time period of two or more cycles but less than the first cycle. If it is determined that there was no access request, it sends a predetermined command to the host device 3. If the host device 3 does not respond to the predetermined command, it determines that a permanent error caused by a soft error due to radiation has occurred.

[0049] If it is determined in step S34 that the host device 3 has made an access request to SSD5 before the second cycle has elapsed, or if it is determined in step S36 that the host device 3 has accessed SSD5 within a predetermined period, or if it is determined in step S38 that the host device 3 has responded to the command, the process shown in the flowchart of Figure 5 is terminated. The process shown in the flowchart of Figure 5 is repeated as long as the host device 3 is powered on.

[0050] In the information processing system 2 shown in Figures 2 to 5, an example is shown in which the second storage unit 12 of the NAND memory chip 6 stores one set of duplicated address translation information and management information. However, the second storage unit 12 may store multiple sets of address translation information and management information for each generation. In this case, when the SSD 5 is initialized, the latest set of duplicated information stored in the second storage unit 12 is reflected in the first storage unit 11 and the firmware is restarted. If the SSD controller 7 still does not operate normally, the second newest set of duplicated information stored in the second storage unit 12 overwrites the first storage unit 11 and the firmware is restarted. The sets of address translation information and management information to be duplicated from the second storage unit 12 to the first storage unit 11 are switched sequentially until the SSD controller 7 operates normally.

[0051] This allows the firmware to be executed by reflecting the address translation information and management information immediately before the soft error occurred in the first storage unit 11, even if it is unclear when the soft error occurred.

[0052] Thus, in this embodiment, if the host device 3 does not request access to the SSD 5 within a predetermined period, the SSD controller 7 determines that a permanent error caused by a soft error has occurred, reflects the address translation information and management information stored in the second storage unit 12 of the NAND memory chip 6 to the first storage unit 11, and then initializes the SSD 5. As a result, the firmware stored in the third storage unit 13 of the NAND memory chip 6 is read and executed by the SSD controller 7. Therefore, even if the firmware stored in the fourth storage unit 14 of the SSD controller 7 undergoes a bit inversion due to a soft error, the firmware can be overwritten and executed again, thus avoiding the effects of a permanent error caused by a soft error. Furthermore, even if there is a bit inversion error in the management information reflected from the fifth storage unit 15 of the SSD controller 7 to the first storage unit 11 of the NAND memory chip 6, the copy information stored in the second storage unit 12 before the error occurred is copied to the fifth storage unit 15 via the first storage unit 11, so the effects of a permanent error caused by a soft error can also be avoided with respect to the management information.

[0053] According to the memory system 1 and information processing system 2 of this embodiment, even if the SRAM or DRAM built into or connected to the SSD controller 7 experiences a soft error, the firmware can be read and executed from the NAND memory chip 6 after a reset, thus avoiding malfunctions due to soft errors. Therefore, the memory system 1 and information processing system 2 of this embodiment can be used in artificial satellites in the low Earth orbit, where the rate of soft errors is higher than on Earth. Thus, the cost of materials for artificial satellites can be reduced, and the reliability of the satellite's internal systems can be improved.

[0054] [Note] [Item 1] Non-volatile memory chips and The system includes a controller for controlling the non-volatile memory chip, The aforementioned controller, Address translation information for converting logical addresses to physical addresses and management information for the controller to manage the non-volatile memory chip are stored in the first storage unit of the non-volatile memory chip. For each first cycle, the address translation information and the management information stored in the first storage unit are stored in the second storage unit of the non-volatile memory chip. Determine whether or not to reflect the copy information stored in the second storage unit in the first storage unit. Memory system. [Item 2] When the controller determines that a soft error has occurred due to radiation, it reflects the duplicated information stored in the second storage unit to the first storage unit. The memory system described in item 1. [Item 3] The controller determines whether or not a soft error caused by radiation has occurred over a time period of two or more cycles, which is shorter than the first cycle. The memory system described in item 2. [Item 4] The controller determines whether or not a soft error caused by radiation has occurred in the second or later cycle, and for a shorter time period than the first cycle. The memory system described in item 3. [Item 5] The controller determines whether or not a soft error caused by radiation has occurred through communication with the host device. The memory system described in item 3 or 4. [Item 6] If no soft error occurs, the host device will make an access request to the non-volatile memory chip every second cycle. The controller determines whether or not there was an access request from the host device over a period of time equal to or greater than the second cycle, and if it is determined that there was no access request, it determines that a soft error caused by radiation has occurred. The memory system described in item 5. [Item 7] The controller determines whether or not an access request has been received from the host device within a period of two or more cycles. If it determines that no access request has been received, it sends a predetermined command to the host device. If the host device does not respond to the predetermined command, it determines that a soft error caused by radiation has occurred. The memory system described in item 6. [Item 8] The controller stores the past multiple copies of the information in the second storage unit. If there is no access request from the host device, the controller prioritizes reading the most recently stored copy information from the second storage unit and reflects it in the first storage unit. A memory system as described in any one of items 5 through 7. [Item 9] The controller restarts the firmware by reading the replicated information stored in the second storage unit in order from the most recent until an access request is received from the host device. The memory system described in item 8. [Item 10] The controller stores the copy information in the second storage unit whenever at least one of the address translation information or the management information stored in the first storage unit is updated. A memory system as described in any one of items 1 through 9. [Item 11] The controller stores in the second storage unit, for each first cycle, the copy information of the address translation information and management information stored in the first storage unit and the user data stored in the non-volatile memory chip. A memory system as described in any one of items 1 through 10. [Item 12] The user data includes at least one of the following: a program for the operating system, a program for application software running on the operating system, data used by the operating system, or data used by the application software. The memory system described in item 11. [Item 13] The non-volatile memory chip has a third storage unit in which firmware for controlling the controller is stored. The controller reads and executes the firmware stored in the third storage unit when the non-volatile memory chip is started up or reset. A memory system as described in any one of items 1 through 12. [Item 14] When the controller reads the firmware stored in the third storage unit, it reads the address translation information and the management information stored in the first storage unit and executes the firmware. The memory system described in item 13. [Item 15] After the duplicated information stored in the second storage unit is reflected in the first storage unit, the non-volatile memory chip is reset. The memory system described in item 13 or 14. [Item 16] The aforementioned controller, A fourth storage unit that stores the firmware read from the third storage unit, It has a fifth storage unit that stores the address translation information and management information read from the first storage unit, The fourth and fifth memory units have a higher probability of experiencing soft errors due to radiation than the non-volatile memory chip. A memory system as described in any one of items 13 through 15. [Item 17] The fourth and fifth memory units are SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), The aforementioned non-volatile memory chip is flash memory. The memory system described in item 16. [Item 18] The controller, upon determining that a soft error has occurred due to radiation, performs a power reset operation to erase the contents of the fourth and fifth storage units, and then determines whether the soft error has been resolved. If it determines that the soft error has not been resolved, it reflects the duplicated information stored in the second storage unit into the first storage unit. The memory system described in item 16 or 17. [Item 19] When the controller updates at least one of the address translation information or the management information, it stores at least one of the updated address translation information or the management information in the first storage unit. A memory system as described in any one of items 1 through 18. [Item 20] The memory system and, The system comprises a host device connected to the memory system, The aforementioned memory system Non-volatile memory chips and The system includes a controller for controlling the non-volatile memory chip, The aforementioned controller, Address translation information that converts logical addresses to physical addresses and management information that the controller uses to manage the non-volatile memory chip are stored in the first storage unit of the non-volatile memory chip. For each first cycle, the address translation information and the management information stored in the first storage unit are stored in the second storage unit of the non-volatile memory chip. Determine whether or not to reflect the copy information stored in the second storage unit in the first storage unit. Information processing system. [Item 21] The system includes a power management device that performs control for initializing the memory system, When the host device determines that a soft error has occurred due to radiation, it instructs the power management device to initialize the memory system. The non-volatile memory chip has a third storage unit that stores firmware for controlling the controller, When the controller initializes the non-volatile memory chip under the control of the power management device, it reflects the copy information stored in the second storage unit to the first storage unit, and then reads and executes the firmware stored in the third storage unit. The information processing system described in item 20. [Item 22] The memory system is located in the low Earth orbit zone. Information processing systems as described in item 20 or 21.

[0055] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0056] 1 Memory system, 2 Information processing system, 3 Host device, 4 Power management chip, 6 NAND memory chip, 7 SSD controller, 11 First storage unit, 11 Memory system, 12 Second storage unit, 13 Third storage unit, 14 Fourth storage unit, 15 Fifth storage unit

Claims

1. Non-volatile memory chips and The system includes a controller for controlling the non-volatile memory chip, The aforementioned controller, Address translation information for converting logical addresses to physical addresses and management information for the controller to manage the non-volatile memory chip are stored in the first storage unit of the non-volatile memory chip. For each first cycle, the address translation information and the management information stored in the first storage unit are stored in the second storage unit of the non-volatile memory chip. A determination is made as to whether or not to reflect the copy information stored in the second storage unit in the first storage unit. Memory system.

2. When the controller determines that a soft error has occurred due to radiation, it reflects the duplicated information stored in the second storage unit to the first storage unit. The memory system according to claim 1.

3. The controller determines whether or not a soft error caused by radiation has occurred within a time period of two or more cycles, which is shorter than the first cycle. The memory system according to claim 2.

4. The controller determines whether or not a soft error caused by radiation has occurred in the second or later cycle, and for a time period shorter than the first cycle. The memory system according to claim 3.

5. The controller determines whether or not a soft error caused by radiation has occurred through communication with the host device. The memory system according to claim 3.

6. If no soft error occurs, the host device will make an access request to the non-volatile memory chip at each of the second cycles. The controller determines whether or not there was an access request from the host device over a period of time equal to or greater than the second cycle, and if it is determined that there was no access request, it determines that a soft error caused by radiation has occurred. The memory system according to claim 5.

7. The controller determines whether or not an access request has been received from the host device within a period of two or more cycles. If it determines that no access request has been received, it sends a predetermined command to the host device. If the host device does not respond to the predetermined command, it determines that a soft error caused by radiation has occurred. The memory system according to claim 6.

8. The controller stores the past multiple copies of the information in the second storage unit. If there is no access request from the host device, the controller prioritizes reading the most recently stored copy information from the second storage unit and reflects it in the first storage unit. The memory system according to claim 5.

9. The controller restarts the firmware by reading the replicated information stored in the second storage unit in order from the most recent until an access request is received from the host device. The memory system according to claim 8.

10. The controller stores the copy information in the second storage unit whenever at least one of the address translation information or the management information stored in the first storage unit is updated. The memory system according to claim 1.

11. The controller stores in the second storage unit, for each first cycle, the copy information of the address translation information and management information stored in the first storage unit and the user data stored in the non-volatile memory chip. The memory system according to claim 1.

12. The user data includes at least one of the following: a program for the operating system, a program for application software running on the operating system, data used by the operating system, or data used by the application software. The memory system according to claim 11.

13. The non-volatile memory chip has a third storage unit in which firmware for controlling the controller is stored. The controller reads and executes the firmware stored in the third storage unit when the non-volatile memory chip is started up or reset. The memory system according to claim 1.

14. When the controller reads the firmware stored in the third storage unit, it reads the address translation information and the management information stored in the first storage unit and executes the firmware. The memory system according to claim 13.

15. After the duplicated information stored in the second storage unit is reflected in the first storage unit, the non-volatile memory chip is reset. The memory system according to claim 13.

16. The aforementioned controller, A fourth storage unit that stores the firmware read from the third storage unit, It has a fifth storage unit that stores the address translation information and management information read from the first storage unit, The fourth and fifth memory units have a higher probability of experiencing soft errors due to radiation than the non-volatile memory chip. The memory system according to claim 13.

17. The fourth and fifth storage units are SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), The aforementioned non-volatile memory chip is flash memory. The memory system according to claim 16.

18. When the controller determines that a soft error has occurred due to radiation, it performs a power reset operation to erase the contents of the fourth and fifth storage units, and then determines whether the soft error has been resolved. If it determines that the soft error has not been resolved, it reflects the duplicated information stored in the second storage unit into the first storage unit. The memory system according to claim 16.

19. When the controller updates at least one of the address translation information or the management information, it stores at least one of the updated address translation information or the management information in the first storage unit. The memory system according to claim 1.

20. The memory system and The system comprises a host device connected to the memory system, The aforementioned memory system Non-volatile memory chips and The system includes a controller for controlling the non-volatile memory chip, The aforementioned controller, Address translation information that converts logical addresses to physical addresses and management information that the controller uses to manage the non-volatile memory chip are stored in the first storage unit of the non-volatile memory chip. For each first cycle, the address translation information and the management information stored in the first storage unit are stored in the second storage unit of the non-volatile memory chip. A determination is made as to whether or not to reflect the copy information stored in the second storage unit in the first storage unit. Information processing system.

21. The system includes a power management device that performs control for initializing the memory system, When the host device determines that a soft error has occurred due to radiation, it instructs the power management device to initialize the memory system. The non-volatile memory chip has a third storage unit that stores firmware for controlling the controller, When the controller initializes the non-volatile memory chip under the control of the power management device, it reflects the copy information stored in the second storage unit to the first storage unit, and then reads and executes the firmware stored in the third storage unit. The information processing system according to claim 20.

22. The memory system is located in the low Earth orbit zone. The information processing system according to claim 20.

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