Disk drive

Abstract

One embodiment aims to provide a disk device capable of appropriately managing information stored in non-volatile memory. [Solution] According to one embodiment, a disk device having a non-volatile memory and a controller is provided. The controller is accessible to the non-volatile memory. The non-volatile memory has an error correction circuit and a storage area. The storage area has a first area, a second area and a third area. The first area includes a plurality of blocks. If the first block among the plurality of blocks contains a bit that becomes a collectible error in the error correction process by the error correction circuit, the controller replaces the information of the first block in the first area and stores it in the second area, and creates or updates address substitution information and stores it in the third area. The address substitution information associates the address of the first block in the first area with the address of the first block in the second area.

Description

Technical Field

[0001] This embodiment relates to a disk device.

Background Art

[0002] In a disk device having a non-volatile memory and a controller, information used by the controller may be stored non-volatily in the non-volatile memory. In a disk device, it is desirable to appropriately manage information stored in the non-volatile memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a disk device capable of appropriately managing information stored in a non-volatile memory.

Means for Solving the Problems

[0005] According to one embodiment, a disk device is provided having non-volatile memory and a controller. The controller is accessible to the non-volatile memory. The non-volatile memory has an error correction circuit and a storage area. The storage area has a first area, a second area and a third area. The first area includes a plurality of blocks. If the first block among the plurality of blocks contains a bit that becomes a collectible error in the error correction process by the error correction circuit, the controller replaces the information of the first block in the first area and stores it in the second area, and creates or updates address substitution information and stores it in the third area. The address substitution information associates the address of the first block in the first area with the address of the first block in the second area. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing the configuration of a disk device according to an embodiment. [Figure 2] A diagram showing the configuration of the non-volatile memory in the embodiment. [Figure 3] A diagram showing the configuration of a memory cell array in an embodiment. [Figure 4] A diagram showing the configuration and generation of address substitution information in an embodiment. [Figure 5] A diagram illustrating the updating of address alternative information in an embodiment. [Figure 6] A flowchart illustrating the inspection process in the embodiment. [Figure 7] A flowchart illustrating the startup process in the embodiment. [Figure 8] A flowchart showing the inspection process in a modified embodiment. [Figure 9] A diagram showing the configuration and updating of address alternative information in a modified embodiment. [Figure 10] A flowchart showing the startup process in a modified embodiment. [Modes for carrying out the invention]

[0007] A disk device according to an embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to this embodiment.

[0008] (Embodiment) The disk device according to this embodiment includes a non-volatile memory and a controller. Information used by the controller may be stored non-volatilely in the non-volatile memory, and measures are taken to appropriately manage the information stored in the non-volatile memory.

[0009] The disk drive 1 may be configured as shown in Figure 1. Figure 1 is a diagram showing the configuration of the disk drive 1.

[0010] Disk device 1 is connected to host 2 via a communication medium and functions as an external storage medium for host 2.

[0011] Disk device 1 is a disk-type storage medium such as an HDD (Hard Disk Drive) or a magneto-optical disk drive. The communication medium may be a serial communication line. Host 2 is, for example, an information terminal such as a computer.

[0012] Disk device 1 transmits data read from disk medium 11 to host 2 based on read commands received from host 2, and writes data to disk medium 11 based on write commands and data received from host 2.

[0013] The disk device 1 includes a head disk assembly (HDA) 10, a driver 20, a head amplifier 30, a volatile memory 70, a non-volatile memory 80, and a controller 90.

[0014] The controller 90 comprehensively controls each part of the disk device 1. The controller 90 may be configured as a single-chip integrated circuit (system-on-a-chip). The controller 90 includes a read / write channel (RWC) 40, a hard disk controller (HDC) 50, and a processor 60.

[0015] The HDA10 is housed in a housing (not shown). The HDA10 has a disk medium 11, a spindle motor (SPM) 12, a voice coil motor (VCM) 13, a pivot 14, an arm 15, and a head 19.

[0016] The example shown in the HDA10 of FIG. 1 has one disk medium 11 and one head 19 installed respectively, but one or more of each may be provided.

[0017] The disk medium 11 is a disk-shaped recording medium, which may be a magnetic disk or a magneto-optical disk. The disk medium 11 is attached to the SPM 12 and rotates by the drive of the SPM 12. The SPM 12 is installed in the housing (not shown) of the disk device 1.

[0018] The disk medium 11 has a plurality of tracks TR set. The plurality of tracks TR are arranged concentrically. In FIG. 1, three tracks TR are illustrated as an example.

[0019] In each track TR, a plurality of servo areas SA and data areas DA may be alternately arranged. In FIG. 1, servo area SA1, data area DA1, servo area SA2, data area DA2, servo area SA3, and data area DA3 are illustrated as an example.

[0020] Servo information is written in each servo area SA. Data is written in each data area DA.

[0021] The VCM 13 is an actuator, and rotates the arm 15 about the pivot 14 based on the current or voltage input from the driver 20.

[0022] The pivot 14 is a bearing for supporting the arm 15 and the like and for causing rotational movement and the like.

[0023] The arm 15 supports the head 19 via the slider 18. The arm 15 transmits power from the VCM 13 to the head 19, driving the head 19 radially into the disk medium 11.

[0024] A micro-actuator 17 is connected to the suspension 16.

[0025] The microactuator (MA) 17 adjusts the position of the head 19, such as tracking control, based on the input current or voltage.

[0026] The slider 18 is equipped with a head 19.

[0027] The head 19 writes data to the disk medium 11 and reads data recorded on the data track of the disk medium 11.

[0028] The head 19 has a write element 19W that writes data to the disk medium 11 and a read element 19R that reads data recorded on the data track of the disk medium 11.

[0029] The driver 20 outputs current or voltage to drive and control the SPM12, VCM13, MA17, etc., under the control of the controller 90.

[0030] The head amplifier 30 includes a read amplifier and a write driver. The read amplifier amplifies the read signal read from the disk medium 11 and outputs it to the RWC 40. The write driver outputs a write current to the head 19 corresponding to the signal output from the RWC 40.

[0031] The RWC40 controls the head amplifier 30 to read data from the disk medium 11 and write data to the disk medium 11, in response to instructions from the HDC50, processor 60, etc.

[0032] The RWC40 receives read signals from the head amplifier 30, extracts read data, generates write signals based on write data issued by write commands, and outputs them to the head amplifier 30.

[0033] The RWC40 also has a function to measure the signal quality of the read data received from the head amplifier 30. The R / W channel 40 may extract position information of the head 19 based on the servo information received from the head amplifier 30.

[0034] HDC50 is the interface between disk device 1 and host 2. HDC50 may consist of a processing unit (processor) equipped with arithmetic functions such as a CPU, an IC chip equipped with other computing functions and various types of memory, a system LSI, an FPGA, etc.

[0035] The various processes of the HDC50 may be performed by software programs (including firmware, etc.), or they may be provided as hardware or a combination of software and hardware.

[0036] The HDC50 receives commands such as a data write command from the host 2 to the disk medium 11 and a data read command from the disk medium 11. Based on the received commands, the HDC50 controls various parts of the disk device 1 and transfers data between the host 2 and the RWC40. The HDC50 may also control the writing of data to the volatile memory 70 and the non-volatile memory 80.

[0037] The processor 60 controls each part of the disk drive 1. The processor 60 may be composed of an IC chip equipped with a CPU, other computing functions, various types of memory, a system LSI, an FPGA, or the like.

[0038] The processor 60 controls the disk device 1 according to firmware pre-stored in the non-volatile memory 80 and disk media 11. The firmware includes initial firmware and control firmware used for normal operation.

[0039] The initial firmware, which is executed first at startup, is stored in non-volatile memory 80.

[0040] The control firmware used for normal operation is recorded on the disk medium 11, and is read from the disk medium 11 and temporarily stored in the volatile memory 70 by control according to the initial firmware.

[0041] The volatile memory 70 temporarily stores information necessary for processing in the disk device 1. The volatile memory 70 is, for example, DRAM (Dynamic Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory).

[0042] The non-volatile memory 80 is a semiconductor memory that records information in a non-volatile manner. The non-volatile memory 80 may include flash memory. The flash memory may include serial NAND flash memory.

[0043] The non-volatile memory 80 may be configured as shown in Figure 2. Figure 2 is a diagram showing the configuration of the non-volatile memory 80.

[0044] The non-volatile memory 80 includes a memory cell array 81, peripheral circuits 82, error correction circuits 83, and an input / output interface 84.

[0045] The peripheral circuit 82 includes a row decoder 821, a sense amplifier 822, a data register 823, a column decoder 824, a status register 825, an address register 826, a command register 827, a control circuit 828, and a voltage generation circuit 829.

[0046] The input / output interface 84 includes an input / output control circuit 841, a logic circuit 842, and a data register 843.

[0047] The memory cell array 81 has multiple non-volatile memory cells associated with rows and columns. Memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line.

[0048] Data reads and writes are performed simultaneously on multiple memory cells connected to the same word line. The unit in which data is read and written is called a page.

[0049] Multiple memory cells connected to the same word line correspond to one or more pages. If each memory cell can store n bits, then multiple memory cells connected to the same word line correspond to n pages. One page of data includes net data and management data. Net data is managed in units called sectors.

[0050] For example, one page contains four sectors, and each sector has a data size of 512 bytes. Management data includes, for example, ECC data (parity) for error correction.

[0051] Error correction is performed sector by sector. Therefore, the management data includes ECC data prepared for each sector.

[0052] Furthermore, data erasure is performed in batches of multiple pages. This unit of data erasure is called a block.

[0053] The row decoder 821 decodes the row direction and page address of the memory cell array 81, specifying the page. Then, it selects the word line and page according to the decoding result and applies the voltage required for writing, reading, and erasing data.

[0054] When reading data, the sense amplifier 822 senses the data read from the memory cell array 81 and transfers it to the data register 823. When writing data, it transfers the data in the data register 823 to the memory cell array 81.

[0055] Data register 823 temporarily holds one page's worth of write or read data.

[0056] The column decoder 824 decodes the column address that specifies the column direction of the memory cell array 81. Then, depending on the decoding result, it transfers the data to the data register 823 when writing, and reads the data from the data register 823 when reading.

[0057] The error correction circuit 83 performs error correction processing. This error correction processing includes error correction coding processing and error correction decoding processing. Error correction processing is also called ECC (Error Correction Code) processing.

[0058] When data is written, the error correction circuit 83 performs error correction coding. Based on the data received from the controller 90 via the input / output interface 84, the error correction circuit 83 generates parity for each sector and transfers the pair of this parity and the net data as a codeword to the data register 823.

[0059] When reading data, the error correction circuit 83 performs error correction decoding. Based on the parity contained in the codeword transferred from the data register 823, the error correction circuit 83 generates a syndrome for each sector of data contained in the codeword and detects the presence or absence of errors.

[0060] When an error is detected, the error correction circuit 83 checks whether the number of error bits exceeds the number of error bits that can be corrected. For example, the number of error bits that can be corrected per sector is 8 bits.

[0061] Furthermore, the error correction circuit 83 can output the number of error bits detected in each sector as status information to the status register 825.

[0062] The error correction circuit 83 identifies the bit location of an error if the number of error bits is less than or equal to the number of error bits that can be corrected, and corrects the error. The error correction circuit 83 supplies the corrected data to the data register 843 and supplies a collectible error notification signal to the controller 90 via the data register 843 and the input / output control circuit 841.

[0063] If the error correction circuit 83 determines that the number of error bits exceeds the number of error bits that can be corrected, it treats it as an uncorrectable error and supplies an uncorrectable error notification signal to the controller 90 via the data register 843 and input / output control circuit 841.

[0064] Logic circuit 842 receives signals / CE, CLE, ALE, / WE, / RE, and / WP from controller 90.

[0065] The input / output control circuit 841 receives the signal IO[n:0]. If the signal IO is an address (ALE="H"), the input / output control circuit 841 stores it in the address register 826.

[0066] Furthermore, if the signal IO is a command (CLE="H"), it is stored in the command register 827. If the signal IO is data (ALE=CLE="L"), it is stored in the data register 843.

[0067] If a collectable error notification signal is held in the data register 843, the input / output control circuit 841 transmits the collectable error notification signal to the controller 90.

[0068] The status register 825 holds various status information of the non-volatile memory 80. This status information includes the number of error bits provided by the error correction circuit 83, and information from the control circuit 828 indicating whether the write and erase operations were successful (passed) or failed (failed).

[0069] The control circuit 828 controls the entire non-volatile memory 80 based on the commands held in the command register 827 and various signals input to the logic circuit 842. The control circuit 828 also generates a ready / busy signal / RB and outputs it to the controller 90.

[0070] The voltage generation circuit 829 generates the voltages necessary for data write, read, and erase operations based on instructions from the control circuit 828, and supplies them to the memory cell array 81, the row decoder 821, and the sense amplifier 822.

[0071] As shown in Figure 3, the memory cell array 81 has a storage area 811 and a redundant area 812. Figure 3 is a diagram showing the configuration of the memory cell array 81, where a horizontal rectangle represents one error correction unit. In the following, we will illustrate the case where the error correction unit by the error correction circuit 83 is a page, but the error correction unit may be a memory cell group in which multiple pages are grouped together for each word line, or it may be a block in which multiple pages are grouped together for multiple word lines and are erased all at once.

[0072] The storage area 811 is an area where information can be stored by the controller 90, and the redundant area 812 is an area used for error correction. The storage area 811 may also store management information by the controller 90. The management information includes management information related to the startup of the disk device 1.

[0073] The storage area 811 includes a firewall area 811a and a parameter area 811b. The firewall area 811a and the parameter area 811b may each be assigned and managed by the controller 90 with physical addresses. The physical addresses may include block addresses, page addresses, and offsets within pages.

[0074] Figure 3 illustrates a case where physical addresses PA_1 to PA_i are assigned to the FW area 811a, and physical addresses PA_i+1 to PA_j are assigned to the parameter area 811b. i is any integer greater than or equal to 3. j is any integer greater than or equal to 3 than i.

[0075] The firmware area 811a stores the firmware for disk device 1. This firmware may be the initial firmware that is executed first when disk device 1 is started. The parameter area 811b stores the parameters for disk device 1. These parameters may be startup parameters that are applied to the initial firmware when disk device 1 is started.

[0076] For example, if the controller 90 in disk drive 1 is unable to read the initial firmware from the non-volatile memory 80, or is unable to read the startup parameters from the non-volatile memory 80, disk drive 1 cannot be started normally, and failure analysis becomes difficult.

[0077] In response, the controller 90 performs error correction processing as a read check of the FW area 811a and parameter area 811b at predetermined inspection timings. Before an uncorrectable error occurs during the error correction process, the controller 90 disables the area as soon as a correctable error occurs, assigns an address to another area where no correctable errors are registered, and stores the error-corrected data there. As a result, read errors in FW / parameters and other areas can be reduced, and startup failures of the disk device 1 can be avoided.

[0078] In other words, the storage area 811 further includes an alternative area 811c and an alternative management area 811d. The alternative area 811c and the alternative management area 811d may each be assigned a physical address and managed by the controller 90.

[0079] Figure 3 illustrates a case where physical addresses PA_j+1 to PA_k are assigned to the alternate area 811c, and physical addresses PA_k+1 to PA_n are assigned to the alternate management area 811d. k is any integer greater than or equal to 3 than j. n is any integer greater than or equal to 2 than k.

[0080] When data is written, in response to a write command from the controller 90, the error correction circuit 83 generates and stores the data and its parity. The data register 823 then stores the data in the storage area 811 and the parity in the redundant area 812. At this time, the physical address of the data in the storage area 811 and the physical address of the parity in the redundant area 812 are associated (for example, by being assigned the same page address).

[0081] For example, if a codeword containing data D1, which is part of the firmware, and its parity P1 is stored in the data register 823, the sense amplifier 822 stores data D1 in physical address PA_1 in the FW area 811a and parity P1 in physical address PA_1' in the redundant area 812. Physical addresses PA_1 and PA_1' are associated (for example, by being on the same page address).

[0082] If a codeword containing data D2 and its parity P2, which are other parts of the firmware, is stored in the data register 823, the sense amplifier 822 stores data D2 in physical address PA_2 in FW area 811a and parity P2 in physical address PA_2' in redundant area 812. Physical addresses PA_2 and PA_2' are associated (for example, by being on the same page).

[0083] If a codeword containing data Di and its parity Pi, which are other parts of the firmware, is stored in data register 823, sense amplifier 822 stores data Di at physical address PA_i in FW area 811a and parity Pi at physical address PA_i' in redundant area 812, where n is any integer greater than or equal to 3. Physical addresses PA_i and PA_i' are associated (for example, by being on the same page).

[0084] When a codeword containing data Di+1 and its parity Pi+1, which are part of the parameters, is stored in data register 823, sense amplifier 822 stores data Di+1 at physical address PA_i+1 in parameter area 811b and parity Pi+1 at physical address PA_i+1' in redundant area 812, where i is any integer greater than or equal to 3. Physical addresses PA_i+1 and PA_i+1' are associated (for example, by being on the same page).

[0085] When a codeword containing data Di+2 and its parity Pi+2, which are part of the parameters, is stored in the data register 823, the sense amplifier 822 stores the data Di+2 at physical address PA_i+2 in the parameter area 811b and the parity Pi+2 at physical address PA_i+2' in the redundant area 812. Physical addresses PA_i+2 and PA_i+2' are associated (for example, by being considered to be the same page address).

[0086] When a codeword containing data Dj and its parity Pj, which are part of the parameters, is stored in the data register 823, the sense amplifier 822 stores the data Dj at physical address PA_j in the parameter area 811b and the parity Pj at physical address PA_j' in the redundancy area 812. Physical addresses PA_j and PA_j' are associated (for example, by being considered to be the same page address).

[0087] The alternate area 811c stores error-corrected data as a replacement when a collectible error occurs in the data of the FW area 811a and / or the parameter area 811b. Accordingly, address replacement information 813 is stored in the alternate management area 811d. The address replacement information 813 is information for managing that error-corrected data has been stored in the alternate area 811c as a replacement for the data in the FW area 811a and / or the parameter area 811b.

[0088] Figure 3 illustrates a case where a collectible error occurs in data D2 in the FW area 811a. The error correction circuit 83 corrects the error in data D2 using parity P2 and generates parity P2 for the corrected data D2''. The error correction circuit 83 transfers the codeword containing data D2'' and parity P2'' to the data register 823 and supplies a collectible error notification signal to the controller 90 via the data register 843 and input / output control circuit 841.

[0089] At this time, the controller 90 may instruct the non-volatile memory 80 to generate address substitution information 813 and store it in the substitution management area 811d. For example, the controller 90 may generate address substitution information 813 on the volatile memory 70 as shown in Figure 4. Figure 4 is a diagram showing the configuration and generation of address substitution information 813.

[0090] Address substitution information 813 associates the source physical address, the destination physical address, and a completion flag for one or more source physical addresses. Address substitution information 813 may be implemented in the form of a table. Address substitution information 813 has a source address field 8131, a destination address field 8132, and a completion flag field 8133. The source address field 8131 records the physical address of the source data. The destination address field 8132 records the physical address of the destination data. The completion flag field 8133 records whether the substitution is complete or not. The completion flag field 8133 may record 0 to indicate incompleteness or 1 to indicate completion.

[0091] When the controller 90 receives a collectable error notification signal for data D2 in FW area 811a, it records the physical address PA_1 of data D2 in the alternative source address field 8131 and records 0 in the corresponding completion flag field 8133, as shown in Figure 4(a). In response to the collectable error notification signal, the controller 90 instructs the non-volatile memory 80 to store data D2'' in the alternative area 811c. In response to this instruction, the control circuit 828 determines that the storage location for data D2'' in data register 823 is the physical address PA_j+1 in the alternative area 811c. The control circuit 828 transfers the physical address PA_j+1 to data register 823. The error correction circuit 83 notifies the controller 90 of the physical address PA_j+1 via data register 843 and input / output control circuit 841.

[0092] When controller 90 receives the physical address PA_j+1, it records the physical address PA_j+1 of data D2" in the alternate address field 8132 corresponding to the alternate source address PA_1, as shown in Figure 4(b).

[0093] In the non-volatile memory 80, the sense amplifier 822 receives notification of the physical address PA_j+1 from the control circuit 828. In response, the sense amplifier 822 stores the data D2'' in the data register 823 at the physical address PA_j+1 in the alternate area 811c, and stores the parity P2'' in the data register 823 at the physical address PA_j+1' in the redundant area 812. The physical addresses PA_j+1 and PA_j+1' are associated (for example, by being considered to be the same page address). The sense amplifier 822 forwards the alternate completion notification signal to the data register 823. The error correction circuit 83 supplies the alternate completion notification signal to the controller 90 via the data register 843 and the input / output control circuit 841.

[0094] When the controller 90 receives a replacement completion notification signal, it records 1 in the completion flag field 8133 corresponding to the replacement source address "PA_1" and the replacement destination address "PA_j+1", as shown in Figure 4(c).

[0095] This makes it possible to replace data D2 in FW area 811a with data D2" in alternative area 811c. The control circuit 828 can access data D2" at physical address PA_j+1 by referring to address substitution information 813, replacing data D2 at physical address PA_1.

[0096] Figure 3 illustrates the case where a collectible error occurs in the data Di+1 in the parameter region 811b. The error correction circuit 83 corrects the error in data Di+1 using parity Pi+1 and generates parity Pi+1" for the corrected data Di+1". The error correction circuit 83 transfers the codeword containing data Di+1" and parity Pi+1" to the data register 823 and supplies a collectible error notification signal to the controller 90 via the data register 843 and input / output control circuit 841.

[0097] At this time, the controller 90 instructs the non-volatile memory 80 to update the address substitution information 813 and store it in the substitution management area 811d. For example, the controller 90 may update the address substitution information 813 on the volatile memory 70 as shown in Figure 5. Figure 5 is a diagram showing the update of the address substitution information 813.

[0098] When the controller 90 receives a collectable error notification signal for data Di+1 in FW area 811a, it records the physical address PA_i+1 of data Di+1 in the alternative source address field 8131 and records 0 in the corresponding completion flag field 8133, as shown in Figure 5(a). In response to the collectable error notification signal, the controller 90 instructs the non-volatile memory 80 to store data Di+1” in the alternative area 811c. In response to this instruction, the control circuit 828 determines that the storage location for data Di+1” in data register 823 is the physical address PA_j+2 in the alternative area 811c. The control circuit 828 transfers the physical address PA_j+2 to data register 823. The error correction circuit 83 notifies the controller 90 of the physical address PA_j+2 via data register 843 and input / output control circuit 841.

[0099] When controller 90 receives the physical address PA_j+2, it records the physical address PA_j+2 of data D2" in the alternate address field 8132 corresponding to the alternate source address PA_i+1, as shown in Figure 5(b).

[0100] In the non-volatile memory 80, the sense amplifier 822 receives notification of the physical address PA_j+2 from the control circuit 828. In response, the sense amplifier 822 stores the data Di+1'' in data register 823 at physical address PA_j+2 in the alternate area 811c, and stores the parity Pi+1'' in data register 823 at physical address PA_j+2' in the redundant area 812. Physical addresses PA_j+2 and PA_j+2' are associated (for example, by being considered to be the same page address). The sense amplifier 822 forwards the alternate completion notification signal to data register 823. The error correction circuit 83 supplies the alternate completion notification signal to the controller 90 via data register 843 and input / output control circuit 841.

[0101] When the controller 90 receives a replacement completion notification signal, it records 1 in the completion flag field 8133 corresponding to the replacement source address "PA_i+1" and the replacement destination address "PA_j+2", as shown in Figure 5(c).

[0102] This makes it possible to substitute the data Di+1 in parameter area 811b with the data Di+1'' in alternative area 811c. The control circuit 828 can then refer to the address substitution information 813 to substitute the data Di+1 in physical address PA_i+1 with the data Di+1'' in physical address PA_j+2 and access the data Di+1'' in physical address PA_j+2.

[0103] Next, the inspection process of the non-volatile memory 80 by the controller 90 will be explained using Figure 6. Figure 6 is a flowchart of the inspection process.

[0104] The controller 90 waits until it is time for the inspection (No in S1). The inspection timing may be when a predetermined period has elapsed since the last inspection, when disk device 1 is started up, when management information related to the startup of disk device 1 is acquired, or when disk device 1 is idle. The predetermined period can be experimentally determined in advance as an appropriate cycle for performing the inspection.

[0105] When it is time to check (Yes in S1), the controller 90 selects an access location in the FW area 811a and parameter area 811b of the non-volatile memory 80 (S2). The controller 90 may also select an unselected physical address from the entire area of ​​the FW area 811a and parameter area 811b as the access location. The controller 90 issues a read command containing the selected physical address and supplies it to the non-volatile memory 80.

[0106] In response to a read command, the non-volatile memory 80 reads the stored information from the physical address selected in S2 (S3) and reads the parity from the corresponding area of ​​the redundant area 812. The non-volatile memory 80 uses the parity to perform error correction and decoding processing on the read information using the error correction circuit 83 (S4) and notifies the controller 90 of the result.

[0107] If no collectible error occurs during the error correction decoding process by the error correction circuit 83 (No in S5), the controller 90 proceeds to S11.

[0108] If a collectible error occurs during the error correction decoding process by the error correction circuit 83 (Yes in S5), the controller 90 registers the address of the error location in the address substitution information 813 (S6).

[0109] For example, in the error correction decoding process by the error correction circuit 83, if a collectable error occurs in the data of the FW area 811a or the parameter area 811b, the non-volatile memory 80 corrects the error in the data using parity and generates parity for the corrected data. The non-volatile memory 80 holds a codeword containing the data and parity and notifies the controller 90 of the collectable error.

[0110] If the reported collectible error is the first collectible error, the controller 90 may create address substitution information 813 on the volatile memory 70, as shown in Figure 4(a), and register the address where the error occurred as the source address in the address substitution information 813.

[0111] Alternatively, if the reported collectible error is the second or subsequent collectible error, the controller 90 may update the address substitution information 813 by registering the address of the error location as the source address in the address substitution information 813, as shown in Figure 5(a).

[0112] The controller 90 determines the storage location in the alternative area 811c of the non-volatile memory 80 (S7).

[0113] For example, if the unused physical address in the alternative area 811c is PA_j+1, the controller 90 determines that PA_j+1 is the alternative physical address for the original alternative address registered in S5.

[0114] Alternatively, if the unused physical address in the alternative area 811c is PA_j+2, the controller 90 determines PA_j+2 to be the alternative physical address for the original alternative address registered in S5.

[0115] The controller 90 further registers the address of the storage location in the address alternative information 813 (S8).

[0116] For example, if the physical address of the storage location determined in S8 is PA_j+1, the controller 90 records the physical address PA_j+1 of data D2" in the alternate address field 8132 corresponding to the alternate source address "PA_1", as shown in Figure 4(b).

[0117] Alternatively, if the physical address of the storage location determined in S8 is PA_j+2, the controller 90 records the physical address PA_j+2 of data D2" in the alternate address field 8132 corresponding to the alternate source address PA_i+1, as shown in Figure 5(b).

[0118] The controller 90 refers to the address substitution information 813 and issues a move command to the non-volatile memory 80 to move the information of the error location in the FW area 811a and / or parameter area 811b of the non-volatile memory 80 to the storage location in the substitution area 811c (S9).

[0119] For example, if the address substitution information 813 registers the source address "PA_1" and the destination address "PA_j+1" as incomplete substitutions, as shown in Figure 4(b), the controller 90 issues a move command instructing the movement of data from physical address "PA_1" to physical address "PA_j+1" and supplies it to the non-volatile memory 80.

[0120] In response to the move command, the non-volatile memory 80 reads the data at physical address "PA_1" and writes the read data to the physical address "PA_j+1" in the alternate area 811c.

[0121] Alternatively, if the address substitution information 813 registers the source address "PA_i+1" and the destination address "PA_j+2" as incomplete substitutions, as shown in Figure 5(b), the controller 90 issues a move command instructing the movement of data from physical address "PA_i+1" to physical address "PA_j+2" and supplies it to the non-volatile memory 80.

[0122] In response to the move command, the non-volatile memory 80 reads the data at physical address "PA_i+1" and writes the read data to the physical address "PA_j+2" in the alternate area 811c.

[0123] The controller 90 registers the completion of the address substitution in the address substitution information 813 (S10).

[0124] For example, when the non-volatile memory 80 writes data to the physical address "PA_j+1" of the alternate area 811c in response to a move command, it notifies the controller 90 that the alternate is complete. In response to this notification, the controller 90 records 1 in the completion flag field 8133 corresponding to the alternate source address "PA_1" and the alternate destination address "PA_j+1", as shown in Figure 4(c).

[0125] Alternatively, when the non-volatile memory 80 writes data to the physical address "PA_j+2" of the alternate area 811c in response to a move command, it notifies the controller 90 that the alternate is complete. In response to this notification, the controller 90 records 1 in the completion flag field 8133 corresponding to the alternate source address "PA_i+1" and the alternate destination address "PA_j+2", as shown in Figure 5(c).

[0126] The controller 90 determines whether there are any unselected access locations among the physical addresses of the entire area of ​​the FW area 811a and the parameter area 811b (S11).

[0127] If the controller 90 finds any unselected physical addresses among the physical addresses in the entire area of ​​the FW region 811a and the parameter region 811b, it determines that there are unselected access locations (Yes in S11) and returns the process to S2.

[0128] If there are no unselected physical addresses among the physical addresses of the entire area of ​​the FW region 811a and the parameter region 811b, the controller 90 will terminate processing, stating that there are no unselected access locations (No in S11).

[0129] Next, the startup process of the disk device 1 by the controller 90 will be explained using Figure 7. Figure 7 is a flowchart of the startup process. Figure 7 illustrates the startup process after the inspection process shown in Figure 6 has been performed and the system has been shut down.

[0130] The controller 90 waits until the disk drive 1 is powered on (No in S21). The controller 90 may determine that the disk drive 1 is not powered on if the power supply voltage received from the power supply circuit (not shown) inside the disk drive 1 is below a threshold. The controller 90 may determine that the disk drive 1 is powered on if the power supply voltage received from the power supply circuit inside the disk drive 1 is above a threshold.

[0131] When the disk device 1 is powered on (Yes in S21), the controller 90 starts the startup sequence (S22), issues a startup command, and supplies it to the non-volatile memory 70.

[0132] In response to the startup command, the non-volatile memory 70 reads the address translation information 813 from the alternative management area 811d and returns it to the controller 90. The controller 90 stores the address translation information 813 in the volatile memory 70.

[0133] The controller 90 selects an access location in the non-volatile memory 80 (S23). For example, the controller 90 may select an unselected physical address from the areas where information in the FW area 811a and the parameter area 811b is stored (the entire storage area) as the access location.

[0134] If the access location selected in S23 is registered in the address translation information 813 (Yes in S24), the controller 90 identifies the storage location (alternative address) of the alternative area 811c corresponding to the selected access location in the address translation information 813, issues a read command including the physical address of the storage location of the alternative area 811c, and supplies it to the non-volatile memory 80. The non-volatile memory 80 reads the information from the physical address of the storage location of the alternative area 811c in response to the read command (S25).

[0135] In S25, the controller 90 temporarily stores the information read from the non-volatile memory 80 in the volatile memory 70.

[0136] If the access location selected in S23 is not registered in the address translation information 813 (No in S24), the controller 90 issues a read command containing the physical address of the access location selected in S23 and supplies it to the non-volatile memory 80. The non-volatile memory 80 reads the information from the physical address of the access location selected in S23 in response to the read command (S26).

[0137] In S26, the controller 90 temporarily stores the information read from the non-volatile memory 80 in the volatile memory 70.

[0138] For example, suppose the address translation information 813 is in the state shown in Figure 5(c).

[0139] If the selected access location is physical address PA_1 (see Figure 3), the controller 90 issues a read command including physical address PA_1 and supplies it to the non-volatile memory 80, because physical address PA_1 is not registered in the address translation information 813. In response to the read command, the non-volatile memory 80 reads information (part of the firmware) from physical address PA_1 in the FW area 811a.

[0140] If the selected access location is physical address PA_2, the controller 90 identifies that physical address PA_2 is registered in address translation information 813 and that the alternative location is physical address PA_j+1. The controller 90 issues a read command including the identified physical address PA_j+1 and supplies it to the non-volatile memory 80. In response to the read command, the non-volatile memory 80 reads information (part of the firmware) from physical address PA_j+1 in the alternative area 811c.

[0141] If the selected access location is physical address PA_i, the controller 90 issues a read command including physical address PA_i and supplies it to the non-volatile memory 80 because physical address PA_i is not registered in the address translation information 813. In response to the read command, the non-volatile memory 80 reads information (part of the firmware) from physical address PA_i in the FW area 811a.

[0142] If the selected access location is physical address PA_i+1, the controller 90 identifies that physical address PA_i+1 is registered in address translation information 813 and that the alternative location is physical address PA_j+2. The controller 90 issues a read command including the identified physical address PA_j+2 and supplies it to the non-volatile memory 80. In response to the read command, the non-volatile memory 80 reads information (part of the parameters) from physical address PA_j+2 in the alternative area 811c.

[0143] If the selected access location is physical address PA_i+2, the controller 90 issues a read command including physical address PA_i+2 and supplies it to the non-volatile memory 80, because physical address PA_i+2 is not registered in the address translation information 813. In response to the read command, the non-volatile memory 80 reads information (part of the parameters) from physical address PA_i+2 in the parameter area 811b.

[0144] If the selected access location is physical address PA_j, the controller 90 issues a read command including physical address PA_j and supplies it to the non-volatile memory 80, because physical address PA_j is not registered in the address translation information 813. In response to the read command, the non-volatile memory 80 reads information (part of the parameters) from physical address PA_j in the parameter area 811b.

[0145] The non-volatile memory 80 uses the parity of the read information to perform error correction and decoding processing in the error correction circuit 83 (S27), and notifies the controller 90 of the result.

[0146] If a collectible error occurs during the error correction decoding process by the error correction circuit 83 (Yes in S28), the controller 90 registers the address of the error location in the address substitution information 813 (S29).

[0147] For example, in the error correction decoding process by the error correction circuit 83, if a collectable error occurs in the data of the FW area 811a or the parameter area 811b, the non-volatile memory 80 corrects the error in the data using parity and generates parity for the corrected data. The non-volatile memory 80 holds a codeword containing the data and parity and notifies the controller 90 of the collectable error.

[0148] The controller 90 determines the storage location in the alternative area 811c of the non-volatile memory 80 (S30).

[0149] The controller 90 further registers the address of the storage location in the address alternative information 813 (S31).

[0150] The controller 90 refers to the address substitution information 813 and issues a move command to the non-volatile memory 80 to move the information of the error location in the FW area 811a and / or parameter area 811b of the non-volatile memory 80 to the storage location in the substitution area 811c (S32).

[0151] In response to the move command, the non-volatile memory 80 reads the data from the original physical address and writes the read data to the physical address of the alternate area 811c.

[0152] The controller 90 registers the completion of the address substitution in the address substitution information 813 (S33).

[0153] The controller 90 determines whether there are any unselected access locations among the physical addresses of all storage areas in the FW area 811a and the parameter area 811b (S34).

[0154] If the controller 90 finds any unselected physical addresses among the physical addresses of all storage areas in the FW area 811a and the parameter area 811b, it determines that there are unselected access locations (Yes in S34) and returns the process to S23.

[0155] If there are no unselected physical addresses among the physical addresses of all storage areas in the FW area 811a and parameter area 811b, the controller 90 assumes there are no unselected access locations (No in S34), and starts the firmware using the information temporarily stored in the volatile memory 70 (S35), and sets the parameters in the firmware (S36). Accordingly, the controller 90 terminates the startup sequence (S37).

[0156] As described above, in this embodiment, in the disk device 1, the controller 90 stores information of error correction units containing bits that become collectible errors among the multiple error correction units contained in the FW area 811a and the parameter area 811b in the alternative area 811c, replacing the information in the FW area 811a and the parameter area 811b. The controller 90 creates or updates address substitution information 813 and stores it in the alternative management area 811d. The address substitution information 813 associates the address of the error correction unit with a collectible error with the address of the error correction unit in the alternative area 811c. As a result, the error correction unit with a collectable error can be stored and managed in the alternative area 811c before it becomes an uncollectible error, thereby reducing read errors such as FW / parameters and avoiding startup failures of the disk device 1.

[0157] As a modification of the embodiment, the inspection process of the non-volatile memory 80 may be performed on the alternative area 811c in addition to the FW area 811a and the parameter area 811b, as shown in Figure 8. Figure 8 is a flowchart showing the inspection process in a modification of the embodiment.

[0158] The controller 90 waits until it is time to check (No in S1), and when it is time to check (Yes in S1), it selects an access location in the FW area 811a, parameter area 811b, and alternate area 811c of the non-volatile memory 80 (S41). The controller 90 may also select an unselected physical address from all areas in the FW area 811a, parameter area 811b, and alternate area 811c as the access location. The controller 90 issues a read command containing the selected physical address and supplies it to the non-volatile memory 80.

[0159] Subsequently, steps S3 and S4 are performed in the same manner as in the embodiment.

[0160] If no collectible error occurs during the error correction decoding process by the error correction circuit 83 (No in S5), the controller 90 proceeds to S11.

[0161] If a collectible error occurs during the error correction decoding process by the error correction circuit 83 (Yes in S5), the controller 90 determines whether or not to perform a replacement (S42).

[0162] For example, if a collectible error occurs in information that has already been replaced in the alternative area 811c, that information should be re-replaced in another storage location within the alternative area 811c. Taking this into consideration, the address replacement information 813a, as shown in Figure 9, has a re-replacement flag associated with it, in addition to the original physical address, the replacement physical address, and the completion flag. Figure 9 shows the configuration and update of the address replacement information 813 in a modified embodiment.

[0163] The address substitution information 813a further includes a re-substitution flag field 8134. The re-substitution flag field 8134 records whether or not re-substitution has occurred. The re-substitution flag field 8134 may record 0 to indicate no re-substitution or 1 to indicate re-substitution.

[0164] If the location where the reported collectible error occurred is registered as an alternative address in the address alternative information 813a, the controller 90 decides to re-allocate (Yes in S42), registers the re-allocation in the address alternative information 813a (S43), and registers the address of the error location in the address alternative information 813a (S6).

[0165] For example, if the reported collectible error occurs at physical address PA_j+1, the controller 90 recognizes that physical address PA_j+1 is registered as an alternative address, as shown in Figure 9(a). Accordingly, the controller 90 records "1" in the re-alternation flag field 8134 corresponding to the alternative address "PA_j+1", as shown in Figure 9(b). At the same time, the controller 90 additionally registers the original alternative address "PA_j+1" and records "0" in its corresponding completion flag field 8133 and re-alternation flag field 8134, respectively.

[0166] The controller 90 determines that if the location where the reported collectible error occurred is not registered as an alternative address in the address alternative information 813a, it should not perform another alternative (No in S42), and registers the address of the error location in the address alternative information 813a without registering another alternative (S6).

[0167] Subsequently, steps S7 to S11 are carried out in the same manner as in the embodiment.

[0168] For example, if the physical address of the storage location determined in S8 is PA_j+3, the controller 90 records the physical address PA_j+3 in the alternate address field 8132 corresponding to the alternate source address "PA_j+1", as shown in Figure 9(c).

[0169] For example, in S9, when the non-volatile memory 80 writes data to the physical address "PA_j+3" of the alternate area 811c in response to the move command, it notifies the controller 90 that the alternate is complete. In response to this notification, the controller 90 records "1" in the completion flag field 8133 corresponding to the alternate source address "PA_j+1" and the alternate destination address "PA_j+3", as shown in Figure 9(d).

[0170] Furthermore, due to the changes in the inspection process, a different startup process may be performed compared to the embodiment, as shown in Figure 10. Figure 10 is a flowchart of the startup process in a modified example of the embodiment. Figure 10 illustrates the startup process after the inspection process shown in Figure 8 has been performed and the system has been shut down.

[0171] S21 to S23 are carried out in the same manner as in the embodiment.

[0172] If the access location selected in S23 is registered in the address translation information 813a (Yes in S51), the controller 90 identifies the storage location (alternate address) of the alternative area 811c corresponding to the selected access location in the address translation information 813a and checks whether re-alternation has occurred. The controller 90 checks the re-alternation flag field 8134 corresponding to the alternative address, and determines that re-alternation has not occurred if the re-alternation flag is "0", and determines that re-alternation has occurred if the re-alternation flag is "1".

[0173] If the controller 90 has not yet been re-allocated, it issues a read command containing the physical address of the re-allocated memory and supplies it to the non-volatile memory 80.

[0174] If a re-allocation has occurred, the controller 90 checks if the re-allocation destination address is in the source address in the address translation information 813a. If it is, it identifies the storage location (re-allocation destination address) of the re-allocation area 811c corresponding to that source address, issues a read command including the physical address of the re-allocation destination, and supplies it to the non-volatile memory 80.

[0175] The non-volatile memory 80 reads information from the physical address of the storage location in the alternate area 811c in response to a read command (S52).

[0176] In S52, the controller 90 temporarily stores the information read from the non-volatile memory 80 in the volatile memory 70.

[0177] If the access location selected in S23 is not registered in the address translation information 813a (No in S51), the controller 90 issues a read command containing the physical address of the access location selected in S23 and supplies it to the non-volatile memory 80. The non-volatile memory 80 reads the information from the physical address of the access location selected in S23 in response to the read command (S26).

[0178] In S26, the controller 90 temporarily stores the information read from the non-volatile memory 80 in the volatile memory 70.

[0179] For example, suppose the address translation information 813 is in the state shown in Figure 9(d).

[0180] If the selected access location is physical address PA_2, the controller 90 identifies that physical address PA_2 is registered in address translation information 813a and that the alternative address is physical address PA_j+1. The controller 90 checks whether that physical address has been re-allocated. The controller 90 confirms that the re-allocation flag corresponding to the alternative address "PA_j+1" is "1" and that re-allocation has occurred. The controller 90 confirms that "PA_j+1" is in the alternative source address field 8131 and identifies that the alternative address corresponding to the alternative source address "PA_j+1" is "PA_j+3". The controller 90 issues a read command containing the physical address "PA_j+3" and supplies it to the non-volatile memory 80. In response to the read command, the non-volatile memory 80 reads information (part of the firmware) from physical address PA_j+3 in the alternative area 811c.

[0181] Subsequently, S27 is carried out in the same manner as in the embodiment.

[0182] If no collectible error occurs during the error correction decoding process by the error correction circuit 83 (No in S28), the controller 90 proceeds to S34.

[0183] If a collectible error occurs during the error correction decoding process by the error correction circuit 83 (Yes in S28), the controller 90 decides whether or not to perform a replacement (S53).

[0184] If the location where the reported collectible error occurred is registered as an alternative address in the address alternative information 813a, the controller 90 decides to re-allocate (Yes in S53), registers the re-allocation in the address alternative information 813a (S54), and registers the address of the error location in the address alternative information 813a (S29).

[0185] The controller 90 determines that if the location where the reported collectible error occurred is not registered as an alternative address in the address alternative information 813a, it should not perform another alternative (No in S53), and registers the address of the error location in the address alternative information 813a without registering another alternative (S29).

[0186] Subsequently, steps S30 to S37 are carried out in the same manner as in the embodiment.

[0187] Even in such a disk device 1, the controller 90 can replace and store the error correction unit of a collectible error in the storage location of the alternative area 811c before it becomes an uncollectible error, thereby reducing read errors such as FW / parameters and avoiding startup failures of the disk device 1.

[0188] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0189] 1 disk drive, 80 non-volatile memory units, 90 controllers.

Claims

1. Non-volatile memory and A controller capable of accessing the aforementioned non-volatile memory, Equipped with, The non-volatile memory has an error correction circuit and a storage area. The storage area comprises a first area, a second area, and a third area. The first region includes a plurality of error correction units, If the controller contains a bit that becomes a collectible error in the error correction process by the error correction circuit, among the plurality of error correction units, it replaces the information of the first error correction unit in the first area and stores it in the second area, and creates or updates address substitution information, which associates the address of the first error correction unit in the first area with the address of the first error correction unit in the second area, and stores it in the third area. Disk drive.

2. The controller performs error correction processing using the error correction circuit on the information read from each of the plurality of error correction units, and checks for the presence or absence of an error correction unit that becomes a collectible error in the first region. The disk device according to claim 1.

3. The first area stores management information related to the startup of the disk device. The disk device according to claim 1.

4. The controller performs error correction processing by the error correction circuit on the information read from each of the plurality of error correction units at at least one of the following timings: when a predetermined period has elapsed since the previous inspection of the first region, when the disk device is started, when the management information is acquired, and when the disk device is idle, and checks whether there are any error correction units in the first region that are collectible errors. The disk device according to claim 3.

5. The aforementioned non-volatile memory further includes a redundant area, The error correction circuit causes parity for the information stored in the storage area to be stored in the redundancy area. The disk device according to claim 1.

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