Memory system, information processing system, and method for controlling a memory system

Abstract

This provides a memory system that frees up storage space that is not limited to the data management unit of the memory system. [Solution] In the information processing system, the memory system 3 includes a data management unit 104 that manages data received from the host 2 in units of a first data size, in units of a second data size larger than the first data size, a data storage unit 106, a write control unit 102, and a data determination unit 121 that determines whether the data of the second data size received by the write control unit matches a pre-set data pattern. If the first data received by the write control unit matches a data pattern, the data management unit sets a flag in the entry corresponding to the first data in the management table 31 indicating that it is a data pattern, and the write control unit discards the first data without writing the first data to the data storage unit.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system, an information processing system, and a method for controlling a memory system.

Background Art

[0002] As one of the connection standards between a host and a memory system, there is CXL (Compute Express Link) (registered trademark). CXL uses the same signals physically as PCIe (Peripheral Component Interconnect-Express) (registered trademark). CXL is composed of three protocols: (CXL.io), (CXL.mem), and (CXL.cache). CXL.io is a PCIe-based protocol. CXL.mem is a protocol for coherently accessing a memory device included in a memory system. CXL.cache is a protocol for a host and a peripheral device to maintain cache coherence and access.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, it is possible to execute the release of a storage area not limited to the data management unit of the memory system.

Means for Solving the Problems

[0005] The memory system according to the embodiment includes a data management unit configured to manage data received from a host in units of a first data size, in units of a second data size larger than the first data size, using a management table; a data storage unit configured to store data; a write control unit configured to control the writing of data to the data storage unit; and a data determination unit configured to determine whether data of the second data size received by the write control unit matches a preset data pattern. In an operation based on a write request, if the first data of the second data size received by the write control unit matches a preset data pattern, the data management unit is further configured to set a flag in the entry corresponding to the first data in the management table indicating that it matches a preset data pattern, and the write control unit is further configured to discard the first data without writing the first data to the data storage unit. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the overall configuration of the information processing system according to the first embodiment. [Figure 2] A block diagram showing an example of the page data structure of the memory system according to the first embodiment. [Figure 3] A diagram showing a specific example of an L2P table included in the memory system according to the first embodiment. [Figure 4] A block diagram showing an example of the functional configuration of a memory system that focuses on the flow of data, according to the memory system of the first embodiment. [Figure 5] A block diagram showing an example of the cache configuration of the memory system according to the first embodiment. [Figure 6] A flowchart showing an example of the overall flow when a host requests the write of SEG data consisting of all "0s" to a memory system in the information processing system according to the first embodiment. [Figure 7]A flowchart showing an example of the read-modify-write operation flow in the memory system according to the first embodiment. [Figure 8] A flowchart showing an example of the flow of refill operations in response to a read request in the memory system according to the first embodiment. [Figure 9] A block diagram showing an example of the functional configuration of a memory system that focuses on the flow of data, according to the memory system of the second embodiment. [Figure 10] A flowchart showing an example of the overall flow when a trim request is made from the host to the memory system in the information processing system according to the second embodiment. [Figure 11] A flowchart showing an example of the trimming process in the memory system according to the second embodiment. [Figure 12] A flowchart showing an example of the trimming process flow in a memory system according to a modified example of the second embodiment. [Figure 13] A diagram showing a specific example of an L2P table included in the memory system according to the third embodiment. [Figure 14] A flowchart illustrating an example of the read-modify-write operation flow in a memory system according to the third embodiment. [Figure 15] A flowchart showing an example of the flow of refill operations in response to read requests in a memory system according to the third embodiment. [Figure 16] A block diagram showing an example of the functional configuration of the host and memory systems, focusing on the flow of data, in the information processing system according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are assigned common reference numerals. When distinguishing between a plurality of components having the same reference numeral, a suffix is added to the common reference numeral for distinction. When no particular distinction is required for a plurality of components, only the common reference numeral is assigned to the plurality of components, and no suffix is added. Here, the suffix is not limited to subscript or superscript characters. For example, it includes small alphabetic characters added to the end of a reference numeral, and indexes indicating an array, etc.

[0008] 1. First Embodiment Hereinafter, a memory system according to an embodiment will be described.

[0009] 1.1 Configuration 1.1.1 Configuration of Information Processing System First, referring to FIG. 1, an example of the configuration of the information processing system 1 will be described. FIG. 1 is a block diagram showing an example of the overall configuration of the information processing system 1.

[0010] As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3. Note that a plurality of hosts 2 may be connected to the memory system 3, or a plurality of memory systems 3 may be connected to the host 2. For example, the memory system 3 is connected to the host 2 via a host bus HB. Note that the memory system 3 may be connected to the host 2 via a network or wireless communication. In this embodiment, the case where CXL (registered trademark) is applied as the connection standard of the host bus HB will be described. Note that the connection standard is not limited to CXL (registered trademark).

[0011] Host 2 is an information processing device that accesses the memory system 3. Host 2 controls the memory system 3. More specifically, for example, Host 2 requests (commands) writing or reading of data to / from the memory system 3. That is, Host 2 sends a write request or a read request to the memory system 3. For example, a write request includes data, a command, and a host physical address. A read request includes a command and a host physical address. The host physical address is an address used by Host 2. For example, Host 2 performs data transmission / reception with the memory system 3 based on the CXL.mem protocol.

[0012] The memory system 3 is, for example, a Type 3 device in CXL (registered trademark). Note that the memory system 3 may be an SSD (solid state drive). The memory system 3 executes various operations and the like based on an access request from Host 2. When an operation based on an access request (command) is completed, the memory system 3 sends a command response to Host 2.

[0013] 1.1.2 Internal Configuration of the Host Continuing, referring to FIG. 1, an example of the internal configuration of Host 2 will be described. Host 2 includes a host CPU (Central Processing Unit) 4 and a host memory 5. The host CPU 4 and the host memory 5 are connected to each other by, for example, an internal bus of Host 2.

[0014] The host CPU 4 controls the entire information processing system 1. More specifically, for example, the host CPU 4 controls the issuance of write requests and read requests to the memory system 3, that is, the input / output of data to / from the memory system 3. For example, the host CPU 4 has a virtual memory function. The memory management unit of the host CPU 4 converts a virtual memory address into a host physical address. The host CPU 4 accesses the host memory 5 and the memory system 3 using the host physical address.

[0015] The software running on the host CPU 4 of this embodiment sends a write request to the memory system 3 to write all "0" to the corresponding memory area in the memory system 3, triggered by a call to free the memory area being used, such as free(). Note that the timing of the release of the memory area is not limited to the call to free().

[0016] The host memory 5 is, for example, volatile memory. The host memory 5 may also be DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). The host memory 5 can be used as a workspace when the host CPU 4 executes the OS and application programs. In this embodiment, the case in which the host memory 5 is located within the host 2 is described, but the embodiment is not limited to this. For example, the host memory 5 may be connected to the host bus HB as a standalone storage device.

[0017] 1.1.3 Memory System Configuration Next, with reference to Figure 1, an example of the configuration of the memory system 3 will be described. The memory system 3 includes a memory controller 10, a non-volatile memory 20, and a volatile memory 30.

[0018] The memory controller 10 is composed of an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 10 may be composed of multiple semiconductor chips. The memory controller 10 controls the non-volatile memory 20 and the volatile memory 30 based on requests from the host 2. The memory controller 10 also manages the memory space of the non-volatile memory 20 and the volatile memory 30.

[0019] The non-volatile memory 20 is a non-volatile storage medium. The non-volatile memory 20 is connected to the memory controller 10, for example, via a NAND bus NB. The non-volatile memory 20 stores data received from the memory controller 10 in a non-volatile manner. The non-volatile memory 20 functions as a data storage unit in the memory system 3. The following describes the case where the non-volatile memory 20 is a NAND flash memory. The non-volatile memory 20 may include multiple memory chips. In this case, the multiple memory chips may each operate independently.

[0020] The non-volatile memory 20 includes one or more memory cell arrays 21. A memory cell array 21 is a collection of multiple memory cells arranged in a matrix. Memory cells store data non-volatilely. In other words, the memory cell array 21 is a physical storage area that stores data non-volatilely.

[0021] The memory cell array 21 includes multiple block BLKs (BLK0, BLK1, ...). A block BLK is a collection of multiple memory cells from which data is erased all at once. In other words, a block BLK is a unit of data erasure. A block BLK also includes multiple page PGs. A page PG is a unit of data that is written (or read) all at once to the memory cell array 21. The non-volatile memory 20 can perform write or read operations on multiple page PGs simultaneously. When data is rewritten in the non-volatile memory 20, the new data is written to another page PG.

[0022] Refer to Figure 2 to illustrate an example of the data structure of a page program (PG). Figure 2 is a block diagram showing an example of the data structure of a page program.

[0023] As shown in Figure 2, a page PG includes multiple cluster CTs. In the example shown in Figure 2, the page PG includes four cluster CTs. A cluster CT is a data management unit in the memory controller 10. For example, the memory controller 10 may perform data encoding and error correction for each cluster CT. The non-volatile memory 20 may transmit only the data from some of the cluster CTs of the read page PG to the memory controller 10.

[0024] Furthermore, each cluster CT contains multiple segment SEGs. In the example shown in Figure 2, the cluster CT contains four segment SEGs. A segment SEG is the unit of data transmitted and received between host 2 and memory system 3. Therefore, the granularity of data accessed between host 2 and memory system 3 is finer than the data management unit in memory system 3. If memory system 3 is an SSD, for example, it is configured so that a minimum of 512 bytes of data are communicated between host 2 and memory system 3. Also, if memory system 3 is a Type 3 device in CXL®, for example, it is configured so that a minimum of 64 bytes of data are communicated between host 2 and memory system 3. In the following description, segment SEG data will be referred to as "SEG data". Cluster CT data will be referred to as "CT data". Page PG data will be referred to as "PG data".

[0025] Furthermore, the memory cell array 21 non-volatilely stores an L2P table (also referred to as a "logic-to-physical conversion table" or "lookup table"). The L2P table is a table that shows the relationship between a logical address and its corresponding physical address. In other words, the L2P table is metadata that manages the data received from the host 2. The logical address is the address used by the host 2 to access the memory system 3. The physical address is the address that identifies the physical storage location in the storage area of ​​the non-volatile memory 20 (memory cell array 21). In this embodiment, the host physical address output from the host 2 is used as the logical address for accessing the memory system 3. In other words, the L2P table is a table that shows the relationship between the host physical address received from the host 2 and the physical address of the non-volatile memory 20.

[0026] Returning to Figure 1, the volatile memory 30 is a volatile storage medium. The volatile memory 30 is connected to the memory controller 10, for example, via a memory bus MB. The volatile memory 30 is, for example, DRAM. The volatile memory 30 is used, for example, as a cache or write buffer for storing data temporarily. The volatile memory 30 also stores the L2P table 31 loaded by the memory controller 10 from the non-volatile memory 20. The memory controller 10 uses the L2P table 31 loaded into the volatile memory 30 to manage the mapping between logical addresses and physical addresses. For example, the L2P table 31 is updated when a write operation is performed in the non-volatile memory 20. For example, the memory controller 10 updates the L2P table stored in the non-volatile memory 20 at any time based on the L2P table 31 in the volatile memory 30. The L2P table 31 contains multiple entries. Each entry contains a logical address LA and the physical address PA corresponding to the logical address LA. If the memory system 3 is a Type 3 device in CXL (registered trademark), the L2P table 31 manages data in units of 256 bytes, consisting of four consecutive data items in address order, for example, 64 bytes of data accessed between the host 2 and the memory system 3.

[0027] Refer to Figure 3 to explain an example of an L2P table 31. Figure 3 is a diagram showing a specific example of an L2P table 31.

[0028] As shown in Figure 3, the L2P table 31 contains information about the logical address LA, the physical address PA, and the ALL0 flag for each entry. The L2P table 31 has an entry for each cluster CT. The example in Figure 3 shows a case where one cluster CT stores four SEG data corresponding to four consecutive logical address LAs. The information about the logical address LAs includes, for example, the information of the first address of the four consecutive logical address LAs. The information about the physical address PA includes, for example, information about the block BLK, page PG, and cluster CT.

[0029] The ALL0 flag indicates whether the data in the cluster CT is all "0". For example, if the cluster CT contains "1" data, that is, if the CT data is not all "0", the ALL0 flag is set to "0". On the other hand, if all the data in the cluster CT is "0" data, that is, if the CT data is all "0", the ALL0 flag is set to "1" (this is also written as setting the ALL0 flag). When the ALL0 flag is "1", the physical address PA corresponding to the logical address LA does not need to be assigned. In other words, when the ALL0 flag is set, a write operation to the non-volatile memory 20 is unnecessary. Note that all "0" may be written to the non-volatile memory 20. Also, when the memory controller 10 receives a read request, it checks the L2P table 31. If the ALL0 flag is "1", the memory controller 10 knows that the corresponding CT data is all "0". In this case, the memory controller 10 can omit the read operation in the non-volatile memory 20.

[0030] Note that the L2P table 31 does not necessarily have an ALL0 flag. For example, instead of the ALL0 flag, a physically unused physical address PA (dummy address) may be set. For example, if the CT data is all "0", a dummy address is assigned to physical address PA. The memory controller 10 can tell that if a dummy address is assigned to physical address PA, the corresponding CT data is all "0".

[0031] For example, if the ALL0 flag is changed from "0" to "1" due to data rewriting, the physical address PA corresponding to the logical address LA of the entry, i.e., the storage area of ​​non-volatile memory 20, becomes free. In other words, the data in that storage area becomes invalid data. Invalid data is data that is not associated with the logical address LA.

[0032] In the example shown in Figure 3, logical address LA "0x1000" is assigned cluster CT0 of page PG0 of block BLK0, and the ALL0 flag is set to "0". Logical address LA "0x1004" is assigned cluster CT0 of page PG1 of block BLK1, and the ALL0 flag is set to "0". The ALL0 flag corresponding to logical address LA "0x1008" is set to "1", and no physical address PA is assigned. Logical address LA "0x1010" is assigned cluster CT3 of page PG0 of block BLK0, and the ALL0 flag is set to "0".

[0033] 1.1.4 Hardware configuration of the memory controller Next, we will describe an example of the hardware configuration of the memory controller 10, referring to Figure 1.

[0034] The memory controller 10 includes a control circuit 11, a host interface circuit (host I / F) 12, a volatile memory interface circuit (VMI / F) 13, and a non-volatile memory interface circuit (NVMI / F) 14. The functions of the control circuit 11, host interface circuit 12, volatile memory interface circuit 13, and non-volatile memory interface circuit 14 described below can be implemented by dedicated hardware, a processor that executes programs, or a combination thereof.

[0035] The control circuit 11 is a circuit that controls the entire memory controller 10. The control circuit 11 includes, for example, a processor such as a CPU, ROM (read-only memory), and RAM (random access memory). For example, the control circuit 11 commands the non-volatile memory 20 to perform various operations based on requests from the host 2 (write requests and read requests, etc.).

[0036] Specifically, for example, if a write request is a data rewrite, the control circuit 11 performs a read-modify-write operation. A read-modify-write operation is an operation in which data read from the non-volatile memory 20 is modified and written back to the non-volatile memory 20. The SEG data received by the memory controller 10 is smaller than the management unit of the memory controller 10. Therefore, when the control circuit 11 receives a write request, it first reads data from the non-volatile memory 20 that includes the logical address LA of the write request, i.e., CT data. In this case, the address range corresponds to one entry in the L2P table 31. Then, it rewrites the data of the corresponding segment SEG from the read CT data and writes it back to the non-volatile memory 20 (hereinafter also referred to as a write-back operation).

[0037] Furthermore, the control circuit 11 performs various processes for managing the non-volatile memory 20, such as garbage collection. Garbage collection is also called compaction. Garbage collection is the process of reading (collecting) valid data from multiple block BLKs of the non-volatile memory 20 and rewriting (copying) it to another block BLK. For example, valid data is data associated with a logical address. A block BLK that has had all its valid data copied by garbage collection becomes erasable. When data is rewritten in the non-volatile memory 20, the new data is written to another page PG. Therefore, as data rewriting progresses, the amount of invalid data in a block BLK increases. If even one valid data remains in a block despite the increase in invalid data, the block BLK cannot be erased. For example, if the number of erasable block BLKs decreases, garbage collection is performed.

[0038] The host interface circuit 12 manages communication between the memory controller 10 and the host 2. The host interface circuit 12 is connected to the host 2 via the host bus HB. The host bus HB conforms to, for example, CXL®. However, the host bus HB may also conform to other standards such as NVMe (non-volatile memory express)®.

[0039] The volatile memory interface circuit 13 manages communication between the memory controller 10 and the volatile memory 30. The memory bus MB connecting the volatile memory 30 and the memory controller 10 conforms to, for example, the DRAM interface standard.

[0040] The non-volatile memory interface circuit 14 manages communication between the memory controller 10 and the non-volatile memory 20. The non-volatile memory interface circuit 14 is connected to the non-volatile memory 20 via a NAND bus NB. The NAND bus NB conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (open NAND flash interface).

[0041] 1.1.5 Functional Configuration of the Memory System Next, with reference to Figure 4, an example of the functional configuration of the memory system 3 will be described. Figure 4 is a block diagram showing an example of the functional configuration of the memory system 3, focusing on the data flow.

[0042] As shown in Figure 4, the memory system 3 includes, functionally, a cache 101, a write control unit 102, a read control unit 103, a data management unit 104, a write buffer 105, and a data storage unit 106. For example, the control circuit 11 implements the functions of the write control unit 102, the read control unit 103, and the data management unit 104.

[0043] Cache 101 temporarily stores data. The data storage area of ​​cache 101 is located on volatile memory 30. Cache 101 sends and receives SEG data to and from host 2 based on the CXL.mem protocol. Cache 101 temporarily stores data that is frequently accessed. Cache 101 stores SEG data received from host 2 and CT data (also referred to as "refill data") read from data storage unit 106 (non-volatile memory 20). Cache 101 has multiple cache lines. A cache line is, for example, a storage area for storing CT data.

[0044] Cache 101 has a limited storage capacity. Therefore, when there are no more free cache lines, data from one of the cache lines will be targeted for eviction. Hereafter, the operation of eviction of data from cache 101 will be referred to as the "eviction operation." For example, cache lines that are accessed infrequently or cache lines that have been used for the longest time may be selected as the cache lines to be evictioned. The CT data (also referred to as "write-back data") evicted from cache 101 is sent to the write control unit 102.

[0045] The write control unit 102 controls the write operation (write-back operation) to the data storage unit 106. The write-back operation is the operation of writing the write-back data stored in the write buffer 105 to the data storage unit 106.

[0046] The write control unit 102 includes a data determination unit 121. The data determination unit 121 is a circuit that determines whether the write-back data (CT data) received from the cache 101 is all "0". In other words, the data determination unit 121 is a circuit that determines whether the write-back data (CT data) received from the cache 101 matches a preset data pattern (in this case, all "0").

[0047] If the write control unit 102 determines, based on the data determination unit 121, that the write-back data is all "0" (matches a pre-set data pattern), it notifies the data management unit 104 that the data is all "0". The data management unit 104 sets the ALL0 flag of the entry corresponding to the write-back data in the L2P table 31 to "1". Then, the write control unit 102 discards the CT data (all "0") received from the cache 101 without performing a write-back operation to the data storage unit 106.

[0048] Furthermore, the write control unit 102 performs a write-back operation if the write-back data (CT data) is not all "0" (i.e., does not match a pre-set data pattern). During the write-back operation, the write control unit 102 accesses the data management unit 104. The data management unit 104 updates the L2P table 31 and assigns the physical address PA to which the write-back data is written.

[0049] The read control unit 103 controls the refill operation. The refill operation is performed when the SEG data for the logical address LA specified by the write request or read request is not stored in the cache 101. In this operation, the data storage unit 106 (or write buffer 105) reads the CT data (refill data) for the address range including the target logical address LA, i.e., the corresponding entry in the L2P table 31, and sends it to the cache 101. In other words, the refill operation is an operation to replenish (or fill) the cache line with data. For example, if there are no free cache lines in the cache 101 during a refill operation, one of the cache lines is selected as the target for eviction.

[0050] The read control unit 103 accesses the data management unit 104 and refers to the L2P table 31 during a refill operation. For example, if the ALL0 flag of the entry corresponding to the refill data is set to "1", the read control unit 103 does not perform a read operation on the data storage unit 106 (or write buffer 105), but instead generates all "0"s and sends them to the cache 101.

[0051] The data management unit 104 manages the L2P tables. In other words, the data management unit 104 manages the data stored in the memory system 3.

[0052] The write buffer 105 temporarily stores data to be written to the data storage unit 106. The data storage area of ​​the write buffer 105 is located on the volatile memory 30. The write buffer 105 may have multiple storage areas of page size. For example, the storage capacity (number of storage areas) of the write buffer 105 may be set based on the number of pages that can be written at once. The write buffer 105 transmits PG data to the non-volatile memory 20.

[0053] The data storage unit 106 stores data in a non-volatile manner. The data storage area of ​​the data storage unit 106 is provided on the non-volatile memory 20.

[0054] 1.1.6 Cache Configuration Next, an example of the configuration of cache 101 will be described with reference to Figure 5. Figure 5 is a block diagram showing an example of the configuration of cache 101.

[0055] As shown in Figure 5, the cache 101 includes multiple cache lines CL (CL1, CL2, ...). Each cache line CL has a storage capacity corresponding to, for example, one cluster CT. Each cache line CL includes multiple storage areas for storing data and a cache management table for managing the data stored in the cache line CL.

[0056] The memory area MR temporarily stores data. One memory area MR corresponds to one SEG data. In the example shown in Figure 5, each cache line CL has four memory areas MR1 ​​to MR4, which correspond to four SEG data contained in one CT data.

[0057] The cache management table includes four valid flags VF (VF1-VF4), a tag TG, and four dirty flags DF (DF1-DF4).

[0058] The valid flags VF1 to VF4 correspond to the four memory areas MR1 ​​to MR4, respectively. The valid flag VF indicates whether the SEG data stored in the corresponding memory area MR is valid data. For example, if the corresponding memory area MR stores valid SEG data (valid data), the valid flag VF is set to "1". On the other hand, if the corresponding memory area MR does not store valid SEG data, the valid flag VF is set to "0".

[0059] The tag TG is information that can identify the logical address LA corresponding to the data stored in the cache line CL.

[0060] Dirty flags DF1 to DF4 correspond to four memory areas MR1 ​​to MR4, respectively. Dirty flag DF is a flag that indicates whether the SEG data stored in the corresponding memory area MR is dirty data that has not yet been written to the data storage unit 106. In other words, dirty flag DF is a flag that indicates whether the SEG data stored in the corresponding memory area MR is SEG data received from host 2. For example, if the corresponding memory area MR stores SEG data received from host 2, dirty flag DF is set to "1". On the other hand, if the corresponding memory area MR stores SEG data included in refill data (CT data), dirty flag DF is set to "0". For example, if at least one of the dirty flags DF1 to DF4 of a cache line CL to be evicted is set to "1", the data of that cache line CL is sent to the write control unit 102 as write-back data. On the other hand, if all dirty flags DF1 to DF4 of a cache line CL to be evicted are set to "0", the cache line CL is clean. Therefore, the data in the cache line CL is discarded and not sent to the write control unit 102. If the data in the cache line CL is retained after the write-back operation, the dirty flags DF1 to DF4 are set to "0" after the data is transferred to the write control unit 102.

[0061] In the example shown in Figure 5, valid SEG data is stored in each of the memory areas MR1 ​​to MR4 of cache line CL1. In this case, valid flags VF1 to VF4 are set to "1". Dirty flags DF1 and DF4 are set to "1", and dirty flags DF2 and DF3 are set to "0". In this case, SEG data received from host 2 is stored in memory areas MR1 ​​and MR4, and SEG data included in the refill data is stored in memory areas MR2 and MR3. No valid SEG data is stored in the memory areas MR1 ​​to MR4 of cache line CL2. That is, cache line CL2 is an empty cache line. In this case, valid flags VF1 to VF4 and dirty flags DF1 and DF4 are set to "0".

[0062] 1.2 The overall flow of a light request with all "0"s Next, with reference to Figure 6, an example of the overall flow when host 2 requests memory system 3 to write SEG data consisting of all "0s" will be described. Figure 6 is a flowchart illustrating an example of the overall flow when host 2 requests memory system 3 to write SEG data consisting of all "0s". The example shown in Figure 6 shows host 2 requesting SEG data consisting of all "0s" based on free(). free() is a function that commands the release of memory space. In this embodiment, host 2 requests the write of SEG data consisting of all "0s" to the corresponding memory space triggered by the call to free(). Note that the request to write SEG data consisting of all "0s" is not limited to free(). The data to be written may simply be valid data consisting of all "0s". That is, the request to write SEG data consisting of all "0s" includes cases based on free() and cases based on normal write operations. Even in the case of a write request based on free(), memory system 3 performs write and read operations with all "0s" as valid data, just as in normal write operations.

[0063] As shown in Figure 6, host 2 calls free() (S1). The memory area freed by free() is represented by a start address Start_addr and a data size Size. The start address Start_addr is, for example, a virtual memory address. The data size Size is arbitrary. For example, if the memory area to be freed is in memory system 3, the data size Size is the same data unit as segment SEG. In this case, the data size Size may be the data size of multiple segments SEG.

[0064] When host CPU4 of host 2 calls free(), it checks whether at least a portion of the memory area to be freed is contained within memory system 3. For example, the memory area from the starting address Start_addr on the virtual memory address to the data size Size may contain a mixture of memory area from memory system 3 and memory area from host memory 5. In this case, a portion of the memory area to be freed will be contained within memory system 3. If at least a portion of the memory area to be freed is not contained within memory system 3 (S2_No), host CPU4 does not make a write request to memory system 3. For example, if the entire memory area to be freed is contained within host memory 5, host CPU4 frees the target memory area in host memory 5 and terminates the operation corresponding to free().

[0065] If at least a portion of the memory area to be freed is located in memory system 3 (S2_Yes), the host CPU 4 sends an all-zero write request to memory system 3 (S3). More specifically, the host CPU 4 translates the virtual memory addresses corresponding to memory system 3 from the virtual memory addresses of data size Size, starting from the starting address Start_addr, to the host physical address (logical address LA). The host CPU 4 then sends a write request to memory system 3 containing the translated host physical address and all zeros. For example, if the memory area to be freed in memory system 3 contains multiple segments SEG, the host CPU 4 sends multiple write requests to memory system 3.

[0066] Memory system 3 performs a read-modify-write operation based on the received write request (S4). Once the read-modify-write operation is complete, memory system 3 sends a command response to host 2.

[0067] 1.3 Read-Modify-Write Operation in Memory Systems Next, with reference to Figure 7, an example of the read-modify-write operation flow in memory system 3 will be described. Figure 7 is a flowchart illustrating an example of the read-modify-write operation flow in memory system 3. In the following explanation, we will focus on the case where the data received from host 2 is SEG data consisting of all "0s".

[0068] As shown in Figure 7, the memory system 3 receives a write request from the host 2 (S101). For example, the memory system 3 receives SEG data consisting of all "0"s as the data to write from the host 2.

[0069] The read control unit 103 checks whether there is data corresponding to the logical address LA of the write request in any of the cache lines CL of the cache 101.

[0070] If there is data in cache 101 (S102_Yes), the refill operation will not be performed.

[0071] If there is no data in cache 101 (S102_No), the read control unit 103 refers to the L2P table 31 and performs a refill operation (S103). More specifically, the read control unit 103 refers to the L2P table. If the ALL0 flag of the corresponding entry is "0", the read control unit 103 reads data from the data storage unit 106 (non-volatile memory 20) or the write buffer 105 and sends it to cache 101. On the other hand, if the ALL0 flag of the corresponding entry is "1", the read control unit 103 generates all "0" refill data and sends it to cache 101. When a refill operation is performed and there are no free cache lines CL, one of the cache lines CL is selected as the target for eviction. If the dirty flags DF1 to DF4 of the cache line CL to be evicted are all "0", that is, if the cache line CL is clean, the data stored in that cache line CL is discarded. In response to this, if at least one of the dirty flags DF1 to DF4 of the cache line CL to be evicted is "1", the data stored in that cache line CL is sent to the write control unit 102. That is, write-back data is sent to the write control unit 102.

[0072] The SEG data received from host 2 is stored in cache 101 (S104). For example, in the case of rewriting to all "0" SEG data, the SEG data in the corresponding memory area MR of cache line CL is rewritten to all "0".

[0073] If there is no write-back data (S105_No), the write control unit 102 terminates the read-modify-write operation.

[0074] If there is write-back data (S105_Yes), the data determination unit 121 of the write control unit 102 checks whether the write-back data is all "0".

[0075] If the write-back data is all "0" (S106_Yes), the data management unit 104 sets the ALL0 flag of the corresponding entry in the L2P table 31 to "1" (S107). Then, the write control unit 102 discards the write-back data without performing the write-back operation (S108). For example, when the ALL0 flag is changed from "0" to "1", the storage area of ​​the physical address PA associated with the logical address LA of the corresponding entry is released. In other words, in the data storage unit 106, the data stored in the storage area corresponding to the physical address PA is treated as invalid data.

[0076] If the write-back data is not all "0" (S106_No), the data management unit 104 sets the ALL0 flag of the corresponding entry in the L2P table 31 to "0" and assigns one of the physical addresses PA (S109). In other words, the L2P table is updated. The write control unit 102 sends the write-back data to the write buffer 105 (S110).

[0077] When the amount of data stored in the write buffer 105 reaches the amount of data used for the write-back operation, PG data is transmitted from the write buffer 105 to the data storage unit 106, and the write-back operation is performed in the data storage unit 106 (S111).

[0078] 1.4 Refill Operation Next, we will explain an example of the refill operation flow with reference to Figure 8. Figure 8 is a flowchart showing an example of the refill operation flow. Figure 8 shows the case where the refill operation is performed based on a read request. The refill operation in a read modify write operation is similar.

[0079] As shown in Figure 8, the memory system 3 receives a read request from the host 2 (S201).

[0080] The read control unit 103 checks whether any cache line CL of the cache 101 contains data corresponding to the logical address LA of the read request.

[0081] If data exists in cache 101 (S202_Yes), the refill operation will not be performed.

[0082] If there is no data in cache 101 (S202_No), the read control unit 103 refers to L2P table 31 (S204).

[0083] If the ALL0 flag of the entry corresponding to the address range containing the logical address LA of the read request is "1" (S205_Yes), the read control unit 103 generates all "0" refill data and refills it into the cache 101 (S206).

[0084] If the ALL0 flag of the entry corresponding to the address range containing the logical address LA of the read request is "0" (S205_No), the read control unit 103 checks whether the write buffer 105 contains data corresponding to the logical address LA of the read request.

[0085] If there is data in the write buffer 105 (S207_Yes), the read control unit 103 refills the cache 101 with the data (CT data) from the write buffer 105 as refill data (S208).

[0086] If there is no data in the write buffer 105 (S207_No), the read control unit 103 performs a read operation in the data storage unit 106 (non-volatile memory 20). The data read from the data storage unit 106 (CT data) is refilled into the cache 101 as refill data (S209).

[0087] If there is data in the cache 101 (S202_Yes), or after the cache 101 has been refilled with data by any of steps S206, S208, and S209, the read control unit 103 outputs SEG data corresponding to the logical address LA of the read request in the cache 101 to the host (S203).

[0088] 1.5 Effects of this embodiment For example, the granularity of data access between host 2 and memory system 3 may be finer than the data management unit in memory system 3. In this case, memory system 3 performs memory space release at the data management unit level.

[0089] In contrast, with the configuration according to this embodiment, when the host 2 frees up the memory area of ​​the memory system 3, it can send a write request to the memory system 3 for SEG data consisting of all "0s". The memory system 3 can replace the SEG data of the memory area to be freed with SEG data consisting of all "0s" through a read-modify-write operation. Therefore, the memory system 3 can free up memory area at a finer granularity than the data management unit.

[0090] Furthermore, in the configuration according to this embodiment, the memory system 3 includes a data determination unit 121 and a data management unit 104. The data determination unit 121 can determine whether the write-back data (CT data) is all "0". The data management unit 104 can set an ALL0 flag in the L2P table 31 to indicate that the CT data corresponding to an entry is all "0". The data management unit 104 can set the ALL0 flag in the L2P table 31. Furthermore, the data management unit 104 can omit the assignment of a physical address PA to an entry in the L2P table for which the ALL0 flag has been set. By managing all "0" in the L2P table 31, the memory area that has been set to all "0" can be freed.

[0091] Furthermore, in the configuration according to this embodiment, if the data determination unit 121 determines that all values ​​are "0", the write control unit 102 can discard the corresponding write-back data without performing a write-back operation in the non-volatile memory 20. Therefore, an increase in the write amplification factor (WAF) in the non-volatile memory 20 can be suppressed. Moreover, since the write-back operation can be omitted, the processing capacity of the memory system 3 can be improved.

[0092] Furthermore, with the configuration according to this embodiment, the writing of all "0" valid data to the non-volatile memory 20 can be omitted. As a result, the copying of all "0"s can be omitted during garbage collection, thereby suppressing the overhead of garbage collection.

[0093] Furthermore, in the configuration according to this embodiment, if the ALL0 flag of the target entry in the L2P table is set during the refill operation, the read control unit 103 can generate all "0" data and refill it into the cache 101. This eliminates the need for a read operation in the non-volatile memory 20. Thus, the latency of the refill operation can be reduced.

[0094] In this embodiment, the case in which host 2 generates SEG data consisting of all "0"s when freeing memory space has been described, but it is not limited to all "0"s. For example, host 2 may generate a preset data pattern other than all "0". The data determination unit 121 of the memory system 3 may determine whether the received data matches a preset data pattern, and if it matches the data pattern, it may set a flag and discard the write-back data.

[0095] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, the case in which host 2 sends a trim request to memory system 3 will be described. The following description will focus on the differences from the first embodiment.

[0096] 2.1 Functional Configuration of the Memory System First, we will explain an example of the functional configuration of the memory system 3 with reference to Figure 9. Figure 9 is a block diagram showing an example of the functional configuration of the memory system 3, focusing on the flow of data.

[0097] As shown in Figure 9, the memory system 3 includes, functionally, a cache 101, a write control unit 102, a read control unit 103, a data management unit 104, a write buffer 105, a data storage unit 106, and a trim control unit 107. For example, the functions of the write control unit 102, read control unit 103, data management unit 104, and trim control unit 107 are realized by the control circuit 11. The cache 101, write control unit 102, read control unit 103, data management unit 104, write buffer 105, and data storage unit 106 are the same as described using Figure 4 of the first embodiment.

[0098] In this embodiment, when the host CPU 4 of host 2 frees a memory area in the memory system 3, for example by calling free(), it sends a trim request to the trim control unit 107 based on the CXL.io protocol. The trim request includes information on the trim command, the starting logical address LA, and the data size. The trim command in this embodiment is a command that requests the writing of all "0"s. The data size in the trim request is the same data unit as the segment SEG. The data size in the trim request may be the data size of multiple segment SEGs. Therefore, the trim request can request the writing of all "0"s to multiple memory areas (multiple segment SEGs) corresponding to multiple consecutive logical addresses LA all at once. By sending the trim request, the host CPU 4 can omit the transmission of all "0" data. In other words, the trim request in this embodiment is a write request of all "0"s that does not involve data transfer.

[0099] The trim control unit 107 controls the trimming process in the memory system 3. In this embodiment, the trimming process is the process of setting all data in the memory area specified by the trimming request to "0" (valid data). The address range for the trimming process is a plurality of consecutive logical addresses LA, starting from the starting logical address LA of the trimming request and equal to the data size. The trim control unit 107 determines the address range for the trimming process from the starting logical address LA of the trimming request and the data size.

[0100] For example, the address range for trimming and the address range of an entry in L2P table 31 may not match. Specifically, for instance, the address range of one entry in L2P table 31 corresponds to four logical addresses LA (four SEG data). However, for example, the number of logical addresses LA included in the trimming address range may not be 4j (where j is any natural number). Also, for example, even if the number of logical addresses LA included in the trimming address range is 4j, the starting logical address LA of the trimming process may not match the starting logical address LA of the entry. In such cases, there may be entries in L2P table 31 where all of the corresponding logical addresses LA are not included in the trimming address range.

[0101] For example, if there is an entry in the L2P table 31 in the address range for trimming that does not include all of the corresponding logical addresses LA, the trimming control unit 107 generates all "0"s for the logical addresses LA of that entry within the address range for trimming. In other words, if there is a cluster CT in the target of trimming that does not include all of the segment SEGs, the trimming control unit 107 generates all "0"s for the segment SEGs included in the cluster CT within the address range for trimming. The trimming control unit 107 sends all "0"s to the cache 101. The cache 101 handles the data received from the trimming control unit 107 in the same way as the data for a write request. That is, a read-modify-write operation is performed.

[0102] Furthermore, for example, if an entry in the L2P table 31 containing all logical addresses LA exists within the address range for trimming, the trimming control unit 107 does not generate all "0" CT data corresponding to that entry, but instead notifies the data management unit 104 that the entry is all "0". The data management unit 104 sets the ALL0 flag of the corresponding entry in the L2P table to "1", similar to the determination result of the data determination unit 121. Hereafter, this process will also be referred to as "ALL0 processing".

[0103] 2.2 Overall flow of trim requests Next, with reference to Figure 10, an example of the overall flow when host 2 makes a trim request to memory system 3 will be described. Figure 10 is a flowchart showing an example of the overall flow when host 2 makes a trim request to memory system 3. The example shown in Figure 10 shows the case where host CPU 4 of host 2 makes a trim request based on free(). Note that a trim request is not limited to a call to free(). Host 2 may send a trim request instead of a write request if the data to be written is all "0".

[0104] As shown in Figure 10, host 2 calls free() (S1), similar to the explanation using Figure 6 of the first embodiment.

[0105] When the host CPU 4 calls free(), it checks whether at least a portion of the memory area to be freed at the virtual memory address is included in the memory system 3, similar to the explanation using Figure 6 of the first embodiment. If at least a portion of the memory area to be freed is not included in the memory system 3 (S2_No), the host CPU 4 does not send a trim request to the memory system 3.

[0106] If at least a portion of the memory area to be freed is included in memory system 3 (S2_Yes), the host CPU 4 determines the starting logical address LA and data size from the virtual memory address and data size corresponding to memory system 3 (S10). Note that multiple pairs of starting logical address LA and data size may be determined from the virtual memory address and data size corresponding to memory system 3.

[0107] The host CPU 4 sends a trim request to the memory system 3 to trim the number of segments SEG corresponding to the data size from the logical address LA (S11). For example, if there are multiple pairs of starting logical address LA and data size, the host CPU 4 may send multiple trim requests corresponding to each combination, or it may provide a command that allows specifying multiple pairs of starting logical address LA and data size within a single trim request.

[0108] The memory system 3 performs the trimming process based on the received trimming request (S12). Once the trimming process is complete, the memory system 3 sends a command response to the host 2.

[0109] Note that the host CPU 4 does not have to send a trim request to the memory system 3 immediately after calling free(). For example, if the host CPU 4 is performing other processing, it may send the trim request after the other processing is completed. Similarly, if the memory system 3 receives a trim request but is performing other processing, it may perform the trim process after the other processing is completed.

[0110] Alternatively, the host CPU 4 may, after accumulating several memory areas to be freed through multiple calls to free(), send multiple trim requests to the memory system 3 all at once.

[0111] 2.3 Flow of trimming in a memory system Next, with reference to Figure 11, an example of the trimming process flow in memory system 3 will be described. Figure 11 is a flowchart showing an example of the trimming process flow in memory system 3.

[0112] As shown in Figure 11, the trim control unit 107 of the memory system 3 receives a trim request from the host 2 (S120).

[0113] The trim control unit 107 checks the L2P table 31 to see if there is an entry that falls within the address range for trimming. More specifically, the trim control unit 107 determines the address range of the logical address LA to be trimmed from the starting logical address LA and data size of the trim request. The trim control unit 107 then refers to the L2P table 31 to see if there is an entry that includes all the corresponding logical addresses LA within the address range for trimming.

[0114] If the L2P table 31 contains an entry that falls within the address range for trimming (S121_Yes), the trimming control unit 107 instructs the data management unit 104 to perform ALL0 processing on the corresponding entry (S122). More specifically, the data management unit 104 sets the ALL0 flag to "1" for the entry in the L2P table 31 that falls within the address range for trimming.

[0115] The trim control unit 107 generates all "0"s corresponding to the address ranges within the trim processing address range where the ALL0 processing has not been performed (S123). More specifically, the trim control unit 107 generates all "0"s corresponding to logical address LA, excluding the logical address LA corresponding to the entry where the ALL0 processing has been performed, within the trim processing address range. The trim control unit 107 sends the generated all "0" data to the cache 101.

[0116] If there is no entry in the L2P table 31 that falls within the address range for trimming (S121_No), the trimming control unit 107 generates all "0" corresponding to the address range for trimming (S124). The trimming control unit 107 sends the generated all "0" to the cache 101.

[0117] When the cache 101 receives all "0" from the trim control unit 107, a read-modify-write operation is performed (S125). The read-modify-write operation is the same as described using Figure 7 of the first embodiment.

[0118] 2.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0119] Furthermore, in the configuration according to this embodiment, the host 2 can send a trim request to the memory system 3 when freeing up the memory area of ​​the memory system 3. The memory system 3 includes a trim control unit 107. Based on the trim request, the trim control unit 107 sets the address range for trimming to all "0", thereby freeing up the memory area at a finer granularity than the data management unit.

[0120] Furthermore, in the configuration according to this embodiment, host 2 can send a trim request to memory system 3 based on the CXL.io protocol. The transmission of all "0" data from host 2 to memory system can be omitted. This reduces the bandwidth usage corresponding to the CXL.mem protocol.

[0121] Furthermore, with the configuration according to this embodiment, by specifying the starting logical address LA and data size in the trim request, a single trim request can command the release of a wider range of memory area than that corresponding to a single segment SEG. As a result, the host CPU 4 does not need to issue a trim request for each segment SEG, thus reducing the overhead of request issuance for the host CPU 4.

[0122] Furthermore, in the configuration according to this embodiment, the trim control unit 107 can execute ALL0 processing if there is an entry in the L2P table 31 that is included in the address range for trim processing. This reduces the amount of all "0" data sent from the trim control unit 107 to the cache 101. Thus, contamination of the cache 101 (increase in dirty data) can be suppressed.

[0123] In this embodiment, the case in which the trim control unit 107 sets the address range for trimming to all "0" based on the trim request has been described, but as in the first embodiment, it is not limited to all "0". The trim control unit 107 may, for example, generate a pre-set data pattern other than all "0".

[0124] 2.5 Modified Examples of the Second Embodiment Next, a modified version of the second embodiment will be described. In this modified version, all "0" values ​​are generated even when there are entries in the L2P table 31 that are included in the address range of the trimming process. The following description will focus on the differences from the second embodiment.

[0125] Referring to Figure 12, an example of the trimming process flow in memory system 3 will be described. Figure 12 is a flowchart of an example of the trimming process flow in memory system 3.

[0126] As shown in Figure 12, the trim control unit 107 of the memory system 3 receives a trim request from the host 2 (S120).

[0127] The trim control unit 107 generates all "0"s corresponding to the address range for trimming (S124). The trim control unit 107 sends the generated all "0"s to the cache 101.

[0128] When the cache 101 receives all "0" from the trim control unit 107, a read-modify-write operation is performed (S125). The read-modify-write operation is the same as described using Figure 7 of the first embodiment.

[0129] 2.6 Effects of Modified Examples of the Second Embodiment With the configuration described in this modified example, the same effects as those of the first embodiment can be obtained. Furthermore, with the configuration according to this modified example, similar to the second embodiment, the trim control unit 107 can free up memory space at a finer granularity than the data management unit by setting the address range for trim processing to all "0" based on the trim request.

[0130] Furthermore, with the configuration according to this modified example, the bandwidth usage corresponding to the CXL.mem protocol can be reduced, similar to the second embodiment.

[0131] Furthermore, with the configuration according to this modified example, the host CPU 4 does not need to issue a trim request for each segment SEG, similar to the second embodiment, thus reducing the overhead for request issuance by the host CPU 4.

[0132] In this modified example, similar to the second embodiment, the trim control unit 107 sets the address range for trimming to all "0" based on the trim request. However, it is not limited to all "0". The trim control unit 107 may, for example, generate a pre-set data pattern other than all "0".

[0133] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a case will be described in which the data determination unit 121 of the memory system 3 detects a preset data pattern (hereinafter referred to as "fixed value").

[0134] In this embodiment, the data determination unit 121 determines whether the write-back data received by the write control unit 102 is a fixed value. The L2P table 31 has flags corresponding to the fixed value. The memory system 3 manages the fixed value in the L2P table, similar to all "0" in the first embodiment, and does not perform a write-back operation to the data storage unit 106. The fixed value may be all "0", all "1", or any data pattern such as "0101...". The following will mainly describe the differences from the first and second embodiments.

[0135] In this embodiment, host 2 may send a write request with a fixed value in response to free().

[0136] 3.1 L2P Table First, let's look at an example of an L2P table 31, referring to Figure 13. Figure 13 is a diagram showing a specific example of an L2P table 31.

[0137] As shown in Figure 13, the L2P table 31 contains information about the logical address LA, the physical address PA, and fixed-value flags for each entry. Note that multiple fixed-value flags may be set.

[0138] The fixed value flag indicates whether the data in the cluster CT is a fixed value or not. For example, if the CT data is not a fixed value, the fixed value flag is set to "0". On the other hand, if the CT data is a fixed value, the fixed value flag is set to "1" (the fixed value flag is set). When the fixed value flag is "1", the physical address PA corresponding to the logical address LA does not need to be assigned. In other words, when the fixed value flag is set, a write-back operation to the non-volatile memory 20 is unnecessary. However, a fixed value may be written to the non-volatile memory 20. Also, when the memory controller 10 receives a read request, it checks the L2P table 31. If the fixed value flag is "1", the memory controller 10 knows that the corresponding CT data is a fixed value. In this case, the memory controller 10 can omit the read operation in the non-volatile memory 20.

[0139] For example, if the fixed value flag is changed from "0" to "1" due to data rewriting, the physical address PA corresponding to the logical address LA, i.e., the storage area of ​​the non-volatile memory 20, becomes free. In other words, the data in that storage area becomes invalid data.

[0140] In the example shown in Figure 13, logical address LA "0x1000" is assigned to cluster CT0 of page PG0 of block BLK0, and the fixed value flag is set to "0". Logical address LA "0x1004" is assigned to cluster CT0 of page PG1 of block BLK1, and the fixed value flag is set to "0". The fixed value flag corresponding to logical address LA "0x1008" is set to "1", and no physical address PA is assigned. Logical address LA "0x1010" is assigned to cluster CT3 of page PG0 of block BLK0, and the fixed value flag is set to "0".

[0141] 3.2 Read-Modify-Write Operations in Memory Systems Next, with reference to Figure 14, an example of the read-modify-write operation flow in memory system 3 will be described. Figure 14 is a flowchart illustrating an example of the read-modify-write operation flow in memory system 3. In the following explanation, we will focus on the case where the data received from host 2 is fixed-value SEG data.

[0142] As shown in Figure 14, the operation of steps S101 to S105 is the same as described using Figure 7 in the first embodiment.

[0143] If there is write-back data (S105_Yes), the data determination unit 121 of the write control unit 102 checks whether the write-back data is a fixed value.

[0144] If the write-back data is a fixed value (S130_Yes), the data management unit 104 sets the fixed value flag of the corresponding entry in the L2P table 31 to "1" (S131). Then, the write control unit 102 discards the write-back data without performing a write-back operation (S108). For example, if the fixed value flag is changed from "0" to "1", the storage area of ​​the physical address PA associated with the logical address LA of the corresponding entry is released. In other words, in the data storage unit 106, the data stored in the storage area corresponding to the physical address PA is treated as invalid data.

[0145] If the write-back data is not a fixed value (S130_No), the data management unit 104 sets the fixed value flag of the corresponding entry in the L2P table 31 to "0" and assigns one of the physical addresses PA (S109). In other words, the L2P table is updated. The write control unit 102 sends the write-back data to the write buffer 105 (S110).

[0146] When the amount of data stored in the write buffer 105 reaches the amount of data used for the write-back operation, PG data is transmitted from the write buffer 105 to the data storage unit 106, and the write-back operation is performed in the data storage unit 106 (S111).

[0147] 3.3 Refill Operation Next, we will explain an example of the refill operation flow with reference to Figure 15. Figure 15 is a flowchart showing an example of the refill operation flow. Figure 15 shows the case where the refill operation is performed based on a read request. The refill operation in a read modify write operation is similar.

[0148] As shown in Figure 15, the operation of steps S201 and S202 is the same as described using Figure 8 in the first embodiment.

[0149] If there is no data in cache 101 (S202_No), the read control unit 103 refers to L2P table 31 (S204).

[0150] If the fixed value flag of the entry corresponding to the address range containing the logical address LA of the read request is "1" (S220_Yes), the read control unit 103 generates fixed value refill data and refills it into the cache 101 (S221).

[0151] If the fixed value flag of the entry corresponding to the address range containing the logical address LA of the read request is "0" (S220_No), the read control unit 103 checks whether the write buffer 105 contains data corresponding to the logical address LA of the read request.

[0152] The operation of steps S207 to S209 is the same as described using Figure 8 in the first embodiment.

[0153] If there is data in the cache 101 (S202_Yes), or after the cache 101 has been refilled with data by any of steps S221, S208, and S209, the read control unit 103 outputs SEG data corresponding to the logical address LA of the read request in the cache 101 to the host (S203).

[0154] 3.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0155] Furthermore, the configuration according to this embodiment can also handle data patterns other than all "0".

[0156] 4. Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, the case in which data is encrypted when it is transmitted from the host 2 to the memory system 3 will be described. Note that data may also be encrypted when it is transmitted from the memory system 3 to the host 2. The following description will focus on the differences from the first to third embodiments.

[0157] 4.1 Functional Configuration of Host and Memory Systems First, an example of the functional configuration of host 2 and memory system 3 will be described with reference to Figure 16. Figure 16 is a block diagram showing an example of the functional configuration of host 2 and memory system 3, focusing on the data flow.

[0158] As shown in Figure 16, the host 2 includes an encryption unit 201 as part of its functional configuration. For example, the host CPU 4 implements the functions of the encryption unit 201.

[0159] The encryption unit 201 encrypts data when it transmits it from the host 2 to the memory system 3.

[0160] The memory system 3 includes, as a functional configuration, a cache 101, a write control unit 102, a read control unit 103, a data management unit 104, a write buffer 105, a data storage unit 106, and a decoding unit 108. For example, the functions of the write control unit 102, read control unit 103, data management unit 104, and decoding unit 108 are realized by the control circuit 11. The cache 101, write control unit 102, read control unit 103, data management unit 104, write buffer 105, and data storage unit 106 are the same as described using Figure 4 of the first embodiment.

[0161] The decoding unit 108 decodes the input data received from the host 2. The decoded data is sent to the cache 101.

[0162] 4.2 Effects of this embodiment The configuration according to this embodiment can be applied to the first to third embodiments. This will provide the same effects as the first to third embodiments.

[0163] Furthermore, with the configuration according to this embodiment, data can be encrypted and transmitted, thereby improving confidentiality.

[0164] 5. Variations, etc. The memory system (3) according to the above embodiment includes a data management unit (104) configured to manage data received from the host (2) for each first data size (SEG) in each second data size (CT) larger than the first data size using a management table (31); a data storage unit (106) configured to store data; a write control unit (102) configured to control the writing of data to the data storage unit; and a data determination unit (121) configured to determine whether the data of the second data size received by the write control unit matches a preset data pattern. In an operation based on a write request, if the first data of the second data size received by the write control unit matches a preset data pattern, the data management unit is further configured to set a flag in the entry corresponding to the first data in the management table indicating that it matches a preset data pattern, and the write control unit is further configured to discard the first data without writing the first data to the data storage unit.

[0165] With the configuration according to the above embodiment, it is possible to provide a memory system that can free up storage areas that are not limited to the data management units of the memory system.

[0166] Furthermore, various modifications are applicable, not limited to the embodiments described above.

[0167] For example, in the above embodiment, a DMAC (Direct Memory Access Controller) may be used for data transfer between the host 2 and the memory system 3. In this case, instead of the host CPU 4, the DMAC may perform data transfer of fixed values ​​such as all "0".

[0168] Furthermore, in the above embodiment, the host CPU 4 may delegate processing such as issuing write requests or trim requests to the memory system 3 to a processor that assists the host CPU 4, such as a DPU (Data Processing Unit).

[0169] Furthermore, the term "connection" in the above embodiment also includes a state in which the devices are indirectly connected by interposing something else, such as a transistor or a resistor.

[0170] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0171] 1...Information processing system, 2...Host, 3...Memory system, 4...Host CPU, 5...Host memory, 10...Memory controller, 11...Control circuit, 12...Host interface circuit, 13...Volatile memory interface circuit, 14...Non-volatile memory interface circuit, 20...Non-volatile memory, 21...Memory cell array, 30...Volatile memory, 31...L2P table, 101...Cache, 102...Write control unit, 103...Read control unit, 104...Data management unit, 105...Write buffer, 106...Data storage unit, 107...Trim control unit, 108...Decryption unit, 121...Data determination unit, 201...Encryption unit, BLK...Block, CL...Cache line, CT...Cluster, DF1~DF4...Dirty flag, MR1~MR4...Storage area, VF1~VF4...Valid flag

Claims

1. A data management unit is configured to manage data received from the host in increments of a first data size, using a management table, in increments of a second data size that is larger than the first data size. A data storage unit configured to store data, A write control unit configured to control the writing of data to the data storage unit, A data determination unit configured to determine whether the data of the second data size received by the write control unit matches a preset data pattern, Equipped with, In an operation based on a write request, if the first data of the second data size received by the write control unit matches the preset data pattern, The data management unit is further configured to set a flag in the entry corresponding to the first data in the management table to indicate that it matches a pre-configured data pattern. The write control unit is further configured to discard the first data without writing the first data to the data storage unit. Memory system.

2. In the operation based on the aforementioned write request, if the first data does not match the preset data pattern, The data management unit is further configured to assign the physical address of the data storage unit to the entry corresponding to the first data in the management table. The write control unit is further configured to write the first data to the storage area corresponding to the physical address of the data storage unit. The memory system according to claim 1.

3. A cache configured to store data, A read control unit configured to control the reading of data from the data storage unit, Furthermore, In the operation based on the aforementioned light request, The read control unit is further configured to populate the cache with second data of the second data size corresponding to a logical address range including the first logical address of the write request. In the cache, a portion of the second data is replaced with a third data of the first data size included in the write request. The memory system according to claim 1.

4. The read control unit is further configured to transmit the data pattern generated as the second data to the cache if the flag is set in the entry corresponding to the logical address range including the first logical address in the management table. The memory system according to claim 3.

5. The read control unit is further configured to transmit the second data read from the data storage unit to the cache if the flag is not set in the entry corresponding to the logical address range including the first logical address in the management table. The memory system according to claim 3.

6. The aforementioned data pattern is all "0". The memory system according to claim 1.

7. In the management table, for entries where the flag is set, the physical address of the data storage unit corresponding to the logical address is not assigned. The memory system according to claim 1.

8. The trim control unit further comprises a trim control unit that receives a first command instructing the writing of the aforementioned data pattern. The trim control unit is configured to generate data corresponding to the data pattern when it receives the first command. The memory system according to claim 1.

9. The trim control unit is further configured to, if the address range corresponding to the first command includes the logical address of any entry in the management table, instruct the data management unit to set the flag for that entry without generating data corresponding to that entry. The memory system according to claim 8.

10. It further comprises a decryption unit configured to decrypt encrypted input data, The memory system according to claim 1.

11. The data storage unit is a NAND flash memory. The memory system according to claim 1.

12. A memory system according to any one of claims 1 to 7 and 10, A host configured to control the aforementioned memory system Equipped with, The host is further configured to send the write request for the data pattern to the memory system when freeing up the storage area of ​​the memory system. Information processing system.

13. The memory system according to claim 8 or 9, A host configured to control the aforementioned memory system Equipped with, The host is further configured to send the first command to the memory system when freeing up the memory area of ​​the memory system. Information processing system.

14. A control method for a memory system that manages data received from a host in units of a first data size, in units of a second data size larger than the first data size, using a management table, wherein the control method is: In operations based on a write request, it is determined whether the first data of the second data size to be written matches a pre-configured data pattern, If the first data matches the pre-set data pattern, In the entry corresponding to the first data in the management table, a flag is set to indicate that it matches the pre-configured data pattern, Discard the first data without writing the first data to the data storage unit. Equipped with, A method for controlling a memory system.

15. In the operation based on the aforementioned write request, if the first data does not match the preset data pattern, In the management table, the physical address of the data storage unit is assigned to the entry corresponding to the first data, Writing the first data to the storage area corresponding to the physical address of the data storage unit, It also has, A method for controlling a memory system according to claim 14.

16. In the operation based on the aforementioned light request, The second data of the second data size corresponding to the logical address range including the first logical address of the write request is loaded into the cache. In the cache, a portion of the second data is replaced with a third data of the first data size corresponding to the write request. It also has, A method for controlling a memory system according to claim 14.

17. If the flag is set in the entry in the management table corresponding to the logical address range including the first logical address, the generated data pattern is sent to the cache as the second data. A method for controlling a memory system according to claim 16.

18. If the flag is not set in the entry corresponding to the logical address range including the first logical address in the management table, the second data read from the data storage unit is transmitted to the cache. A method for controlling a memory system according to claim 16.

19. The aforementioned data pattern is all "0". A method for controlling a memory system according to claim 14.

20. Non-volatile memory that is connectable to a host and configured to store data, Control the non-volatile memory, The host sends and receives data in units of the first data size, Using a management table, data is managed in units of a second data size that is larger than the first data size. Determine whether the data of the second data size matches a pre-set data pattern. A memory controller configured in such a way Equipped with, The memory controller, when the first data of the second data size included in the data based on the write request received from the host is the data pattern, The system is configured to set a flag in the entry corresponding to the first data in the management table that indicates it matches a pre-configured data pattern, and to discard the first data without writing it to the non-volatile memory. Memory system.

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