Memory device

Abstract

To provide a storage device having small memory cells. [Solution] A memory device according to one embodiment includes a first conductor, a first semiconductor, a first insulator, a second conductor, a third conductor, and a second insulator. The first conductor extends in a first direction. The first semiconductor surrounds the first conductor along a first plane intersecting the first direction. The first insulator surrounds the first semiconductor along the first plane. The second conductor surrounds the first insulator along the first plane. The third conductor is located in a first direction from the first semiconductor and surrounds the first conductor along the first plane. The second insulator is located between the first semiconductor and the third conductor.

Description

Technical Field

[0001] Embodiments generally relate to a memory device.

Background Art

[0002] As a memory device, DRAM (Dynamic Random Access Memory) is known. The memory cell of DRAM includes a capacitor and a transistor. In order to increase the memory capacity of DRAM, reduction of the cell size is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provide a memory device having a memory cell of a small size.

Means for Solving the Problems

[0005] A memory device according to an embodiment includes a first conductor, a first semiconductor, a first insulator, a second conductor, a third conductor, and a second insulator. The first conductor extends in a first direction. The first semiconductor surrounds the first conductor along a first plane intersecting the first direction. The first insulator surrounds the first semiconductor along the first plane. The second conductor surrounds the first insulator along the first plane. The third conductor is positioned in the first direction from the first semiconductor and surrounds the first conductor along the first plane. The second insulator is between the first semiconductor and the third conductor.

Brief Description of the Drawings

[0006] [Figure 1]Figure 1 shows the components of the storage device according to the first embodiment and the connections between the components. [Figure 2] Figure 2 shows the components of the memory cell of the first embodiment and the connections between the components. [Figure 3] Figure 3 is a perspective view of a part of the structure of the storage device of the first embodiment. [Figure 4] Figure 4 shows some of the components of the storage device of the first embodiment and the connections between the components. [Figure 5] Figure 5 shows the layout of some of the components in the storage device of the first embodiment. [Figure 6] Figure 6 shows the structure of a cross-section of a part of the storage device of the first embodiment. [Figure 7] Figure 7 shows the structure of a cross-section of a part of the storage device of the first embodiment. [Figure 8] Figure 8 shows the structure of a cross-section of a part of the storage device of the first embodiment. [Figure 9] Figure 9 shows the voltage applied to the wiring during a certain operation of the memory device in the first embodiment. [Figure 10] Figure 10 shows one state during the manufacturing of the memory device of the first embodiment. [Figure 11] Figure 11 shows one state during the manufacturing of the memory device of the first embodiment. [Figure 12] Figure 12 shows one state during the manufacturing of the memory device according to the first embodiment. [Figure 13] Figure 13 shows one state during the manufacturing of the memory device according to the first embodiment. [Figure 14] Figure 14 shows one state during the manufacturing of the memory device of the first embodiment. [Figure 15] Figure 15 shows one state during the manufacturing of the memory device of the first embodiment. [Figure 16] Figure 16 shows one state during the manufacturing of the memory device according to the first embodiment. [Figure 17] Figure 17 shows one state during the manufacturing of the memory device according to the first embodiment. [Figure 18] Figure 18 shows one state during the manufacturing of the memory device of the first embodiment. [Figure 19] Figure 19 shows a state during the manufacture of the memory device of the first embodiment. [Figure 20] Figure 20 shows a state during the manufacture of the memory device of the first embodiment. [Figure 21] Figure 21 shows a state during the manufacture of the memory device of the first embodiment. [Figure 22] Figure 22 shows a state during the manufacture of the memory device of the first embodiment. [Figure 23] Figure 23 shows a state during the manufacture of the memory device of the first embodiment. [Figure 24] Figure 24 shows a state during the manufacture of the memory device of the first embodiment. [Figure 25] Figure 25 shows a state during the manufacture of the memory device of the first embodiment. [Figure 26] Figure 26 shows a state during the manufacture of the memory device of the first embodiment. [Figure 27] Figure 27 shows a state during the manufacture of the memory device of the first embodiment. [Figure 28] Figure 28 shows a state during the manufacture of the memory device of the first embodiment. [Figure 29] Figure 29 shows a state during the manufacture of the memory device of the first embodiment. [Figure 30] Figure 30 shows a state during the manufacture of the memory device of the first embodiment. [Figure 31] Figure 31 shows a state during the manufacture of the memory device of the first embodiment. [Figure 32] Figure 32 shows a state during the manufacture of the memory device of the first embodiment. [Figure 33] Figure 33 shows a state during the manufacture of the memory device of the first embodiment. [Figure 34] Figure 34 shows a state during the manufacture of the memory device of the first embodiment. [Figure 35] Figure 35 shows a state during the manufacture of the memory device of the first embodiment. [Figure 36] Figure 36 shows a state during the manufacture of the memory device of the first embodiment. [Figure 37] Figure 37 shows one state during the manufacturing of the memory device according to the first embodiment. [Figure 38] Figure 38 shows one state during the manufacturing of the memory device of the first embodiment. [Figure 39] Figure 39 shows one state during the manufacturing of the memory device according to the first embodiment. [Figure 40] Figure 40 shows the structure of a cross-section of a part of the storage device of the second embodiment. [Figure 41] Figure 41 shows the structure of a cross-section of a part of the storage device of the second embodiment. [Figure 42] Figure 42 shows the structure of a cross-section of a part of the storage device of the second embodiment. [Figure 43] Figure 43 shows one state during the manufacturing of the memory device according to the second embodiment. [Figure 44] Figure 44 shows one state during the manufacturing of the memory device according to the second embodiment. [Figure 45] Figure 45 shows one state during the manufacturing of the memory device according to the second embodiment. [Figure 46] Figure 46 shows one state during the manufacturing of the memory device according to the second embodiment. [Figure 47] Figure 47 shows one state during the manufacturing of the memory device according to the second embodiment. [Figure 48] Figure 48 shows one state during the manufacturing of the memory device according to the second embodiment. [Figure 49] Figure 49 shows the structure of a cross-section of a part of the storage device of the second embodiment. [Figure 50] Figure 50 shows the structure of a cross-section of a part of the storage device of the second embodiment. [Figure 51] Figure 51 shows the structure of a cross-section of a part of the storage device of the second embodiment. [Figure 52] Figure 52 shows the structure of a cross-section of a part of the storage device of the third embodiment. [Figure 53] Figure 53 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 54] Figure 54 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 55]Figure 55 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 56] Figure 56 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 57] Figure 57 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 58] Figure 58 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 59] Figure 59 shows the structure of a cross-section of a part of the storage device of the third embodiment. [Figure 60] Figure 60 shows the structure of a cross-section of a part of the storage device of the third embodiment. [Figure 61] Figure 61 shows the structure of a cross-section of a part of the storage device of the third embodiment. [Figure 62] Figure 62 shows the structure of a cross-section of a part of the storage device of the third embodiment. [Figure 63] Figure 63 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 64] Figure 64 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 65] Figure 65 shows one state during the manufacturing of the memory device according to the third embodiment. [Figure 66] Figure 66 shows the structure of a cross-section of a part of the storage device of the fourth embodiment. [Figure 67] Figure 67 shows the structure of a cross-section of a part of the storage device of the fourth embodiment. [Figure 68] Figure 68 shows one state during the manufacturing of the memory device according to the fourth embodiment. [Figure 69] Figure 69 shows one state during the manufacturing of the memory device according to the fourth embodiment. [Figure 70] Figure 70 shows the structure of a cross-section of a part of the storage device of the fifth embodiment. [Figure 71] Figure 71 shows the structure of a cross-section of a part of the storage device of the fifth embodiment. [Figure 72] Figure 72 shows the structure of a cross-section of a part of the storage device of the fifth embodiment. [Figure 73]Figure 73 shows one state during the manufacturing of the memory device according to the fifth embodiment. [Figure 74] Figure 74 shows one state during the manufacturing of the memory device according to the fifth embodiment. [Figure 75] Figure 75 shows one state during the manufacturing of the memory device according to the fifth embodiment. [Figure 76] Figure 76 shows one state during the manufacturing of the memory device according to the fifth embodiment. [Figure 77] Figure 77 shows the structure of a cross-section of a part of the storage device of the sixth embodiment. [Figure 78] Figure 78 shows the structure of a cross-section of a part of the storage device of the seventh embodiment. [Figure 79] Figure 79 shows one state during the manufacturing of the seventh embodiment of the memory device. [Figure 80] Figure 80 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 81] Figure 81 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 82] Figure 82 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 83] Figure 83 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 84] Figure 84 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 85] Figure 85 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 86] Figure 86 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 87] Figure 87 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 88] Figure 88 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 89] Figure 89 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 90] Figure 90 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 91]Figure 91 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 92] Figure 92 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Figure 93] Figure 93 shows one state during the manufacturing of the memory device according to the seventh embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may have additional numbers or letters appended to the end of their reference numerals to distinguish them from one another. Embodiments following a previously described embodiment primarily describe the differences from the previously described embodiment. All descriptions of an embodiment also apply to descriptions of other embodiments unless explicitly or obviously excluded.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may differ from reality. Furthermore, there may be differences in dimensional relationships and ratios between drawings.

[0009] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0010] The following embodiments are described using a three-dimensional Cartesian coordinate system. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, with upwards pointing in the Z direction. The direction opposite to the Z direction is referred to as the -Z direction, with downwards pointing in the -Z direction.

[0011] 1. First Embodiment 1.1.Configuration (Structure) Figure 1 shows the components and connections of the storage device of the first embodiment. The storage device 1 is a device for storing data. The storage device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a row selection circuit 15, a column selection circuit 16, a write circuit 17, a read circuit 18, and a sense amplifier 19.

[0012] The memory cell array 11 is a collection of multiple memory cells MC arranged in a sequence. Each memory cell MC can store 1 bit of data. Multiple word lines WL and multiple bit lines BL are located within the memory cell array 11. Each memory cell MC is connected to one bit line BL and one word line WL. The memory cell MC is connected between the bit line BL and a plate line (not shown). The word line WL is associated with a row. The bit line BL is associated with a column. By selecting one row and one column, one memory cell MC is identified.

[0013] The input / output circuit 12 is a circuit that performs input and output of data and signals. The input / output circuit 12 receives control signal CNT, command CMD, address signal ADD, and data DAT from outside the storage device 1, for example from the memory controller. The input / output circuit 12 outputs data DAT.

[0014] The control circuit 13 is a circuit that controls the operation of the memory device 1. The control circuit 13 receives a command CMD and a control signal CNT from the input / output circuit 12. Based on the control instructed by the command CMD and the control signal CNT, the control circuit 13 controls the write circuit 17 and the read circuit 18.

[0015] The voltage generation circuit 14 is a circuit that generates various voltages used in the memory device 1. Based on the control of the control circuit 13, the voltage generation circuit 14 generates multiple voltages of different magnitudes. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0016] The row selection circuit 15 is a circuit that selects a row of memory cell MC. The row selection circuit 15 receives an address signal ADD from the input / output circuit 12. The row selection circuit 15 uses the voltage received from the voltage generation circuit 14 to select one word line WL associated with the row identified by the received address signal ADD.

[0017] The column selection circuit 16 is a circuit that selects a column of memory cells MC. The column selection circuit 16 receives an address signal ADD from the input / output circuit 12. The column selection circuit 16 uses the voltage received from the voltage generation circuit 14 to select the bit line BL associated with the column identified by the received address signal ADD.

[0018] The writing circuit 17 is a circuit that performs processing and control for writing data to the memory cell MC. The writing circuit 17 receives data to be written from the input / output circuit 12. Based on the control and data from the control circuit 13, the writing circuit 17 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16.

[0019] The read circuit 18 is a circuit that performs processing and control for reading data from the memory cell MC. Based on the control of the control circuit 13, the read circuit 18 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16. The read circuit 18 supplies multiple control signals for data reading to the sense amplifier 19.

[0020] The sense amplifier 19 is a circuit for determining the data stored in the memory cell MC. The sense amplifier 19 includes multiple sense amplifier circuits SAC (not shown). The sense amplifier 19 receives multiple voltages from the voltage generation circuit 14 and operates using the received voltages. During data reading, the sense amplifier 19 amplifies the potential on the bit line BL to determine the data stored in the memory cell MC from which the data is to be read. The determined data is supplied to the input / output circuit 12.

[0021] Figure 2 shows the components of the memory cell of the first embodiment and the connections of the components. Hereinafter, one of the source and drain of a transistor may be referred to as one end of the transistor, and the other as the other end of the transistor.

[0022] As shown in Figure 2, each memory cell MC includes a cell capacitor CC and an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) CT. The cell capacitor CC is connected to a plate wire PL at one end and to one end of the transistor CT at the other end. The cell capacitor CC stores data using the charge accumulated at the node connected to the transistor CT. The node of the cell capacitor CC connected to the transistor CT may hereafter be referred to as the storage node SN.

[0023] The state of whether a storage node SN is accumulating charge corresponds to the state in which a memory cell MC is storing "1" data or "0" data. For example, a state in which the storage node SN is relatively charged to a positive potential is treated as a state in which the memory cell MC is storing "1" data, and a state in which the storage node SN is not relatively charged to a positive potential is treated as a state in which the memory cell MC is storing "0" data.

[0024] The transistor CT is connected to one bit line BL at its other end and to one word line WL at its gate.

[0025] Figure 3 is a perspective view of a part of the structure of the memory device of the first embodiment. As shown in Figure 3, the memory device 1 comprises a substrate 21, layers LA and LB, sublayers SLA and SLB, conductor 23, insulator 24, conductor 26, insulator 27, semiconductor 28, insulator 29, and conductor 31 Includes.

[0026] Multiple layers LA and LB are located in the Z direction from the substrate 21. Layers LA and LB extend along the xy plane. Layers LA and LB are arranged one by one in the Z direction. Each layer LA contains two sublayers SLA and one sublayer SLB. In each layer LA, one of the two sublayers SLA is located in the Z direction from sublayer SLB, and the other of the two sublayers SLA is located in the -Z direction from sublayer SLB.

[0027] Each sublayer SLA includes one conductor 23 and multiple insulators 24. The conductor 23 extends along the xy plane across the sublayer SLA. In the figure, multiple portions of the conductor 23 that are connected to each other at locations not shown are visible. Two conductors 23 in each of the two sublayer SLAs in each layer LA are connected to each other at locations not shown. Multiple conductors 23 in different layers LA are not connected. In one example, the conductor 23 includes tungsten (W), molybdenum (Mo), or ruthenium (Ru), or is substantially composed of tungsten, molybdenum, or ruthenium. The phrase "substantially composed" and similar phrases mean that the "substantially composed" components may contain unintended impurities. In one example, the conductor 23 includes tungsten, molybdenum, or ruthenium and titanium nitride (TiN) on the surface of the tungsten, molybdenum, or ruthenium. In one example, the conductor 23 comprises polysilicon which is conductive due to the presence of a dopant. In another example, the conductor 23 comprises polysilicon which is conductive due to the presence of a dopant and germanium (Ge) on the surface of the polysilicon. The conductor 23 functions as at least part of a word line WL.

[0028] Each of the several insulators 24 covers the surface of one portion of the conductor 23, i.e., the Z-direction side surface, the -Z-direction side surface, the X-direction side surface, and the -X-direction side surface. The surface of the conductor 23 facing the second portion 262 described later (i.e., the X-direction side surface) is not covered by the insulator 24. The insulator 24 functions as a gate insulator for the transistor CT. In one example, the insulator 24 includes or is substantially composed of silicon oxide, silicon nitride, hafnium oxide, or hafnium-zirconium (Zr) oxide.

[0029] Each sublayer SLB includes one first portion 261, multiple first portions 271, and multiple semiconductors 28. Each first portion 261 is part of the conductor 26. Each first portion 261 extends along the xy plane across the sublayer SLB. In the figure, multiple first portions 261 connected to each other at locations not shown are visible. In one example, the conductor 26 contains or is substantially composed of tungsten, molybdenum, or ruthenium. In one example, the conductor 26 includes tungsten, molybdenum, or ruthenium and titanium nitride on the surface of the tungsten, molybdenum, or ruthenium. In one example, the conductor 26 contains polysilicon which is conductive due to the presence of a dopant. In one example, the conductor 26 contains polysilicon which is conductive due to the presence of a dopant and germanium on the surface of the polysilicon. The conductor 26 functions as at least part of the plate wire PL.

[0030] The first part 271 is part of the insulator 27. Each first part 271 covers the surface of one first part 261, i.e., the Z-direction side face, the -Z-direction side face, the X-direction side face, and the -X-direction side face. In one example, the insulator 27 includes or substantially consists of laminated zirconium oxide, aluminum (Al) oxide, zirconium oxide (ZAZ), hafnium oxide, or hafnium-zirconium oxide. Each first part 271 functions as an insulator for one cell capacitor CC.

[0031] Each semiconductor 28 covers a side surface of one conductor 31, as described later. In one example, the semiconductor 28 contains or is substantially made of silicon. In one example, the semiconductor 28 contains or is substantially made of an oxide semiconductor. Examples of oxide semiconductors include oxides containing one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), tungsten, and molybdenum. More specific examples of oxide semiconductors include In-O, Ga-O, Zn-O, Sn-O, ITO (Indium Tin Oxide), In-Ga-Zn-O, Ti-O, WO, and Mo-O. Each semiconductor 28 is in contact with one insulator 24 on its Z-direction side surface (top surface) and with another insulator 24 on its -Z-direction side surface (bottom surface). Each semiconductor 28 functions as a region in which the channel of one transistor CT is formed.

[0032] Layer LB includes an insulator 29. The insulator 29 extends along the xy-plane across layer LB. In the figure, multiple portions of the insulator 29 that are connected to each other in a location not shown are visible. In one example, the insulator 29 includes or substantially consists of silicon oxide or silicon nitride.

[0033] Each conductor 31 has a columnar shape and extends in the Z direction. The conductors 31 penetrate layers LA and LB. In one example, each conductor 31 contains or is substantially composed of tungsten, molybdenum, or ruthenium. In one example, the conductor 31 contains tungsten, molybdenum, or ruthenium and titanium nitride on the surface of the tungsten, molybdenum, or ruthenium. In one example, the conductor 31 contains polysilicon which is conductive due to the presence of a dopant. In one example, the conductor 31 contains polysilicon which is conductive due to the presence of a dopant and germanium on the surface of the polysilicon. The conductor 31 functions as part of a single bit line BL.

[0034] Each second portion 262 of the conductor 26 extends along the yz-plane. The second portion 262 is connected to the first portion 261. The first portion 261 and the second portion 262 are a single unit.

[0035] Each second portion 272 of the insulator 27 covers the side (the X-direction side) of the second portion 262 and extends along the yz plane. The second portion 272 is connected to several first portions 271. The connected first portions 271 and second portions 272 are a single unit. The second portion 272 covers the surface of the conductor 23 that faces the second portion 262 (i.e., the X-direction side).

[0036] A certain semiconductor 28, an insulator 24 in contact with the semiconductor 28, and the portion of the conductor 23 that faces the semiconductor 28 via the insulator 24 function as a single transistor CT.

[0037] A certain semiconductor 28, a first portion 271 in contact with the semiconductor 28, and a portion of the conductor 26 that faces the semiconductor 28 via the first portion 271 function as a single cell capacitor CC.

[0038] Figure 3 shows an example with two layers of LA, but three or more layers of LA may be provided.

[0039] Figure 4 shows some of the components of the storage device of the first embodiment and the connections between the components. Figure 4 is a circuit diagram of the structure shown in Figure 3, and each component (element in the circuit) is shown in correspondence with its position in the structure shown in Figure 3.

[0040] Referring to Figure 3, and based on the structure described above, each memory cell MC, as shown in Figure 4, includes two transistors CT_A and CT_B connected in parallel. The gates of transistor CT_A and CT_B are connected. In each layer LA, multiple memory cells MC are arranged in the X and Y directions.

[0041] The bit line BL extends in the Z direction and is connected to multiple transistors CT_A and CT_B in multiple different layers LA.

[0042] Figure 5 shows the layout of components in a part of the storage device of the first embodiment. Figure 5 shows the region located in the Z direction from the structure shown in Figure 3, along the xy plane.

[0043] As shown in Figure 5, several conductors 31 are arranged in the X direction to form a row. Figure 5 shows an example where each row of conductors 31 contains three conductors 31. Each row of the pillar may contain four or more conductors 31. The rows of conductors 31 are arranged in the Y direction. The x-axis positions (coordinates) of two adjacent conductors 31 in the Y direction are offset. That is, when one first row of conductors 31 is adjacent to another second row of conductors 31, the conductors 31 have the following arrangement: Each conductor 31 in the first row is not aligned in the X direction with any of the conductors 31 in the second row. The x-axis coordinate (x-axis coordinate) of each conductor 31 in the first row is between the x-axis coordinates of two adjacent conductors 31 in the second row. In one example, the x-axis coordinate of each conductor 31 in the first column is the x-axis coordinate of the midpoint between the x-axis coordinates of two adjacent conductors 31 in the second column.

[0044] The memory device 1 further includes a plurality of conductors 33. The conductors 33 extend in the X direction and are aligned in the Y direction. Each conductor 33 overlaps with at least one conductor 31. In the example of Figure 5, three aligned conductors 33 overlap with one row of conductors 31. Each conductor 33 is connected to one conductor 31 via a contact CP. The contact CP is in contact with one conductor 31 and another conductor 31. Each conductor 33 functions as part of one bit line BL.

[0045] Figures 6, 7, and 8 show the structure of a cross-section of a part of the memory device of the first embodiment. Figure 7 shows the structure of the sublayer SLA along the xy plane, and the structure along the line VII-VII in Figure 6. Figure 8 shows the structure of the sublayer SLB along the xy plane, and the structure along the line VIII-VIII in Figure 6. Figure 6 shows the structure along the line VI-VI in Figures 7 and 8.

[0046] As shown in Figures 6, 7, and 8, each insulator 24 surrounds one conductor 31 along the xy-plane. Each insulator 24 is surrounded by one conductor 23.

[0047] Each semiconductor 28 surrounds one conductor 31 along the xy plane. Each semiconductor 28 is surrounded along the xy plane by an insulator 27 (in particular, a first portion 271). Each insulator 27 (in particular, a first portion 271) is surrounded by a conductor 26.

[0048] 1.2.Operation The voltage applied to the wiring during data writing and reading is the same as that in a typical DRAM, as described below.

[0049] Figure 9 shows the voltage applied to the wiring during a certain operation of the memory device in the first embodiment. As shown in Figure 9, "Selected" in the figure indicates that the wiring belonging to the "Selected" column is connected to the memory cell MC that is the target of data writing or reading, i.e., it is a selected wiring. "Not Selected" indicates that the wiring belonging to the "Not Selected" column is not a selected wiring.

[0050] During the writing of "1" data, the writing of "0" data, and the reading of data, the unselected bit line (unselected bit line) BL, the unselected word line (unselected word line) WL, and the plate line PL receive voltages Vdd / 2, ground voltage Vss, and Vdd / 2, respectively. The ground voltage Vss is the ground voltage supplied to the storage device 1 from outside the storage device 1, and is 0V in one example. Voltage Vdd is the power supply voltage supplied to the storage device 1 from outside the storage device 1, and is higher than the ground voltage Vss.

[0051] During the writing of "1" data, the selected bit line (selected bit line) BL, the selected word line (selected word line) WL, and the plate line PL receive voltages Vdd, Vpp, and Vdd / 2, respectively. Voltage Vpp is an internal voltage generated by the voltage generation circuit 14 from the power supply voltage Vdd, and in one example, is lower than the power supply voltage Vdd.

[0052] During the writing of "0" data, the selection bit line BL, selection word line WL, and plate line PL receive the ground voltage Vss, voltage Vpp, and voltage Vdd / 2, respectively.

[0053] During data retrieval, the selection word line WL and the plate line PL receive voltages Vpp and Vdd / 2, respectively. During data retrieval, the selection bit line BL receives voltage Vdd / 2, then stops receiving voltage Vdd / 2, i.e., is placed in an electrically floating state. During the stopped (i.e., electrically floating) period, a potential based on the data stored in the memory cell MC to be retrieved appears on the bit line BL. Subsequently, the potential on the bit line BL is amplified by a sense amplifier to perform data discrimination.

[0054] 1.3. Manufacturing method Figures 10 to 39 show a state during the manufacturing of the memory device of the first embodiment. Figures 10, 13, 16, 18, 21, 24, 27, 30, 32, 35, and 38 show the region shown in Figure 6. Figures 11, 14, 19, 22, 25, 28, 31, 33, and 36 show the region shown in Figure 7. Figures 12, 15, 17, 20, 23, 26, 29, 34, 37, and 39 show the region shown in Figure 8.

[0055] As shown in Figures 10, 11, and 12, multiple sets of insulator 29A, sacrificial material 41, sacrificial material 42, and sacrificial material 41 are deposited. In each set, sacrificial material 41 is located on the Z-side surface (top surface) of insulator 29A, sacrificial material 42 is located on the top surface of sacrificial material 41, and sacrificial material 41 is located on the top surface of sacrificial material 42.

[0056] Insulator 29A occupies the layer where layer LB is to be located. Insulator 29A is an element that will be formed into insulator 29 in a later process. Insulator 29A contains the same material as insulator 29, or is substantially made from the same material as insulator 29.

[0057] The sacrificial material 41 occupies the layer in which the sublayer SLA is to be located. The sacrificial material 41 consists of a material having a different etching rate from that of the insulator 29A and the sacrificial material 42 for a given etching. In one example, the sacrificial material 41 contains or is substantially composed of silicon nitride.

[0058] The sacrificial material 42 occupies the layer where the sublayer SLB is to be located. The sacrificial material 42 is made of a material having a different etching rate from that of the insulator 29A and the sacrificial material 41 for a given etching. In one example, the semiconductor 28 contains or is substantially made of polysilicon.

[0059] Examples of methods for forming the insulator 29A, sacrificial material 41, and sacrificial material 42 include CVD (Chemical Vapor Deposition).

[0060] As shown in Figures 13, 14, and 15, a hole HL is formed. The hole HL extends in the Z direction and penetrates the insulator 29A, sacrificial material 41, and sacrificial material 42. The hole HL is located in the region where the conductor 31 is to be formed. In the hole HL, the insulator 29A, sacrificial material 41, and sacrificial material 42 are exposed. An example of a method for forming a hole HL includes a combination of a photolithography process and anisotropic etching. More specifically, a mask with an opening is formed on the upper surface of the uppermost insulator 29A. The mask has an opening above the region where the hole HL is to be formed. Anisotropic etching is then performed through the mask. An example of anisotropic etching includes RIE (Reactive Ion Etching).

[0061] As shown in Figures 16 and 17, the portion of the sacrificial material 42 that includes the surface exposed in the hole HL is removed. This creates a space SP1 in the region where the removed portion of the sacrificial material 42 was located. Space SP1 is connected to the hole HL. Space SP1 surrounds the hole HL along the xy plane. An example of a removal method includes wet etching.

[0062] As shown in Figures 18, 19, and 20, semiconductor 28A is formed. Semiconductor 28A is an element that will be formed into semiconductor 28 in a later process. Semiconductor 28A fills holes HL and spaces SP1. Semiconductor 28A is in contact with sacrificial material 42 in spaces SP1. Semiconductor 28A is made of substantially the same material as semiconductor 28. An example of a method for forming semiconductor 28A includes CVD.

[0063] As shown in Figures 21, 22, and 23, semiconductor 28A is partially removed. Specifically, the portion of semiconductor 28A containing holes HL is removed. This removal allows semiconductor 28 to be formed from the portion of semiconductor 28A other than the portion containing holes HL. The partial removal of semiconductor 28A allows holes HL to be re-formed. Examples of removal methods include anisotropic etching such as RIE.

[0064] As shown in Figures 24, 25, and 26, a conductor 31 is formed. The conductor 31 fills the hole HL. The conductor 31 is in contact with the semiconductor 28. An example of a formation method includes CVD.

[0065] As shown in Figures 27, 28, and 29, a slit SLT is formed. The slit SLT is located in the region where the second portion 262 of the conductor 26 and the second portion 272 of the insulator 27 are to be formed. The slit SLT penetrates the insulator 29A, as well as the sacrificial materials 41 and 42. The slit SLT extends along the xz plane. An example of a formation method includes a combination of a photolithography process and anisotropic etching. An example of anisotropic etching includes RIE.

[0066] As shown in Figures 30 and 31, the sacrificial material 41 is removed. The removal creates a space SP2 in the area where the sacrificial material 41 was located. Space SP2 is connected to the slit SLT. An example of a removal method includes wet etching. The wet etching solution reaches the sacrificial material 41 from the slit SLT and removes the sacrificial material 41.

[0067] As shown in Figures 32, 33, and 34, an insulator 24A and a conductor 23A are formed. Specifically, first, the insulator 24A is formed. The insulator 24A covers the surface of the space SP2 and the surface of the element defining the slit SLT. That is, the insulator 24A covers the surface of the insulator 29 exposed in space SP2 and the surface exposed in the slit SLT, and the surface of the sacrificial material 42 exposed in space SP2 and the surface exposed in the slit SLT. The insulator 24A covers the portion of the semiconductor 28 surface exposed in space SP2. The insulator 24A is an element that will be formed into the insulator 24 in a later process. The insulator 24A is substantially made of the same material as the insulator 24. An example of a method for forming the insulator 24A includes CVD.

[0068] Next, the space SP2 and the slit SLT are filled with the conductor 23A. The conductor 23A is an element that will be formed into the conductor 23 in a later process. The conductor 23A is substantially made of the same material as the conductor 23. An example of a method for forming the conductor 23A includes CVD.

[0069] As shown in Figures 35, 36, and 37, the conductor 23A and the insulator 24A are partially removed. Specifically, the portion of the conductor 23A within the slit SLT is removed first. This forms the conductor 23 from the remaining portion of the conductor 23A. An example of a method for partial removal of the conductor 23A includes a combination of a photolithography process and anisotropic etching. An example of anisotropic etching includes RIE.

[0070] Next, the portion of the insulator 24A within the slit SLT, i.e., the portion of the insulator 24A that is on the surface of the insulator 29 and sacrificial material 42 facing the slit SLT, is removed. This forms the insulator 24 from the remaining portion of the insulator 24A. An example of a method for partial removal of the insulator 24A includes a combination of a photolithography process and anisotropic etching. An example of anisotropic etching includes RIE.

[0071] By partially removing the conductor 23A and the insulator 24A, the slit SLT is reformed.

[0072] As shown in Figures 38 and 39, the sacrificial material 42 is removed. The removal of the sacrificial material 42 creates a space SP3 in the area where the sacrificial material 42 was located. Space SP3 is connected to the slit SLT. Space SP3 surrounds the semiconductor 28 along the xy plane. Space SP3 exposes the semiconductor 28. An example of a removal method includes wet etching. The wet etching solution reaches the sacrificial material 42 from the slit SLT and removes the sacrificial material 42.

[0073] As shown in Figures 6, 7, and 8, the insulator 27 and the conductor 26 are formed. That is, first, the surfaces of the elements defining the slit SLT and space SP2 are covered. Specifically, the insulator 27 covers the surface of the insulator 29 exposed in the slit SLT, the surface of the conductor 23 exposed in the slit SLT, the surface of the insulator 24 exposed in the slit SLT and space SP3, and the portion of the semiconductor 28 exposed in space SP3. An example of a deposition method is CVD.

[0074] Next, a conductor 26 is formed on the insulator 27. The conductor 26 fills the slit SLT and space SP3 through the insulator 27. An example of the formation method includes CVD.

[0075] 1.4. Advantages (Effects) The memory device 1 of the first embodiment includes a conductor 31 extending in the Z direction, a semiconductor 28 surrounding the conductor 31, an insulator 27 surrounding the semiconductor 28, a conductor 26 surrounding the insulator 27, an insulator 24 located in the Z or -Z direction from the semiconductor 28 and in contact with the semiconductor 28, and a conductor 23 located in the Z or -Z direction from the semiconductor 28, in contact with the insulator 24 and surrounding the conductor 31. The semiconductor 28, the insulator 24, and the portion of the conductor 23 that faces the semiconductor 28 via the insulator 24 can function as a single transistor CT. The semiconductor 28, the insulator 27, and the conductor 26 can function as a single cell capacitor CC. Therefore, the structure of the memory device 1 makes it possible to realize a DRAM structure having a small memory cell MC.

[0076] 2. Second Embodiment 2.1. Structure Figures 40, 41, and 42 show the structure of a cross-section of a part of the storage device of the second embodiment. Figures 40, 41, and 42 show regions corresponding to the regions shown in Figures 6, 7, and 8 of the first embodiment, respectively. Figure 41 shows the structure along the XLI-XLI line in Figure 40. Figure 42 shows the structure along the XLII-XLII line in Figure 40. Figure 40 shows the structure along the XL-XL line in Figures 41 and 42.

[0077] As shown in Figures 40, 41, and 42, the memory device 1 of the second embodiment further includes a plurality of conductors 45. The conductors 45 are located in the sublayer SLB (the layer on which the semiconductor 28 is located). Each conductor 45 surrounds one semiconductor 28, is in contact with one semiconductor 28, and covers one semiconductor 28 along the xy plane. Each conductor 45 is surrounded by one insulator 27 along the xy plane. In one example, the conductors 45 include or are substantially made of ITO or titanium nitride.

[0078] 2.2. Manufacturing method Figures 43 to 48 show a state during the manufacturing of the memory device of the second embodiment. Figures 43, 45, and 47 show the region shown in Figure 40. Figures 44, 46, and 48 show the region shown in Figure 42.

[0079] First, the steps up to the above-described steps are performed with reference to Figures 16 and 17 of the manufacturing method of the first embodiment.

[0080] As shown in Figures 43 and 44, an insulator 27 and a conductor 45 are formed. The insulator 27 covers the surface of the sacrificial material 42 that is exposed in space SP1. The conductor 45 covers the surface of the insulator 27 that is exposed in space SP1.

[0081] As shown in Figures 45 and 46, semiconductor 28A is formed. Semiconductor 28A fills the holes HL and space SP1. Semiconductor 28A is in contact with the conductor 45 in space SP1.

[0082] As shown in Figures 47 and 48, the conductor 31, conductor 23, insulator 24, and slit SLT are formed. That is, first, the portion of the semiconductor 28A in the holes HL is removed by the same process as described above with reference to Figures 21 to 23 of the first embodiment, thereby forming the semiconductor 28.

[0083] The conductor 31 is formed by the same process as described above, referring to Figures 24 to 26 of the first embodiment.

[0084] The slit SLT is formed by the same process as described above, referring to Figures 27 to 29 of the first embodiment.

[0085] The sacrificial material 41 is removed by the same process as described above, with reference to Figures 30 and 31 of the first embodiment, thereby forming the space SP2.

[0086] The conductor 23 and the insulator 24 are formed, and the slit SLT is formed, by the same steps as described above with reference to Figures 32 to 34 of the first embodiment, and by the same steps as described above with reference to Figures 35 to 37.

[0087] The sacrificial material 42 is removed by the same process as described above, referring to Figures 38 and 39 of the first embodiment, thereby forming the space SP3.

[0088] As shown in Figures 40, 41, and 42, the insulator 27 and the conductor 26 are formed by the same process as described above with reference to Figures 6, 7, and 8 of the first embodiment.

[0089] 2.3. Advantages The structure of the second embodiment also enables the realization of a DRAM structure having small memory cells (MC), similar to the structure of the first embodiment.

[0090] 2.4. Variations The conductor 45 may be formed using a slit SLT. That is, after the steps described above with reference to Figures 38 and 39 of the first embodiment, the conductor 45 is formed on the surface of the semiconductor 28 exposed in space SP3 through the slit SLT. Subsequently, the insulator 24 is formed.

[0091] 3. Third Embodiment 3.1. Composition Figures 49, 50, and 51 show the cross-sectional structure of a part of the memory device of the third embodiment. Figures 49, 50, and 51 show regions corresponding to the regions shown in Figures 6, 7, and 8 of the first embodiment, respectively. Figure 50 shows the structure along the LI-LI line in Figure 49. Figure 51 shows the structure along the xy plane of the sublayer SLB and the structure along the LII-LII line in Figure 49. Figure 49 shows the structure along the XLIX-XLIX line in Figures 50 and 51.

[0092] As shown in Figures 49, 50, and 51, the memory device 1 of the third embodiment does not include a semiconductor 28, but instead includes an oxide semiconductor 48. The memory device 1 of the third embodiment further includes conductors 51, 52, 53, and 54.

[0093] The oxide semiconductor 48 occupies the region of the semiconductor 28 in the first embodiment. The oxide semiconductor 48 is conductive. Examples of oxide semiconductors 48 include oxides containing one or more of indium, gallium, zinc, tin, titanium, tungsten, and molybdenum.

[0094] The conductor 51 surrounds, contacts, and covers the conductor 31 along the xy-plane. The conductor 51 has a cylindrical shape. The conductor 51 extends in the Z direction and, like the conductor 31, penetrates layers LA and LB. In one example, the conductor 51 contains or is substantially made of titanium nitride.

[0095] The conductor 52 surrounds, contacts, and covers the conductor 51 along the xy-plane. The conductor 52 has a cylindrical shape. The conductor 52 extends in the Z direction and, like the conductor 31, penetrates layers LA and LB. In one example, the conductor 52 contains or is substantially made of ITO.

[0096] The conductor 53 is located in the sublayer SLB (the layer on which the oxide semiconductor 48 is located). Each conductor 53 surrounds one oxide semiconductor 48, is in contact with one oxide semiconductor 48, and covers the conductor 53 along the xy plane. In one example, the conductor 53 contains or is substantially made of ITO.

[0097] The conductors 54 are located in the sublayer SLB (the layer on which the semiconductor 28 is located). Each conductor 54 surrounds, touches, and covers one conductor 53 along the xy plane. Each conductor 54 is surrounded by one insulator 27 along the xy plane. In one example, the conductors 54 contain or are substantially made of titanium nitride.

[0098] 3.2. Manufacturing method Figures 52 to 65 show a state during the manufacturing of the memory device of the third embodiment. Figures 52, 54, 57, 60, and 63 show the region shown in Figure 49. Figures 55, 58, 61, and 64 show the region shown in Figure 50. Figures 53, 56, 59, 62, and 65 show the region shown in Figure 51.

[0099] First, the steps up to the steps described above are performed with reference to Figures 16 and 17 of the first embodiment.

[0100] As shown in Figures 52 and 53, conductors 54 and 53 are formed. Conductor 54 covers the surface of the sacrificial material 42 that is exposed in the space SP1. Conductor 54 covers the surface of conductor 53.

[0101] As shown in Figures 54, 55, and 56, a sacrificial material 56 is formed. The sacrificial material 56 fills the hole HL and the space SP1. In one example, the sacrificial material 56 contains or is substantially made of amorphous silicon. An example of a formation method includes CVD.

[0102] As shown in Figures 57, 58, and 59, the conductor 23, the insulator 24, and the slit SLT are formed. That is, first, the slit SLT is formed by the same process as described above with reference to Figures 27 to 29 of the first embodiment.

[0103] The sacrificial material 41 is removed by the same process as described above, with reference to Figures 30 and 31 of the first embodiment, thereby forming the space SP2.

[0104] The conductor 23 and the insulator 24 are formed, and the slit SLT is formed, by the same steps as described above with reference to Figures 32 to 34 of the first embodiment, and by the same steps as described above with reference to Figures 35 to 37.

[0105] The sacrificial material 42 is removed by the same process as described above, referring to Figures 38 and 39 of the first embodiment, thereby forming the space SP3.

[0106] As shown in Figures 60, 61, and 62, the insulator 27 and the conductor 26 are formed by the same process as described above with reference to Figures 6, 7, and 8 of the first embodiment.

[0107] As shown in Figures 63, 64, and 65, an oxide semiconductor 48 is formed. That is, first, the sacrificial material 56 is removed. By removal, holes HL and spaces SP1 are reformed. An example of a removal method includes wet etching.

[0108] The oxide semiconductor 48A is formed by the same process as described above, with reference to Figures 18, 19, and 20 of the first embodiment. The oxide semiconductor 48A fills the holes HL and spaces SP1. An example of the formation method includes CVD.

[0109] The oxide semiconductor 48A is partially removed by the same process as described above, with reference to Figures 21, 22, and 23 of the first embodiment. As a result, the oxide semiconductor 48 is formed from the remaining portion of the oxide semiconductor 48A. Due to the partial removal of the oxide semiconductor 48A, holes HL are formed again. The oxide semiconductor 48 is exposed in the holes HL.

[0110] As shown in Figures 49, 50, and 51, the conductors 52, 51, and 31 are formed. Specifically, the conductor 52 is first formed on the surface of the element defining the hole HL, i.e., on the surface of the insulator 29 exposed in the hole HL, and on the surface of the insulator 27 exposed in the hole HL. An example of a formation method includes CVD.

[0111] A conductor 51 is formed on the surface of the conductor 52. An example of a formation method includes CVD.

[0112] A conductor 31 is formed on the surface of the conductor 51. The conductor 31 fills the areas of hole HL where conductors 51 and 52 are not located.

[0113] 3.3. Advantages The structure of the third embodiment also enables the realization of a DRAM structure having small memory cells (MC), similar to the structure of the first embodiment.

[0114] 3.4. Variant The memory device 1 does not necessarily have to include one or more of the conductors 51, 52, 53, and 54. Also, the third embodiment and the first embodiment may be combined. That is, the memory device 1 includes a semiconductor 28 instead of an oxide semiconductor 48 and includes one or more of the conductors 51, 52, 53, and 54.

[0115] 4. Fourth Embodiment The fourth embodiment can be combined with the first, second, or third embodiment. The following description relates to an example in which the fourth embodiment is based on the third embodiment.

[0116] 4.1. Composition Figures 66 and 67 show the structure of a cross-section of a part of the memory device of the fourth embodiment. Figures 66 and 67 show regions corresponding to the regions shown in Figures 6 and 8 of the first embodiment, respectively. Figure 67 shows the structure along the line LXVII-LXVII in Figure 66. Figure 66 shows the structure along the line LXVI-LXVI in Figure 67. The structure of the layer in which the conductor 23 is located is the same as in Figure 50 of the third embodiment.

[0117] As shown in Figures 66 and 67, the memory device 1 of the fourth embodiment does not include a semiconductor 28, but instead includes an insulator 61 and a semiconductor 62. The insulator 61 and semiconductor 62 pair occupy the position of the semiconductor 28. The insulator 61 is in contact with the conductor 52. In one example, the insulator 61 includes or is substantially made of silicon oxide.

[0118] The semiconductor 62 covers the surface of the insulator 61, excluding the portion that is in contact with the conductor 53. That is, the semiconductor 62 is located between the insulator 61 and the insulator 27, and between the insulator 61 and the conductor 53, and is in contact with the insulator 27 and the conductor 53. The semiconductor 62 contains or is substantially made of the same material as the semiconductor 28.

[0119] 4.2. Manufacturing method Figures 68 and 69 show a state during the manufacturing of the storage device of the fourth embodiment. Figure 68 shows the region shown in Figure 66. Figure 69 shows the region shown in Figure 67.

[0120] First, the steps up to those described above are performed with reference to Figures 60, 61, and 62 of the fourth embodiment.

[0121] As shown in Figures 69 and 70, the sacrificial material 56 is removed by the same process as described above with reference to Figures 63, 64, and 65 of the fourth embodiment. The semiconductor 62A is then formed in the holes HL and space SP1. The semiconductor 62A covers the surface of the insulator 29 exposed in the holes HL, the surface of the insulator 27 exposed in the holes HL and space SP1, and the surface of the conductor 53 in space SP1. An example of a formation method includes CVD.

[0122] Next, the surface portions of the semiconductor 62A that are exposed in the holes HL of the insulator 29 and the surface portions of the insulator 27 that are exposed in the holes HL are removed. As a result, the semiconductor 62 is formed from the remaining portions.

[0123] Next, an insulator 61 is deposited on the semiconductor 62. The subsequent steps are the same as those described above with reference to Figures 63, 64, and 65 of the fourth embodiment.

[0124] 4.3. Advantages The structure of the third embodiment, like that of the first embodiment, can realize a DRAM structure having small memory cells (MC). Furthermore, according to the fourth embodiment, the presence of the insulator 61 results in small channel deposition of the transistor CT. Therefore, the transistor CT is easily cut off.

[0125] 5. Fifth Embodiment The fifth embodiment can be combined with the first, second, third, or fourth embodiment. The following description relates to an example in which the fifth embodiment is based on the second embodiment.

[0126] 5.1. Composition Figures 70, 71, and 72 show the structure of a cross-section of a part of the memory device of the fifth embodiment. Figures 70, 71, and 72 show regions corresponding to the regions shown in Figures 6, 7, and 8 of the first embodiment, respectively. Figure 71 shows the structure along the line LXXI-LXXI in Figure 70. Figure 72 shows the structure along the line LXXII-LXXII in Figure 70. Figure 70 shows the structure along the line LXX-LXX in Figures 71 and 72.

[0127] As shown in Figures 70, 71, and 72, the storage device 1 of the fifth embodiment does not include the conductor 23, but instead includes the conductor 65.

[0128] Each conductor 65 is located in the sublayer SLA. Each conductor 65 surrounds, touches, and covers one conductor 31 along the xy plane. The surface of each conductor 65 is covered by an insulator 24. Each conductor 65 faces one conductor 31 through the insulator 24. Depending on the dimensions and arrangement of the conductors 31, the conductors 65 surrounding each adjacent conductor 31 are connected to each other, and the insulators 24 surrounding each adjacent conductor 31 are connected to each other. Figures 70, 71, and 72 show such examples. When adjacent conductors 31 are sufficiently far apart, the conductors 65 and the insulators 24 are independent.

[0129] In the sublayer SLA, a sacrificial material 41 is provided in the regions where the conductor 31, conductor 65, insulator 24, conductor 26, and insulator 27 are not located.

[0130] 5.2. Manufacturing method Figures 73 to 76 show a state during the manufacturing of the memory device of the fifth embodiment. Figures 73 and 75 show the region shown in Figure 70. Figures 74 and 76 show the region shown in Figure 71.

[0131] First, the steps up to the above-described steps are performed with reference to Figures 13, 14, and 15 of the manufacturing method of the first embodiment.

[0132] As shown in Figures 73 and 74, the portion of the sacrificial material 41 that includes the surface exposed in the hole HL is removed. This creates a space SP4 in the region where the removed portion of the sacrificial material 41 was located. The space SP4 is connected to the hole HL. The space SP4 surrounds the hole HL along the xy plane. An example of the removal method includes wet etching. The space SP4 occupies the region where the conductor 65 and insulator 24 are formed. Therefore, the shape of the space SP4 depends on the shape of the conductor 65 and insulator 24. In the example in Figures 73 and 74, multiple spaces SP4 are connected to each other in adjacent holes HL.

[0133] As shown in Figures 75 and 76, the insulator 24 and the conductor 65 are formed. The insulator 24 covers the surface of the element defining the space SP4. That is, the insulator 24 covers the surface of the insulator 29A exposed by the space SP4, the surface of the sacrificial material 42 exposed by the space SP4, and the surface of the sacrificial material 41 exposed by the space SP4. An example of a formation method includes CVD.

[0134] A conductor 65 is formed on the surface of the insulator 24. The conductor 65 fills the region of space SP4 where the insulator 24 is not located. An example of a formation method includes CVD.

[0135] Further, the remaining portion of the insulator 24 is formed on the surface of the conductor 65 that is exposed by the holes HL. An example of a formation method includes CVD.

[0136] The conductor 31 is formed by the same process as described above, referring to Figures 24 to 26 of the first embodiment.

[0137] The slit SLT is formed by the same process as described above, referring to Figures 27 to 29 of the first embodiment.

[0138] The sacrificial material 42 is removed by the same process as described above, referring to Figures 38 and 39 of the first embodiment, thereby forming the space SP3.

[0139] As shown in Figures 70, 71, and 72, the insulator 27 and the conductor 26 are formed by the same process as described above with reference to Figures 6, 7, and 8 of the first embodiment.

[0140] 5.3. Advantages The structure of the fifth embodiment also enables the realization of a DRAM structure having small memory cells (MC), similar to the structure of the first embodiment.

[0141] 6. Sixth Embodiment The sixth embodiment can be combined with the first, second, third, fourth, or fifth embodiment. The following description relates to an example in which the sixth embodiment is based on the second embodiment.

[0142] Figure 77 shows the structure of a cross-section of a part of the storage device of the sixth embodiment. Figure 77 shows the region corresponding to the region shown in Figure 6 of the first embodiment.

[0143] As shown in Figure 77, the storage device 1 of the sixth embodiment does not include the conductor 23 and the insulator 24 in one of the sublayers SLA within each layer LA. The region that does not include the conductor 23 and the insulator 24 is provided with an insulator 29. Figure 77 shows an example in which the lower sublayer SLA does not include the conductor 23 and the insulator 24.

[0144] The structure of the sixth embodiment also enables the realization of a DRAM structure having small memory cells (MC), similar to the structure of the first embodiment.

[0145] 7. Seventh Embodiment The seventh embodiment can be combined with the first, second, third, fourth, fifth, or sixth embodiment. The following description relates to an example in which the seventh embodiment is based on the second embodiment.

[0146] 7.1. Composition Figure 78 shows the structure of a cross-section of a part of the memory device of the seventh embodiment. Figure 78 corresponds to the region shown in Figure 6 of the first embodiment.

[0147] As shown in Figure 78, the memory device 1 further includes an oxidized region 71 in the substrate 21. The memory device 1 of the seventh embodiment includes an insulator 72 instead of an insulator 29.

[0148] The oxidation region 71 is located below the set of conductors 31, 51, and 52, and includes the upper surface of the substrate 21. The oxidation region 71 contains oxides of the substrate 21 material.

[0149] In the seventh embodiment, unlike the first embodiment, the conductor 26 protrudes away from the center in layer LB (the layer in which the insulator 72 is located). That is, the conductor 26 includes a portion located between two conductors 23 aligned in the Z direction in layer LB. Based on this shape of the conductor 26, the insulator 27 also includes a portion located between two conductors 23 aligned in the Z direction in layer LB.

[0150] 7.2. Manufacturing method Figures 79 to 93 show one state during the manufacturing of the memory device of the seventh embodiment. Figures 79 to 93 show the region shown in Figure 78.

[0151] As shown in Figure 79, multiple sacrificial materials 75 and multiple sacrificial materials 76a are formed alternately one by one in the Z direction on the substrate 21.

[0152] The sacrificial material 75 occupies the layer in which the sublayer SLA is to be located. In one example, the sacrificial material 75 contains or is substantially composed of silicon nitride. An example of a method for forming the sacrificial material 75 includes CVD.

[0153] Sacrificial material 76a occupies the layer where the sublayer SLA is to be located and the layer where layer LB is to be located. The sacrificial material 76a in the layer where the sublayer SLA is to be located may be referred to as sacrificial material 76a_1. The sacrificial material 76a in the layer where layer LB is to be located may be referred to as sacrificial material 76a_2. The thickness of sacrificial material 76a_2 (dimension along the Z direction) is smaller than the thickness of sacrificial material 76a_1. In one example, sacrificial material 76a contains silicon oxide. An example of a method for forming sacrificial material 76a includes CVD.

[0154] As shown in Figure 80, a hole HL is formed. The hole HL extends in the Z direction and penetrates the sacrificial materials 75 and 76a. The sacrificial materials 75 and 76a are exposed within the hole HL. At the bottom of the hole HL, the substrate 21 is exposed. An example of a formation method includes a combination of a photolithography process and anisotropic etching.

[0155] As shown in Figure 81, the portion of the sacrificial material 76a including the surface exposed in the hole HL is removed. This creates a space SP5 in the region where the removed portion of the sacrificial material 76a was located, and sacrificial material 76_1 is formed from sacrificial material 76a_1. Space SP5 is connected to the hole HL. Space SP5 surrounds the hole HL along the xy plane. An example of a removal method includes wet etching.

[0156] As shown in Figure 82, sacrificial material 76b is formed in the hole HL and space SP1. Sacrificial material 76b contains or is substantially made of the same material as sacrificial material 76a. Sacrificial material 76b covers the surface of the element defining the hole HL and the surface of the element defining space SP1. That is, sacrificial material 76b covers the surface of sacrificial material 75 exposed in the slit SLT and space SP5, the surface of sacrificial material 76a exposed in the slit SLT and space SP5, and the surface of substrate 21 exposed in the hole HL. Due to the difference in thickness between sacrificial material 76_1 and 76a_2, sacrificial material 76b fills the space SP5 in contact with sacrificial material 76a_2. On the other hand, due to the difference in thickness between sacrificial material 76_1 and 76a_2, sacrificial material 76b does not fill the space SP5 in contact with sacrificial material 76a_1, and the space SP5 in contact with sacrificial material 76_1 remains partially intact. An example of a method for depositing the sacrificial material 76b includes CVD.

[0157] As shown in Figure 83, the sacrificial material 76b is partially removed. Specifically, the portion of the sacrificial material 76b in the hole HL and the portion in contact with the sacrificial material 76_1 are removed. This allows the space SP5 to be reformed in the layer where the sacrificial material 76_1 is located. On the other hand, even after the removal, the portion of the sacrificial material 76b in contact with the sacrificial material 76a_2 remains. This allows the sacrificial material 76_2 to be formed in the layer where the sacrificial material 76_2 is located by the remaining portions of the sacrificial material 76a_2 and the sacrificial material 76b. An example of a removal method includes wet etching.

[0158] Next, the surface of the substrate 21 that is exposed in the hole HL is oxidized, forming an oxidized region 71.

[0159] As shown in Figure 84, a sacrificial material 56 is formed. The sacrificial material 56 fills the hole HL and the space SP5. An example of the formation method is CVD.

[0160] As shown in Figure 85, the slit SLT is formed by the same process as described above with reference to Figures 27, 28, and 29 of the first embodiment. The slit SLT extends in the Z direction and penetrates the sacrificial materials 75 and 76.

[0161] As shown in Figure 86, the sacrificial material 75 is removed by the same process as described above with reference to Figures 30 and 31 of the first embodiment. This creates a space SP6 in the area where the sacrificial material 75 was located. Space SP6 is connected to the slit SLT. Space SP6 surrounds the hole HL along the xy plane. An example of removal includes wet etching. The wet etching solution reaches the sacrificial material 75 from the slit SLT and removes the sacrificial material 75.

[0162] As shown in Figure 87, the insulator 24 and conductor 23 are formed in the space SP6 by the same process as described above with reference to Figures 32, 33, 34, 35, 36, and 37 of the first embodiment. The insulator 24 covers the surface of the elements that define the space SP6. That is, the insulator 24 covers the surface of the sacrificial material 76 exposed in the space SP6 and the surface of the sacrificial material 56 exposed in the space SP6. The conductor 23 is located on the surface of the insulator 24. The set of insulator 24 and conductor 23 fills the space SP6.

[0163] As shown in Figure 88, sacrificial materials 76_1 and 76_2 are removed. This creates space SP7_1 in the area where sacrificial material 76_1 was located, and space SP7_2 in the area where sacrificial material 76_2 was located. The thickness of space SP7_2 is greater than the thickness of space SP7_1. An example of a removal method includes wet etching.

[0164] As shown in Figure 89, an insulator 72A is formed. Insulator 72A is an element that will be molded into insulator 72 in a later process. Insulator 72A is substantially made of the same material as insulator 72. Due to the difference in thickness between spaces SP7_1 and SP7_2, insulator 72A fills space SP7_2. On the other hand, due to the difference in thickness between spaces SP7_1 and SP7_2, insulator 72A does not fill space SP7_2, and space SP7_2 remains partially intact. An example of a formation method includes CVD.

[0165] As shown in Figure 90, the insulator 72A is partially removed. Specifically, the portion of the insulator 72A including the exposed surface is removed. This re-forms space SP7_1, which exposes the sacrificial material 56. The removal also removes a portion of the insulator 72A that was filling space SP7_2. This forms space SP8 in the area where the removed portion of the insulator 72A was located, and the remaining portion of the insulator 72 forms the insulator 72. An example of a removal method includes wet etching.

[0166] As shown in Figure 91, the insulator 27 and the conductor 26 are formed by the same process as described above with reference to Figures 6, 7, and 8 of the first embodiment.

[0167] As shown in Figure 92, the sacrificial material 56 is removed. Removal re-forms the hole HL and space SP5. An example of a removal method includes wet etching. Space SP5 exposes the insulator 27.

[0168] As shown in Figure 93, the semiconductor 28 is formed. That is, first, the semiconductor 28A is formed by the same process as described above with reference to Figures 45, 46, and 47 of the second embodiment. The semiconductor 28A fills the holes HL and the space SP5. The semiconductor 28A is in contact with the insulator 27 in the space SP5. Next, the portion of the semiconductor 28A in the holes HL is removed by the same process as described above with reference to Figures 21, 22, and 23 of the first embodiment. As a result, the semiconductor 28 is formed from the remaining portion of the semiconductor 28A.

[0169] As shown in Figure 78, the conductors 51, 52, and 31 are formed by the same process as described above with reference to Figures 49, 50, and 51 of the third embodiment.

[0170] 7.3. Advantages The structure of the seventh embodiment also enables the realization of a DRAM structure having small memory cells (MC), similar to the first embodiment.

[0171] 7.4. Variations The insulator 24 may be formed after the steps described above with reference to Figure 92. In this case, only the conductor 23 is deposited by the steps described above with reference to Figure 87. As a result, the conductor 23 is exposed in the hole HL and the space SP5 by the steps described above with reference to Figure 92. Then, after the steps described above with reference to Figure 92, the insulator 24 is deposited on the surface of the element defining the hole HL. This results in the insulator 24 being deposited on the surface of the conductor 23 that is exposed in the hole HL and the space SP5.

[0172] If the seventh embodiment is based on the third embodiment, an oxide semiconductor 48 is provided instead of the semiconductor 28.

[0173] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0174] 1...Storage device, 11…Memory cell array, 12…Input / Output Circuits, 13…Control circuits, 14…Voltage generation circuit, 15... Row selection circuit, 16…Column selection circuit, 17…Writing circuit, 18...Read circuit, 19...Sense Amp, MC…Memory cell WL... Word line, BL... bit line, CC... Cell Capacitor, CT...transistor, PL...plate wire, LA, LB... layers, SLA, SLB... sub-layers, 21... Circuit board, 23, 26, 31... Conductors, 24, 27, 29...insulators, 28… Semiconductors

Claims

1. A first conductor extending in a first direction, A first semiconductor surrounds the first conductor along a first plane intersecting the first direction, A first insulator surrounds the first semiconductor along the first plane, A second conductor surrounding the first insulator along the first plane, A third conductor located in a first direction from the first semiconductor and surrounding the first conductor along the first plane, A second insulator between the first semiconductor and the third conductor, A storage device equipped with the following features.

2. The second conductor extends along the first plane, The storage device according to claim 1.

3. The third conductor extends along the first plane, The storage device according to claim 1.

4. The second conductor and the third conductor extend along the first plane and face each other along the first plane. The storage device according to claim 1.

5. The second insulator has a first portion that is in contact with the third conductor and extends along the first plane, The first insulator has a second portion that is in contact with the second conductor and extends along the first plane, The first part and the second part are in contact with each other. The storage device according to claim 4.

6. A second semiconductor positioned in the first direction from the third conductor and surrounding the first conductor along the first plane, A third insulator surrounds the second semiconductor along the first plane, A fourth conductor surrounding the third insulator along the first plane, A fifth conductor located in the first direction from the second semiconductor and surrounding the first conductor along the first plane, The fourth insulator between the second semiconductor and the fifth conductor, Furthermore, The storage device according to claim 1.

7. The sixth conductor further comprises a third portion extending in the first direction, The second conductor and the fourth conductor are part of the sixth conductor, The fifth insulator further includes a fourth portion and a fifth portion extending in the first direction, The first insulator and the third insulator are part of the fifth insulator. The fourth portion is located between the sixth conductor and the third conductor, The fifth portion is located between the sixth conductor and the fifth conductor, The storage device according to claim 6.

8. A seventh conductor extending in the first direction, The third semiconductor surrounding the seventh conductor, A sixth insulator surrounds the third semiconductor along the first plane, A seventh insulator between the third semiconductor and the third conductor, Furthermore, The second conductor further surrounds the sixth insulator along the first plane, The third conductor further surrounds the seventh conductor along the first plane. The storage device according to claim 1.

9. An eighth conductor located in a fourth direction opposite to the first direction from the first semiconductor, and surrounding the first conductor along the first plane, A second insulator between the first semiconductor and the eighth conductor, Furthermore, The storage device according to claim 1.

10. The present invention further comprises a ninth conductor between the first semiconductor and the second conductor. The storage device according to claim 1.

11. The first semiconductor comprises an oxide semiconductor, The storage device according to claim 1.

12. The first semiconductor comprises an oxide containing one or more elements selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo). The storage device according to claim 1.

13. A tenth conductor between the first semiconductor and the second conductor, An eleventh conductor between the tenth conductor and the second conductor, Furthermore, The storage device according to claim 12.

14. A twelfth conductor between the first conductor and the first semiconductor, A thirteenth conductor between the twelfth conductor and the first semiconductor, Furthermore, The storage device according to claim 12.

15. A tenth conductor between the first semiconductor and the second conductor, An eleventh conductor between the tenth conductor and the second conductor, A twelfth conductor between the first conductor and the first semiconductor, A thirteenth conductor between the twelfth conductor and the first semiconductor, Furthermore, The storage device according to claim 12.

16. The present invention further comprises a ninth insulator provided between the first conductor and the first semiconductor and surrounded by the first semiconductor, The storage device according to claim 1.

17. The second insulator surrounds the third conductor along the first plane, The storage device according to claim 1.

18. During data writing, After a first voltage is applied to the first conductor, the application of the first voltage is stopped. The first voltage is applied to the second conductor, A second voltage is applied to the third conductor. The aforementioned first voltage has half the magnitude of the positive third voltage. The second voltage has a magnitude smaller than the third voltage. The storage device according to claim 1.

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