Semiconductor memory

Abstract

To provide a semiconductor memory device with superior characteristics. [Solution] The semiconductor memory device of the embodiment includes a memory cell including a semiconductor layer, a gate electrode layer containing a ferroelectric material, and first and second wiring connected to the semiconductor layer, and a control circuit. The control circuit is capable of performing a first write operation, which involves applying a first voltage of first polarity to the memory cell, and a second write operation, which involves applying a second voltage to the memory cell that has an absolute value smaller than the first voltage of first polarity. The control circuit is capable of performing a first operation on the memory cell before the second write operation on the memory cell. The first operation involves applying a voltage to the memory cell that has an absolute value larger than the second voltage of first polarity, and applying a voltage with the opposite polarity to the first voltage that has an absolute value larger than the second voltage.

Description

Technical Field

[0005] ,

[0001] Embodiments of the present invention relate to semiconductor memory devices.

Background Art

[0002] There is a non-volatile semiconductor memory device that uses a ferroelectric material in memory cells.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device with excellent characteristics.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises a memory cell including a semiconductor layer, a gate electrode layer, and a gate insulating layer including a ferroelectric material provided between the semiconductor layer and the gate electrode layer; a first wiring and a second wiring electrically connected to the semiconductor layer; and a control circuit for controlling the memory cell, wherein the control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring; the control circuit is capable of performing an erase operation to the memory cell, the erase operation involves applying a second voltage pulse having a second polarity opposite to the first polarity and a second pulse width between the gate electrode layer and at least one of the first wiring and the second wiring; and the control circuit controls The control circuit is capable of performing a second write operation to the memory cell, the second write operation applying a third voltage pulse having a third voltage of first polarity and a third pulse width, which has an absolute value smaller than the absolute value of the first voltage, between the gate electrode layer and at least one of the first wiring and the second wiring, and the control circuit is capable of performing a first operation to the memory cell that is continuous with the second write operation before the second write operation, the first operation applying a fourth voltage pulse having a fourth voltage of first polarity and a fourth pulse width, which has an absolute value larger than the absolute value of the third voltage, and a fifth voltage pulse having a fifth voltage of second polarity and a fifth pulse width, which is continuous with the application of the fourth voltage pulse, between the gate electrode layer and at least one of the first wiring and the second wiring. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram of a memory system including a semiconductor memory device according to the first embodiment. [Figure 2] An equivalent circuit diagram of a portion of the memory cell array of a semiconductor memory device according to the first embodiment. [Figure 3]A schematic cross-sectional view including a memory cell of a semiconductor memory device according to the first embodiment. [Figure 4] Diagram illustrating the memory cell of the semiconductor memory device according to the first embodiment. [Figure 5] A timing chart illustrating a control method for a semiconductor memory device according to the first embodiment. [Figure 6] A timing chart illustrating a control method for a semiconductor memory device according to the first embodiment. [Figure 7] A diagram illustrating the operation and effects of the semiconductor memory device according to the first embodiment. [Figure 8] A diagram illustrating a memory cell of a modified semiconductor memory device according to the first embodiment. [Figure 9] A timing chart illustrating a control method for a modified example of the semiconductor memory device of the first embodiment. [Figure 10] A timing chart illustrating a control method for a modified example of the semiconductor memory device of the first embodiment. [Figure 11] A diagram illustrating the operation and effects of a modified example of the semiconductor memory device according to the first embodiment. [Figure 12] Block diagram of a memory system including a semiconductor memory device according to a second embodiment. [Figure 13] A timing chart illustrating a control method for a semiconductor memory device according to a second embodiment. [Figure 14] A timing chart illustrating a control method for a semiconductor memory device according to a second embodiment. [Figure 15] A timing chart illustrating a control method for a modified example of the semiconductor memory device of the second embodiment. [Figure 16] A timing chart illustrating a control method for a modified example of the semiconductor memory device of the second embodiment. [Figure 17] A block diagram of a memory system including a semiconductor memory device according to a third embodiment. [Figure 18] Equivalent circuit diagram of the memory block of the semiconductor memory device according to the third embodiment. [Figure 19] An equivalent circuit diagram of a portion of the memory cell array of a semiconductor memory device according to the third embodiment. [Figure 20] Schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to the third embodiment. [Figure 21] Schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to the third embodiment. [Figure 22] Block diagram of a memory system including a semiconductor memory device according to the fourth embodiment. [Figure 23] Timing chart for explaining a control method of a semiconductor memory device according to the fourth embodiment. [Figure 24] Timing chart for explaining a control method of a modified example of a semiconductor memory device according to the fourth embodiment. [Figure 25] Block diagram of a memory system including a semiconductor memory device according to the fifth embodiment. [Figure 26] Equivalent circuit diagram of a part of a memory cell array of a semiconductor memory device according to the fifth embodiment. [Figure 27] Schematic cross-sectional view including a memory cell of a semiconductor memory device according to the fifth embodiment. [Figure 28] Block diagram of a memory system including a semiconductor memory device according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate. In addition, for components with reference numerals accompanied by numbers or letters at the end for differentiation, when there is no need to distinguish between the components in the description, reference numerals with the numbers or letters at the end omitted may be used.

[0008] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor memory device described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), electron energy loss spectroscopy (EELS), or X-ray photoelectron spectroscopy (XPS). Furthermore, a transmission electron microscope (TEM) can be used, for example, to measure the thickness of the components constituting the semiconductor memory device, the distance between components, etc. Furthermore, to identify the crystal space group of the components constituting semiconductor memory devices, for example, scanning transmission electron microscopes (STEM), X-ray diffraction (XRD), electron beam diffraction (EBD), X-ray photoelectron spectroscopy (XPS), or synchrotron radiation X-ray absorption fine structure (XAFS) can be used.

[0009] (First Embodiment) The semiconductor memory device of the first embodiment includes a memory cell comprising a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric material provided between the semiconductor layer and the gate electrode layer; a first wiring and a second wiring electrically connected to the semiconductor layer; and a control circuit for controlling the memory cell. The control circuit is capable of performing a first write operation to the memory cell. The first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase operation to the memory cell. The erase operation involves applying a second voltage pulse having a second polarity opposite to the first polarity, and a second pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell. The second write operation applies a third voltage pulse having a third voltage of first polarity and a third pulse width, with an absolute value smaller than the absolute value of the first voltage, between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit can perform the first operation on the memory cell that is continuous with the second write operation before the second write operation. The first operation applies a fourth voltage pulse having a fourth voltage of first polarity and a fourth pulse width, with an absolute value larger than the absolute value of the third voltage, between the gate electrode layer and at least one of the first wiring and the second wiring, followed by the application of a fifth voltage pulse having a fifth voltage of second polarity and a fifth pulse width, with an absolute value larger than the absolute value of the third voltage, and a fifth voltage pulse.

[0010] The semiconductor memory device of the first embodiment is a ferroelectric memory using a ferroelectric material. The semiconductor memory device of the first embodiment includes a two-dimensional NOR memory. The semiconductor memory device of the first embodiment uses a field-effect transistor with a ferroelectric material in its gate insulating layer as a memory cell. The semiconductor memory device of the first embodiment is a multi-level memory in which a single memory cell can hold three or more states (levels).

[0011] Figure 1 is a block diagram of a memory system including a semiconductor memory device of a first embodiment. The memory system of the first embodiment includes, for example, a two-dimensional NOR memory 100, a controller 200, and a host device 300. The semiconductor memory device of the first embodiment includes, for example, a two-dimensional NOR memory 100 and a controller 200.

[0012] The two-dimensional NOR memory 100 is, for example, a two-dimensional NOR memory chip. The controller 200 is, for example, a controller chip. The two-dimensional NOR memory 100 and the controller 200 may be provided on the same semiconductor chip, for example.

[0013] The host device 300 is, for example, a personal computer.

[0014] As shown in Figure 1, the two-dimensional NOR memory 100 includes a memory cell array 110 and peripheral circuits 120.

[0015] The peripheral circuitry 120 is provided around the memory cell array 110. The peripheral circuitry 120 has a function to control the operation of the memory cell array 110 in response to instructions received from the controller 200, for example.

[0016] The controller 200 controls the two-dimensional NOR memory 100. The controller 200 also accesses the two-dimensional NOR memory 100 in response to commands received from the host device 300.

[0017] The peripheral circuits 120 and controller 200 of the two-dimensional NOR memory 100 control, for example, writing data to memory cells included in the memory cell array 110, reading data from memory cells, or erasing data from memory cells. The peripheral circuits 120 and controller 200 of the two-dimensional NOR memory 100 are an example of the control circuit of the first embodiment.

[0018] As shown in Figure 1, the controller 200 includes a processor 210 (CPU), built-in memory 220 (RAM, ROM), a NOR interface circuit 230, a buffer memory 240, and a host interface circuit 250.

[0019] The processor 210 controls the overall operation of the controller 200. The processor 210 has the function of performing various processes for managing the two-dimensional NOR memory 100.

[0020] The internal memory 220 is, for example, semiconductor memory. The internal memory 220 is used, for example, as a workspace for the processor. The internal memory 220 also stores, for example, firmware for managing the two-dimensional NOR memory 100 and various management tables.

[0021] The NOR interface circuit 230 is connected to the two-dimensional NOR memory 100 via a NOR bus. The NOR interface circuit 230 has a function to control communication with the two-dimensional NOR memory 100.

[0022] The buffer memory 240 has the function of temporarily storing, for example, data written to memory cells and data read from memory cells.

[0023] The host interface circuit 250 is connected to the host device 300 via the host bus. The host interface circuit 250, for example, forwards instructions received from the host device 300 to the processor 210. The host interface circuit 250 also, for example, forwards data received from the host device 300 to the buffer memory 240. The host interface circuit 250 also, for example, forwards data in the buffer memory 240 to the host device 300 in response to instructions from the processor 210.

[0024] Figure 2 is an equivalent circuit diagram of a portion of the memory cell array of the semiconductor memory device of the first embodiment. Figure 2 is an equivalent circuit diagram of a portion of the memory cell array 110 of the two-dimensional NOR memory 100.

[0025] As shown in Figure 2, the memory cell array 110 includes a plurality of memory cells MC, a plurality of source lines SL, a plurality of bit lines BL, and a plurality of word lines WL. The plurality of memory cells MC include memory cell MCa, memory cell MCb, memory cell MCc, and memory cell MCd. The plurality of source lines SL include a first source line SL1 and a second source line SL2. The plurality of bit lines BL include a first bit line BL1 and a second bit line BL2. The plurality of word lines WL include a first word line WL1 and a second word line WL2.

[0026] Multiple word lines WL are arranged parallel to each other and spaced apart. Multiple bit lines BL intersect, for example, with the word lines WL. Multiple bit lines BL are arranged parallel to each other and spaced apart. Multiple source lines SL intersect, for example, with the word lines WL. Multiple source lines SL are arranged parallel to each other and spaced apart.

[0027] One memory cell MC can be selected by selecting one source line SL, one bit line BL, and one word line WL. The word line WL is the gate electrode of the transistor that constitutes the memory cell MC. The transistor of the memory cell MC is a field-effect transistor whose operation is controlled by the voltage applied to its gate electrode.

[0028] The two-dimensional NOR memory 100 is configured to enable random access to multiple memory cells MC included in the memory cell array 110.

[0029] Figure 3 is a schematic cross-sectional view including the memory cell of the semiconductor memory device according to the first embodiment.

[0030] As shown in Figure 3, the memory cell MC comprises a semiconductor layer 10, a word line WL, a gate insulating layer 11, and a contact plug CP. The semiconductor layer 10 includes a source region 10x, a drain region 10y, and a channel region 10z. The source line SL and bit line BL are connected to the memory cell MC.

[0031] The word line WL is an example of a gate electrode layer. The source line SL is an example of a first wiring. The bit line BL is an example of a second wiring.

[0032] The semiconductor layer 10 is, for example, single-crystal silicon. The source region 10x and drain region 10y are, for example, n-type semiconductors. The channel region 10z is, for example, a p-type semiconductor.

[0033] The source line SL is electrically connected to the source region 10x using a contact plug CP. The bit line BL is electrically connected to the drain region 10y using a contact plug CP.

[0034] The word wire WL is a conductor. For example, the word wire WL is a metal. The contact plug CP is a conductor. For example, the contact plug CP is a metal.

[0035] The gate insulating layer 11 contains a ferroelectric material. For example, the gate insulating layer 11 is a ferroelectric layer.

[0036] The gate insulating layer 11 includes, for example, at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

[0037] The gate insulating layer 11 is, for example, polycrystalline. The gate insulating layer 11 includes, for example, a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Oxides of hafnium (Hf) or zirconium (Zr) having space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), or Pmn21 (space group number 31) are ferroelectrics.

[0038] Figure 4 is an explanatory diagram of the memory cell of the semiconductor memory device according to the first embodiment. Figure 4 is an explanatory diagram of the possible states (levels) of the memory cell MC.

[0039] As shown in Figure 4, the memory cell MC can exist in three states: erase state, program state, and intermediate state. The transistors of the memory cell MC can have threshold voltages corresponding to each state. Because the memory cell MC can exist in three states, the two-dimensional NOR memory 100 functions as a multi-level memory.

[0040] As shown in Figure 4, we consider that there are two polarization domains with different coercive voltages (Vc) within the ferroelectric material of the memory cell MC. These are the low-coercive-voltage domain (Low Vc domain) and the high-coercive-voltage domain (High Vc domain). Each polarization domain can independently take on either an erased state or a programmed state. The polarization direction of the polarization domain differs between the erased state and the programmed state.

[0041] When the memory cell MC is in the erase state, the low-resistance domain is in the erase state (E), and the high-resistance domain is in the erase state (E). When the memory cell MC is in the intermediate state, the low-resistance domain is in the programmed state (P), and the high-resistance domain is in the erase state (E). When the memory cell MC is in the programmed state, the low-resistance domain is in the programmed state (P), and the high-resistance domain is in the programmed state (P).

[0042] For example, performing a first write operation on a memory cell MC in the erased state causes polarization reversal in the low-resistance domain and the high-resistance domain, resulting in the low-resistance domain and the high-resistance domain entering the programmed state (P). As a result, the memory cell MC transitions from the erased state to the programmed state.

[0043] Furthermore, for example, by performing a second write operation on a memory cell MC in the erased state, domain polarization reversal occurs only in the low-resistance domain, causing the low-resistance domain to enter the programmed state (P) while the high-resistance domain remains in the erased state (E). As a result, the memory cell MC transitions from the erased state to an intermediate state.

[0044] Furthermore, for example, by performing an erase operation on a programmed memory cell (MC), polarization reversal occurs in the low-resistance domain and the high-resistance domain, causing the low-resistance domain and the high-resistance domain to enter an erased state (E). As a result, the memory cell (MC) transitions from the programmed state to the erased state.

[0045] Furthermore, for example, by performing an erase operation on a memory cell MC in an intermediate state, polarization reversal occurs in the low-resistance domain, causing the low-resistance domain to enter the erased state (E). As a result, the memory cell MC transitions from the intermediate state to the erased state.

[0046] Figure 5 is a timing chart illustrating the control method of the semiconductor memory device according to the first embodiment. Figure 5 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110. Figure 5 shows the voltage pulses applied to the memory cells MC during the first write operation, the second write operation, and the erase operation.

[0047] The peripheral circuits 120 and controller 200 of the 2D NOR memory 100 control, for example, multiple memory cells MC in the memory cell array 110. For example, the peripheral circuits 120 and controller 200 control memory cells MCa to MCd.

[0048] The peripheral circuit 120 and controller 200 can, for example, perform a first write operation, a second write operation, and an erase operation on any one memory cell MC selected from memory cells MCa to MCd. Furthermore, the peripheral circuit 120 and controller 200 can, for example, read data stored in any one memory cell MC selected from memory cells MCa to MCd.

[0049] Figure 5 illustrates the case where a first write operation, a second write operation, and an erase operation are performed on a memory cell MC. The following explanation will use the case where a first write operation, a second write operation, and an erase operation are performed on a memory cell MCa as an example. In this case, the first word line WL1 is an example of a gate electrode layer, the first source line SL1 is the first wiring, and the first bit line BL1 is an example of a second wiring.

[0050] The first write operation involves applying a first write voltage pulse WP1 between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The first write operation also involves applying the first write voltage pulse WP1 to the gate isolation layer 11 of the memory cell MCa.

[0051] The first write voltage pulse WP1 has a first write voltage Vwrite1 of first polarity and a first pulse width w1. The first write voltage pulse WP1 is an example of a first voltage pulse. The first write voltage Vwrite1 is an example of a first voltage.

[0052] The erase process involves applying an erase voltage pulse EP between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The erase process also involves applying the erase voltage pulse EP to the gate insulation layer of the memory cell MC, for example.

[0053] The erase voltage pulse EP has an erase voltage Verase with a second polarity opposite to the first polarity, and a second pulse width w2. The erase voltage pulse EP is an example of the second voltage pulse. The erase voltage Verase is an example of the second voltage.

[0054] For example, it is possible to perform erase operations on memory cells MCa to MCd simultaneously.

[0055] Furthermore, during the erasure process, it is also possible to apply an erasure voltage pulse EP between the word line WL of the memory cell MC and the channel region 10z of the semiconductor layer 10 using, for example, wiring not shown in Figure 3 that is connected to the channel region 10z. In this case, the wiring not shown in Figure 3 that is connected to the channel region 10z is an example of the first wiring or the second wiring.

[0056] The second write process involves applying a second write voltage pulse WP2 between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The second write process also involves applying the second write voltage pulse WP2 to the gate insulating layer 11 of the memory cell MCa.

[0057] The second write voltage pulse WP2 has a second write voltage Vwrite2 of first polarity and a third pulse width w3. The second write voltage pulse WP2 is an example of a third voltage pulse. The second write voltage Vwrite2 is an example of a third voltage.

[0058] The absolute value of the second write voltage Vwrite2 is less than the absolute value of the first write voltage Vwrite1. The third pulse width w3 is equal to, for example, the first pulse width w1.

[0059] For example, the first polarity is the polarity in which the word line WL is positive relative to the source line SL or bit line BL, and the second polarity is the polarity in which the word line WL is negative relative to the source line SL or bit line BL. In other words, for example, the first polarity is the polarity in which the word line WL is positive relative to the semiconductor layer 10, and the second polarity is the polarity in which the word line WL is negative relative to the semiconductor layer 10.

[0060] Figure 6 is a timing chart illustrating the control method of the semiconductor memory device according to the first embodiment. Figure 6 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110. Figure 6 shows the voltage pulses applied to the memory cells MC during the second write operation and the suppression operation performed before the second write operation.

[0061] The peripheral circuits 120 and controller 200 of the two-dimensional NOR memory 100 can, for example, perform a suppression process on any one memory cell MC selected from memory cells MCa to MCd, and a second write process following the suppression process. The suppression process is an example of the first process.

[0062] The suppression process is a process to suppress the occurrence of imprinting in the polarization domain of the memory cell MC. Imprinting refers to the phenomenon in which the resistance voltage required for polarization reversal changes while the polarization state is being maintained.

[0063] Figure 6 illustrates a case where suppression processing and a second write processing are performed on a memory cell MC. For example, when suppression processing and a second write processing are performed on a memory cell MCa, the first word line WL1 is an example of a gate electrode layer, the first source line SL1 is an example of a first wiring, and the first bit line BL1 is an example of a second wiring.

[0064] The suppression process applies a first suppression voltage pulse SP1 and a second suppression voltage pulse SP2 between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The suppression process also applies the first suppression voltage pulse SP1 and the second suppression voltage pulse SP2 to the gate insulating layer 11 of the memory cell MCa.

[0065] The first suppression voltage pulse SP1 has a first suppression voltage Vsup1 of first polarity and a fourth pulse width w4. The first suppression voltage pulse SP1 is an example of a fourth voltage pulse. The first suppression voltage Vsup1 is an example of a fourth voltage.

[0066] The absolute value of the first suppression voltage Vsup1 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the first suppression voltage Vsup1 is, for example, greater than or equal to the absolute value of the first write voltage Vwrite1. The absolute value of the first suppression voltage Vsup1 is, for example, equal to the absolute value of the first write voltage Vwrite1.

[0067] The fourth pulse width w4 of the first suppression voltage pulse SP1 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fourth pulse width w4 is, for example, greater than the third pulse width w3.

[0068] The fourth pulse width w4 is, for example, greater than or equal to the first pulse width w1 of the first write voltage pulse WP1.

[0069] The second suppression voltage pulse SP2 has a second suppression voltage Vsup2 of second polarity and a fifth pulse width w5. The second suppression voltage pulse SP2 is an example of a fifth voltage pulse. The second suppression voltage Vsup2 is an example of a fifth voltage.

[0070] The absolute value of the second suppression voltage Vsup2 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the second suppression voltage Vsup2 is, for example, greater than or equal to the absolute value of the erase voltage Verase. The absolute value of the second suppression voltage Vsup2 is, for example, equal to the absolute value of the erase voltage Verase.

[0071] The fifth pulse width w5 of the second suppression voltage pulse SP2 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fifth pulse width w5 is, for example, greater than the third pulse width. The fifth pulse width w5 is, for example, greater than or equal to the second pulse width w2 of the erase voltage pulse EP.

[0072] The second suppression voltage pulse SP2 is applied immediately after the application of the first suppression voltage pulse SP1. For example, no other pulses are applied between the application of the first suppression voltage pulse SP1 and the application of the second suppression voltage pulse SP2.

[0073] The suppression process is performed immediately after the second write process. After the suppression process is performed, the second write process is performed immediately.

[0074] The application of the first suppression voltage pulse SP1, the second suppression voltage pulse SP2, and the second write voltage pulse WP2 are performed sequentially. For example, no other pulses are applied between the application of the second suppression voltage pulse SP2 and the application of the second write voltage pulse WP2.

[0075] Next, the operation and effects of the semiconductor memory device according to the first embodiment will be described.

[0076] In non-volatile semiconductor memory devices that use field-effect transistors containing a ferroelectric material in their gate insulating layer as memory cells, problems can arise where desired writing or erasing operations to the memory cell cannot be performed, and the transistor's threshold voltage cannot be controlled to the desired threshold voltage. In other words, data writing failures or data erasure operations to the memory cell may occur.

[0077] One possible cause of data writing failures or data erasure issues in memory cells is imprinting.

[0078] As is clear from Figure 4, when only the second write and erase operations are repeated for a single memory cell MC, the low-resistance domain undergoes repeated polarization reversal, but the high-resistance domain does not undergo any polarization reversal. Therefore, imprinting is unlikely to occur in the low-resistance domain where polarization reversal occurs, but imprinting may become apparent in the high-resistance domain where no polarization reversal occurs. Consequently, even if the write and erase operations to the memory cell MC are repeated, imprinting may occur in the memory cell MC, potentially leading to write or erase failures.

[0079] For example, in the case of a memory cell MC that does not use intermediate states, i.e., not a multi-level memory, only the first write operation and erase operation are repeated in the memory cell MC. In this case, both the low-resistance domain and the high-resistance domain will undergo repeated polarization reversals. Therefore, in the case of a non-multi-level memory, as long as the write operation and erase operation to the memory cell MC are repeated, imprinting in the memory cell MC becomes less likely, and write or erase failures of the memory cell MC are suppressed.

[0080] As described above, there is a problem inherent to multi-level memory using ferroelectrics in that even if writing and erasing operations are repeatedly performed on the memory cell MC, there is a risk of imprinting on the memory cell MC. Furthermore, the inventors' studies have revealed that the imprinting that occurs when only the second writing and erasing operations are repeatedly performed on the memory cell MC is greater than the imprinting that occurs when the memory cell MC is left unattended without performing the second writing or erasing operations, resulting in a larger change in the resistance voltage. This is thought to be because the voltage stress associated with the second writing and erasing operations is applied to the high resistance voltage domain where polarization reversal does not occur, accelerating the imprinting of the high resistance voltage domain.

[0081] Figure 7 is an explanatory diagram of the operation and effects of the semiconductor memory device of the first embodiment. Figure 7 is a timing chart illustrating the control method of the semiconductor memory device of the first embodiment. Figure 7 shows the voltage pulses applied to the memory cell MC when no suppression processing is performed before the second write process and when suppression processing is performed before the second write process.

[0082] Figure 7 schematically shows the polarization states of the low-resistance domain and the high-resistance domain before and after the application of each pulse. The left side of the two tangent squares shows the polarization state of the low-resistance domain, and the right side shows the polarization state of the high-resistance domain. It also indicates whether each domain is in the erased state (E) or the programmed state (P).

[0083] As shown in Figure 7, if suppression processing is not performed before the second write process, the high-resistance domain remains in the erased state (E) and its state does not change even if the second write process and erase process are repeated. On the other hand, if suppression processing is always performed before the second write process, as in the control method for the semiconductor memory device of the first embodiment, polarization reversal occurs in the high-resistance domain, and the high-resistance domain transitions between the erased state (E) and the programmed state (P).

[0084] By always performing a suppression process before the second write operation, polarization reversal can be induced in all polarization domains of the memory cell MC. Therefore, imprinting of the memory cell MC is suppressed, and write or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a two-dimensional NOR memory 100, can be realized.

[0085] From the viewpoint of suppressing imprinting that occurs in the memory cell MC, it is preferable that the absolute value of the first suppression voltage Vsup1 is greater than or equal to the absolute value of the first write voltage Vwrite1. Also from the same viewpoint, it is preferable that the fourth pulse width w4 of the first suppression voltage pulse SP1 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also from the same viewpoint, it is preferable that the fourth pulse width w4 is greater than or equal to the first pulse width w1 of the first write voltage pulse WP1.

[0086] From the viewpoint of suppressing imprinting that occurs in the memory cell MC, it is preferable that the absolute value of the second suppression voltage Vsup2 is greater than or equal to the absolute value of the erase voltage Verase. Also, from the same viewpoint, it is preferable that the fifth pulse width w5 of the second suppression voltage pulse SP2 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also, from the same viewpoint, it is preferable that the fifth pulse width w5 is greater than or equal to the second pulse width w2 of the erase voltage pulse EP.

[0087] (modified version) A modified version of the semiconductor memory device of the first embodiment differs from the semiconductor memory device of the first embodiment in that the second writing process applies a third voltage pulse having a third voltage of second polarity with an absolute value smaller than the absolute value of the second voltage and a third pulse width between the gate electrode layer and at least one of the first wiring and the second wiring, and the first process applies a fourth voltage pulse having a fourth voltage of second polarity with an absolute value larger than the absolute value of the third voltage and a fourth pulse width, followed by the application of a fifth voltage pulse having a fifth voltage of first polarity with an absolute value larger than the absolute value of the third voltage and a fifth pulse width, between the gate electrode layer and at least one of the first wiring and the second wiring.

[0088] Figure 8 is an explanatory diagram of a modified memory cell of the semiconductor memory device of the first embodiment. Figure 8 is an explanatory diagram of the possible states of the memory cell MC.

[0089] As shown in Figure 8, a memory cell MC can exist in three states: erase state, program state, and intermediate state. The transistors in the memory cell MC can have threshold voltages corresponding to each state.

[0090] As shown in Figure 8, we consider that there are two polarization domains with different coercive voltages (Vc) within the ferroelectric material of the memory cell MC. These are the low-coercive-voltage domain (Low Vc domain) and the high-coercive-voltage domain (High Vc domain).

[0091] When the memory cell MC is in the erase state, the low-resistance domain is in the erase state (E), and the high-resistance domain is in the erase state (E). When the memory cell MC is in the intermediate state, the low-resistance domain is in the erase state (E), and the high-resistance domain is in the programmed state (P). When the memory cell MC is in the programmed state, the low-resistance domain is in the programmed state (P), and the high-resistance domain is in the programmed state (P).

[0092] For example, performing a first write operation on a memory cell MC in the erased state causes polarization reversal in the low-resistance domain and the high-resistance domain, resulting in the low-resistance domain and the high-resistance domain entering the programmed state (P). As a result, the memory cell MC transitions from the erased state to the programmed state.

[0093] Furthermore, for example, by performing a second write operation on a programmed memory cell MC, domain polarization reversal occurs only in the low-resistance domain, causing the low-resistance domain to enter the erased state (E) while the high-resistance domain remains in the programmed state (P). As a result, the memory cell MC transitions from the programmed state to an intermediate state.

[0094] Furthermore, for example, performing an erase operation on a programmed memory cell (MC) causes a polarization reversal between the low-resistance domain and the high-resistance domain, resulting in both the low-resistance domain and the high-resistance domain entering an erased state (E). As a result, the memory cell (MC) transitions from the programmed state to the erased state.

[0095] Furthermore, for example, by performing an erase operation on a memory cell MC in an intermediate state, polarization reversal occurs in the high-resistance domain, causing the high-resistance domain to enter the erased state (E). As a result, the memory cell MC transitions from the intermediate state to the erased state.

[0096] Figure 9 is a timing chart illustrating a control method for a modified example of the semiconductor memory device of the first embodiment. Figure 9 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110. Figure 9 shows the voltage pulses applied to the memory cells MC during the first write operation, the second write operation, and the erase operation.

[0097] Figure 9 illustrates a case in which a first write operation, a second write operation, and an erase operation are performed on a memory cell MC. The first write operation and the erase operation are the same as in the first embodiment. The following explanation will use the case in which a second write operation is performed on a memory cell MCa as an example. In this case, the first word line WL1 is an example of a gate electrode layer, the first source line SL1 is a first wiring, and the first bit line BL1 is an example of a second wiring.

[0098] The second write operation applies a second write voltage pulse WP2 between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The second write operation applies the second write voltage pulse WP2 to the gate insulating layer 11 of the memory cell MCa. Before the second write operation, the memory cell MCa must be in a programmed state. For example, the first write operation is performed immediately before the second write operation is performed on the memory cell MCa. Also, for example, data is read from the memory cell MCa immediately before the second write operation is performed, and it is confirmed that the data is in a programmed state.

[0099] The second write voltage pulse WP2 has a second write voltage Vwrite2 of second polarity and a third pulse width w3. The second write voltage pulse WP2 is an example of a third voltage pulse. The second write voltage Vwrite2 is an example of a third voltage.

[0100] The absolute value of the second write voltage Vwrite2 is less than the absolute value of the erase voltage Verase. The third pulse width w3 of the second write voltage pulse WP2 is equal to, for example, the first pulse width w1 of the first write voltage pulse WP1.

[0101] Figure 10 is a timing chart illustrating a control method for a modified example of the semiconductor memory device of the first embodiment. Figure 10 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110. Figure 10 shows the voltage pulses applied to the memory cells MC during the second write operation and the suppression operation performed before the second write operation.

[0102] Figure 10 illustrates a case where suppression processing and a second write processing are performed on a memory cell MC. For example, when suppression processing and a second write processing are performed on a memory cell MCa, the first word line WL1 is an example of a gate electrode layer, the first source line SL1 is an example of a first wiring, and the first bit line BL1 is an example of a second wiring.

[0103] The suppression process applies a first suppression voltage pulse SP1 and a second suppression voltage pulse SP2 between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The suppression process also applies the first suppression voltage pulse SP1 and the second suppression voltage pulse SP2 to the gate insulating layer 11 of the memory cell MCa.

[0104] The first suppression voltage pulse SP1 has a first suppression voltage Vsup1 of second polarity and a fourth pulse width w4. The first suppression voltage pulse SP1 is an example of a fourth voltage pulse. The first suppression voltage Vsup1 is an example of a fourth voltage.

[0105] The absolute value of the first suppression voltage Vsup1 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the first suppression voltage Vsup1 is, for example, greater than or equal to the absolute value of the erase voltage Verase. The absolute value of the first suppression voltage Vsup1 is, for example, equal to the absolute value of the erase voltage Verase.

[0106] The fourth pulse width w4 of the first suppression voltage pulse SP1 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fourth pulse width w4 is, for example, greater than the third pulse width w3.

[0107] The fourth pulse width w4 is, for example, greater than or equal to the second pulse width w2 of the erase voltage pulse EP.

[0108] The second suppression voltage pulse SP2 has a second suppression voltage Vsup2 of the first polarity and a fifth pulse width w5. The second suppression voltage pulse SP2 is an example of a fifth voltage pulse. The second suppression voltage Vsup2 is an example of a fifth voltage.

[0109] The absolute value of the second suppression voltage Vsup2 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the second suppression voltage Vsup2 is, for example, greater than or equal to the absolute value of the first write voltage Vwrite1. The absolute value of the second suppression voltage Vsup2 is, for example, equal to the absolute value of the first write voltage Vwrite1.

[0110] The fifth pulse width w5 of the second suppression voltage pulse SP2 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fifth pulse width w5 is, for example, greater than the third pulse width w3. The fifth pulse width w5 is, for example, greater than or equal to the first pulse width w1.

[0111] The second suppression voltage pulse SP2 is applied immediately after the application of the first suppression voltage pulse SP1. For example, no other pulses are applied between the application of the first suppression voltage pulse SP1 and the application of the second suppression voltage pulse SP2.

[0112] The suppression process is performed immediately after the second write process. After the suppression process is performed, the second write process is performed immediately.

[0113] The application of the first suppression voltage pulse SP1, the second suppression voltage pulse SP2, and the second write voltage pulse WP2 are performed sequentially. For example, no other pulses are applied between the application of the second suppression voltage pulse SP2 and the application of the second write voltage pulse WP2.

[0114] Next, the operation and effects of a modified example of the semiconductor memory device of the first embodiment will be described.

[0115] As is clear from Figure 8, when only the first and second write operations are repeated for a single memory cell MC, the low-resistance domain undergoes repeated polarization reversal, but the high-resistance domain does not undergo any polarization reversal at all. Therefore, imprinting is less likely to occur in the low-resistance domain where polarization reversal occurs, but imprinting may become apparent in the high-resistance domain where no polarization reversal occurs. Consequently, even if the write operation to the memory cell MC is performed repeatedly, imprinting may occur in the memory cell MC, potentially leading to write failures or erase failures of the memory cell MC.

[0116] For example, in the case of a memory cell MC that does not use intermediate states, i.e., not a multi-level memory, only the first write operation and erase operation are repeated in the memory cell MC. In this case, both the low-resistance domain and the high-resistance domain will undergo repeated polarization reversals. Therefore, in the case of a non-multi-level memory, as long as the write operation and erase operation to the memory cell MC are repeated, imprinting in the memory cell MC becomes less likely, and write or erase failures of the memory cell MC are suppressed.

[0117] As mentioned above, there is a problem inherent to multi-level memory in that imprints may occur on the memory cell MC even if the writing process to the memory cell MC is performed repeatedly. Furthermore, the inventors' studies have revealed that the imprints that occur when only the first and second writing processes are repeated on the memory cell MC result in a larger change in resistance voltage compared to the imprints that occur when the memory cell MC is simply left without performing the first or second writing processes.

[0118] Figure 11 is an explanatory diagram illustrating the operation and effects of a modified semiconductor memory device of the first embodiment. Figure 11 is a timing chart illustrating the control method of the modified semiconductor memory device of the first embodiment. Figure 11 shows the voltage pulses applied to the memory cell MC when suppression processing is not performed before the second write process and when suppression processing is performed before the second write process.

[0119] Figure 11 schematically shows the polarization states of the low-resistance domain and the high-resistance domain before and after the application of each pulse. The left side of the two tangent squares shows the polarization state of the low-resistance domain, and the right side shows the polarization state of the high-resistance domain. It also indicates whether each domain is in the erased state (E) or the programmed state (P).

[0120] As shown in Figure 11, if suppression processing is not performed before the second write operation, the high-resistance domain remains in the program state (P) and its state does not change even if the first and second write operations are repeated. On the other hand, if suppression processing is always performed before the second write operation, as in the control method of the modified semiconductor memory device of the first embodiment, polarization reversal occurs in the high-resistance domain, and the high-resistance domain transitions between the erase state (E) and the program state (P).

[0121] By always performing a suppression process before the second write operation, polarization reversal can be caused in all polarization domains of the memory cell MC. Therefore, according to the modification of the first embodiment, imprinting of the memory cell MC is suppressed, and write failures or erase failures of the memory cell MC are suppressed, similar to the first embodiment. Thus, a semiconductor memory device with excellent characteristics, including a two-dimensional NOR memory 100, can be realized.

[0122] From the viewpoint of suppressing imprinting that occurs in the memory cell MC, it is preferable that the absolute value of the first suppression voltage Vsup1 is greater than or equal to the absolute value of the erase voltage Verase. Also, from the same viewpoint, it is preferable that the fourth pulse width w4 of the first suppression voltage pulse SP1 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also, from the same viewpoint, it is preferable that the fourth pulse width w4 is greater than or equal to the second pulse width w2 of the erase voltage pulse EP.

[0123] From the viewpoint of suppressing imprinting that occurs in the memory cell MC, it is preferable that the absolute value of the second suppression voltage Vsup2 is greater than or equal to the absolute value of the first write voltage Vwrite1. Also from the same viewpoint, it is preferable that the fifth pulse width w5 of the second suppression voltage pulse SP2 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also from the same viewpoint, it is preferable that the fifth pulse width w5 is greater than or equal to the first pulse width w1 of the first write voltage pulse WP1.

[0124] As described above, according to the first embodiment and its modifications, memory cell imprinting is suppressed, and a semiconductor memory device with superior characteristics can be realized.

[0125] (Second embodiment) The semiconductor memory device of the second embodiment includes a memory cell comprising a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric material provided between the semiconductor layer and the gate electrode layer; a first wiring and a second wiring electrically connected to the semiconductor layer; and a control circuit for controlling the memory cell. The control circuit is capable of performing a first write operation to the memory cell. The first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase operation to the memory cell. The erase operation involves applying a second voltage pulse having a second polarity opposite to the first polarity, and a second pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell. The second write operation applies a third voltage pulse having a third voltage of first polarity and a third pulse width, with an absolute value smaller than the absolute value of the first voltage, between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit can determine whether the number of executions of the second write operation to the memory cell has reached a predetermined first number. If the control circuit determines that the number of executions has reached a predetermined first number, it can perform the first operation on the memory cell. The first operation applies a fifth voltage pulse, which is a continuation of the application of a fourth voltage pulse having a fourth voltage of first polarity and a fourth pulse width, with an absolute value larger than the absolute value of the third voltage, between the gate electrode layer and at least one of the first wiring and the second wiring, and the application of a fifth voltage pulse having a fifth voltage of second polarity and a fifth pulse width, with an absolute value larger than the absolute value of the third voltage.

[0126] The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that it performs a recovery operation. Some descriptions that overlap with the first embodiment may be omitted below.

[0127] Figure 12 is a block diagram of a memory system including a semiconductor memory device of a second embodiment. The memory system of the second embodiment includes, for example, a two-dimensional NOR memory 100, a controller 200, and a host device 300. The semiconductor memory device of the second embodiment includes, for example, a two-dimensional NOR memory 100 and a controller 200.

[0128] The peripheral circuits 120 and controller 200 of the 2D NOR memory 100 are an example of the control circuit of the second embodiment.

[0129] The processor 210 of the second embodiment differs from the processor 210 of the first embodiment in that it includes a judgment circuit 211.

[0130] The internal memory 220 stores, for example, the number of times a second write operation has been performed on each memory cell included in the two-dimensional NOR memory 100. The internal memory 220 also stores, for example, a predetermined first number of times the second write operation has been performed, which serves as a criterion for determining whether or not to perform a recovery operation. Based on the number of times the second write operation has been performed on a particular memory cell and the predetermined first number of times the second write operation has been performed, the determination circuit 211 can determine whether or not the number of times the second write operation has been performed on a particular memory cell has reached the predetermined first number.

[0131] The peripheral circuits 120 and controller 200 of the two-dimensional NOR memory 100 can perform a recovery process on a specific memory cell when they determine that the number of times a second write operation has been performed on that specific memory cell has reached a predetermined first number of times. The recovery process is an example of the first process.

[0132] The possible states of the memory cell MC of the semiconductor memory device in the second embodiment are the same as those of the first embodiment described with reference to Figure 4. Furthermore, the first write process, the second write process, and the erase process in the control of the semiconductor memory device in the second embodiment are the same as those of the semiconductor memory device in the first embodiment.

[0133] Figure 13 is a timing chart illustrating the control method of a semiconductor memory device according to the second embodiment. Figure 13 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110. Figure 13 shows the voltage pulses applied to the memory cells MC during the recovery process.

[0134] The recovery process is a process to recover the imprints that have occurred in the polarization domains of the memory cell MC.

[0135] For example, when performing a recovery operation on a memory cell MCa, the first word line WL1 is an example of a gate electrode layer, the first source line SL1 is an example of a first wiring, and the first bit line BL1 is an example of a second wiring.

[0136] The recovery process applies a first recovery voltage pulse RP1 and a second recovery voltage pulse RP2 between the first word line WL1 of the memory cell MCa and at least one of the first source line SL1 and the first bit line BL1. The recovery process also applies the first recovery voltage pulse RP1 and the second recovery voltage pulse RP2 to the gate insulating layer 11 of the memory cell MCa.

[0137] The first recovery voltage pulse RP1 has a first recovery voltage Vrp1 of first polarity and a fourth pulse width w4. The first recovery voltage pulse RP1 is an example of a fourth voltage pulse. The first recovery voltage Vrp1 is an example of a fourth voltage.

[0138] The absolute value of the first recovery voltage Vrp1 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the first recovery voltage Vrp1 is, for example, greater than or equal to the absolute value of the first write voltage Vwrite1. The absolute value of the first recovery voltage Vrp1 is, for example, equal to the absolute value of the first write voltage Vwrite1.

[0139] The fourth pulse width w4 of the first recovery voltage pulse RP1 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fourth pulse width w4 is, for example, greater than the third pulse width w3.

[0140] The fourth pulse width w4 is, for example, greater than or equal to the first pulse width w1 of the first write voltage pulse WP1.

[0141] The second recovery voltage pulse RP2 has a second recovery voltage Vrp2 of second polarity and a fifth pulse width w5. The second recovery voltage pulse RP2 is an example of the fifth voltage pulse. The second recovery voltage Vrp2 is an example of the fifth voltage.

[0142] The absolute value of the second recovery voltage Vrp2 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the second recovery voltage Vrp2 is, for example, greater than or equal to the absolute value of the erase voltage Verase. The absolute value of the second recovery voltage Vrp2 is, for example, equal to the absolute value of the erase voltage Verase.

[0143] The fifth pulse width w5 of the second recovery voltage pulse RP2 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fifth pulse width w5 is, for example, greater than the third pulse width. The fifth pulse width w5 is, for example, greater than or equal to the second pulse width w2.

[0144] The second recovery voltage pulse RP2 is applied, for example, immediately following the application of the first recovery voltage pulse RP1. No other pulses are applied between the application of the first recovery voltage pulse RP1 and the application of the second recovery voltage pulse RP2.

[0145] Figure 14 is a timing chart illustrating the control method of a semiconductor memory device according to the second embodiment. Figure 14 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110.

[0146] As shown in Figure 14, a recovery process is executed when the number of executions of the second write operation to the memory cell MC reaches a predetermined first number. The predetermined first number is set to a number well below the number of executions required to make the imprint apparent by the second write operation to the memory cell MC, for example, by measuring the number of executions required in advance.

[0147] The number of times the second write operation is performed is the number of times the second write voltage pulse WP2 is applied to the memory cell MC.

[0148] The predetermined first number of times is, for example, the number of times the second write process is performed consecutively without the first write process in between. In this case, the control circuit is configured to determine whether the number of times the second write process is performed consecutively without the first write process in between has reached the predetermined first number.

[0149] The recovery process, for example, is performed immediately after the last second write operation.

[0150] The application of the second write voltage pulse WP2, the application of the first recovery voltage pulse RP1, and the application of the second recovery voltage pulse RP2 are performed, for example, in succession.

[0151] Furthermore, the recovery process may be performed multiple times in succession. In this case, the control circuit is configured to execute the recovery process multiple times in succession.

[0152] Next, the operation and effects of the semiconductor memory device of the second embodiment will be described.

[0153] As explained with reference to Figure 4 in the first embodiment, when only the second write and erase operations are repeated for a single memory cell MC, the low-resistance domain undergoes repeated polarization reversal, but the high-resistance domain does not undergo any polarization reversal. Therefore, imprinting is less likely to occur in the low-resistance domain where polarization reversal occurs, but imprinting may become apparent in the high-resistance domain where no polarization reversal occurs. Consequently, even if the write and erase operations to the memory cell MC are repeated, imprinting may occur in the memory cell MC, potentially leading to write failures or erase failures of the memory cell MC. This problem is specific to multi-level memory using ferroelectric materials.

[0154] As described above, there is a problem inherent to multi-level memory using ferroelectrics in that even if the memory cell MC is repeatedly written to and erased, there is a risk of imprinting on the memory cell MC. Furthermore, the inventors' studies have revealed that the imprinting that occurs when only the second write and erase process is repeatedly performed on the memory cell MC results in a larger change in resistance voltage compared to the imprinting that occurs when the memory cell MC is simply left without performing the second write or erase process.

[0155] In the semiconductor memory device of the second embodiment, when the second write process, which accelerates the imprinting of the memory cell MC, reaches a predetermined first number of times, a recovery process is performed to restore the imprinting of the memory cell MC. Therefore, the imprinting of the memory cell MC is effectively restored, and write failures or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a two-dimensional NOR memory 100, can be realized.

[0156] From the viewpoint of effectively recovering the imprint that occurs in the memory cell MC, it is preferable that the absolute value of the first recovery voltage Vrp1 is greater than or equal to the absolute value of the first write voltage Vwrite1. Also from the same viewpoint, it is preferable that the fourth pulse width w4 of the first recovery voltage pulse RP1 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also from the same viewpoint, it is preferable that the fourth pulse width w4 is greater than or equal to the first pulse width w1 of the first write voltage pulse WP1.

[0157] From the viewpoint of effectively recovering the imprint that occurs in the memory cell MC, it is preferable that the absolute value of the second recovery voltage Vrp2 is greater than or equal to the absolute value of the erase voltage Verase. Also from the same viewpoint, it is preferable that the fifth pulse width w5 of the second recovery voltage pulse RP2 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also from the same viewpoint, it is preferable that the fifth pulse width w5 is greater than or equal to the second pulse width w2 of the erase voltage pulse EP. (modified version) A modified version of the semiconductor memory device of the second embodiment differs from the semiconductor memory device of the second embodiment in that the second writing process applies a third voltage pulse having a third voltage of second polarity and a third pulse width, with an absolute value smaller than the absolute value of the second voltage, between the gate electrode layer and at least one of the first wiring and the second wiring, and the first process applies a fifth voltage pulse consisting of a fourth voltage having a second polarity and a fourth pulse width, with an absolute value larger than the absolute value of the third voltage, and a fifth voltage pulse having a first polarity and a fifth pulse width, in succession, between the gate electrode layer and at least one of the first wiring and the second wiring.

[0158] The possible states of the memory cell MC in the modified semiconductor memory device of the second embodiment are the same as those of the modified semiconductor memory device of the first embodiment described with reference to Figure 8. Furthermore, the first write process, the second write process, and the erase process in the control of the modified semiconductor memory device of the second embodiment are the same as those of the semiconductor memory device of the modified semiconductor memory device of the first embodiment.

[0159] Figure 15 is a timing chart illustrating a control method for a modified example of the semiconductor memory device of the second embodiment. Figure 15 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110. Figure 15 shows the voltage pulses applied to the memory cells MC during the recovery process.

[0160] The first recovery voltage pulse RP1 has a first recovery voltage Vrp1 of second polarity and a fourth pulse width w4. The first recovery voltage pulse RP1 is an example of a fourth voltage pulse. The first recovery voltage Vrp1 is an example of a fourth voltage.

[0161] The absolute value of the first recovery voltage Vrp1 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the first recovery voltage Vrp1 is, for example, greater than or equal to the absolute value of the erase voltage Verase. The absolute value of the first recovery voltage Vrp1 is, for example, equal to the absolute value of the erase voltage Verase.

[0162] The fourth pulse width w4 of the first recovery voltage pulse RP1 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fourth pulse width w4 is, for example, greater than the third pulse width w3.

[0163] The fourth pulse width w4 is, for example, greater than or equal to the second pulse width w2 of the erase voltage pulse EP.

[0164] The second recovery voltage pulse RP2 has a second recovery voltage Vrp2 of first polarity and a fifth pulse width w5. The second recovery voltage pulse RP2 is an example of the fifth voltage pulse. The second recovery voltage Vrp2 is an example of the fifth voltage.

[0165] The absolute value of the second recovery voltage Vrp2 is greater than the absolute value of the second write voltage Vwrite2. The absolute value of the second recovery voltage Vrp2 is, for example, greater than or equal to the absolute value of the first write voltage Vwrite1. The absolute value of the second recovery voltage Vrp2 is, for example, equal to the absolute value of the first write voltage Vwrite1.

[0166] The fifth pulse width w5 of the second recovery voltage pulse RP2 is, for example, greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. The fifth pulse width w5 is, for example, greater than the third pulse width w3. The fifth pulse width w5 is, for example, greater than or equal to the first pulse width w1 of the first write voltage pulse.

[0167] Figure 16 is a timing chart illustrating a control method for a modified example of the semiconductor memory device of the second embodiment. Figure 16 shows the voltage pulses applied to the memory cells MC included in the memory cell array 110.

[0168] As shown in Figure 16, when the number of executions of the second write process reaches a predetermined first number, the recovery process is executed.

[0169] Next, the operation and effects of a semiconductor memory device of a modified version of the second embodiment will be described.

[0170] As explained with reference to Figure 8 in the first embodiment, when only the first and second write operations are repeated for a single memory cell MC, the low-resistance domain undergoes repeated polarization reversal, but the high-resistance domain does not undergo any polarization reversal. Therefore, imprinting is less likely to occur in the low-resistance domain where polarization reversal occurs, but imprinting may become apparent in the high-resistance domain where no polarization reversal occurs. Consequently, even if the write operation to the memory cell MC is performed repeatedly, imprinting may occur in the memory cell MC, potentially leading to write failures or erase failures of the memory cell MC. This problem is inherent to multi-level memory using ferroelectric materials.

[0171] As mentioned above, there is a problem inherent to multi-level memory in that imprints may occur on the memory cell MC even if the writing process to the memory cell MC is performed repeatedly. Furthermore, the inventors' studies have revealed that the imprints that occur when only the first and second writing processes are repeated on the memory cell MC result in a larger change in resistance voltage compared to the imprints that occur when the memory cell MC is simply left without performing the first or second writing processes.

[0172] A modification of the semiconductor memory device of the second embodiment involves performing a recovery process to restore the imprint of the memory cell MC when the second write process, which accelerates the imprinting of the memory cell MC, reaches a predetermined first number of times. Therefore, the imprint of the memory cell MC is effectively restored, and write failures or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a two-dimensional NOR memory 100, can be realized.

[0173] From the viewpoint of effectively recovering the imprint that occurs in the memory cell MC, it is preferable that the absolute value of the first recovery voltage Vrp1 is greater than or equal to the absolute value of the erase voltage Verase. Also from the same viewpoint, it is preferable that the fourth pulse width w4 of the first recovery voltage pulse RP1 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also from the same viewpoint, it is preferable that the fourth pulse width w4 is greater than or equal to the second pulse width w2 of the erase voltage pulse EP.

[0174] From the viewpoint of effectively recovering the imprint that occurs in the memory cell MC, it is preferable that the absolute value of the second recovery voltage Vrp2 is greater than or equal to the absolute value of the first write voltage Vwrite1. Also from the same viewpoint, it is preferable that the fifth pulse width w5 of the second recovery voltage pulse RP2 is greater than or equal to the third pulse width w3 of the second write voltage pulse WP2. Also from the same viewpoint, it is preferable that the fifth pulse width w5 is greater than or equal to the first pulse width w1 of the first write voltage pulse WP1.

[0175] As described above, according to the second embodiment and its modifications, the imprint of the memory cell is effectively recovered, and a semiconductor memory device with superior characteristics can be realized.

[0176] (Third embodiment) The semiconductor memory device of the third embodiment includes a first semiconductor layer extending in a first direction, a plurality of gate electrode layers stacked in the first direction, a first wiring electrically connected to the first semiconductor layer, a second wiring electrically connected to the first semiconductor layer, a plurality of first memory cells, each first memory cell comprising a first semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer including a ferroelectric material provided between the first semiconductor layer and the gate electrode layer, a memory cell array, and a control circuit for controlling the plurality of first memory cells. The control circuit is capable of performing a first write operation to one first memory cell selected from the plurality of first memory cells. The first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between one gate electrode layer of one first memory cell and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase operation to one first memory cell. The erase process applies a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width between one gate electrode layer of one first memory cell and at least one of the first wiring and the second wiring. The control circuit can perform a second write process to one first memory cell. The second write process applies a third voltage pulse having a third voltage with a first polarity smaller in absolute value than the absolute value of the first voltage and a third pulse width between one gate electrode layer of one first memory cell and at least one of the first wiring and the second wiring. The control circuit can perform a first process to one first memory cell that is consecutive to the second write process before the second write process. The first process involves applying a fourth voltage pulse having a fourth voltage with a first polarity and a fourth pulse width, and a fourth voltage pulse having a fourth voltage with a second polarity and a fourth pulse width, between one gate electrode layer of one first memory cell and at least one of the first wiring and the second wiring, and applying a fifth voltage pulse that is a fourth voltage with a second polarity and a fifth pulse width, and a fourth voltage pulse having a fifth voltage with a second polarity and a fourth voltage pulse, to at least one of the first wiring and the second wiring of one first memory cell.

[0177] The semiconductor memory device of the third embodiment differs from the semiconductor memory device of the first embodiment in that it includes a three-dimensional NAND flash memory instead of a two-dimensional NOR memory. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0178] The semiconductor memory device of the third embodiment includes a three-dimensional NAND flash memory. The semiconductor memory device of the third embodiment uses a field-effect transistor with a ferroelectric material in its gate insulating layer as a memory cell. The semiconductor memory device of the third embodiment is a multi-level memory in which a single memory cell can hold three or more states (levels).

[0179] Figure 17 is a block diagram of a memory system including a semiconductor memory device of a third embodiment. The memory system of the third embodiment includes, for example, a three-dimensional NAND flash memory 400, a controller 500, and a host device 600. The semiconductor memory device of the third embodiment includes, for example, a three-dimensional NAND flash memory 400 and a controller 500.

[0180] The 3D NAND flash memory 400 is, for example, a 3D NAND flash memory chip. The controller 500 is, for example, a controller chip.

[0181] The 3D NAND flash memory 400 and controller 500 are, for example, implemented in a memory card or a Solid State Drive (SSD) that combines both components.

[0182] The 3D NAND flash memory 400 and the controller 500 may, for example, be located on the same semiconductor chip.

[0183] The host device 600 is, for example, a digital camera or a personal computer.

[0184] As shown in Figure 17, the three-dimensional NAND flash memory 400 includes a memory cell array 410 and peripheral circuits 420.

[0185] The memory cell array 410 includes a plurality of memory blocks MB0 to MBj (where j is a natural number). Each of the plurality of memory blocks MB0 to MBj includes a plurality of pages P. In the third embodiment, data write operations and data read operations are performed, for example, on a page P basis. Also in the third embodiment, data erase operations are performed, for example, on a memory block MBi (where i is a natural number less than or equal to j) basis.

[0186] The peripheral circuit 420 is provided around the memory cell array 410. The peripheral circuit 420 has the function of controlling the operation of the memory cell array 410 in response to instructions received from the controller 500. For example, the peripheral circuit 420 performs data writing or data reading operations for page P specified by the controller 500. The peripheral circuit 420 also performs data erasure operations for memory block MBi specified by the controller 500. The peripheral circuit 420 also performs recovery operations for memory block MBi specified by the controller 500.

[0187] The controller 500 controls the 3D NAND flash memory 400. The controller 500 also accesses the 3D NAND flash memory 400 in response to commands received from the host device 600.

[0188] The peripheral circuitry 420 and controller 500 of the 3D NAND flash memory 400 are an example of the control circuit of the third embodiment.

[0189] As shown in Figure 17, the controller 500 includes a processor 510 (CPU), built-in memory 520 (RAM, ROM), NAND interface circuit 530, buffer memory 540, and host interface circuit 550.

[0190] The processor 510 controls the overall operation of the controller 500. The processor 510 has the ability to perform various processes for managing the 3D NAND flash memory 400.

[0191] The internal memory 520 is, for example, semiconductor memory. The internal memory 520 is used, for example, as a workspace for the processor. The internal memory 520 also stores, for example, firmware for managing the 3D NAND flash memory 400 and various management tables.

[0192] The NAND interface circuit 530 is connected to the 3D NAND flash memory 400 via a NAND bus. The NAND interface circuit 530 has a function to control communication with the 3D NAND flash memory 400.

[0193] The buffer memory 540 has the function of temporarily storing data written to memory cells and data read from memory cells, for example.

[0194] The host interface circuit 550 is connected to the host device 600 via the host bus. The host interface circuit 550, for example, forwards instructions received from the host device 600 to the processor 510. The host interface circuit 550 also, for example, forwards data received from the host device 600 to the buffer memory 540. The host interface circuit 550 also, for example, forwards data from the buffer memory 540 to the host device 600 in response to instructions from the processor 510.

[0195] Figure 18 is an equivalent circuit diagram of a memory block of a semiconductor memory device according to the third embodiment. Figure 18 is an equivalent circuit diagram of a memory block MBi of a 3D NAND flash memory 400.

[0196] The memory block MBi is connected to the peripheral circuit 420 by a common source line CSL, multiple bit lines BL, multiple word lines WL, a source selection gate line SGS, and a drain selection gate line SGD.

[0197] A memory block MBi comprises multiple memory fingers MF. Each memory finger MF contains multiple memory strings MS.

[0198] One end of each of the multiple memory strings MS is connected to the common source line CSL. The other end of each of the multiple memory strings MS is connected to the bit line BL.

[0199] Each of the multiple memory strings MS includes a source selection transistor STS, multiple memory cells MC, and a drain selection transistor STD, all connected in series between a common source line CSL and a bit line BL. The source selection transistor STS, the multiple memory cells MC, and the drain selection transistor STD are field-effect transistors (FETs) whose operation is controlled by the voltage applied to their gate electrodes.

[0200] A word line WL is connected to the gate electrode of each of the multiple memory cells MC. The word line WL is commonly connected to all memory strings MS within a single memory finger MF. Furthermore, within a single memory block MBi, multiple word lines WL connected to one memory finger MF are commonly connected to multiple word lines connected to the remaining memory fingers MF. In addition, within a single memory finger MF, multiple memory cells MC commonly connected to one word line WL constitute a page P.

[0201] The gate electrode of the source-selection transistor STS is connected to the source-selection gate wire SGS. The gate electrode of the drain-selection transistor STD is connected to the drain-selection gate wire SGD.

[0202] Figure 19 is an equivalent circuit diagram of a portion of the memory cell array of a semiconductor memory device according to the third embodiment. Figure 19 is an equivalent circuit diagram of a portion of the memory cell array 410 of a three-dimensional NAND flash memory 400. Figure 19 is an equivalent circuit diagram of a portion of the memory block MBi of the three-dimensional NAND flash memory 400.

[0203] Multiple word lines WL are arranged in the z direction, spaced apart from each other. Multiple word lines WL are arranged stacked in the z direction. Multiple word lines WL include a first word line WL1, a second word line WL2, a third word line WL3, and a fourth word line WL4.

[0204] Multiple bit lines BL extend, for example, in the x-direction. Multiple bit lines BL include a first bit line BL1 and a second bit line BL2.

[0205] Multiple memory strings MS extend in the z direction. These multiple memory strings MS include a first memory string MS1 and a second memory string MS2. The first memory string MS1 is connected to the first bit line BL1. The second memory string MS2 is connected to the second bit line BL2.

[0206] Hereafter, we define the x-direction as the third direction, the y-direction as the second direction, and the z-direction as the first direction. The x, y, and z directions intersect with each other and are, for example, perpendicular to each other.

[0207] As shown in Figure 19, the memory string MS comprises a source selection transistor STS connected in series between a common source line CSL and a bit line BL, a plurality of memory cells MC, and a drain selection transistor STD. The memory string MS is electrically connected to the common source line CSL and the bit line BL. The common source line CSL is an example of a first wiring configuration. The bit line BL is an example of a second or third wiring configuration.

[0208] The first memory string MS1 includes, for example, a plurality of first memory cells MC1a, MC1b, MC1c, and MC1d. The second memory string MS2 includes, for example, a plurality of second memory cells MC2a, MC2b, MC2c, and MC2d.

[0209] Note that while Figure 19 shows the case where a single memory string MS contains four memory cells MC, the number of memory cells MC is not limited to four. The number of memory cells MC can be three or fewer, or five or more.

[0210] By selecting one bit line BL and one drain selection gate line SGD, one memory string MS is selected, and by selecting one word line WL, one memory cell MC becomes selectable. The word line WL is the gate electrode of the memory cell transistor that constitutes the memory cell MC.

[0211] Figures 20 and 21 are schematic cross-sectional views of a portion of the memory cell array of a semiconductor memory device according to a third embodiment. Figures 20 and 21 show cross-sections of multiple memory cells MC in the first memory string MS1 and the second memory string MS2 within the memory cell array 410 of Figure 19.

[0212] Figure 20 is a yz cross-sectional view of the memory cell array 410. Figure 20 is the BB' cross-section of Figure 21. Figure 21 is an xy cross-sectional view of the memory cell array 410. Figure 21 is the AA' cross-section of Figure 20. In Figure 20, the area enclosed by the dashed line is a single memory cell MC.

[0213] As shown in Figures 20 and 21, the memory cell array 410 comprises word lines WL, semiconductor layers 10, gate insulating layers 21, interlayer insulating layers 13, and core insulating regions 20. Multiple word lines WL and multiple interlayer insulating layers 13 constitute a laminate 30.

[0214] The word line WL is an example of a gate electrode layer.

[0215] The memory cell array 110 is provided, for example, on a semiconductor substrate (not shown). The semiconductor substrate has, for example, surfaces parallel to the x and y directions.

[0216] The word lines WL and the interlayer insulating layer 13 are alternately stacked on the semiconductor substrate in the z direction. The word lines WL are repeatedly arranged in the z direction, spaced apart from each other. The word lines WL function as control electrodes for the memory cell transistor.

[0217] The word wire WL is, for example, a plate-shaped conductor. The word wire WL is, for example, a metal.

[0218] The interlayer insulating layer 13 is provided in the z-direction of the word line WL. The word line WL and the interlayer insulating layer 13 are repeatedly arranged in the z-direction.

[0219] The interlayer insulating layer 13 separates the word wires WL from each other. The interlayer insulating layer 13 electrically separates the word wires WL from each other.

[0220] The interlayer insulating layer 13 is, for example, an oxide, an oxynitride, or a nitride. The interlayer insulating layer 13 is, for example, silicon oxide.

[0221] The semiconductor layer 10 is provided within the laminate 30. The semiconductor layer 10 extends in the z direction. The semiconductor layer 10 extends in a direction perpendicular to the surface of the semiconductor substrate.

[0222] The semiconductor layer 10 is provided penetrating the laminate 30. The semiconductor layer 10 is surrounded by multiple word lines WL. The semiconductor layer 10 is, for example, cylindrical. The semiconductor layer 10 functions as a channel for a memory cell transistor.

[0223] The semiconductor layer 10 is, for example, a polycrystalline semiconductor. The semiconductor layer 10 is, for example, polycrystalline silicon.

[0224] The semiconductor layer 10 includes, for example, a first semiconductor layer 10a and a second semiconductor layer 10b.

[0225] The semiconductor layer 10 is electrically connected to the common source line CSL and the bit line BL. The first semiconductor layer 10a and the second semiconductor layer 10b are electrically connected to the common source line CSL and the bit line BL.

[0226] The common source line CSL is an example of the first wiring. The bit line BL is an example of the second or third wiring. For example, the first bit line BL1 electrically connected to the first semiconductor layer 10a is an example of the second wiring. Also, for example, the second bit line BL2 electrically connected to the second semiconductor layer 10b is an example of the third wiring.

[0227] The gate insulating layer 21 is provided between the semiconductor layer 10 and the word line WL and contains a ferroelectric material. The gate insulating layer 21 is, for example, a ferroelectric layer.

[0228] The gate insulating layer 21 includes, for example, at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

[0229] The gate insulating layer 21 is, for example, polycrystalline. The gate insulating layer 11 includes, for example, a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Oxides of hafnium (Hf) or zirconium (Zr) having space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), or Pmn21 (space group number 31) are ferroelectrics.

[0230] The core insulating region 20 is provided within the laminate 30. The core insulating region 20 extends in the z direction. The core insulating region 20 penetrates the laminate 30. The core insulating region 20 is surrounded by the semiconductor layer 10. The core insulating region 20 is surrounded by a plurality of word lines WL. The core insulating region 20 is columnar. The core insulating region 20 is, for example, cylindrical.

[0231] The core insulating region 20 is, for example, an oxide, an oxynitride, or a nitride. The core insulating region 20 includes, for example, silicon (Si) and oxygen (O). The core insulating region 20 is, for example, silicon oxide.

[0232] The peripheral circuits 420 and controller 500 of the 3D NAND flash memory 400 control, for example, multiple memory cells MC in the memory cell array 410. The peripheral circuits 420 and controller 500 of the 3D NAND flash memory 400 control, for example, writing data to memory cells included in the memory cell array 410, reading data from memory cells, or erasing data from memory cells.

[0233] The peripheral circuitry 420 and controller 500 of the 3D NAND flash memory 400 control, for example, the first memory cells MC1a to MC1d included in the first memory string MS1. Also, for example, the peripheral circuitry 420 and controller 500 control the second memory cells MC2a to MC2d included in the second memory string MS2.

[0234] The possible states of the memory cell MC of the semiconductor memory device in the third embodiment are the same as those of the first embodiment described with reference to Figure 4.

[0235] The peripheral circuit 420 and the controller 500 can, for example, perform a first write operation, an erase operation, a second write operation, and a suppression operation that precedes the second write operation and is continuous with the second write operation, on any one first memory cell MC1 selected from the first memory cells MC1a to MC1d. The voltage pulses applied to the memory cell MC in the first write operation, second write operation, erase operation, and suppression operation in the control of the semiconductor memory device of the third embodiment are the same as those in the semiconductor memory device of the first embodiment. The suppression operation is an example of the first operation.

[0236] For example, when performing a first write operation, an erase operation, a second write operation, and a suppression operation on the first memory cell MC1a, the first word line WL1 is an example of a gate electrode layer, the common source line CSL is an example of a first wiring, and the first bit line BL1 is an example of a second wiring. The following explanation will use the case where the first write operation, an erase operation, a second write operation, and a suppression operation are performed on the first memory cell MC1a as an example.

[0237] The first write operation involves applying a first write voltage pulse WP1 between the first word line WL1 of the first memory cell MC1a and at least one of the common source line CSL and the first bit line BL1. The first write operation also involves applying the first write voltage pulse WP1 to the gate insulating layer 21 of the first memory cell MC1a.

[0238] The first write voltage pulse WP1 has a first write voltage Vwrite1 of first polarity and a first pulse width w1. The first write voltage pulse WP1 is an example of a first voltage pulse. The first write voltage Vwrite1 is an example of a first voltage.

[0239] The erase process involves applying an erase voltage pulse EP between the first word line WL1 of the first memory cell MC1a and at least one of the common source line CSL and the first bit line BL1. The erase process also involves applying the erase voltage pulse EP to the gate insulating layer 21 of the first memory cell MC1a, for example.

[0240] The erase voltage pulse EP has an erase voltage Verase with a second polarity opposite to the first polarity, and a second pulse width w2. The erase voltage pulse EP is an example of the second voltage pulse. The erase voltage Verase is an example of the second voltage.

[0241] The second write process involves applying a second write voltage pulse WP2 between the first word line WL1 of the first memory cell MC1a and at least one of the common source line CSL and the first bit line BL1. The second write process also involves applying the second write voltage pulse WP2 to the gate insulating layer 21 of the first memory cell MC1a.

[0242] The second write voltage pulse WP2 has a second write voltage Vwrite2 of first polarity and a third pulse width w3. The second write voltage pulse WP2 is an example of a third voltage pulse. The second write voltage Vwrite2 is an example of a third voltage.

[0243] The suppression process applies a first suppression voltage pulse SP1 and a second suppression voltage pulse SP2 between the first word line WL1 of the first memory cell MC1a and at least one of the common source line CSL and the first bit line BL1. The suppression process also applies the first suppression voltage pulse SP1 and the second suppression voltage pulse SP2 to the gate insulating layer 21 of the first memory cell MC1a.

[0244] The first suppression voltage pulse SP1 has a first suppression voltage Vsup1 of first polarity and a fourth pulse width w4. The first suppression voltage pulse SP1 is an example of a fourth voltage pulse. The first suppression voltage Vsup1 is an example of a fourth voltage.

[0245] The second suppression voltage pulse SP2 has a second suppression voltage Vsup2 of second polarity and a fifth pulse width w5. The second suppression voltage pulse SP2 is an example of a fifth voltage pulse. The second suppression voltage Vsup2 is an example of a fifth voltage.

[0246] For example, the first polarity is the polarity in which the word line WL is positive relative to the common source line CSL or bit line BL, and the second polarity is the polarity in which the word line WL is negative relative to the common source line CSL or bit line BL. In other words, for example, the first polarity is the polarity in which the word line WL is positive relative to the semiconductor layer 10, and the second polarity is the polarity in which the word line WL is negative relative to the semiconductor layer 10.

[0247] In the third embodiment, similar to the semiconductor memory device of the first embodiment, a suppression process is performed before the second write process, thereby causing polarization reversal in all polarization domains of the memory cell MC. Therefore, imprinting of the memory cell MC is suppressed, and write or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a 3D NAND flash memory 400, can be realized.

[0248] (modified version) A modified version of the semiconductor memory device of the third embodiment differs from the semiconductor memory device of the third embodiment in that the second write process applies a third voltage pulse having a third voltage of second polarity and a third pulse width, with an absolute value smaller than the absolute value of the second voltage, between the gate electrode layer and at least one of the first wiring and the second wiring, and the first process applies a fourth voltage pulse having a fourth voltage of second polarity and a fourth pulse width, with an absolute value larger than the absolute value of the third voltage, between the gate electrode layer and at least one of the first wiring and the second wiring, followed by the application of a fifth voltage pulse having a fifth voltage of first polarity and a fifth pulse width, which is a continuation of the application of the fourth voltage pulse, with an absolute value larger than the absolute value of the third voltage.

[0249] The possible states of the memory cell MC in the modified semiconductor memory device of the third embodiment are the same as those of the modified first embodiment described with reference to Figure 8. Furthermore, the voltage pulses applied to the memory cell MC during the first write process, second write process, erase process, and suppression process in the control of the modified semiconductor memory device of the third embodiment are the same as those of the semiconductor memory device of the modified first embodiment.

[0250] In the modification of the semiconductor memory device of the third embodiment, similar to the modification of the semiconductor memory device of the first embodiment, a suppression process is performed before the second write process, thereby causing polarization reversal in all polarization domains of the memory cell MC. Therefore, imprinting of the memory cell MC is suppressed, and write or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a 3D NAND flash memory 400, can be realized.

[0251] As described above, according to the third embodiment and its modifications, memory cell imprinting is suppressed, and a semiconductor memory device with superior characteristics can be realized.

[0252] (Fourth embodiment) The semiconductor memory device of the fourth embodiment includes a first semiconductor layer extending in a first direction, a second semiconductor layer extending in a first direction, a plurality of gate electrode layers stacked in a first direction, a first wiring electrically connected to the first semiconductor layer and the second semiconductor layer, a second wiring electrically connected to the first semiconductor layer, a third wiring connected to the second semiconductor layer, a plurality of first memory cells, each first memory cell comprising a first semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the first semiconductor layer and the one gate electrode layer, a plurality of second memory cells, each second memory cell comprising a second semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the second semiconductor layer and the one gate electrode layer, a memory cell array, and a control circuit for controlling the plurality of first memory cells and the plurality of second memory cells. The control circuit is capable of performing a first write operation on any one memory cell among a plurality of first memory cells and a plurality of second memory cells. The first write operation, if one memory cell is one of the first memory cells, applies a first voltage pulse having a first polarity and a first pulse width between one gate electrode layer of one memory cell and at least one of the first wiring and the second wiring. The first write operation, if one memory cell is one of the second memory cells, applies a first voltage pulse having a first polarity and a first pulse width between one gate electrode layer of one memory cell and at least one of the first wiring and the third wiring. The control circuit is capable of performing an erase operation on a plurality of first memory cells and a plurality of second memory cells. The erase operation applies a second voltage pulse having a second polarity opposite to the first polarity and a second pulse width between a plurality of gate electrode layers and the first wiring. The control circuit is capable of performing a second write operation on one memory cell.The second write operation applies a third voltage pulse having a third voltage of a first polarity with an absolute value smaller than the absolute value of the first voltage and a third pulse width between one gate electrode layer of one memory cell and at least one of the first wiring and the second wiring. The second write operation applies a third voltage pulse having a third voltage of a first polarity with an absolute value smaller than the absolute value of the first voltage and a third pulse width between one gate electrode layer of one memory cell and at least one of the first wiring and the third wiring. The control circuit can determine whether the number of executions of the second write operation to each of the multiple first memory cells and the multiple second memory cells has reached a predetermined first number. If the control circuit determines that the number of executions to any of the multiple first memory cells and the multiple second memory cells has reached a predetermined first number, it can perform the first operation on the multiple first memory cells and the multiple second memory cells. The first process involves applying a fourth voltage pulse between multiple gate electrode layers and the first wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth polarity and a fourth pulse width, followed by the application of a fifth voltage pulse, which is a fourth voltage with a second polarity and a fifth pulse width, and which is a fourth voltage pulse, both having an absolute value greater than the absolute value of the third voltage.

[0253] The semiconductor memory device of the fourth embodiment differs from the semiconductor memory device of the third embodiment in that it performs a recovery process. Some descriptions that overlap with the third embodiment may be omitted below.

[0254] Figure 22 is a block diagram of a memory system including a semiconductor memory device according to the fourth embodiment. The processor 510 of the fourth embodiment differs from the processor 510 of the third embodiment in that it includes a judgment circuit 511.

[0255] The internal memory 520 stores, for example, the number of times a second write operation has been performed on each memory cell included in the 3D NAND flash memory 400. The internal memory 520 also stores, for example, a predetermined first number of times the second write operation has been performed, which serves as a criterion for determining whether or not to perform a recovery operation. Based on the number of times the second write operation has been performed on any memory cell and the predetermined first number of times the second write operation has been performed, the determination circuit 511 can determine whether or not the number of times the second write operation has been performed on any memory cell has reached a predetermined number.

[0256] The peripheral circuit 420 and controller 500 can, for example, measure and store the number of times the second write operation is performed on each of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d. The peripheral circuit 420 and controller 500 can also determine whether the number of times the second write operation is performed on each of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d has reached a predetermined first number. If the peripheral circuit 420 and controller 500 determine that the number of executions on either the first memory cells MC1a to MC1d or the second memory cells MC2a to MC2d has reached a predetermined first number, they can perform a recovery operation on the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d. The recovery operation is an example of the first operation.

[0257] The possible states of the memory cell MC of the semiconductor memory device in the fourth embodiment are the same as those of the first embodiment described with reference to Figure 4.

[0258] The peripheral circuit 420 and the controller 500 can, for example, perform a first write operation and a second write operation on any one memory cell MC selected from the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2b. Furthermore, the peripheral circuit 420 and the controller 500 can perform erase and recover operations on all memory cells MC of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2b.

[0259] In the control of the semiconductor memory device of the fourth embodiment, the voltage pulses applied to the memory cell MC during the first write process, second write process, erase process, and recover process are the same as those in the semiconductor memory device of the second embodiment.

[0260] For example, when performing a first write operation and a second write operation on the first memory cell MC1a, the first word line WL1 is an example of a gate electrode layer, the common source line CSL is an example of a first wiring, and the first bit line BL1 is an example of a second wiring. Similarly, when performing a first write operation and a second write operation on the second memory cell MC2c, the third word line WL3 is an example of a gate electrode layer, the common source line CSL is an example of a first wiring, and the second bit line BL2 is an example of a third wiring. The following explanation will use the case where the first write operation and the second write operation are performed on the first memory cell MC1a or the second memory cell MC2c as an example.

[0261] When the first write operation is performed on the first memory cell MC1a, the first write voltage pulse WP1 is applied between the first word line WL1 and at least one of the common source line CSL and the first bit line BL1. The first write operation also applies the first write voltage pulse WP1 to the gate insulating layer 21 of the first memory cell MC1a.

[0262] When the first write operation is performed on the second memory cell MC2c, the first write voltage pulse WP1 is applied between the third word line WL3 and at least one of the common source line CSL and the second bit line BL2. The first write operation is also performed by applying the first write voltage pulse WP1 to the gate isolation layer 21 of the second memory cell MC2c.

[0263] The first write voltage pulse WP1 has a first write voltage Vwrite1 of first polarity and a first pulse width w1. The first write voltage pulse WP1 is an example of a first voltage pulse. The first write voltage Vwrite1 is an example of a first voltage.

[0264] The erase process involves applying an erase voltage pulse EP between the first word line WL1, the second word line WL2, the third word line WL3, and the fourth word line WL4, and the common source line CSL. The erase process also involves applying the erase voltage pulse EP to the gate insulating layer 21 of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d, for example.

[0265] The erase voltage pulse EP has an erase voltage Verase with a second polarity opposite to the first polarity, and a second pulse width w2. The erase voltage pulse EP is an example of the second voltage pulse. The erase voltage Verase is an example of the second voltage.

[0266] When the second write operation is performed on the first memory cell MC1a, the second write voltage pulse WP2 is applied between the first word line WL1 and at least one of the common source line CSL and the first bit line BL1. The second write operation applies the second write voltage pulse WP2 to the gate insulating layer 21 of the first memory cell MC1a.

[0267] When the second write operation is performed on the second memory cell MC2c, the second write voltage pulse WP2 is applied between the third word line WL3 and at least one of the common source line CSL and the second bit line BL2. The second write operation applies the second write voltage pulse WP2 to the gate insulating layer 21 of the second memory cell MC2c.

[0268] The second write voltage pulse WP2 has a second write voltage Vwrite2 of first polarity and a third pulse width w3. The second write voltage pulse WP2 is an example of a third voltage pulse. The second write voltage Vwrite2 is an example of a third voltage.

[0269] The recovery process applies a first recovery voltage pulse RP1 and a second recovery voltage pulse RP2 between the first word line WL1, the second word line WL2, the third word line WL3, and the fourth word line WL4, and the common source line CSL. The recovery process applies the first recovery voltage pulse RP1 and the second recovery voltage pulse RP2 to the gate insulating layers 21 of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d.

[0270] The first recovery voltage pulse RP1 has a first recovery voltage Vrp1 of the first polarity and a fourth pulse width w4. The first recovery voltage pulse RP1 is an example of the fourth voltage pulse. The first recovery voltage Vrp1 is an example of the fourth voltage.

[0271] The second recovery voltage pulse RP2 has a second recovery voltage Vrp2 of the second polarity and a fifth pulse width w5. The second recovery voltage pulse RP2 is an example of the fifth voltage pulse. The second recovery voltage Vrp2 is an example of the fifth voltage.

[0272] FIG. 23 is a timing chart for explaining a control method of a semiconductor memory device according to the fourth embodiment. FIG. 23 shows voltage pulses applied to the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d included in the memory cell array 410.

[0273] As shown in FIG. 23, for example, assume that the number of executions of the second writing process for each of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d reaches a predetermined first number, and in this case, the recovery process is executed collectively for all of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d.

[0274] Similar to the second embodiment, the semiconductor memory device of the fourth embodiment performs a recovery process for recovering the imprint of the memory cell MC when the second write process for accelerating the imprint of the memory cell MC reaches a predetermined first number of times. Therefore, the imprint of the memory cell MC is effectively recovered, and write failures or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics including the 3D NAND flash memory 400 can be realized.

[0275] (Modified Example) In the modified example of the semiconductor memory device of the fourth embodiment, the second write process applies a third voltage pulse having a third voltage with a second polarity whose absolute value is smaller than the absolute value of the second voltage and a third pulse width, and the first process applies a fourth voltage pulse having a fourth voltage with a second polarity whose absolute value is larger than the absolute value of the third voltage and a fourth pulse width, and a fifth voltage pulse having a fifth voltage with a first polarity whose absolute value is larger than the absolute value of the third voltage and a fifth pulse width, and is continuous with the application of the fourth voltage pulse between the gate electrode layer and the first wiring. This is different from the semiconductor memory device of the fourth embodiment.

[0276] The possible states of the memory cell MC in the modified example of the semiconductor memory device of the fourth embodiment are the same as those in the modified example of the first embodiment described using FIG. 8. Also, the voltage pulses applied to the memory cell MC in the first write process, the second write process, the erase process, and the recovery process in the control of the modified example of the semiconductor memory device of the fourth embodiment are the same as those in the modified example of the semiconductor memory device of the second embodiment.

[0277] FIG. 24 is a timing chart for explaining the control method of the modified example of the semiconductor memory device of the fourth embodiment. FIG. 24 shows the voltage pulses applied to the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d included in the memory cell array 410.

[0278] As shown in Figure 24, for example, when the number of executions of the second write operation of the first memory cell MC1b reaches a predetermined first number, a recovery process is performed on all of the first memory cells MC1a to MC1d and the second memory cells MC2a to MC2d at once.

[0279] In the modification of the semiconductor memory device of the fourth embodiment, similar to the modification of the second embodiment, when the second write process that accelerates the imprinting of the memory cell MC reaches a predetermined first number of times, a recovery process is performed to restore the imprinting of the memory cell MC. Therefore, the imprinting of the memory cell MC is effectively restored, and write failures or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a three-dimensional NAND flash memory 400, can be realized.

[0280] As described above, according to the fourth embodiment and its modifications, the imprint of the memory cell is effectively recovered, and a semiconductor memory device with superior characteristics can be realized.

[0281] (Fifth embodiment) The semiconductor memory device of the fifth embodiment includes a memory cell comprising a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer including a ferroelectric material provided between the first conductive layer and the second conductive layer; a first wiring electrically connected to the first conductive layer via the semiconductor layer; a second wiring electrically connected to the second conductive layer; and a control circuit for controlling the memory cell. The control circuit is capable of performing a first write operation to the memory cell. The first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the first wiring and the second wiring. The control circuit is capable of performing an erase operation to the memory cell. The erase operation involves applying a second voltage pulse having a second polarity opposite to the first polarity, a second voltage, and a second pulse width between the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell. The second write operation applies a third voltage pulse between the first and second wiring, having a third voltage of first polarity with an absolute value smaller than the absolute value of the first voltage and a third pulse width. The control circuit can perform the first operation on the memory cell that is continuous with the second write operation before the second write operation. The first operation applies a fourth voltage pulse between the first and second wiring, having a fourth voltage of first polarity with an absolute value larger than the absolute value of the third voltage and a fourth pulse width, followed by a fifth voltage pulse that is continuous with the fourth voltage pulse having second polarity with an absolute value larger than the absolute value of the third voltage and a fifth pulse width.

[0282] The semiconductor memory device of the fifth embodiment differs from the semiconductor memory device of the first embodiment in that it includes a ferroelectric random access memory (FeRAM) that uses a ferroelectric capacitor instead of a two-dimensional NOR memory. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0283] The semiconductor memory device of the fifth embodiment includes FeRAM using a ferroelectric capacitor. The semiconductor memory device of the fifth embodiment uses a capacitor in which a ferroelectric material is included in the capacitor insulating layer as a memory cell. The semiconductor memory device of the fifth embodiment is a multi-level memory in which a single memory cell can hold three or more states (levels).

[0284] Figure 25 is a block diagram of a memory system including a semiconductor memory device according to a fifth embodiment. The memory system of the fifth embodiment includes, for example, FeRAM 700, a controller 800, and a host device 900. The semiconductor memory device of the fifth embodiment includes, for example, FeRAM 700 and a controller 800.

[0285] FeRAM700 is, for example, an FeRAM chip. Similarly, controller800 is, for example, a controller chip.

[0286] The FeRAM700 and the controller800 may, for example, be located on the same semiconductor chip.

[0287] The host device 900 is, for example, a personal computer.

[0288] As shown in Figure 25, the FeRAM 700 includes a memory cell array 710 and peripheral circuits 720.

[0289] The controller 800 controls the FeRAM 700. The controller 800 also accesses the FeRAM 700 in response to commands received from the host device 900.

[0290] The peripheral circuitry 720 and controller 200 of the FeRAM 700 control, for example, writing data to memory cells included in the memory cell array 710, reading data from memory cells, or erasing data from memory cells. The peripheral circuitry 720 and controller 800 of the FeRAM 700 are an example of the control circuit of the fifth embodiment.

[0291] As shown in FIG. 25, the controller 800 includes a processor 810 (CPU), a built-in memory 820 (RAM, ROM), a RAM interface circuit 830, a buffer memory 840, and a host interface circuit 850.

[0292] The processor 810 controls the overall operation of the controller 800. The processor 810 has a function of executing various processes for managing the FeRAM 700.

[0293] The built-in memory 820 is, for example, a semiconductor memory. The built-in memory 820 is used, for example, as a work area for the processor. Also, the built-in memory 820 stores, for example, firmware for managing the FeRAM 700 and various management tables.

[0294] The RAM interface circuit 830 is connected to the FeRAM 700 via a RAM bus. The RAM interface circuit 830 has a function of controlling communication with the FeRAM 700.

[0295] The buffer memory 840 has a function of temporarily storing, for example, write data to the memory cell and read data from the memory cell.

[0296] The host interface circuit 850 is connected to the host device 900 via a host bus. The host interface circuit 850 transfers, for example, an instruction received from the host device 900 to the processor 810. Also, the host interface circuit 850 transfers, for example, data received from the host device 900 to the buffer memory 840. Also, the host interface circuit 850 transfers, for example, data in the buffer memory 840 to the host device 900 in response to an instruction from the processor 810.

[0297] Figure 26 is an equivalent circuit diagram of a portion of the memory cell array of the semiconductor memory device of the fifth embodiment. Figure 26 is an equivalent circuit diagram of a portion of the memory cell array 710 of the FeRAM 700.

[0298] As shown in Figure 26, the memory cell array 710 includes a plurality of memory cells MC, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of plate lines PL. The plurality of memory cells MC include memory cells MCa, MCb, MCc, and MCd. The plurality of word lines WL include a first word line WL1 and a second word line WL2. The plurality of bit lines BL include a first bit line BL1 and a second bit line BL2. The plurality of plate lines PL include a first plate line PL1 and a second plate line PL2.

[0299] Multiple word lines WL are arranged parallel to each other and spaced apart. Multiple bit lines BL intersect, for example, with the word lines WL. Multiple bit lines BL are arranged parallel to each other and spaced apart. Multiple plate lines PL intersect, for example, with the word lines WL. Multiple plate lines PL are arranged parallel to each other and spaced apart.

[0300] By selecting one plate line (PL), one bit line (BL), and one word line (WL), one memory cell (MC) can be selected.

[0301] A memory cell (MC) contains one transistor and one capacitor. The capacitor is a ferroelectric capacitor that uses a ferroelectric material as the capacitor insulating layer. The word line (WL) is the gate electrode of the transistor that constitutes the memory cell (MC). The transistor is a field-effect transistor whose operation is controlled by the voltage applied to its gate electrode. The transistor acts as a switching element to write data to and read data stored in the capacitor.

[0302] The FeRAM700 is configured to enable random access to multiple memory cells MC included in the memory cell array 710.

[0303] Figure 27 is a schematic cross-sectional view including a memory cell of a semiconductor memory device according to the fifth embodiment.

[0304] As shown in Figure 27, the memory cell MC comprises a semiconductor layer 50, a word line WL, a gate insulating layer 51, a contact plug CP, a capacitor insulating layer 60, a first capacitor electrode 61, and a second capacitor electrode 62. The semiconductor layer 50 includes a source region 50x, a drain region 50y, and a channel region 50z. The bit line BL and plate line PL are connected to the memory cell MC.

[0305] The word line WL is an example of a gate electrode layer. The first capacitor electrode 61 is an example of a first conductive layer. The second capacitor electrode 62 is an example of a second conductive layer. The bit line BL is an example of a first wiring. The plate line PL is an example of a second wiring.

[0306] The semiconductor layer 50 is, for example, single-crystal silicon. The source region 50x and drain region 50y are, for example, n-type semiconductors. The channel region 10z is, for example, p-type semiconductor.

[0307] The word wire WL is a conductor. For example, the word wire WL is a metal. The contact plug CP is a conductor. For example, the contact plug CP is a metal.

[0308] The gate insulating layer 51 contains a paraelectric material. For example, the gate insulating layer 51 is silicon oxide.

[0309] The capacitor insulating layer 60 is provided between the first capacitor electrode 61 and the second capacitor electrode 62. The capacitor insulating layer 60 includes a ferroelectric material. For example, the capacitor insulating layer 60 is a ferroelectric layer.

[0310] The capacitor insulating layer 60 includes, for example, at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

[0311] The capacitor insulating layer 60 is, for example, polycrystalline. The gate insulating layer 11 includes, for example, a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Oxides of hafnium (Hf) or zirconium (Zr) having space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), or Pmn21 (space group number 31) are ferroelectrics.

[0312] The first capacitor electrode 61 is electrically connected to the semiconductor layer 50 using a contact plug CP. The first capacitor electrode 61 is also electrically connected to the drain region 50y.

[0313] The bit line BL is electrically connected to the semiconductor layer 50 using a contact plug CP. The bit line BL is electrically connected to the source region 50x. The bit line BL is electrically connected to the first capacitor electrode 61 via the semiconductor layer 50. The bit line BL is electrically connected to the first capacitor electrode 61 when the transistor of the memory cell MC is turned on.

[0314] The plate wire PL is electrically connected to the second capacitor electrode 62 using a contact plug CP.

[0315] In the FeRAM700 memory cell MC, data corresponding to the polarization amount of the ferroelectric material contained in the capacitor insulating layer 60 is stored. The possible states of the memory cell MC of the semiconductor memory device in the fifth embodiment are the same as those of the first embodiment described with reference to Figure 4. In the fifth embodiment, the ferroelectric material is contained in the capacitor insulating layer rather than the gate insulating layer, as in the first embodiment, but the problems of write failures and erase failures that may occur due to the imprinting of the ferroelectric material are the same as in the first embodiment.

[0316] The peripheral circuit 720 and controller 800 can, for example, perform a first write operation, an erase operation, a second write operation, and a suppression operation that precedes the second write operation and is continuous with the second write operation, on any one memory cell MC selected from memory cells MCa to MCd. The voltage pulses applied to the memory cell MC in the first write operation, erase operation, second write operation, and suppression operation in the control of the semiconductor memory device of the fifth embodiment are the same as those in the semiconductor memory device of the first embodiment. The suppression operation is an example of the first operation.

[0317] For example, when performing a first write operation, an erase operation, a second write operation, and a suppression operation on a memory cell MCa, the first bit line BL1 is an example of the first wiring, and the first plate line PL1 is an example of the second wiring. The following explanation will use the case where a first write operation, an erase operation, a second write operation, and a suppression operation are performed on a memory cell MCa as an example.

[0318] The first write operation applies a first write voltage pulse WP1 between the first bit line BL1 and the first plate line PL1. At this time, for example, the first word line WL1 is controlled to turn on the transistor. The first write operation applies the first write voltage pulse WP1 to the capacitor insulating layer 60 of the memory cell MCa.

[0319] The first write voltage pulse WP1 has a first write voltage Vwrite1 of first polarity and a first pulse width w1. The first write voltage pulse WP1 is an example of a first voltage pulse. The first write voltage Vwrite1 is an example of a first voltage.

[0320] The erase process involves applying an erase voltage pulse EP between the first bit line BL1 and the first plate line PL1. At this time, for example, the first word line WL1 is controlled to turn on the transistor. The erase process also involves applying the erase voltage pulse EP to the capacitor insulating layer 60 of the memory cell MCa.

[0321] The erase voltage pulse EP has an erase voltage Verase with a second polarity opposite to the first polarity, and a second pulse width w2. The erase voltage pulse EP is an example of the second voltage pulse. The erase voltage Verase is an example of the second voltage.

[0322] The second writing process involves applying a second writing voltage pulse WP2 between the first bit line BL1 and the first plate line PL1. At this time, for example, the first word line WL1 is controlled to turn on the transistor. The second writing process involves applying the second writing voltage pulse WP2 to the capacitor insulating layer 60 of the memory cell MCa.

[0323] The second write voltage pulse WP2 has a second write voltage Vwrite2 of first polarity and a third pulse width w3. The second write voltage pulse WP2 is an example of a third voltage pulse. The second write voltage Vwrite2 is an example of a third voltage.

[0324] The suppression process applies a first suppression voltage pulse SP1 and a second suppression voltage pulse SP2 between the first bit line BL1 and the first plate line PL1. The suppression process also applies the first suppression voltage pulse SP1 and the second suppression voltage pulse SP2 to the capacitor insulating layer 60 of the memory cell MCa.

[0325] The first suppression voltage pulse SP1 has a first suppression voltage Vsup1 of first polarity and a fourth pulse width w4. The first suppression voltage pulse SP1 is an example of a fourth voltage pulse. The first suppression voltage Vsup1 is an example of a fourth voltage.

[0326] The second suppression voltage pulse SP2 has a second suppression voltage Vsup2 of second polarity and a fifth pulse width w5. The second suppression voltage pulse SP2 is an example of a fifth voltage pulse. The second suppression voltage Vsup2 is an example of a fifth voltage.

[0327] For example, the first polarity is the polarity in which the first plate wire PL1 has a positive voltage relative to the first bit wire BL1, and the second polarity is the polarity in which the first plate wire PL1 has a negative voltage relative to the first bit wire BL1.

[0328] The semiconductor memory device of the fifth embodiment, like the semiconductor memory device of the first embodiment, can induce polarization reversal in all polarization domains of the memory cell MC by performing a suppression process before the second write process. Therefore, imprinting of the memory cell MC is suppressed, and write or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a 3D NAND flash memory 400, can be realized.

[0329] (modified version) A modified version of the semiconductor memory device of the fifth embodiment differs from the semiconductor memory device of the fifth embodiment in that the second writing process applies a third voltage pulse having a third voltage of second polarity and a third pulse width, with an absolute value smaller than the absolute value of the second voltage, between the first wiring and the second wiring, and the first process applies a fourth voltage pulse having a fourth voltage of second polarity and a fourth pulse width, with an absolute value larger than the absolute value of the third voltage, between the first wiring and the second wiring, followed by the application of a fifth voltage pulse having a fifth voltage of first polarity and a fifth pulse width, which is a continuation of the fourth voltage pulse, with an absolute value larger than the absolute value of the third voltage.

[0330] The possible states of the memory cell MC in the modified semiconductor memory device of the fifth embodiment are the same as those of the modified semiconductor memory device of the first embodiment described with reference to Figure 8. Furthermore, the voltage pulses applied to the memory cell MC during the first write process, erase process, second write process, and suppression process in the control of the modified semiconductor memory device of the fifth embodiment are the same as those of the modified semiconductor memory device of the first embodiment.

[0331] In the modified semiconductor memory device of the fifth embodiment, similar to the modified semiconductor memory device of the first embodiment, a suppression process is performed before the second write process, thereby causing polarization reversal in all polarization domains of the memory cell MC. Therefore, imprinting of the memory cell MC is suppressed, and write or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including a 3D NAND flash memory 400, can be realized.

[0332] As described above, according to the fifth embodiment and its modifications, the imprinting of memory cells is suppressed, and a semiconductor memory device with superior characteristics can be realized.

[0333] (Sixth embodiment) The semiconductor memory device of the sixth embodiment includes a memory cell comprising a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer including a ferroelectric material provided between the first conductive layer and the second conductive layer; a first wiring electrically connected to the first conductive layer via the semiconductor layer; a second wiring electrically connected to the second conductive layer; and a control circuit for controlling the memory cell. The control circuit is capable of performing a first write operation to the memory cell. The first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the first wiring and the second wiring. The control circuit is capable of performing an erase operation to the memory cell. The erase operation involves applying a second voltage pulse having a second polarity opposite to the first polarity, and a second pulse width between the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell. The second write operation applies a third voltage pulse between the first and second wirings, having a third voltage of first polarity with an absolute value smaller than the absolute value of the first voltage and a third pulse width. The control circuit can determine whether the number of executions of the second write operation to the memory cell has reached a predetermined first number. If the control circuit determines that the number of executions has reached a predetermined first number, it can perform the first operation on the memory cell. The first operation applies a fifth voltage pulse between the first and second wirings, following the application of a fourth voltage pulse having a fourth voltage of first polarity with an absolute value larger than the absolute value of the third voltage and a fourth pulse width, and the application of a fourth voltage pulse having a fifth voltage of second polarity with an absolute value larger than the absolute value of the third voltage and a fifth pulse width.

[0334] The semiconductor memory device of the sixth embodiment differs from the semiconductor memory device of the fifth embodiment in that it performs a recovery process. Some descriptions that overlap with the fifth embodiment may be omitted below.

[0335] Figure 28 is a block diagram of a memory system including a semiconductor memory device according to the sixth embodiment. The memory system of the sixth embodiment includes, for example, FeRAM 700, a controller 800, and a host device 900. The semiconductor memory device of the fifth embodiment includes, for example, FeRAM 700 and a controller 800.

[0336] The peripheral circuitry 720 and controller 800 of the FeRAM 700 are an example of the control circuit of the sixth embodiment.

[0337] The processor 810 of the sixth embodiment differs from the processor 810 of the fifth embodiment in that it includes a judgment circuit 811.

[0338] The internal memory 820 stores, for example, the number of times a second write operation has been performed on each memory cell included in the FeRAM 700. The internal memory 820 also stores, for example, a predetermined first number of times the second write operation has been performed, which serves as a criterion for determining whether or not to perform a recovery operation. Based on the number of times the second write operation has been performed stored in the internal memory 820 and the predetermined first number of times the second write operation has been performed, the determination circuit 811 can determine whether or not the number of times the second write operation has been performed on the memory cells has reached a predetermined number.

[0339] The peripheral circuitry 720 and controller 800 of the FeRAM 700 can perform a recovery process on a specific memory cell when they determine that the number of times a second write operation has been performed on that specific memory cell has reached a predetermined first number of times. The recovery process is an example of the first process.

[0340] The possible states of the memory cell MC of the semiconductor memory device in the sixth embodiment are the same as those of the first embodiment described with reference to Figure 4.

[0341] The peripheral circuit 720 and controller 800 can, for example, perform a first write operation, an erase operation, a second write operation, and a recovery operation on any one memory cell MC selected from memory cells MCa to MCd. The first write operation, erase operation, and second write operation in the control of the semiconductor memory device of the sixth embodiment are the same as those of the semiconductor memory device of the fifth embodiment. Also, the voltage pulse applied to the memory cell MC in the recovery operation is the same as that of the semiconductor memory device of the second embodiment.

[0342] For example, when performing a recovery operation on a memory cell MCa, the first bit line BL1 is an example of the first wiring, and the first plate line PL1 is an example of the second wiring. The following explanation will use the case of performing a recovery operation on a memory cell MCa as an example.

[0343] The recovery process applies a first recovery voltage pulse RP1 and a second recovery voltage pulse RP2 between the first bit line BL1 and the first plate line PL1. The recovery process also applies the first recovery voltage pulse RP1 and the second recovery voltage pulse RP2 to the capacitor insulating layer 60 of the memory cell MCa.

[0344] The first recovery voltage pulse RP1 has a first recovery voltage Vrp1 of first polarity and a fourth pulse width w4. The first recovery voltage pulse RP1 is an example of a fourth voltage pulse. The first recovery voltage Vrp1 is an example of a fourth voltage.

[0345] The second recovery voltage pulse RP2 has a second recovery voltage Vrp2 of second polarity and a fifth pulse width w5. The second recovery voltage pulse RP2 is an example of the fifth voltage pulse. The second recovery voltage Vrp2 is an example of the fifth voltage.

[0346] For example, the first polarity is the polarity in which the first plate wire PL1 has a positive voltage relative to the first bit wire BL1, and the second polarity is the polarity in which the first plate wire PL1 has a negative voltage relative to the first bit wire BL1.

[0347] The semiconductor memory device of the sixth embodiment, similar to the second embodiment, performs a recovery process to restore the imprint of the memory cell MC when the second write process, which accelerates the imprinting of the memory cell MC, reaches a predetermined first number of times. Therefore, the imprint of the memory cell MC is effectively restored, and write or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including FeRAM 700, can be realized.

[0348] (modified version) A modified version of the semiconductor memory device of the sixth embodiment differs from the semiconductor memory device of the sixth embodiment in that the second writing process applies a third voltage pulse having a third voltage of second polarity and a third pulse width, with an absolute value smaller than the absolute value of the second voltage, between the first wiring and the second wiring, and the first process applies a fourth voltage pulse having a fourth voltage of second polarity and a fourth pulse width, with an absolute value larger than the absolute value of the third voltage, between the first wiring and the second wiring, followed by the application of a fifth voltage pulse having a fifth voltage of first polarity and a fifth pulse width, which is a continuation of the application of the fourth voltage pulse, with an absolute value larger than the absolute value of the third voltage.

[0349] The possible states of the memory cell MC in the modified semiconductor memory device of the sixth embodiment are the same as those of the modified first embodiment described with reference to Figure 8. Furthermore, the first write process, erase process, and second write process in the control of the modified semiconductor memory device of the sixth embodiment are the same as those of the modified fifth embodiment. Also, the voltage pulse applied to the memory cell MC during the recovery process is the same as that of the modified semiconductor memory device of the second embodiment.

[0350] A modification of the semiconductor memory device according to the sixth embodiment, similar to the modification of the second embodiment, performs a recovery process to restore the imprint of the memory cell MC when the second write process, which accelerates the imprinting of the memory cell MC, reaches a predetermined first number of times. Therefore, the imprint of the memory cell MC is effectively restored, and write failures or erase failures of the memory cell MC are suppressed. Thus, a semiconductor memory device with excellent characteristics, including FeRAM 700, can be realized.

[0351] As described above, according to the sixth embodiment and its modifications, the imprint of the memory cell is effectively recovered, and a semiconductor memory device with superior characteristics can be realized.

[0352] In the third and fourth embodiments, a structure in which the semiconductor layer 10 is surrounded by word lines WL was described as an example, but it is also possible to have a structure in which the semiconductor layer 10 is sandwiched between two divided word lines WL. In this structure, it is possible to double the number of memory cells in the stack 30.

[0353] Furthermore, although the third and fourth embodiments described an example of a structure in which one semiconductor layer 10 is provided in one memory hole, it is also possible to have a structure in which multiple semiconductor layers 10, divided into two or more, are provided in one memory hole. In this structure, it is possible to more than double the number of memory cells in the stacked body 30.

[0354] Furthermore, although the third and fourth embodiments were described using a three-dimensional NAND flash memory as an example, the NAND flash memory may also have a two-dimensional structure.

[0355] Furthermore, while the first and second embodiments described a two-dimensional NOR memory, the third and fourth embodiments described a three-dimensional NAND flash memory, and the fifth and sixth embodiments described FeRAM using a ferroelectric capacitor as examples, the present invention can also be applied to other semiconductor memory devices that use an insulating layer containing a ferroelectric material in the memory cell.

[0356] Furthermore, in the first to sixth embodiments, it is also possible to reverse the positive and negative directions of the first and second polarities.

[0357] Furthermore, although the first to sixth embodiments were described using the case where there is one intermediate state as an example, it is also possible to have a configuration in which there are multiple different intermediate states and the memory cell has four or more states.

[0358] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0359] Embodiments of the present invention include the following technical proposals.

[0360] (Technical proposal 1) A memory cell comprising a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric material provided between the semiconductor layer and the gate electrode layer, A first wiring and a second wiring electrically connected to the semiconductor layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, the erase process involves applying a second voltage pulse having a second voltage and a second pulse width having a second polarity opposite to the first polarity between the gate electrode layer and at least one of the first wiring and the second wiring, The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse having a third voltage of second polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the second voltage, between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing a first process on the memory cell that is contiguous with the second write process, before the second write process. The first process involves applying a fourth voltage pulse between the gate electrode layer and at least one of the first wiring and the second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of second polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of first polarity and a fifth pulse width, to at least one of the first wiring and the second wiring, in a semiconductor memory device.

[0361] (Technical proposal 2) The semiconductor memory device according to Technical Proposal 1, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the second voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the first voltage.

[0362] (Technical proposal 3) The semiconductor memory device according to Technical Proposal 1, wherein the fourth pulse width is greater than or equal to the third pulse width, and the fifth pulse width is greater than or equal to the third pulse width.

[0363] (Technical proposal 4) The semiconductor memory device according to Technical Proposal 1, wherein the gate insulating layer comprises at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

[0364] (Technical proposal 5) The semiconductor memory device according to Technical Proposal 4, wherein the gate insulating layer includes a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31).

[0365] (Technical proposal 6) A memory cell comprising a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric material provided between the semiconductor layer and the gate electrode layer, A first wiring and a second wiring electrically connected to the semiconductor layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, the erase process involves applying a second voltage pulse having a second voltage and a second pulse width having a second polarity opposite to the first polarity between the gate electrode layer and at least one of the first wiring and the second wiring, The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse having a third voltage of second polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the second voltage, between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of determining whether the number of times the second write operation to the memory cell has been performed has reached a predetermined first number of times. The control circuit can perform the first process on the memory cell when it determines that the number of executions has reached the predetermined first number. The first process involves applying a fourth voltage pulse between the gate electrode layer and at least one of the first wiring and the second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of second polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of first polarity and a fifth pulse width, to at least one of the first wiring and the second wiring, in a semiconductor memory device.

[0366] (Technical proposal 7) The semiconductor memory device according to Technical Proposal 6, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the second voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the first voltage.

[0367] (Technical proposal 8) The semiconductor memory device according to Technical Proposal 6, wherein the fourth pulse width is greater than or equal to the third pulse width, and the fifth pulse width is greater than or equal to the third pulse width.

[0368] (Technical proposal 9) The control circuit is capable of executing the first process multiple times in succession, as described in Technical Proposal 6, for the semiconductor memory device.

[0369] (Technical proposal 10) The semiconductor memory device according to Technical Proposal 6, wherein the control circuit can determine whether the number of consecutive executions of the second write operation to the memory cell has reached a predetermined first number.

[0370] (Technical proposal 11) The semiconductor memory device according to Technical Proposal 6, wherein the gate insulating layer comprises at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

[0371] (Technical proposal 12) The semiconductor memory device according to Technical Proposal 11, wherein the gate insulating layer includes a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31).

[0372] (Technical proposal 13) A first semiconductor layer extending in a first direction, A plurality of gate electrode layers stacked in the first direction, A first wiring electrically connected to the first semiconductor layer, A second wiring electrically connected to the first semiconductor layer, A plurality of first memory cells, wherein each first memory cell comprises a first semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the first semiconductor layer and the one gate electrode layer. A memory cell array including, The system comprises a control circuit for controlling the plurality of first memory cells, The control circuit is capable of performing a first write operation to one first memory cell selected from the plurality of first memory cells, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage and a first pulse width between one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase operation on one of the first memory cells, the erase operation involves applying a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width between one gate electrode layer of the one of the first memory cells and at least one of the first wiring and the second wiring, The control circuit is capable of performing a second write operation to the one first memory cell, the second write operation involves applying a third voltage pulse having a third voltage of second polarity and a third pulse width, which is smaller in absolute value than the absolute value of the second voltage, between the one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring. The control circuit is capable of performing a first process on one of the first memory cells, which is continuous with the second write process, before the second write process. The first process, in the second write process, applies a fourth voltage pulse having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of second polarity and a fourth pulse width, and a fifth voltage pulse that is continuous with the application of the fourth voltage pulse having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of first polarity and a fifth pulse width, between the gate electrode layer of one first memory cell and at least one of the first wiring and the second wiring, the first voltage.

[0373] (Technical proposal 14) The semiconductor memory device according to Technical Proposal 13, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the second voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the first voltage.

[0374] (Technical proposal 15) A first semiconductor layer extending in a first direction, A second semiconductor layer extending in the first direction, A plurality of gate electrode layers stacked in the first direction, A first wiring electrically connected to the first semiconductor layer and the second semiconductor layer, A second wiring electrically connected to the first semiconductor layer, A third wiring connected to the second semiconductor layer, A plurality of first memory cells, wherein each first memory cell comprises a first semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the first semiconductor layer and the one gate electrode layer. A plurality of second memory cells, wherein each second memory cell comprises a second semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the second semiconductor layer and the one gate electrode layer. A memory cell array including, The system comprises a plurality of first memory cells and a control circuit for controlling the plurality of second memory cells, The control circuit is capable of performing a first write operation on any one memory cell among the plurality of first memory cells and the plurality of second memory cells, wherein the first write operation, when the memory cell is one of the first memory cells, applies a first voltage pulse having a first polarity and a first pulse width between the gate electrode layer of the memory cell and at least one of the first wiring and the second wiring, and when the memory cell is one of the second memory cells, applies a first voltage pulse having a first polarity and a first pulse width between the gate electrode layer of the memory cell and at least one of the first wiring and the third wiring, The control circuit is capable of performing erase operations on the plurality of first memory cells and the plurality of second memory cells, and the erase operation involves applying a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width between the plurality of gate electrode layers and the first wiring, The control circuit is capable of performing a second write operation to one of the memory cells, the second write operation, if the memory cell is one of the first memory cells, applies a third voltage pulse having a third voltage of second polarity and a third pulse width, which is smaller in absolute value than the absolute value of the second voltage, between the gate electrode layer of the memory cell and at least one of the first wiring and the second wiring; the second write operation, if the memory cell is one of the second memory cells, applies a third voltage pulse having a third voltage of second polarity and a third pulse width, which is smaller in absolute value than the absolute value of the second voltage, between the gate electrode layer of the memory cell and at least one of the first wiring and the third wiring; The control circuit is capable of determining whether the number of times the second write operation has been performed on each of the plurality of first memory cells and the plurality of second memory cells has reached a predetermined first number of times. The control circuit can perform the first processing on the plurality of first memory cells and the plurality of second memory cells when it determines that the number of executions on any of the plurality of first memory cells and the plurality of second memory cells has reached a predetermined first number of executions. The first process involves applying a fourth voltage pulse between the plurality of gate electrode layers and the first wiring, the fourth voltage having a second polarity and a fourth pulse width, which has an absolute value greater than the absolute value of the third voltage, and a fifth voltage pulse that is continuous with the application of the fourth voltage pulse having a first polarity and a fifth pulse width, which has an absolute value greater than the absolute value of the third voltage.

[0375] (Technical proposal 16) The semiconductor memory device according to Technical Proposal 15, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the second voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the first voltage.

[0376] (Technical proposal 17) A memory cell comprising a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer containing a ferroelectric material provided between the first conductive layer and the second conductive layer, A first wiring electrically connected to the first conductive layer via the semiconductor layer, and a second wiring electrically connected to the second conductive layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, and the erase process involves applying a second voltage pulse having a second voltage and a second pulse width having a second polarity opposite to the first polarity between the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse between the first wiring and the second wiring, having a third voltage of second polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the second voltage. The control circuit is capable of performing a first process on the memory cell that is contiguous with the second write process, before the second write process. The first process involves applying a fourth voltage pulse between the first and second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of second polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of first polarity and a fifth pulse width, to the first wiring and the second wiring, in a semiconductor memory device.

[0377] (Technical proposal 18) The semiconductor memory device according to Technical Proposal 17, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the second voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the first voltage.

[0378] (Technical proposal 19) A memory cell comprising a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer containing a ferroelectric material provided between the first conductive layer and the second conductive layer, A first wiring electrically connected to the first conductive layer via the semiconductor layer, and a second wiring electrically connected to the second conductive layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, and the erase process involves applying a second voltage pulse having a second voltage and a second pulse width having a second polarity opposite to the first polarity between the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse between the first wiring and the second wiring, having a third voltage of second polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the second voltage. The control circuit is capable of determining whether the number of times the second write operation to the memory cell has been performed has reached a predetermined first number of times. The control circuit can perform the first process on the memory cell when it determines that the number of executions has reached the predetermined first number. The first process involves applying a fourth voltage pulse between the first and second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of second polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of first polarity and a fifth pulse width, to the first wiring and the second wiring, in a semiconductor memory device.

[0379] (Technical proposal 20) The semiconductor memory device according to Technical Proposal 19, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the second voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the first voltage. [Explanation of Symbols]

[0380] 10 Semiconductor Layers 10a First semiconductor layer 10b Second semiconductor layer 11 Gate Insulation Layer 21 Gate Insulation Layer 50 Semiconductor Layers 60 Capacitor insulating layer 61 First capacitor electrode (first conductive layer) 62 Second capacitor electrode (second conductive layer) 120 Peripheral circuits (control circuits) 200 Controller (control circuit) 410 memory cell array 420 Peripheral circuits (control circuits) 500 Controller (Control Circuit) 720 Peripheral circuits (control circuits) 800 Controller (Control Circuit) w1 First pulse width w2 Second pulse width w3 Third pulse width w4 4th pulse width w5 Fifth pulse width BL1 First bit line (first wiring, second wiring) BL3 Second bit line (third wiring) CSL Common Source Line (First Wiring) EP erase voltage pulse (second voltage pulse) MC memory cell MC1 First memory cell MC2 Second Memory Cell PL1 First plate wire (second wiring) RP1 First recovery voltage pulse (fourth voltage pulse) RP2 Second recovery voltage pulse (fifth voltage pulse) SL1 First source line (first wiring) SP1 First suppression voltage pulse (fourth voltage pulse) SP2 Second suppression voltage pulse (fifth voltage pulse) Vrp1 First recovery voltage (fourth voltage) Vrp2 Second recovery voltage (fifth voltage) Vsup1 First suppression voltage (fourth voltage) Vsup2 Second suppression voltage (fifth voltage) Vwrite1 First write voltage (first voltage) Vwrite2 Second write voltage (third voltage) Verase erase voltage (second voltage) WL Word line (gate electrode layer) WL1 First word line (gate electrode layer) WP1 First write voltage pulse (first voltage pulse) WP2 Second write voltage pulse (third voltage pulse)

Claims

1. A memory cell comprising a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric material provided between the semiconductor layer and the gate electrode layer, A first wiring and a second wiring electrically connected to the semiconductor layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, and the erase process involves applying a second voltage pulse having a second voltage and a second pulse width with a second polarity opposite to the first polarity between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse having a third voltage of first polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the first voltage, between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing a first process on the memory cell that is continuous with the second write process, before the second write process. The first process involves applying a fourth voltage pulse between the gate electrode layer and at least one of the first wiring and the second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of first polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of second polarity and a fifth pulse width, to at least one of the first wiring and the second wiring, in a semiconductor memory device.

2. The semiconductor memory device according to claim 1, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the first voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the second voltage.

3. The semiconductor memory device according to claim 1, wherein the fourth pulse width is greater than or equal to the third pulse width, and the fifth pulse width is greater than or equal to the third pulse width.

4. The semiconductor memory device according to claim 1, wherein the gate insulating layer comprises at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

5. The semiconductor memory device according to claim 4, wherein the gate insulating layer includes a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31).

6. A memory cell comprising a semiconductor layer, a gate electrode layer, and a gate insulating layer containing a ferroelectric material provided between the semiconductor layer and the gate electrode layer, A first wiring and a second wiring electrically connected to the semiconductor layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, and the erase process involves applying a second voltage pulse having a second voltage and a second pulse width with a second polarity opposite to the first polarity between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse having a third voltage of first polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the first voltage, between the gate electrode layer and at least one of the first wiring and the second wiring. The control circuit is capable of determining whether the number of times the second write operation to the memory cell has been performed has reached a predetermined first number of times. The control circuit can perform the first processing on the memory cell when it determines that the number of executions has reached the predetermined first number of times. The first process involves applying a fourth voltage pulse between the gate electrode layer and at least one of the first wiring and the second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of first polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of second polarity and a fifth pulse width, to at least one of the first wiring and the second wiring, in a semiconductor memory device.

7. The semiconductor memory device according to claim 6, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the first voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the second voltage.

8. The semiconductor memory device according to claim 6, wherein the fourth pulse width is greater than or equal to the third pulse width, and the fifth pulse width is greater than or equal to the third pulse width.

9. The semiconductor memory device according to claim 6, wherein the control circuit is capable of executing the first process multiple times in succession.

10. The semiconductor memory device according to claim 6, wherein the control circuit can determine whether the number of consecutive executions of the second write operation to the memory cell has reached a predetermined first number.

11. The semiconductor memory device according to claim 6, wherein the gate insulating layer comprises at least one element selected from the group consisting of hafnium (Hf) and zirconium (Zr), and oxygen.

12. The semiconductor memory device according to claim 11, wherein the gate insulating layer includes a crystal having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31).

13. A first semiconductor layer extending in a first direction, A plurality of gate electrode layers stacked in the first direction, A first wiring electrically connected to the first semiconductor layer, A second wiring electrically connected to the first semiconductor layer, A plurality of first memory cells, wherein each first memory cell includes a first semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the first semiconductor layer and the one gate electrode layer. A memory cell array including, The system comprises a control circuit for controlling the plurality of first memory cells, The control circuit is capable of performing a first write operation to one first memory cell selected from the plurality of first memory cells, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage and a first pulse width between one gate electrode layer of the one first memory cell and at least one of the first wiring and the second wiring, The control circuit is capable of performing an erase process on one of the first memory cells, the erase process involves applying a second voltage pulse having a second voltage and a second pulse width with a second polarity opposite to the first polarity between one gate electrode layer of the one of the first memory cells and at least one of the first wiring and the second wiring, The control circuit is capable of performing a second write operation to one of the first memory cells, the second write operation involves applying a third voltage pulse having a third voltage of first polarity and a third pulse width, which is smaller in absolute value than the absolute value of the first voltage, between one gate electrode layer of the one of the first memory cells and at least one of the first wiring and the second wiring. The control circuit is capable of performing a first process on one first memory cell that is continuous with the second write process, before the second write process. The first process involves applying a fourth voltage pulse having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of first polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of second polarity and a fifth pulse width, between the gate electrode layer of one first memory cell and at least one of the first wiring and the second wiring, the first voltage pulse.

14. The semiconductor memory device according to claim 13, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the first voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the second voltage.

15. A first semiconductor layer extending in a first direction, A second semiconductor layer extending in the first direction, A plurality of gate electrode layers stacked in the first direction, A first wiring electrically connected to the first semiconductor layer and the second semiconductor layer, A second wiring electrically connected to the first semiconductor layer, A third wiring connected to the second semiconductor layer, A plurality of first memory cells, wherein each first memory cell includes a first semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the first semiconductor layer and the one gate electrode layer. A plurality of second memory cells, wherein each second memory cell includes a second semiconductor layer, one gate electrode layer among the plurality of gate electrode layers, and a gate insulating layer containing a ferroelectric material provided between the second semiconductor layer and the one gate electrode layer. A memory cell array including, The system comprises a plurality of first memory cells and a control circuit for controlling the plurality of second memory cells, The control circuit is capable of performing a first write operation on any one memory cell among the plurality of first memory cells and the plurality of second memory cells, wherein, if the memory cell is one of the first memory cells, the first write operation applies a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer of the memory cell and at least one of the first wiring and the second wiring, and if the memory cell is one of the second memory cells, the first write operation applies a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the gate electrode layer of the memory cell and at least one of the first wiring and the third wiring, The control circuit is capable of performing erase operations on the plurality of first memory cells and the plurality of second memory cells, and the erase operation involves applying a second voltage pulse having a second voltage with a second polarity opposite to the first polarity and a second pulse width between the plurality of gate electrode layers and the first wiring, The control circuit is capable of performing a second write operation to one of the memory cells, the second write operation, when the one memory cell is one of the first memory cells, applies a third voltage pulse having a third voltage of a first polarity and a third pulse width, which is smaller in absolute value than the absolute value of the first voltage, between the one gate electrode layer of the one memory cell and at least one of the first wiring and the second wiring; the second write operation, when the one memory cell is one of the second memory cells, applies a third voltage pulse having a third voltage of a first polarity and a third pulse width, which is smaller in absolute value than the absolute value of the first voltage, between the one gate electrode layer of the one memory cell and at least one of the first wiring and the third wiring; The control circuit is capable of determining whether the number of times the second write operation has been performed on each of the plurality of first memory cells and the plurality of second memory cells has reached a predetermined first number of times. The control circuit can perform the first processing on the plurality of first memory cells and the plurality of second memory cells when it determines that the number of executions on any of the plurality of first memory cells and the plurality of second memory cells has reached a predetermined first number of executions. The first process is, A semiconductor memory device wherein a fourth voltage pulse having a fourth voltage and a fourth pulse width of first polarity, and having an absolute value greater than the absolute value of the third voltage, is applied between the plurality of gate electrode layers and the first wiring, and a fifth voltage pulse is applied consecutively to the application of the fourth voltage pulse having a fifth voltage and a fifth pulse width of second polarity, and having an absolute value greater than the absolute value of the third voltage.

16. The semiconductor memory device according to claim 15, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the first voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the second voltage.

17. A memory cell comprising a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer containing a ferroelectric material provided between the first conductive layer and the second conductive layer, A first wiring electrically connected to the first conductive layer via the semiconductor layer, and a second wiring electrically connected to the second conductive layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, and the erase process involves applying a second voltage pulse having a second voltage and a second pulse width having a second polarity opposite to the first polarity between the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse between the first wiring and the second wiring, having a third voltage of first polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the first voltage. The control circuit is capable of performing a first process on the memory cell that is continuous with the second write process, before the second write process. The first process involves applying a fourth voltage pulse between the first and second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of first polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of second polarity and a fifth pulse width, to the first wiring and the second wiring, respectively, in a semiconductor memory device.

18. The semiconductor memory device according to claim 17, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the first voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the second voltage.

19. A memory cell comprising a semiconductor layer, a gate electrode layer, a gate insulating layer provided between the semiconductor layer and the gate electrode layer, a first conductive layer electrically connected to the semiconductor layer, a second conductive layer, and a capacitor insulating layer containing a ferroelectric material provided between the first conductive layer and the second conductive layer, A first wiring electrically connected to the first conductive layer via the semiconductor layer, and a second wiring electrically connected to the second conductive layer, The system comprises a control circuit for controlling the memory cell, The control circuit is capable of performing a first write operation to the memory cell, the first write operation involves applying a first voltage pulse having a first polarity, a first voltage, and a first pulse width between the first wiring and the second wiring. The control circuit is capable of performing an erase process on the memory cell, and the erase process involves applying a second voltage pulse having a second voltage and a second pulse width having a second polarity opposite to the first polarity between the first wiring and the second wiring. The control circuit is capable of performing a second write operation to the memory cell, the second write operation involves applying a third voltage pulse between the first wiring and the second wiring, having a third voltage of first polarity and a third pulse width, the absolute value of which is smaller than the absolute value of the first voltage. The control circuit is capable of determining whether the number of times the second write operation to the memory cell has been performed has reached a predetermined first number of times. The control circuit can perform the first processing on the memory cell when it determines that the number of executions has reached the predetermined first number of times. The first process involves applying a fourth voltage pulse between the first and second wiring, having an absolute value greater than the absolute value of the third voltage and having a fourth voltage of first polarity and a fourth pulse width, and applying a fifth voltage pulse that is continuous with the application of the fourth voltage pulse, having an absolute value greater than the absolute value of the third voltage and having a fifth voltage of second polarity and a fifth pulse width, to the first wiring and the second wiring, respectively, in a semiconductor memory device.

20. The semiconductor memory device according to claim 19, wherein the absolute value of the fourth voltage is greater than or equal to the absolute value of the first voltage, and the absolute value of the fifth voltage is greater than or equal to the absolute value of the second voltage.

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