Semiconductor structure and method for manufacturing the same

Abstract

This invention provides a semiconductor structure and a method for manufacturing the same. [Solution] The semiconductor structure includes a device region, a junction termination region, a street region, and a protective layer. The junction termination region is provided to surround the outer periphery of the device region and has a plurality of protective rings. The protective rings are provided within the junction termination region and surround the outer periphery of the device region. The street region is provided to surround the outer periphery of the junction termination region. The protective layer covers the junction termination region and the street region. The protective layer substantially prevents arc generation in the street region during high-voltage testing.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a power semiconductor device.

Background Art

[0002] A silicon carbide (SiC) power semiconductor device is a high-performance power device manufactured based on a silicon carbide material. Compared with conventional silicon (Si) semiconductors, SiC power semiconductor devices have a higher breakdown electric field strength, thermal conductivity, and electron saturation velocity. Therefore, SiC power semiconductors are significantly superior in high-power, high-temperature, and high-frequency applications.

[0003] In the manufacture of SiC power semiconductor devices, usually, a chip probing (CP) test is performed, especially at a high voltage (for example, 1200V, 1700V, or 3300V, etc.). However, in the current SiC semiconductor structure, during the CP test, arcing occurs at the edge of the chip. Arcing may interfere with the test or damage the device. The area indicated by the dashed line in FIG. 1 is the damaged area at the edge of the chip.

[0004] Arcing is caused by the electric field becoming excessively strong under high voltage, resulting in dielectric breakdown in air or a medium and instantaneous discharge. To avoid this phenomenon, the following preventive measures are taken in the conventional CP test. The first preventive measure is to use isolation oil. Cover the test area of the probe device with isolation oil to increase the dielectric strength and reduce the concentration of the electric field, thereby effectively preventing arc discharge in the air. However, in order to avoid contamination of the test equipment and the wafer surface, careful cleaning is required after using the isolation oil. The second precaution is to create a sealed test chamber inside the prober and fill the test chamber with nitrogen (N2). By utilizing the inert gas properties of nitrogen, the probability of arc formation is effectively reduced. However, this method requires the creation of a separate sealed space within the apparatus and cannot be applied to all test environments. The third precaution is to install a gas flow path in the probe card and introduce clean dry air (CDA). Dry, clean air is used to maintain low humidity in the probe card and test environment, preventing arcing caused by moisture and impurities. However, compared to the two preventative measures mentioned above, the CDA probe card has a weaker arc suppression effect under extremely high voltages. Therefore, reducing arc generation during the CP testing process of power semiconductor devices is currently an urgent issue that the industry needs to address. [Overview of the Initiative]

[0005] The main objective of the present invention is to provide an innovative semiconductor structure and a method for manufacturing the same that prevents damage to the element caused by arc generation in the edge region of the structure during high-voltage testing.

[0006] To achieve the above objective, the present invention provides a semiconductor structure comprising a device region, a junction termination region, a street region, and a protective layer. The junction termination region is provided so as to surround the outer periphery of the device region and has a plurality of protective rings. The protective rings are provided within the junction termination region and so as to surround the outer periphery of the device region. The street region is provided so as to surround the outer periphery of the junction termination region. The protective layer covers the junction termination region and the street region. The protective layer substantially prevents arc generation in the street region during high-voltage testing.

[0007] In embodiments of the semiconductor structure of the present invention, the protective layer is one or a combination selected from the group consisting of silicon dioxide, silicon nitride, and photoresist (PR) materials.

[0008] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further includes a chip edge region provided to surround the area between the junction termination region and the street region. The protective layer covers the junction termination region, the chip edge region, and the street region to prevent arcing in the street region during high-voltage testing.

[0009] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further includes an interlayer dielectric layer provided between a protective layer and a junction termination region. The interlayer dielectric layer covers the junction termination region and a portion of the chip edge region.

[0010] In an embodiment of the semiconductor structure of the present invention, the interlayer dielectric layer covers the junction termination region, the chip edge region, and the street region.

[0011] In an embodiment of the semiconductor structure of the present invention, each protective ring is a heavily doped region.

[0012] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further includes a polysilicon layer provided between the interlayer dielectric layer and the junction termination region, thereby improving the breakdown voltage of the semiconductor structure.

[0013] To achieve the above objective, the present invention provides a semiconductor structure comprising a silicon carbide substrate, an epitaxial layer, at least one active element, a plurality of protective rings, and a protective layer. The silicon carbide substrate is divided into a device region, a junction termination region, and a street region from the inside out. The epitaxial layer covers the silicon carbide substrate. The active element is provided within the epitaxial layer of the device region. The protective ring is provided within the epitaxial layer of the junction termination region and surrounds the outer periphery of the device region. The protective layer covers the epitaxial layers of the junction termination region and the street region, substantially preventing arc generation in the street region during high-voltage testing.

[0014] To achieve the above objective, the present invention provides a method for manufacturing a semiconductor structure. The manufacturing method includes the steps of: preparing a silicon carbide substrate divided into a device region, a junction termination region, and a street region from the inside out; forming an epitaxial layer covering the silicon carbide substrate; forming a plurality of protective rings provided within the epitaxial layer of the junction termination region and surrounding the outer periphery of the device region; and forming a protective layer covering the epitaxial layers of the junction termination region and the street region. The protective layer substantially prevents arc generation in the street region during high-voltage testing.

[0015] In an embodiment of the semiconductor structure manufacturing method of the present invention, the step of forming a protective layer is a step of forming a protective layer using one or a combination selected from the group consisting of silicon dioxide, silicon nitride, and photoresist material.

[0016] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the process further includes a step of forming a chip edge region. The aforementioned chip edge region is provided so as to surround the area between the joint end region and the street region. The protective layer covers the joint termination region, the tip edge region, and the street region, and prevents arc generation in the street region during high-voltage testing.

[0017] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method further includes a step of forming an interlayer dielectric layer, The interlayer dielectric layer is provided between a protective layer and a junction termination region, and covers the junction termination region and a part of the chip edge region.

[0018] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method further includes a step of forming an interlayer dielectric layer, The interlayer dielectric layer is provided between a protective layer and a junction termination region, and covers the junction termination region, the chip edge region, and the street region.

[0019] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method further includes a step of forming a polysilicon layer, The polysilicon layer is provided between the interlayer dielectric layer and the junction termination region to improve the breakdown voltage of the semiconductor structure.

[0020] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method further includes a step of forming at least one active element, The active element is provided in the epitaxial layer of the device region.

[0021] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below.

Brief Description of the Drawings

[0022] [Figure 1] An enlarged view showing a state where a part of the edge of a conventional power semiconductor chip is damaged by an arc [Figure 2] A cross-sectional view of a semiconductor structure in the manufacturing process of an embodiment of the present invention [Figure 3] A cross-sectional view of a semiconductor structure in the manufacturing process of an embodiment of the present invention [Figure 4] A cross-sectional view of a semiconductor structure in the manufacturing process of an embodiment of the present invention [Figure 5] A cross-sectional view of a semiconductor structure in the manufacturing process of an embodiment of the present invention [Figure 6] Cross-sectional view of a semiconductor structure according to another embodiment of the present invention [Figure 7] Flowchart of the manufacturing process of a semiconductor structure according to an embodiment of the present invention [Modes for carrying out the invention]

[0023] The present invention will be described below through examples. It should be noted that the embodiments of the present invention are merely examples of embodiments and are not intended to limit the present invention to the environments, uses, or specific embodiments described in the embodiments. Therefore, the description of the examples is for illustrative purposes only, and does not limit the present invention. In the embodiments and drawings, components not directly related to the present invention are omitted and not shown. The dimensional relationships of each component in the drawings are for the purpose of facilitating understanding and do not limit the actual dimensions.

[0024] The following explanation will be given with reference to Figures 2 through 5. A method for manufacturing a semiconductor structure according to an embodiment of the present invention, particularly a method for manufacturing a power semiconductor device, will be described below. The present invention will be explained below using silicon carbide power semiconductor devices as an example. First, prepare the silicon carbide substrate 10. The silicon carbide substrate 10 is of the first conductivity type (e.g., N-type). The silicon carbide substrate 10 is divided into four regions from the inside out: device region A, junction termination region B, chip edge region C, and street region D. Device region A is the core region within the chip that includes active elements. The junction termination region B includes an edge termination structure and is a region designed to avoid excessive electric field concentration at the edges of the power semiconductor device. Street area D is a street located between each chip on the wafer, and is an area for forming individual chips by wafer division. The chip edge region C is the region between the chip's bonding termination region B and the street region D. In the subsequent manufacturing process of the power element, different elements are formed in different regions, as described below.

[0025] Next, an epitaxial layer 20 is formed on the silicon carbide substrate 10, covering the silicon carbide substrate 10. In a specific embodiment, the epitaxial layer 20 is of the first conductivity type. Furthermore, in device region A, at least one active element 30 is formed within the epitaxial layer 20. Note that the active element 30 shown in the figure is for illustrative purposes only and is not limited to this. The active element 30 may be a metal oxide semiconductor field-effect transistor (MOSFET), or other types of elements, such as an insulated gate bipolar transistor (IGBT), depending on the actual requirements.

[0026] Next, a plurality of protective rings 40 are formed within the epitaxial layer 20 of the junction termination region B, surrounding the outer periphery of the active element 30 in the device region A. The protective ring forms multiple P-type or N-type heavily doped regions on the outer surface region of the silicon carbide substrate 10 by doping techniques (such as ion implantation or diffusion). In this embodiment, the protective ring 40 is of the second conductivity type (P type), which is opposite to the first conductivity type. The electric field at the edge of a power semiconductor chip is very strong, making it prone to causing damage to the edge. Therefore, by using different doping concentrations and widths of impurities, a transition region can be formed around the protective ring where the electric field strength gradually changes. This can alleviate electric field concentration on the surface of power semiconductors and suppress damage. This effectively prevents electric field concentration at the junction edge under high voltage, preventing a decrease in breakdown voltage and damage to the element, thereby improving the reliability and service life of the element.

[0027] Next, as shown in Figure 3, a thin-film process is performed on the surface of the silicon carbide substrate 10 to form a polycrystalline silicon (Poly) layer 50 and an interlayer dielectric (ILD) layer 60. The polysilicon layer 50 and the interlayer dielectric layer 60 are patterned by etching. The patterned polysilicon layer 50 is provided on the surface of the epitaxial layer 20 within the junction termination region B and is covered by the patterned interlayer dielectric layer 60. In particular, the patterned polysilicon layer 50 is positioned above the protective ring 40 and electrically connected to an appropriate bias voltage, thereby generating a field plate electric field. This structure allows for the control and optimization of the surface electric field gradient, suppressing a rapid increase in the electric field at the junction end and improving the breakdown voltage of the semiconductor structure. On the other hand, in this embodiment, the patterned interlayer dielectric layer 60 is left mainly only on the junction termination region B, while the interlayer dielectric layer 60 on the chip edge region C and the street region D is substantially completely removed by etching.

[0028] Next, as shown in Figure 4, the device is subjected to a metal wiring process to form a patterned metal layer 70 in a portion of the device region A and the bonding termination region B. The metal layer 70 includes the active element 30, the upper electrode of the polysilicon layer 50, and the lower electrode formed on the back surface of the silicon carbide substrate 10. Next, as shown in Figure 5, a dielectric layer deposition process is performed to form a protective layer 80 in the junction termination region B, the chip edge region C, and the street region D. The protective layer 80 covers a portion of the metal layer 70, a portion of the interlayer dielectric layer 60, and a portion of the exposed epitaxial layer 20, respectively. The materials for the protective layer 80 and the interlayer dielectric layer 60 are one or a combination selected from the group consisting of silicon dioxide, silicon nitride, and photoresist (PR) materials. Compared to conventional power semiconductor structures, the semiconductor structure of the present invention has insulating protection by a protective layer 80 in the chip edge region C and street region D at the edge of the chip. This not only reduces electric field concentration phenomena at the edge but also effectively suppresses the possibility of arc discharge during high-voltage testing.

[0029] Figure 6 shows a semiconductor structure in another embodiment of the present invention. Unlike the previously described embodiment, this semiconductor structure involves two dielectric layer deposition processes: an interlayer dielectric layer 60 and a protective layer 80. After these processes, the interlayer dielectric layer 60 and the protective layer 80 completely cover the junction termination region B, the chip edge region C, and the street region D. This achieves higher dielectric strength and superior insulation, reduces electric field concentration at the edges, and effectively prevents arc discharge in the air, allowing it to withstand higher voltages and prevent dielectric breakdown. Therefore, the semiconductor structures of the present invention shown in Figure 5 or Figure 6 can effectively suppress the occurrence of arc discharge, prevent damage to the device, and improve the reliability of the device.

[0030] Figure 7 is a flowchart of the manufacturing process for the semiconductor structure of the present invention. First, in step S01, a silicon carbide substrate is prepared. The silicon carbide substrate is divided into a device region, a junction termination region, and a street region, starting from the inside out. Next, in step S02, an epitaxial layer is formed covering the silicon carbide substrate. Next, in step S03, multiple protective rings are formed. These protective rings are provided within the epitaxial layer of the bonding termination region and are positioned to surround the outer periphery of the device region. Finally, in step S04, a protective layer is formed. The protective layer covers the epitaxial layer in the joint termination region and the street region, substantially preventing damage caused by arcing in the street region during high-voltage testing. The technical details of the other elements are as described above and will not be explained again here.

[0031] The above-described embodiments illustrate embodiments of the present invention and describe the characteristic configuration of the present invention. The present invention is not limited to the embodiments described above. Modifications or equal arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of this invention shall be based on the scope of the patent application. [Explanation of Symbols]

[0032] 10 Silicon carbide substrate 20 Epitaxial Layer 30 Active elements 40 protective rings 50 Polysilicon Layers 60 Interlayer Dielectric Layers 70 metal layer 80 protective layer A device area B Junction termination area C tip edge region D Street Area

Claims

1. It is a semiconductor structure, Device area and A bonding termination region provided so as to surround the outer periphery of the device region, comprising a plurality of protective rings arranged within the bonding termination region and provided so as to surround the outer periphery of the device region, A street area is provided so as to surround the outer periphery of the aforementioned joint termination region, A semiconductor structure comprising a protective layer that covers the junction termination region and the street region, substantially preventing the generation of arcs in the street region during high-voltage testing.

2. The semiconductor structure according to claim 1, characterized in that the protective layer is one or a combination selected from the group consisting of silicon dioxide, silicon nitride, and photoresist (PR) materials.

3. It further includes a tip edge region provided so as to surround the area between the joint termination region and the street region, The semiconductor structure according to claim 1, characterized in that the protective layer covers the junction termination region, the chip edge region, and the street region, and prevents arc generation in the street region during high-voltage testing.

4. The material further includes an interlayer dielectric layer provided between the protective layer and the bonding termination region, The semiconductor structure according to claim 3, characterized in that the interlayer dielectric layer covers a portion of the junction termination region and the chip edge region.

5. The semiconductor structure according to claim 4, characterized in that the interlayer dielectric layer covers the junction termination region, the chip edge region, and the street region.

6. The semiconductor structure according to claim 1, characterized in that each of the aforementioned protective rings is a heavily doped region.

7. The semiconductor structure according to claim 4, further comprising a polysilicon layer provided between the interlayer dielectric layer and the junction termination region, thereby improving the breakdown voltage of the semiconductor structure.

8. It is a semiconductor structure, A silicon carbide substrate divided into a device region, a junction termination region, and a street region from the inside out, The epitaxial layer covering the silicon carbide substrate, An active element provided within the epitaxial layer of the device region, A plurality of protective rings are provided within the epitaxial layer of the bonding termination region and are provided so as to surround the outer periphery of the device region, A semiconductor structure comprising a protective layer that covers the epitaxial layer in the junction termination region and the street region, substantially preventing the generation of an arc in the street region during high-voltage testing.

9. The semiconductor structure according to claim 8, characterized in that the protective layer is one or a combination selected from the group consisting of silicon dioxide, silicon nitride, and photoresist materials.

10. The silicon carbide substrate further includes a chip edge region provided so as to surround the area between the bonding termination region and the street region, The semiconductor structure according to claim 8, characterized in that the protective layer covers the junction termination region, the chip edge region, and the street region, and prevents arcing in the street region during high-voltage testing.

11. The material further includes an interlayer dielectric layer provided between the protective layer and the bonding termination region, The semiconductor structure according to claim 10, characterized in that the interlayer dielectric layer covers a portion of the junction termination region and the chip edge region.

12. The semiconductor structure according to claim 11, characterized in that the interlayer dielectric layer covers the junction termination region, the chip edge region, and the street region.

13. The semiconductor structure according to claim 8, characterized in that each of the aforementioned protective rings is a heavily doped region.

14. A method for manufacturing a semiconductor structure, A process of preparing a silicon carbide substrate divided into a device region, a bonding termination region, and a street region from the inside out, A step of forming an epitaxial layer covering the silicon carbide substrate, A step of forming a plurality of protective rings provided within the epitaxial layer of the bonding termination region and provided so as to surround the outer periphery of the device region, The step includes forming a protective layer that covers the epitaxial layer in the bonding end region and the street region, A method for manufacturing a semiconductor structure, wherein the protective layer substantially prevents arc generation in the street region during high-voltage testing.

15. The manufacturing method according to claim 14, characterized in that the step of forming the protective layer is a step of forming the protective layer using one or a combination selected from the group consisting of silicon dioxide, silicon nitride, and photoresist material.

16. The process further includes the step of forming a chip edge region, The chip edge region is provided so as to surround the area between the joint end region and the street region. The manufacturing method according to claim 14, characterized in that the protective layer covers the joint termination region, the tip edge region, and the street region, and prevents arc generation in the street region during high-voltage testing.

17. The process further includes the step of forming an interlayer dielectric layer, The manufacturing method according to claim 16, characterized in that the interlayer dielectric layer is provided between the protective layer and the junction termination region and covers a portion of the junction termination region and the chip edge region.

18. The process further includes the step of forming an interlayer dielectric layer, The manufacturing method according to claim 16, characterized in that the interlayer dielectric layer is provided between the protective layer and the junction termination region and covers the junction termination region, the chip edge region, and the street region.

19. The process further includes a step of forming a polysilicon layer, The manufacturing method according to claim 17, characterized in that the polysilicon layer is provided between the interlayer dielectric layer and the junction termination region to improve the breakdown voltage of the semiconductor structure.

20. The manufacturing method according to claim 14, further comprising the step of forming at least one active element provided in the epitaxial layer of the device region.

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