Substrate for mounting semiconductor devices

Abstract

This invention provides a technology to improve the heat resistance of the insulating layer in a substrate for mounting semiconductor devices. [Solution] The substrate for mounting semiconductor elements comprises a base material, electrodes connected to the semiconductor elements, and an insulating layer disposed between the base material and the electrodes, wherein the insulating layer has an insulating film with a Knoop hardness of 147 GPa HK 0.4903 N or higher.

Description

Technical Field

[0001] The present invention relates to a substrate for mounting semiconductor elements.

[0002] Conventionally, a substrate for mounting semiconductor elements having electrodes connected to semiconductor elements has been known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, even with the prior art such as Patent Document 1, there was still room for improvement in the technology for improving the heat resistance of the insulating layer in the substrate for mounting semiconductor elements.

[0005] An object of the present invention is to provide a technology for improving the heat resistance of an insulating layer in a substrate for mounting semiconductor elements.

Means for Solving the Problems

[0006] The present invention has been made to solve at least a part of the above problems and can be realized in the following forms.

[0007] (1) According to one aspect of the present invention, a substrate for mounting semiconductor elements is provided. This substrate for mounting semiconductor elements includes a base material, an electrode connected to a semiconductor element, and an insulating layer disposed between the base material and the electrode, and the insulating layer has an insulating film having a Knoop hardness of 147 GPa HK0.4903N or more.

[0008] According to this configuration, the insulating layer has an insulating film with a Knoop hardness of 147 GPa HK 0.4903 N or higher. This improves resistance to thermal stress generated in the insulating layer due to temperature changes during the manufacturing of substrates for mounting semiconductor devices, for example, thereby suppressing defects such as cracks in the insulating layer. Therefore, the heat resistance of the insulating layer can be improved.

[0009] (2) In the semiconductor device mounting substrate of the above form, the insulating layer comprises a first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film, wherein the first insulating film and the second insulating film may have the same composition. According to this configuration, the insulating layer comprises a first insulating film and a second insulating film having a Knoop hardness lower than that of the first insulating film. Since the first insulating film and the second insulating film have the same composition, when forming the insulating layer in the manufacturing of the semiconductor device mounting substrate, the material used when forming the first insulating film and the material used when forming the second insulating film are basically the same. As a result, the time required to switch materials when forming the insulating layer is eliminated, and the time required to form the insulating layer can be shortened. Therefore, the production efficiency of the semiconductor device mounting substrate can be improved.

[0010] (3) In the semiconductor element mounting substrate of the above form, the insulating layer comprises a first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film, wherein the first insulating film may be positioned on the substrate side of the insulating layer than the second insulating film. With this configuration, the insulating layer comprises a first insulating film and a second insulating film having a Knoop hardness lower than that of the first insulating film. In this way, by making a part of the insulating layer a second insulating film with a relatively low Knoop hardness, it is possible to suppress warping of the semiconductor element mounting substrate while maintaining the overall thickness of the insulating layer.

[0011] (4) In the semiconductor element mounting substrate of the above form, the insulating layer comprises a first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or more, and a second insulating film having a Knoop hardness lower than that of the first insulating film, wherein the second insulating film may be positioned on the substrate side of the insulating layer than the first insulating film. According to this configuration, the insulating layer comprises a first insulating film and a second insulating film having a Knoop hardness lower than that of the first insulating film. In the insulating layer, the second insulating film is positioned on the substrate side of the first insulating film. By positioning the second insulating film, which has a relatively low Knoop hardness, on the substrate side in this way, stress can be relieved so that thermal stress generated in the substrate is not transmitted to the first insulating film, which has a relatively high Knoop hardness. This suppresses the occurrence of defects such as cracks in the insulating layer, and thus improves the heat resistance of the insulating layer.

[0012] (5) In the semiconductor element mounting substrate of the above configuration, the insulating layer may be formed of aluminum nitride. With this configuration, the aluminum nitride forming the insulating layer has relatively high thermal conductivity and relatively high electrical insulation properties. This allows for efficient dissipation of heat generated in the semiconductor element connected to the electrode via the substrate, while maintaining insulation between the electrode and the substrate.

[0013] (6) In the semiconductor element mounting substrate of the above configuration, the substrate may be made of a material mainly composed of copper or aluminum. With this configuration, the substrate is made of copper or aluminum, which have relatively high thermal conductivity. This makes it possible to efficiently dissipate the heat generated in the semiconductor element connected to the electrode through the substrate.

[0014] (7) The semiconductor element mounting substrate of the above configuration may further include an adhesion layer disposed between the substrate and the insulating layer. With this configuration, an adhesion layer is formed between the substrate and the insulating layer to improve the adhesion between the substrate and the insulating layer. This improves resistance to stress caused by differences in thermal expansion between the substrate and the insulating layer due to temperature changes, for example, and thus suppresses the occurrence of cracks in the insulating layer. Therefore, the heat resistance of the insulating layer can be further improved.

[0015] Furthermore, the present invention can be realized in various forms, for example, in the form of a substrate having an insulating layer, a product including a substrate for mounting semiconductor elements, a semiconductor package including a substrate for mounting semiconductor elements, a method for manufacturing the substrate for mounting semiconductor elements and the semiconductor package. [Brief explanation of the drawing]

[0016] [Figure 1] This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the first embodiment. [Figure 2] Figure 1 illustrates the results of the evaluation test regarding bias voltage. [Figure 3] This is the second figure illustrating the results of the evaluation test regarding bias voltage. [Figure 4] This is the third figure illustrating the results of the evaluation test regarding bias voltage. [Figure 5] This is the fourth figure illustrating the results of the evaluation test regarding bias voltage. [Figure 6] This is the fifth figure illustrating the results of the evaluation test regarding bias voltage. [Figure 7] This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the second embodiment. [Figure 8] This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the third embodiment. [Figure 9] This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the fourth embodiment. [Modes for carrying out the invention]

[0017] <First Embodiment> FIG. 1 is a schematic cross-sectional view of a substrate 1 for mounting a semiconductor element according to the first embodiment. The substrate 1 for mounting a semiconductor element according to the present embodiment supports an optical semiconductor such as a light-emitting diode (LED: Light Emitting Diode) or a semiconductor laser (LD: Laser Diode) as the semiconductor element 5 via an electrode 40, and functions as a heat dissipation substrate that releases heat generated during light emission to the outside. The substrate 1 for mounting a semiconductor element includes a base material 10, an adhesion layer 20, an insulating layer 30, and an electrode 40. In addition, in FIG. 1, the relationship between the thicknesses of the base material 10, the adhesion layer 20, the insulating layer 30, and the electrode 40 is illustrated to be different from the actual thickness relationship for convenience of explanation.

[0018] The base material 10 is a member having a flat plate shape and serves as a base of the substrate 1 for mounting a semiconductor element. In the present embodiment, the thickness of the base material 10 is, for example, 1 mm. The base material 10 is made of metal. In the present embodiment, the base material 10 is made of copper (Cu). The base material 10 may be formed of a material mainly composed of copper, aluminum (Al), or a material mainly composed of aluminum. Here, the “main component” refers to a component having a mass percentage greater than 50% in the target material. The base material 10 may be made of an alloy of copper and aluminum. By forming the base material 10 of these metals, heat generated in the semiconductor element 5 can be efficiently released to the outside through the base material 10.

[0019] The adhesion layer 20 is disposed between the base material 10 and the insulating layer 30. In the present embodiment, the adhesion layer 20 is made of titanium (Ti). The thickness of the adhesion layer 20 is, for example, 0.5 μm. The adhesion layer 20 adheres the base material 10 and the insulating layer 30 and suppresses the occurrence of cracks in the insulating layer 30 due to the difference in the coefficient of thermal expansion between the base material 10 and the insulating layer 30. The material forming the adhesion layer 20 is not limited to titanium, and may be chromium (Cr), molybdenum (Mo), copper, etc. having adhesion to both the insulating layer and the base material. Note that it is desirable that the material forming the adhesion layer 20 has a value of the coefficient of thermal expansion between the value of the coefficient of thermal expansion of the material forming the base material 10 and the value of the coefficient of thermal expansion of the material forming the insulating layer 30.

[0020] The insulating layer 30 is disposed between the base material 10 and the electrode 40, more specifically, between the adhesion layer 20 and the electrode 40. The insulating layer 30 has a single-layer structure formed of aluminum nitride (AlN). The thickness of the insulating layer 30 is 3 to 4 μm, and the thickness of the insulating layer 30 in the present embodiment is 3.4 μm. The insulating layer 30 insulates the base material 10 made of metal and the electrode 40. Note that the material forming the insulating layer 30 is not limited to aluminum nitride, and may be silicon nitride (SiN).

[0021] The insulating layer 30 in the present embodiment has a Knoop hardness of 147 GPa HK0.4903N (= 1500 HK0.05) or more. That is, it can be said that the insulating layer 30 has an insulating film with a Knoop hardness of 147 GPa HK0.4903N or more. The insulating layer 30 in the present embodiment has a Knoop hardness of 233.4 GPa HK0.4903N (= 2380 HK0.05), and particularly, in order to improve the heat resistance, it has a Knoop hardness of 195.7 GPa HK0.4903N (= 2000 HK0.05) or more, which is a more preferable Knoop hardness. The Knoop hardness of the insulating layer 30 is measured by the Knoop hardness test method described in JIS Z2251:2009. Also, the Knoop hardness of the insulating layer 30 may be obtained by converting the measurement result of the Vickers hardness test described in JIS B7725:2010 or the measurement result of the Vickers hardness measured using a nanoindenter into the Knoop hardness.

[0022] The electrode 40 is positioned on the surface of the insulating layer 30 opposite to the substrate 10. The electrode 40 is connected to the semiconductor element 5. The electrode 40 is made of gold (Au). The thickness of the electrode 40 is, for example, 3.0 μm. The electrode 40 has a predetermined pattern shape so as to connect to a predetermined location on the semiconductor element 5 on which it is mounted. Note that the material forming the electrode 40 is not limited to gold, but may be made of copper.

[0023] Next, the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment will be described. In the manufacturing of the semiconductor element mounting substrate 1, first, the material that will become the base material 10 is pre-treated. Specifically, a plate-shaped rolled copper is prepared. After the surface of the prepared rolled copper is mirror-polished, nickel or the like, which has resistance to gold etching solution, is plated onto the mirror-polished surface. As a result, the manufactured base material 10 becomes less susceptible to oxidation and its corrosion resistance is improved. An adhesion layer 20 made of titanium is formed on the surface of the manufactured base material 10. The adhesion layer 20 is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Note that chemical polishing may be used instead of mirror polishing for the surface treatment of the prepared rolled copper.

[0024] Next, an insulating layer 30 is formed on the adhesion layer 20. In the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment, the insulating layer 30 is formed by reactive sputtering. The insulating layer 30 is formed on the surface of the adhesion layer 20 by using Al as the target, maintaining the temperature of the substrate 10 at 100 to 300°C, and flowing argon (Ar) and nitrogen (N2) at a vacuum of 0.1 to 0.8 Pa. In the formation of the insulating layer 30 of this embodiment, aluminum nitride is formed while applying a bias voltage of 125 (V) to the substrate 10.

[0025] Next, an electrode 40 is formed on the insulating layer 30. Specifically, first, an adhesion layer to improve adhesion with the insulating layer 30 and a seed layer to improve the bonding strength between the gold film that will become the electrode 40 and the adhesion layer are formed on the surface 31 of the insulating layer 30 as a base for the electrode 40. In this embodiment, the adhesion layer is formed from titanium using sputtering, and the seed layer is formed from palladium (Pd) using sputtering. Next, a gold film that will become the electrode 40 is formed on the seed layer, for example, by electroplating. The gold film may also be formed by sputtering or vapor deposition. Next, after forming the gold film on the seed layer, electrode patterning is performed. Specifically, for example, the gold film is coated with a resist by forming a dry film resist with a laminator, and a resist pattern is formed by exposure and development. Next, using the resist as a mask, the gold film, seed layer, and a part of the adhesion layer are removed by etching, and the resist is peeled off with a stripping solution to form the electrode 40. This process manufactures a semiconductor device mounting substrate 1. However, the manufacturing method of the semiconductor device mounting substrate 1 is not limited to these methods.

[0026] Next, an evaluation test relating to the semiconductor element mounting substrate 1 of this embodiment will be described. In this evaluation test, the effect of the bias voltage in the process of forming the insulating layer was evaluated. Specifically, a sample for the evaluation test was prepared by fabricating the insulating layer using a method similar to the manufacturing method of the semiconductor element mounting substrate 1 described above. At this time, multiple samples with insulating layers having different film formation conditions were prepared by changing the bias voltage applied to the substrate during the deposition of the insulating layer by reactive sputtering. The prepared samples were subjected to Knoop hardness measurement and a heat resistance test (ambient temperature: 350°C, ambient gas: air, test time: 10 minutes), after which the surface of the sample was observed to confirm the effect of the bias voltage.

[0027] Figure 2 is the first figure illustrating the results of the evaluation test related to bias voltage. Figure 2 shows the "bias voltage" applied to the substrate when forming the insulating layer, the "Knoop hardness" of the insulating layer, and an image of the surface of the insulating layer after the heat resistance test for each of the four types of samples 1 to 4 used in this evaluation test. In this evaluation test, the bias voltages applied to the substrate were 125(V), 94(V), 40(V), and 0(V). The Knoop hardness shown in Figure 2 was measured using the Knoop hardness test method described in JIS Z 2251:2009, similar to the semiconductor element mounting substrate 1 in this embodiment. As shown in Figure 2, it was confirmed that the Knoop hardness of the insulating layer increases as the bias voltage applied to the substrate increases.

[0028] Figure 2 shows images of the insulating layer surface after the heat resistance test. For each of samples 1 to 4, images P10, P20, P30, and P40 were taken using a microscope at 400x magnification of a 740 μm × 560 μm area of ​​the insulating layer surface after the heat resistance test at an ambient temperature of 350°C. The images in Figure 2 were taken using oblique light mode. No cracks or other defects were visually observed on the surface of the insulating layer of the samples from the images in Figure 2.

[0029] Figure 3 is a second figure illustrating the results of the evaluation test regarding the bias voltage. Figure 3 shows a magnified image P11 of a portion of image P10 of sample 1 shown in Figure 2. In sample 1, where the bias voltage was 125(V), no cracks were observed on the surface of the insulating layer, as shown in image P11.

[0030] Figure 4 is the third figure illustrating the results of the evaluation test regarding the bias voltage. Figure 4 shows a magnified image P21 of a portion of image P20 of sample 2 shown in Figure 2. Even in sample 2, where the bias voltage was 94(V), no cracks were observed on the surface of the insulating layer, as shown in image P21.

[0031] Figure 5 is the fourth figure illustrating the results of the evaluation test regarding the bias voltage. Figure 5 shows a magnified image P31 of a portion of image P30 of sample 3 shown in Figure 2. In sample 3, where the bias voltage was 40(V), it was confirmed that a crack CK was formed on the surface of the insulating layer, as shown in image P31.

[0032] Figure 6 is the fifth figure illustrating the results of the evaluation test related to bias voltage. Figure 6 shows a magnified image P41 of a portion of image P40 of sample 4 shown in Figure 2. In sample 4, where the bias voltage was 0 (V), i.e., no bias voltage was applied to the substrate, it was confirmed that more cracks CK were formed on the surface of the insulating layer than in sample 3, as shown in image P41. Thus, it was confirmed that applying a bias voltage above a certain value to the substrate during the deposition of the insulating layer by reactive sputtering increases the Knoop hardness. As a result, it was confirmed that the formation of cracks on the surface of the insulating layer is suppressed under the heat resistance test conditions.

[0033] As described above, the semiconductor element mounting substrate 1 of this embodiment has an insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 30 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 1, thereby suppressing defects such as cracks in the insulating layer 30. Therefore, the heat resistance of the insulating layer 30 can be improved.

[0034] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, the insulating layer 30 is formed of aluminum nitride. Aluminum nitride has relatively high thermal conductivity and relatively high electrical insulation properties. This allows for efficient dissipation of heat generated in the semiconductor element 5 connected to the electrode 40 via the substrate 10, while maintaining insulation between the electrode 40 and the substrate 10.

[0035] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, the base material 10 is made of copper, which has relatively high thermal conductivity. As a result, heat generated in the semiconductor element 5 connected to the electrode 40 can be efficiently released through the base material 10.

[0036] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, an adhesion layer 20 is formed between the base material 10 and the insulating layer 30 to improve the adhesion between the base material 10 and the insulating layer 30. This improves resistance to stress caused by differences in thermal expansion between the base material 10 and the insulating layer 30 due to temperature changes, for example, and thus suppresses the occurrence of cracks in the insulating layer 30. Therefore, the heat resistance of the insulating layer 30 can be further improved.

[0037] <Second Embodiment> Figure 7 is a cross-sectional view of the semiconductor element mounting substrate 2 of the second embodiment. The semiconductor element mounting substrate 2 of the second embodiment has a different insulating layer configuration compared to the semiconductor element mounting substrate 1 of the first embodiment (Figure 1).

[0038] The semiconductor element mounting substrate 2 of the second embodiment comprises a base material 10, an adhesion layer 20, an insulating layer 50, and an electrode 40. Note that the thickness relationships of the base material 10, adhesion layer 20, insulating layer 50, and electrode 40 in Figure 7 are illustrated differently from the actual thickness relationships for the sake of explanation.

[0039] The insulating layer 50 is positioned between the adhesion layer 20 formed on the substrate 10 and the electrode 40. The insulating layer 50 has a first insulating film 51 with a Knoop hardness of 147 GPa HK 0.4903 N or higher, and a second insulating film 52 with a Knoop hardness lower than that of the first insulating film 51. The first insulating film 51 and the second insulating film 52 have the same composition. Both the first insulating film 51 and the second insulating film 52 are formed of aluminum nitride. The insulating layer 50 insulates the substrate 10 from the electrode 40.

[0040] Next, the manufacturing method for the semiconductor element mounting substrate 2 of this embodiment will be described. The manufacturing method for the semiconductor element mounting substrate 2 is similar to the manufacturing method for the semiconductor element mounting substrate 1 of the first embodiment, but the method of forming the insulating layer is different. Here, we will explain the parts of the manufacturing method for the semiconductor element mounting substrate 2 that differ from the manufacturing method for the semiconductor element mounting substrate 1.

[0041] In the manufacturing of the semiconductor device mounting substrate 2, when depositing an insulating layer 50 on the adhesion layer 20, the bias voltage applied to the substrate 10 is changed. Specifically, when depositing the insulating layer 50 on the adhesion layer 20, first, the first insulating film 51 is deposited with a bias voltage of, for example, 125(V). After depositing the first insulating film 51, the second insulating film 52 is deposited with a bias voltage lower than the bias voltage used when depositing the first insulating film 51, for example, 94(V). As a result, an insulating layer 50 is deposited consisting of a first insulating film 51 and a second insulating film 52 that have the same composition but different Knoop hardness. In the deposition of the insulating layer 50, the target used in reactive sputtering is aluminum for both the first insulating film 51 and the second insulating film 52. That is, when depositing the insulating layer 50, there is no need to change the sputtering target.

[0042] As described above, the semiconductor element mounting substrate 2 of this embodiment has a first insulating film 51 having a Knoop hardness of 147 GPa HK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 50 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 2, thereby improving the heat resistance of the insulating layer 50.

[0043] Furthermore, in the semiconductor element mounting substrate 2 of this embodiment, a portion of the insulating layer 50 is a second insulating film 52 with relatively low Knoop hardness. This makes it possible to reduce stress in the insulating layer 50 while maintaining the thickness of the insulating layer 50, thereby suppressing warping of the semiconductor element mounting substrate 2.

[0044] Furthermore, according to the semiconductor device mounting substrate 2 of this embodiment, the insulating layer 50 has a first insulating film 51 and a second insulating film 52 having a lower Knoop hardness than the first insulating film 51. Since both the first insulating film 51 and the second insulating film 52 are formed of aluminum nitride, when depositing the insulating layer 50 in the manufacturing of the semiconductor device mounting substrate 2, the target used when depositing the first insulating film 51 and the target used when depositing the second insulating film 52 are the same. As a result, there is no need to switch targets when depositing the insulating layer 50, and the time required to deposit the insulating layer 50 can be shortened. Therefore, the production efficiency of the semiconductor device mounting substrate 2 can be improved.

[0045] Furthermore, according to the semiconductor element mounting substrate 2 of this embodiment, the insulating layer 50 is formed while a bias voltage is applied to the substrate 10. As a result, the coverage of the substrate 10 surface by the insulating layer 50 is improved, and thus the irregularities of the substrate 10 can be absorbed.

[0046] <Third Embodiment> Figure 8 is a cross-sectional view of the semiconductor element mounting substrate 3 of the third embodiment. The semiconductor element mounting substrate 3 of the third embodiment has a different insulating layer configuration compared to the semiconductor element mounting substrate 1 of the first embodiment (Figure 1).

[0047] The semiconductor element mounting substrate 3 of the third embodiment comprises a base material 10, an adhesion layer 20, an insulating layer 60, and an electrode 40. Note that the thickness relationships of the base material 10, the adhesion layer 20, the insulating layer 60, and the electrode 40 in Figure 8 are illustrated differently from the actual thickness relationships for the sake of explanation.

[0048] The insulating layer 60 is positioned between the adhesion layer 20 formed on the substrate 10 and the electrode 40. The insulating layer 60 comprises a first insulating film 61 having a Knoop hardness of 147 GPa HK 0.4903 N or higher, and a second insulating film 62 having a Knoop hardness lower than that of the first insulating film 61. In the insulating layer 60, the first insulating film 61 is positioned closer to the substrate 10 than the second insulating film 62. In this embodiment, the first insulating film 61 is made of silicon nitride (SiN), and the second insulating film 62 is made of aluminum nitride. The insulating layer 60 insulates the substrate 10 from the electrode 40.

[0049] Next, the manufacturing method of the semiconductor element mounting substrate 3 of this embodiment will be described. The manufacturing method of the semiconductor element mounting substrate 3 is similar to the manufacturing method of the semiconductor element mounting substrate 1 of the first embodiment, but the method of forming the insulating layer is different. Here, we will explain the parts of the manufacturing method of the semiconductor element mounting substrate 3 that differ from the manufacturing method of the semiconductor element mounting substrate 1.

[0050] In the manufacturing of the semiconductor device mounting substrate 3, when depositing an insulating layer 60 on the adhesion layer 20, the target in reactive sputtering is changed. Specifically, when depositing the insulating layer 60 on the adhesion layer 20, first, the target is set to Si and a first insulating film 61 is deposited. After depositing the first insulating film 61, the target is changed to Al and a second insulating film 62 is deposited. As a result, an insulating layer 60 consisting of the first insulating film 61 and the second insulating film 62 is deposited. Note that the point of depositing the film while applying a bias voltage to the substrate 10 is the same as in the manufacturing method of the semiconductor device mounting substrate 1.

[0051] As described above, the semiconductor element mounting substrate 3 of this embodiment has a first insulating film 61 having a Knoop hardness of 147 GPa HK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 60 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 3, thereby improving the heat resistance of the insulating layer 60.

[0052] Furthermore, in the semiconductor element mounting substrate 3 of this embodiment, a portion of the insulating layer 60 is a second insulating film 62 with relatively low Knoop hardness. This makes it possible to reduce stress in the insulating layer 60 while maintaining the thickness of the insulating layer 60, thereby suppressing warping of the semiconductor element mounting substrate 3.

[0053] <Fourth Embodiment> Figure 9 is a cross-sectional view of the semiconductor element mounting substrate 4 of the fourth embodiment. The semiconductor element mounting substrate 4 of the fourth embodiment has a different insulating layer configuration compared to the semiconductor element mounting substrate 1 of the first embodiment (Figure 1).

[0054] The semiconductor element mounting substrate 4 of the fourth embodiment comprises a base material 10, an adhesion layer 20, an insulating layer 70, and an electrode 40. Note that the thickness relationships of the base material 10, the adhesion layer 20, the insulating layer 70, and the electrode 40 in Figure 9 are illustrated differently from the actual thickness relationships for the sake of explanation.

[0055] The insulating layer 70 is positioned between the adhesion layer 20 formed on the substrate 10 and the electrode 40. The insulating layer 70 has a first insulating film 71 with a Knoop hardness of 147 GPa HK 0.4903 N or higher, and a second insulating film 72 with a Knoop hardness lower than that of the first insulating film 71. The second insulating film 72 is positioned on the substrate 10 side of the insulating layer 70 than the first insulating film 71. In this embodiment, the first insulating film 71 is made of silicon nitride, and the second insulating film 72 is made of aluminum nitride. The insulating layer 70 insulates the substrate 10 from the electrode 40.

[0056] Next, the manufacturing method of the semiconductor element mounting substrate 4 of this embodiment will be described. The manufacturing method of the semiconductor element mounting substrate 4 is similar to the manufacturing method of the semiconductor element mounting substrate 1 of the first embodiment, but the method of forming the insulating layer is different. Here, we will explain the parts of the manufacturing method of the semiconductor element mounting substrate 4 that differ from the manufacturing method of the semiconductor element mounting substrate 1.

[0057] In the manufacturing of the semiconductor device mounting substrate 4, when depositing an insulating layer 70 on the adhesion layer 20, the target in reactive sputtering is changed. Specifically, when depositing the insulating layer 70 on the adhesion layer 20, first, the target is set to Si and a second insulating film 72 is deposited. After depositing the second insulating film 72, the target is changed to Al and the first insulating film 71 is deposited. As a result, an insulating layer 70 consisting of the first insulating film 71 and the second insulating film 72 is deposited. Note that the point of depositing the film while applying a bias voltage to the substrate 10 is the same as in the manufacturing method of the semiconductor device mounting substrate 1.

[0058] As described above, the semiconductor element mounting substrate 4 of this embodiment has a first insulating film 71 having a Knoop hardness of 147 GPa HK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 70 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 4, thereby improving the heat resistance of the insulating layer 60.

[0059] Furthermore, according to the semiconductor element mounting substrate 4 of this embodiment, the insulating layer 70 has a first insulating film 71 and a second insulating film 72 having a lower Knoop hardness than the first insulating film 71. In the insulating layer 70, the second insulating film 72 is positioned closer to the substrate 10 than the first insulating film 71. By positioning the second insulating film 72, which has a relatively low Knoop hardness, closer to the substrate 10, it is possible to relieve stress so that thermal stress generated in the substrate 10 is not transmitted to the first insulating film 71, which has a relatively high Knoop hardness. This suppresses the occurrence of defects such as cracks in the insulating layer 70, and thus improves the heat resistance of the insulating layer 70.

[0060] Furthermore, in the semiconductor element mounting substrate 4 of this embodiment, a first insulating film 71 with a relatively high Knoop hardness is arranged on the side of the insulating layer 70 opposite to the base material 10. As a result, the surface 70a of the insulating layer 70 is relatively hard, making it less susceptible to scratches during the manufacturing process of the semiconductor element mounting substrate 4. Therefore, it is possible to suppress the occurrence of defects in the semiconductor element mounting substrate 4, such as insulation defects in the insulating layer 70.

[0061] <Modified form of this embodiment> The present invention is not limited to the embodiments described above, and can be implemented in various forms without departing from its spirit, for example, the following modifications are also possible.

[0062] [Example 1] In the above-described embodiment, the semiconductor element mounting substrate had an insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher. A Knoop hardness of 195.7 GPa HK 0.4903 N or higher is more preferable because it can further suppress the occurrence of cracks in the insulating properties.

[0063] [Differentiation 2] In the second, third, and third embodiments, the insulating layer has multiple insulating films with different Knoop hardnesses. The Knoop hardness in the insulating layer may change continuously in the lamination direction between the substrate and the insulating layer. Such an insulating layer can be formed by, for example, continuously changing the bias voltage applied to the substrate when forming the insulating layer.

[0064] [Difference 3] In the embodiments described above, the heat resistance of the insulating layer was described as a characteristic of temperature changes during the manufacturing of the semiconductor element mounting substrate. The temperature changes that can be accommodated are not limited to those during the manufacturing of the semiconductor element mounting substrate.

[0065] [Differentiation Example 4] In the embodiments described above, the semiconductor element 5 mounted on the semiconductor element mounting substrate was described as a light-emitting diode or a semiconductor laser, but it is not limited to these. It may also be a power semiconductor or the like, which generates a relatively large amount of heat.

[0066] [Difference 5] In the above-described embodiment, the substrate for mounting semiconductor elements is provided with an adhesion layer placed between the substrate and the insulating layer. The adhesion layer is not required, but by providing it, resistance to stress caused by the difference in thermal expansion between the substrate and the insulating layer due to temperature changes can be improved.

[0067] [Modification 6] In the second to fourth embodiments, the insulating layer comprises a first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film. The configuration of the insulating layer is not limited to these. The insulating layer may also have other films besides the first insulating film and the second insulating film. That is, the insulating layer may be formed by laminating three or more films, including the first insulating film and the second insulating film.

[0068] The embodiments of this specification have been described above based on the embodiments and modifications described above. The embodiments described above are for the purpose of facilitating understanding of this specification and do not limit it. This specification may be modified and improved without departing from its spirit and the scope of the claims, and equivalents thereof are included in this specification. Furthermore, any technical features that are not described as essential in this specification may be deleted as appropriate.

[0069] (Application Example 1) A substrate for mounting semiconductor devices, Substrate and semiconductor element cross-electrode, The facility comprises an insulating layer disposed between the substrate and the electrode, The insulating layer is characterized by having an insulating film with a Knoop hardness of 147 GPa HK 0.4903 N or higher. A substrate for mounting semiconductor devices. (Application Example 2) A semiconductor element mounting substrate as described in Application Example 1, The insulating layer is A first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher, The invention comprises a second insulating film having a Knoop hardness lower than that of the first insulating film, The first insulating film and the second insulating film are characterized by having the same composition. A substrate for mounting semiconductor devices. (Application Example 3) A semiconductor element mounting substrate according to claim 1 or claim 2, The insulating layer is A first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher, The invention comprises a second insulating film having a Knoop hardness lower than that of the first insulating film, The first insulating film is characterized in that, in the insulating layer, it is positioned closer to the substrate than the second insulating film. A substrate for mounting semiconductor devices. (Application Example 4) A semiconductor element mounting substrate as described in any one of Application Examples 1 to 3, The insulating layer is A first insulating film having a Knoop hardness of 147 GPa HK 0.4903 N or higher, The invention comprises a second insulating film having a Knoop hardness lower than that of the first insulating film, The second insulating film is characterized in that, in the insulating layer, it is positioned closer to the substrate than the first insulating film. A substrate for mounting semiconductor devices. (Application Example 5) A semiconductor element mounting substrate as described in any one of Application Examples 1 to 4, The insulating layer is characterized by being formed of aluminum nitride. A substrate for mounting semiconductor devices. (Application Example 6) A semiconductor element mounting substrate as described in any one of Application Examples 1 to 5, The substrate is characterized by being formed from a material mainly composed of copper or aluminum. A substrate for mounting semiconductor devices. (Application Example 7) A semiconductor device mounting substrate described in any one of Application Examples 1 to 6 is further, The invention is characterized by comprising an adhesion layer disposed between the substrate and the insulating layer. A substrate for mounting semiconductor devices. [Explanation of Symbols]

[0070] 1, 2, 3, 4… Substrates for mounting semiconductor devices 10...Base material 20… Close contact layer 30, 50, 60, 70… Insulating layer 40...electrode 51, 61, 71… First insulating film 52, 62, 72… Second insulating film

Claims

1. A substrate for mounting semiconductor devices, Substrate and semiconductor element cross-electrode, The facility comprises an insulating layer disposed between the substrate and the electrode, The insulating layer is characterized by having an insulating film with a Knoop hardness of 14.7 GPaHK 0.4903 N or higher. A substrate for mounting semiconductor devices.

2. A semiconductor element mounting substrate according to claim 1, The insulating layer is A first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, The invention comprises a second insulating film having a Knoop hardness lower than that of the first insulating film, The first insulating film and the second insulating film are characterized by having the same composition. A substrate for mounting semiconductor devices.

3. A semiconductor element mounting substrate according to claim 1, The insulating layer is A first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, The invention comprises a second insulating film having a Knoop hardness lower than that of the first insulating film, The first insulating film is characterized in that, in the insulating layer, it is positioned closer to the substrate than the second insulating film. A substrate for mounting semiconductor devices.

4. A semiconductor element mounting substrate according to claim 1, The insulating layer is A first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, The invention comprises a second insulating film having a Knoop hardness lower than that of the first insulating film, The second insulating film is characterized in that, in the insulating layer, it is positioned closer to the substrate than the first insulating film. A substrate for mounting semiconductor devices.

5. A semiconductor element mounting substrate according to any one of claims 1 to 4, The insulating layer is characterized by being formed of aluminum nitride. A substrate for mounting semiconductor devices.

6. A semiconductor element mounting substrate according to any one of claims 1 to 4, The substrate is characterized by being formed from a material mainly composed of copper or aluminum. A substrate for mounting semiconductor devices.

7. The semiconductor element mounting substrate according to any one of claims 1 to 4 further, The invention is characterized by comprising an adhesion layer disposed between the substrate and the insulating layer. A substrate for mounting semiconductor devices.

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